1 /* Public Domain */ 2 3 /* 4 * RK3288 clocks. 5 */ 6 7 #define RK3288_PLL_APLL 1 8 #define RK3288_PLL_CPLL 3 9 #define RK3288_PLL_GPLL 4 10 #define RK3288_PLL_NPLL 5 11 #define RK3288_ARMCLK 6 12 13 #define RK3288_CLK_SDMMC 68 14 #define RK3288_CLK_TSADC 72 15 #define RK3288_CLK_UART0 77 16 #define RK3288_CLK_UART1 78 17 #define RK3288_CLK_UART2 79 18 #define RK3288_CLK_UART3 80 19 #define RK3288_CLK_UART4 81 20 #define RK3288_CLK_MAC_RX 102 21 #define RK3288_CLK_MAC_TX 103 22 #define RK3288_CLK_SDMMC_DRV 114 23 #define RK3288_CLK_SDMMC_SAMPLE 118 24 #define RK3288_CLK_MAC 151 25 26 #define RK3288_ACLK_GMAC 196 27 28 #define RK3288_PCLK_I2C0 332 29 #define RK3288_PCLK_I2C1 333 30 #define RK3288_PCLK_I2C2 334 31 #define RK3288_PCLK_I2C3 335 32 #define RK3288_PCLK_I2C4 336 33 #define RK3288_PCLK_I2C5 337 34 #define RK3288_PCLK_TSADC 346 35 #define RK3288_PCLK_GMAC 349 36 37 #define RK3288_HCLK_HOST0 450 38 #define RK3288_HCLK_SDMMC 456 39 40 #define RK3288_XIN24M 1023 41 42 /* 43 * RK3308 clocks. 44 */ 45 46 #define RK3308_PLL_APLL 1 47 #define RK3308_PLL_DPLL 2 48 #define RK3308_PLL_VPLL0 3 49 #define RK3308_PLL_VPLL1 4 50 #define RK3308_ARMCLK 5 51 52 #define RK3308_USB480M 14 53 #define RK3308_CLK_RTC32K 15 54 #define RK3308_CLK_UART0 17 55 #define RK3308_CLK_UART1 18 56 #define RK3308_CLK_UART2 19 57 #define RK3308_CLK_UART3 20 58 #define RK3308_CLK_UART4 21 59 #define RK3308_CLK_PWM0 26 60 #define RK3308_CLK_TSADC 36 61 #define RK3308_CLK_SARADC 37 62 #define RK3308_CLK_CRYPTO 41 63 #define RK3308_CLK_CRYPTO_APK 42 64 #define RK3308_CLK_SDMMC 48 65 #define RK3308_CLK_SDMMC_DRV 49 66 #define RK3308_CLK_SDMMC_SAMPLE 50 67 #define RK3308_CLK_SDIO 53 68 #define RK3308_CLK_SDIO_DRV 54 69 #define RK3308_CLK_SDIO_SAMPLE 55 70 #define RK3308_CLK_EMMC 58 71 #define RK3308_CLK_MAC_SRC 63 72 #define RK3308_CLK_MAC 64 73 #define RK3308_CLK_MAC_RMII 67 74 75 #define RK3308_ACLK_BUS_SRC 130 76 #define RK3308_ACLK_BUS 131 77 #define RK3308_ACLK_PERI_SRC 132 78 #define RK3308_ACLK_PERI 133 79 #define RK3308_ACLK_MAC 134 80 #define RK3308_ACLK_CRYPTO 135 81 #define RK3308_ACLK_GIC 137 82 83 #define RK3308_HCLK_BUS 150 84 #define RK3308_HCLK_PERI 151 85 #define RK3308_HCLK_SDMMC 154 86 #define RK3308_HCLK_CRYPTO 171 87 88 #define RK3308_PCLK_BUS 190 89 #define RK3308_PCLK_PERI 192 90 #define RK3308_PCLK_MAC 195 91 92 #define RK3308_XIN24M 1023 93 94 /* 95 * RK3328 clocks. 96 */ 97 98 #define RK3328_PLL_APLL 1 99 #define RK3328_PLL_DPLL 2 100 #define RK3328_PLL_CPLL 3 101 #define RK3328_PLL_GPLL 4 102 #define RK3328_PLL_NPLL 5 103 #define RK3328_ARMCLK 6 104 105 #define RK3328_CLK_RTC32K 30 106 #define RK3328_CLK_SDMMC 33 107 #define RK3328_CLK_SDIO 34 108 #define RK3328_CLK_EMMC 35 109 #define RK3328_CLK_TSADC 36 110 #define RK3328_CLK_UART0 38 111 #define RK3328_CLK_UART1 39 112 #define RK3328_CLK_UART2 40 113 #define RK3328_CLK_WIFI 53 114 #define RK3328_CLK_I2C0 55 115 #define RK3328_CLK_I2C1 56 116 #define RK3328_CLK_I2C2 57 117 #define RK3328_CLK_I2C3 58 118 #define RK3328_CLK_CRYPTO 59 119 #define RK3328_CLK_PDM 61 120 #define RK3328_CLK_VDEC_CABAC 65 121 #define RK3328_CLK_VDEC_CORE 66 122 #define RK3328_CLK_VENC_DSP 67 123 #define RK3328_CLK_VENC_CORE 68 124 #define RK3328_CLK_TSP 92 125 #define RK3328_CLK_MAC2IO_SRC 99 126 #define RK3328_CLK_MAC2IO 100 127 #define RK3328_CLK_MAC2IO_EXT 102 128 129 #define RK3328_DCLK_LCDC 120 130 #define RK3328_HDMIPHY 122 131 #define RK3328_USB480M 123 132 #define RK3328_DCLK_LCDC_SRC 124 133 134 #define RK3328_ACLK_VOP_PRE 131 135 #define RK3328_ACLK_RGA_PRE 133 136 #define RK3328_ACLK_BUS_PRE 136 137 #define RK3328_ACLK_PERI_PRE 137 138 #define RK3328_ACLK_RKVDEC_PRE 138 139 #define RK3328_ACLK_RKVENC 140 140 #define RK3328_ACLK_VPU_PRE 141 141 #define RK3328_ACLK_VIO_PRE 142 142 143 #define RK3328_PCLK_BUS_PRE 216 144 #define RK3328_PCLK_PERI 230 145 146 #define RK3328_HCLK_PERI 308 147 #define RK3328_HCLK_BUS_PRE 328 148 #define RK3328_HCLK_CRYPTO_SLV 337 149 150 #define RK3328_XIN24M 1023 151 #define RK3328_CLK_24M 1022 152 #define RK3328_GMAC_CLKIN 1021 153 154 /* 155 * RK3399 clocks. 156 */ 157 158 #define RK3399_PLL_ALPLL 1 159 #define RK3399_PLL_ABPLL 2 160 #define RK3399_PLL_DPLL 3 161 #define RK3399_PLL_CPLL 4 162 #define RK3399_PLL_GPLL 5 163 #define RK3399_PLL_NPLL 6 164 #define RK3399_PLL_VPLL 7 165 #define RK3399_ARMCLKL 8 166 #define RK3399_ARMCLKB 9 167 168 #define RK3399_CLK_I2C1 65 169 #define RK3399_CLK_I2C2 66 170 #define RK3399_CLK_I2C3 67 171 #define RK3399_CLK_I2C5 68 172 #define RK3399_CLK_I2C6 69 173 #define RK3399_CLK_I2C7 70 174 #define RK3399_CLK_SDMMC 76 175 #define RK3399_CLK_SDIO 77 176 #define RK3399_CLK_EMMC 78 177 #define RK3399_CLK_TSADC 79 178 #define RK3399_CLK_UART0 81 179 #define RK3399_CLK_UART1 82 180 #define RK3399_CLK_UART2 83 181 #define RK3399_CLK_UART3 84 182 #define RK3399_CLK_SPDIF_8CH 85 183 #define RK3399_CLK_I2S0_8CH 86 184 #define RK3399_CLK_I2S1_8CH 87 185 #define RK3399_CLK_I2S2_8CH 88 186 #define RK3399_CLK_I2S_8CH_OUT 89 187 #define RK3399_CLK_MAC_RX 103 188 #define RK3399_CLK_MAC_TX 104 189 #define RK3399_CLK_MAC 105 190 #define RK3399_CLK_UPHY0_TCPDCORE 126 191 #define RK3399_CLK_UPHY1_TCPDCORE 128 192 #define RK3399_CLK_USB3OTG0_REF 129 193 #define RK3399_CLK_USB3OTG1_REF 130 194 #define RK3399_CLK_USB3OTG0_SUSPEND 131 195 #define RK3399_CLK_USB3OTG1_SUSPEND 132 196 #define RK3399_CLK_PCIEPHY_REF 138 197 #define RK3399_CLK_SDMMC_DRV 154 198 #define RK3399_CLK_SDMMC_SAMPLE 155 199 #define RK3399_CLK_PCIEPHY_REF100M 167 200 201 #define RK3399_DCLK_VOP0 180 202 #define RK3399_DCLK_VOP1 181 203 #define RK3399_DCLK_VOP0_DIV 182 204 #define RK3399_DCLK_VOP1_DIV 183 205 #define RK3399_DCLK_VOP0_FRAC 185 206 #define RK3399_DCLK_VOP1_FRAC 186 207 208 #define RK3399_ACLK_PERIPH 192 209 #define RK3399_ACLK_PERILP0 194 210 #define RK3399_ACLK_CCI 201 211 #define RK3399_ACLK_GMAC 213 212 #define RK3399_ACLK_VOP0_NOC 216 213 #define RK3399_ACLK_VOP0 217 214 #define RK3399_ACLK_VOP1_NOC 218 215 #define RK3399_ACLK_VOP1 219 216 #define RK3399_ACLK_HDCP 222 217 #define RK3399_ACLK_VIO 227 218 #define RK3399_ACLK_EMMC 240 219 #define RK3399_ACLK_USB3OTG0 246 220 #define RK3399_ACLK_USB3OTG1 247 221 #define RK3399_ACLK_USB3_GRF 249 222 #define RK3399_ACLK_GIC_PRE 262 223 224 #define RK3399_PCLK_PERIPH 320 225 #define RK3399_PCLK_PERILP0 322 226 #define RK3399_PCLK_PERILP1 323 227 #define RK3399_PCLK_I2C1 341 228 #define RK3399_PCLK_I2C2 342 229 #define RK3399_PCLK_I2C3 343 230 #define RK3399_PCLK_I2C5 344 231 #define RK3399_PCLK_I2C6 345 232 #define RK3399_PCLK_I2C7 346 233 #define RK3399_PCLK_TSADC 356 234 #define RK3399_PCLK_GMAC 358 235 #define RK3399_PCLK_DDR 376 236 #define RK3399_PCLK_WDT 380 237 238 #define RK3399_HCLK_PERIPH 448 239 #define RK3399_HCLK_PERILP0 449 240 #define RK3399_HCLK_PERILP1 450 241 #define RK3399_HCLK_HOST0 456 242 #define RK3399_HCLK_HOST0_ARB 457 243 #define RK3399_HCLK_HOST1 458 244 #define RK3399_HCLK_HOST1_ARB 459 245 #define RK3399_HCLK_SDMMC 462 246 #define RK3399_HCLK_VOP0_NOC 472 247 #define RK3399_HCLK_VOP0 473 248 #define RK3399_HCLK_VOP1_NOC 474 249 #define RK3399_HCLK_VOP1 475 250 251 /* PMUCRU */ 252 253 #define RK3399_PLL_PPLL 1 254 255 #define RK3399_CLK_I2C0 9 256 #define RK3399_CLK_I2C4 10 257 #define RK3399_CLK_I2C8 11 258 259 #define RK3399_PCLK_I2C0 27 260 #define RK3399_PCLK_I2C4 28 261 #define RK3399_PCLK_I2C8 29 262 #define RK3399_PCLK_RKPWM 30 263 264 #define RK3399_XIN24M 1023 265 #define RK3399_CLK_32K 1022 266 #define RK3399_XIN12M 1021 267 #define RK3399_CLK_I2S0_DIV 1020 268 #define RK3399_CLK_I2S0_FRAC 1019 269 #define RK3399_CLK_I2S1_DIV 1018 270 #define RK3399_CLK_I2S1_FRAC 1017 271 #define RK3399_CLK_I2S2_DIV 1016 272 #define RK3399_CLK_I2S2_FRAC 1015 273 #define RK3399_CLK_I2SOUT_SRC 1014 274