1 /* $OpenBSD: sxitwi.c,v 1.11 2018/12/04 11:25:48 kettenis Exp $ */ 2 /* $NetBSD: gttwsi_core.c,v 1.2 2014/11/23 13:37:27 jmcneill Exp $ */ 3 /* 4 * Copyright (c) 2008 Eiji Kawauchi. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Eiji Kawauchi. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2005 Brocade Communcations, inc. 35 * All rights reserved. 36 * 37 * Written by Matt Thomas for Brocade Communcations, Inc. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. The name of Brocade Communications, Inc. may not be used to endorse 48 * or promote products derived from this software without specific prior 49 * written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE 55 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 61 * OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Marvell Two-Wire Serial Interface (aka I2C) master driver 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/device.h> 71 #include <sys/kernel.h> 72 #include <sys/rwlock.h> 73 74 #define _I2C_PRIVATE 75 #include <dev/i2c/i2cvar.h> 76 77 #include <machine/bus.h> 78 #include <machine/fdt.h> 79 80 #include <dev/ofw/openfirm.h> 81 #include <dev/ofw/ofw_clock.h> 82 #include <dev/ofw/ofw_pinctrl.h> 83 #include <dev/ofw/fdt.h> 84 85 #define TWSI_SLAVEADDR 0 86 #define TWSI_EXTEND_SLAVEADDR 1 87 #define TWSI_DATA 2 88 #define TWSI_CONTROL 3 89 #define TWSI_STATUS 4 90 #define TWSI_CLOCK 5 91 #define TWSI_SOFTRESET 6 92 #define TWSI_NREG 7 93 94 #define SLAVEADDR_GCE_MASK 0x01 95 #define SLAVEADDR_SADDR_MASK 0xfe 96 97 #define EXTEND_SLAVEADDR_MASK 0xff 98 99 #define DATA_MASK 0xff 100 101 #define CONTROL_ACK (1 << 2) 102 #define CONTROL_IFLG (1 << 3) 103 #define CONTROL_STOP (1 << 4) 104 #define CONTROL_START (1 << 5) 105 #define CONTROL_TWSIEN (1 << 6) 106 #define CONTROL_INTEN (1 << 7) 107 108 #define STAT_BE 0x00 /* Bus Error */ 109 #define STAT_SCT 0x08 /* Start condition transmitted */ 110 #define STAT_RSCT 0x10 /* Repeated start condition transmitted */ 111 #define STAT_AWBT_AR 0x18 /* Address + write bit transd, ack recvd */ 112 #define STAT_AWBT_ANR 0x20 /* Address + write bit transd, ack not recvd */ 113 #define STAT_MTDB_AR 0x28 /* Master transd data byte, ack recvd */ 114 #define STAT_MTDB_ANR 0x30 /* Master transd data byte, ack not recvd */ 115 #define STAT_MLADADT 0x38 /* Master lost arbitr during addr or data tx */ 116 #define STAT_ARBT_AR 0x40 /* Address + read bit transd, ack recvd */ 117 #define STAT_ARBT_ANR 0x48 /* Address + read bit transd, ack not recvd */ 118 #define STAT_MRRD_AT 0x50 /* Master received read data, ack transd */ 119 #define STAT_MRRD_ANT 0x58 /* Master received read data, ack not transd */ 120 #define STAT_SAWBT_AR 0xd0 /* Second addr + write bit transd, ack recvd */ 121 #define STAT_SAWBT_ANR 0xd8 /* S addr + write bit transd, ack not recvd */ 122 #define STAT_SARBT_AR 0xe0 /* Second addr + read bit transd, ack recvd */ 123 #define STAT_SARBT_ANR 0xe8 /* S addr + read bit transd, ack not recvd */ 124 #define STAT_NRS 0xf8 /* No relevant status */ 125 126 #define SOFTRESET_VAL 0 /* reset value */ 127 128 struct sxitwi_softc { 129 struct device sc_dev; 130 bus_space_tag_t sc_iot; 131 bus_space_handle_t sc_ioh; 132 int sc_node; 133 u_int sc_started; 134 u_int sc_twsien_iflg; 135 struct i2c_controller sc_ic; 136 struct rwlock sc_buslock; 137 void *sc_ih; 138 uint8_t sc_regs[TWSI_NREG]; 139 int sc_delay; 140 }; 141 142 void sxitwi_attach(struct device *, struct device *, void *); 143 int sxitwi_match(struct device *, void *, void *); 144 void sxitwi_bus_scan(struct device *, struct i2cbus_attach_args *, void *); 145 146 int sxitwi_intr(void *); 147 int sxitwi_acquire_bus(void *, int); 148 void sxitwi_release_bus(void *, int); 149 int sxitwi_send_start(void *, int); 150 int sxitwi_send_stop(void *, int); 151 int sxitwi_initiate_xfer(void *, i2c_addr_t, int); 152 int sxitwi_read_byte(void *, uint8_t *, int); 153 int sxitwi_write_byte(void *, uint8_t, int); 154 int sxitwi_wait(struct sxitwi_softc *, u_int, u_int, int); 155 static inline u_int sxitwi_read_4(struct sxitwi_softc *, u_int); 156 static inline void sxitwi_write_4(struct sxitwi_softc *, u_int, u_int); 157 158 struct cfdriver sxitwi_cd = { 159 NULL, "sxitwi", DV_DULL 160 }; 161 162 struct cfattach sxitwi_ca = { 163 sizeof(struct sxitwi_softc), sxitwi_match, sxitwi_attach 164 }; 165 166 int 167 sxitwi_match(struct device *parent, void *match, void *aux) 168 { 169 struct fdt_attach_args *faa = aux; 170 171 return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-i2c") || 172 OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-i2c") || 173 OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-i2c") || 174 OF_is_compatible(faa->fa_node, "marvell,mv78230-i2c") || 175 OF_is_compatible(faa->fa_node, "marvell,mv78230-a0-i2c")); 176 } 177 178 void 179 sxitwi_attach(struct device *parent, struct device *self, void *aux) 180 { 181 struct sxitwi_softc *sc = (struct sxitwi_softc *)self; 182 struct fdt_attach_args *faa = aux; 183 struct i2cbus_attach_args iba; 184 uint32_t freq, parent_freq; 185 uint32_t m, n, nbase; 186 187 if (faa->fa_nreg < 1) { 188 printf(": no registers\n"); 189 return; 190 } 191 192 nbase = 1; 193 sc->sc_regs[TWSI_SLAVEADDR] = 0x00; 194 sc->sc_regs[TWSI_EXTEND_SLAVEADDR] = 0x04; 195 sc->sc_regs[TWSI_DATA] = 0x08; 196 sc->sc_regs[TWSI_CONTROL] = 0x0c; 197 sc->sc_regs[TWSI_STATUS] = 0x10; 198 sc->sc_regs[TWSI_CLOCK] = 0x14; 199 sc->sc_regs[TWSI_SOFTRESET] = 0x18; 200 201 if (OF_is_compatible(faa->fa_node, "marvell,mv78230-i2c") || 202 OF_is_compatible(faa->fa_node, "marvell,mv78230-a0-i2c")) { 203 nbase = 2; 204 sc->sc_delay = 1; 205 sc->sc_regs[TWSI_SLAVEADDR] = 0x00; 206 sc->sc_regs[TWSI_EXTEND_SLAVEADDR] = 0x10; 207 sc->sc_regs[TWSI_DATA] = 0x04; 208 sc->sc_regs[TWSI_CONTROL] = 0x08; 209 sc->sc_regs[TWSI_STATUS] = 0x0c; 210 sc->sc_regs[TWSI_CLOCK] = 0x0c; 211 sc->sc_regs[TWSI_SOFTRESET] = 0x1c; 212 } 213 214 /* 215 * Calculate clock dividers up front such that we can bail out 216 * early if the desired clock rate can't be obtained. Make 217 * sure the bus clock rate is never above the desired rate. 218 */ 219 parent_freq = clock_get_frequency(faa->fa_node, NULL); 220 freq = OF_getpropint(faa->fa_node, "clock-frequency", 100000); 221 if (parent_freq == 0) { 222 printf(": unknown clock frequency\n"); 223 return; 224 } 225 n = 0, m = 0; 226 while ((freq * (nbase << n) * 16 * 10) < parent_freq) 227 n++; 228 while ((freq * (nbase << n) * (m + 1) * 10) < parent_freq) 229 m++; 230 if (n > 8 || m > 16) { 231 printf(": clock frequency too high\n"); 232 return; 233 } 234 235 sc->sc_node = faa->fa_node; 236 sc->sc_iot = faa->fa_iot; 237 238 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 239 faa->fa_reg[0].size, 0, &sc->sc_ioh)) { 240 printf(": can't map registers\n"); 241 return; 242 } 243 244 rw_init(&sc->sc_buslock, sc->sc_dev.dv_xname); 245 246 /* 247 * On the Allwinner A31 we need to write 1 to clear a pending 248 * interrupt. 249 */ 250 sc->sc_twsien_iflg = CONTROL_TWSIEN; 251 if (OF_is_compatible(sc->sc_node, "allwinner,sun6i-a31-i2c")) 252 sc->sc_twsien_iflg |= CONTROL_IFLG; 253 254 sc->sc_started = 0; 255 sc->sc_ic.ic_cookie = sc; 256 sc->sc_ic.ic_acquire_bus = sxitwi_acquire_bus; 257 sc->sc_ic.ic_release_bus = sxitwi_release_bus; 258 sc->sc_ic.ic_exec = NULL; 259 sc->sc_ic.ic_send_start = sxitwi_send_start; 260 sc->sc_ic.ic_send_stop = sxitwi_send_stop; 261 sc->sc_ic.ic_initiate_xfer = sxitwi_initiate_xfer; 262 sc->sc_ic.ic_read_byte = sxitwi_read_byte; 263 sc->sc_ic.ic_write_byte = sxitwi_write_byte; 264 265 pinctrl_byname(faa->fa_node, "default"); 266 267 /* Enable clock */ 268 clock_enable(faa->fa_node, NULL); 269 reset_deassert_all(faa->fa_node); 270 271 /* Set clock rate. */ 272 sxitwi_write_4(sc, TWSI_CLOCK, (m << 3) | (n << 0)); 273 274 /* Put the controller into Soft Reset. */ 275 sxitwi_write_4(sc, TWSI_SOFTRESET, SOFTRESET_VAL); 276 277 /* Establish interrupt */ 278 sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, 279 sxitwi_intr, sc, sc->sc_dev.dv_xname); 280 if (sc->sc_ih == NULL) { 281 printf(": can't establish interrupt\n"); 282 return; 283 } 284 285 printf("\n"); 286 287 /* Configure its children */ 288 memset(&iba, 0, sizeof(iba)); 289 iba.iba_name = "iic"; 290 iba.iba_tag = &sc->sc_ic; 291 iba.iba_bus_scan = sxitwi_bus_scan; 292 iba.iba_bus_scan_arg = &sc->sc_node; 293 294 config_found(&sc->sc_dev, &iba, iicbus_print); 295 } 296 297 void 298 sxitwi_bus_scan(struct device *self, struct i2cbus_attach_args *iba, void *arg) 299 { 300 int iba_node = *(int *)arg; 301 struct i2c_attach_args ia; 302 char name[32]; 303 uint32_t reg[1]; 304 int node; 305 306 for (node = OF_child(iba_node); node; node = OF_peer(node)) { 307 memset(name, 0, sizeof(name)); 308 memset(reg, 0, sizeof(reg)); 309 310 if (OF_getprop(node, "compatible", name, sizeof(name)) == -1) 311 continue; 312 if (name[0] == '\0') 313 continue; 314 315 if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg)) 316 continue; 317 318 memset(&ia, 0, sizeof(ia)); 319 ia.ia_tag = iba->iba_tag; 320 ia.ia_addr = bemtoh32(®[0]); 321 ia.ia_name = name; 322 ia.ia_cookie = &node; 323 config_found(self, &ia, iic_print); 324 } 325 } 326 327 u_int 328 sxitwi_read_4(struct sxitwi_softc *sc, u_int reg) 329 { 330 KASSERT(reg < TWSI_NREG); 331 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, sc->sc_regs[reg]); 332 } 333 334 void 335 sxitwi_write_4(struct sxitwi_softc *sc, u_int reg, u_int val) 336 { 337 KASSERT(reg < TWSI_NREG); 338 bus_space_write_4(sc->sc_iot, sc->sc_ioh, sc->sc_regs[reg], val); 339 } 340 341 int 342 sxitwi_intr(void *arg) 343 { 344 struct sxitwi_softc *sc = arg; 345 u_int val; 346 347 val = sxitwi_read_4(sc, TWSI_CONTROL); 348 if (val & CONTROL_IFLG) { 349 sxitwi_write_4(sc, TWSI_CONTROL, val & ~CONTROL_INTEN); 350 return 1; 351 } 352 return 0; 353 } 354 355 int 356 sxitwi_acquire_bus(void *arg, int flags) 357 { 358 struct sxitwi_softc *sc = arg; 359 360 if (flags & I2C_F_POLL) 361 return 0; 362 363 return rw_enter(&sc->sc_buslock, RW_WRITE); 364 } 365 366 void 367 sxitwi_release_bus(void *arg, int flags) 368 { 369 struct sxitwi_softc *sc = arg; 370 371 if (flags & I2C_F_POLL) 372 return; 373 374 rw_exit(&sc->sc_buslock); 375 } 376 377 int 378 sxitwi_send_start(void *v, int flags) 379 { 380 struct sxitwi_softc *sc = v; 381 int expect; 382 383 if (sc->sc_started) 384 expect = STAT_RSCT; 385 else 386 expect = STAT_SCT; 387 sc->sc_started = 1; 388 389 return sxitwi_wait(sc, CONTROL_START, expect, flags); 390 } 391 392 int 393 sxitwi_send_stop(void *v, int flags) 394 { 395 struct sxitwi_softc *sc = v; 396 397 sc->sc_started = 0; 398 399 /* 400 * No need to wait; the controller doesn't transmit the next 401 * START condition until the bus is free. 402 */ 403 sxitwi_write_4(sc, TWSI_CONTROL, CONTROL_STOP | sc->sc_twsien_iflg); 404 if (sc->sc_delay) 405 delay(5); 406 return 0; 407 } 408 409 int 410 sxitwi_initiate_xfer(void *v, i2c_addr_t addr, int flags) 411 { 412 struct sxitwi_softc *sc = v; 413 u_int data, expect; 414 int error, read; 415 416 sxitwi_send_start(v, flags); 417 418 read = (flags & I2C_F_READ) != 0; 419 if (read) 420 expect = STAT_ARBT_AR; 421 else 422 expect = STAT_AWBT_AR; 423 424 /* 425 * First byte contains whether this xfer is a read or write. 426 */ 427 data = read; 428 if (addr > 0x7f) { 429 /* 430 * If this is a 10bit request, the first address byte is 431 * 0b11110<b9><b8><r/w>. 432 */ 433 data |= 0xf0 | ((addr & 0x300) >> 7); 434 sxitwi_write_4(sc, TWSI_DATA, data); 435 error = sxitwi_wait(sc, 0, expect, flags); 436 if (error) 437 return error; 438 /* 439 * The first address byte has been sent, now to send 440 * the second one. 441 */ 442 if (read) 443 expect = STAT_SARBT_AR; 444 else 445 expect = STAT_SAWBT_AR; 446 data = (uint8_t)addr; 447 } else 448 data |= (addr << 1); 449 450 sxitwi_write_4(sc, TWSI_DATA, data); 451 return sxitwi_wait(sc, 0, expect, flags); 452 } 453 454 int 455 sxitwi_read_byte(void *v, uint8_t *valp, int flags) 456 { 457 struct sxitwi_softc *sc = v; 458 int error; 459 460 if (flags & I2C_F_LAST) 461 error = sxitwi_wait(sc, 0, STAT_MRRD_ANT, flags); 462 else 463 error = sxitwi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, flags); 464 if (!error) 465 *valp = sxitwi_read_4(sc, TWSI_DATA); 466 if ((flags & (I2C_F_LAST | I2C_F_STOP)) == (I2C_F_LAST | I2C_F_STOP)) 467 error = sxitwi_send_stop(sc, flags); 468 return error; 469 } 470 471 int 472 sxitwi_write_byte(void *v, uint8_t val, int flags) 473 { 474 struct sxitwi_softc *sc = v; 475 int error; 476 477 sxitwi_write_4(sc, TWSI_DATA, val); 478 error = sxitwi_wait(sc, 0, STAT_MTDB_AR, flags); 479 if (flags & I2C_F_STOP) 480 sxitwi_send_stop(sc, flags); 481 return error; 482 } 483 484 int 485 sxitwi_wait(struct sxitwi_softc *sc, u_int control, u_int expect, int flags) 486 { 487 u_int status; 488 int timo; 489 490 sxitwi_write_4(sc, TWSI_CONTROL, control | sc->sc_twsien_iflg); 491 492 for (timo = 10000; timo > 0; timo--) { 493 control = sxitwi_read_4(sc, TWSI_CONTROL); 494 if (control & CONTROL_IFLG) 495 break; 496 delay(1); 497 } 498 if (timo == 0) 499 return ETIMEDOUT; 500 501 if (sc->sc_delay) 502 delay(5); 503 504 status = sxitwi_read_4(sc, TWSI_STATUS); 505 if (status != expect) 506 return EIO; 507 return 0; 508 } 509