1 /* $OpenBSD: adwlib.c,v 1.23 2011/04/07 15:30:16 miod Exp $ */ 2 /* $NetBSD: adwlib.c,v 1.20 2000/07/04 04:17:03 itojun Exp $ */ 3 4 /* 5 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from: 35 */ 36 /* 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-2000 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 */ 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/queue.h> 54 #include <sys/device.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <scsi/scsi_all.h> 60 #include <scsi/scsiconf.h> 61 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/ic/adwlib.h> 65 #include <dev/microcode/adw/adwmcode.h> 66 #include <dev/ic/adw.h> 67 68 69 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t); 70 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, 71 u_int8_t); 72 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 73 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, 74 ADW_DVC_CFG *); 75 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, 76 ADW_DVC_CFG *); 77 78 u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 79 ADW_EEPROM *); 80 void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 81 ADW_EEPROM *); 82 u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int); 83 void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t); 84 85 void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 86 87 void AdwSleepMilliSecond(u_int32_t); 88 void AdwDelayMicroSecond(u_int32_t); 89 90 91 /* 92 * EEPROM Configuration. 93 * 94 * All drivers should use this structure to set the default EEPROM 95 * configuration. The BIOS now uses this structure when it is built. 96 * Additional structure information can be found in adwlib.h where 97 * the structure is defined. 98 */ 99 const static ADW_EEPROM adw_3550_Default_EEPROM = { 100 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 101 0x0000, /* 01 cfg_msw */ 102 0xFFFF, /* 02 disc_enable */ 103 0xFFFF, /* 03 wdtr_able */ 104 { 0xFFFF }, /* 04 sdtr_able */ 105 0xFFFF, /* 05 start_motor */ 106 0xFFFF, /* 06 tagqng_able */ 107 0xFFFF, /* 07 bios_scan */ 108 0, /* 08 scam_tolerant */ 109 7, /* 09 adapter_scsi_id */ 110 0, /* bios_boot_delay */ 111 3, /* 10 scsi_reset_delay */ 112 0, /* bios_id_lun */ 113 0, /* 11 termination */ 114 0, /* reserved1 */ 115 0xFFE7, /* 12 bios_ctrl */ 116 { 0xFFFF }, /* 13 ultra_able */ 117 { 0 }, /* 14 reserved2 */ 118 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 119 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 120 0, /* 16 dvc_cntl */ 121 { 0 }, /* 17 bug_fix */ 122 { 0,0,0 }, /* 18-20 serial_number[3] */ 123 0, /* 21 check_sum */ 124 { /* 22-29 oem_name[16] */ 125 0,0,0,0,0,0,0,0, 126 0,0,0,0,0,0,0,0 127 }, 128 0, /* 30 dvc_err_code */ 129 0, /* 31 adw_err_code */ 130 0, /* 32 adw_err_addr */ 131 0, /* 33 saved_dvc_err_code */ 132 0, /* 34 saved_adw_err_code */ 133 0 /* 35 saved_adw_err_addr */ 134 }; 135 136 const static ADW_EEPROM adw_38C0800_Default_EEPROM = { 137 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 138 0x0000, /* 01 cfg_msw */ 139 0xFFFF, /* 02 disc_enable */ 140 0xFFFF, /* 03 wdtr_able */ 141 { 0x4444 }, /* 04 sdtr_speed1 */ 142 0xFFFF, /* 05 start_motor */ 143 0xFFFF, /* 06 tagqng_able */ 144 0xFFFF, /* 07 bios_scan */ 145 0, /* 08 scam_tolerant */ 146 7, /* 09 adapter_scsi_id */ 147 0, /* bios_boot_delay */ 148 3, /* 10 scsi_reset_delay */ 149 0, /* bios_id_lun */ 150 0, /* 11 termination_se */ 151 0, /* termination_lvd */ 152 0xFFE7, /* 12 bios_ctrl */ 153 { 0x4444 }, /* 13 sdtr_speed2 */ 154 { 0x4444 }, /* 14 sdtr_speed3 */ 155 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 156 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 157 0, /* 16 dvc_cntl */ 158 { 0x4444 }, /* 17 sdtr_speed4 */ 159 { 0,0,0 }, /* 18-20 serial_number[3] */ 160 0, /* 21 check_sum */ 161 { /* 22-29 oem_name[16] */ 162 0,0,0,0,0,0,0,0, 163 0,0,0,0,0,0,0,0 164 }, 165 0, /* 30 dvc_err_code */ 166 0, /* 31 adw_err_code */ 167 0, /* 32 adw_err_addr */ 168 0, /* 33 saved_dvc_err_code */ 169 0, /* 34 saved_adw_err_code */ 170 0, /* 35 saved_adw_err_addr */ 171 { /* 36-55 reserved1[16] */ 172 0,0,0,0,0,0,0,0,0,0, 173 0,0,0,0,0,0,0,0,0,0 174 }, 175 0, /* 56 cisptr_lsw */ 176 0, /* 57 cisprt_msw */ 177 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 178 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 179 { 0,0,0,0 } /* 60-63 reserved2[4] */ 180 }; 181 182 const static ADW_EEPROM adw_38C1600_Default_EEPROM = { 183 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 184 0x0000, /* 01 cfg_msw */ 185 0xFFFF, /* 02 disc_enable */ 186 0xFFFF, /* 03 wdtr_able */ 187 { 0x5555 }, /* 04 sdtr_speed1 */ 188 0xFFFF, /* 05 start_motor */ 189 0xFFFF, /* 06 tagqng_able */ 190 0xFFFF, /* 07 bios_scan */ 191 0, /* 08 scam_tolerant */ 192 7, /* 09 adapter_scsi_id */ 193 0, /* bios_boot_delay */ 194 3, /* 10 scsi_reset_delay */ 195 0, /* bios_id_lun */ 196 0, /* 11 termination_se */ 197 0, /* termination_lvd */ 198 0xFFE7, /* 12 bios_ctrl */ 199 { 0x5555 }, /* 13 sdtr_speed2 */ 200 { 0x5555 }, /* 14 sdtr_speed3 */ 201 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 202 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 203 0, /* 16 dvc_cntl */ 204 { 0x5555 }, /* 17 sdtr_speed4 */ 205 { 0,0,0 }, /* 18-20 serial_number[3] */ 206 0, /* 21 check_sum */ 207 { /* 22-29 oem_name[16] */ 208 0,0,0,0,0,0,0,0, 209 0,0,0,0,0,0,0,0 210 }, 211 0, /* 30 dvc_err_code */ 212 0, /* 31 adw_err_code */ 213 0, /* 32 adw_err_addr */ 214 0, /* 33 saved_dvc_err_code */ 215 0, /* 34 saved_adw_err_code */ 216 0, /* 35 saved_adw_err_addr */ 217 { /* 36-55 reserved1[16] */ 218 0,0,0,0,0,0,0,0,0,0, 219 0,0,0,0,0,0,0,0,0,0 220 }, 221 0, /* 56 cisptr_lsw */ 222 0, /* 57 cisprt_msw */ 223 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 224 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 225 { 0,0,0,0 } /* 60-63 reserved2[4] */ 226 }; 227 228 229 /* 230 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 231 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 232 * all of this is done. 233 * 234 * For a non-fatal error return a warning code. If there are no warnings 235 * then 0 is returned. 236 * 237 * Note: Chip is stopped on entry. 238 */ 239 int 240 AdwInitFromEEPROM(sc) 241 ADW_SOFTC *sc; 242 { 243 bus_space_tag_t iot = sc->sc_iot; 244 bus_space_handle_t ioh = sc->sc_ioh; 245 ADW_EEPROM eep_config; 246 u_int16_t warn_code; 247 u_int16_t sdtr_speed = 0; 248 u_int8_t tid, termination; 249 int i, j; 250 251 252 warn_code = 0; 253 254 /* 255 * Read the board's EEPROM configuration. 256 * 257 * Set default values if a bad checksum is found. 258 * 259 * XXX - Don't handle big-endian access to EEPROM yet. 260 */ 261 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 262 warn_code |= ADW_WARN_EEPROM_CHKSUM; 263 264 /* 265 * Set EEPROM default values. 266 */ 267 switch(sc->chip_type) { 268 case ADW_CHIP_ASC3550: 269 eep_config = adw_3550_Default_EEPROM; 270 break; 271 case ADW_CHIP_ASC38C0800: 272 eep_config = adw_38C0800_Default_EEPROM; 273 break; 274 case ADW_CHIP_ASC38C1600: 275 eep_config = adw_38C1600_Default_EEPROM; 276 277 // XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 278 if (sc->cfg.pci_slot_info != 0) { 279 u_int8_t lsw_msb; 280 281 lsw_msb = eep_config.cfg_lsw >> 8; 282 /* 283 * Set Function 1 EEPROM Word 0 MSB 284 * 285 * Clear the BIOS_ENABLE (bit 14) and 286 * INTAB (bit 11) EEPROM bits. 287 * 288 * Disable Bit 14 (BIOS_ENABLE) to fix 289 * SPARC Ultra 60 and old Mac system booting 290 * problem. The Expansion ROM must 291 * be disabled in Function 1 for these systems. 292 */ 293 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 294 ADW_EEPROM_INTAB) >> 8) & 0xFF); 295 /* 296 * Set the INTAB (bit 11) if the GPIO 0 input 297 * indicates the Function 1 interrupt line is 298 * wired to INTA. 299 * 300 * Set/Clear Bit 11 (INTAB) from 301 * the GPIO bit 0 input: 302 * 1 - Function 1 intr line wired to INT A. 303 * 0 - Function 1 intr line wired to INT B. 304 * 305 * Note: Adapter boards always have Function 0 306 * wired to INTA. 307 * Put all 5 GPIO bits in input mode and then 308 * read their input values. 309 */ 310 ADW_WRITE_BYTE_REGISTER(iot, ioh, 311 IOPB_GPIO_CNTL, 0); 312 if (ADW_READ_BYTE_REGISTER(iot, ioh, 313 IOPB_GPIO_DATA) & 0x01) { 314 /* 315 * Function 1 interrupt wired to INTA; 316 * Set EEPROM bit. 317 */ 318 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 319 & 0xFF; 320 } 321 eep_config.cfg_lsw &= 0x00FF; 322 eep_config.cfg_lsw |= lsw_msb << 8; 323 } 324 break; 325 } 326 327 /* 328 * Assume the 6 byte board serial number that was read 329 * from EEPROM is correct even if the EEPROM checksum 330 * failed. 331 */ 332 for (i=2, j=1; i>=0; i--, j++) { 333 eep_config.serial_number[i] = 334 AdwReadEEPWord(iot, ioh, ADW_EEP_DVC_CFG_END - j); 335 } 336 337 AdwSetEEPROMConfig(iot, ioh, &eep_config); 338 } 339 /* 340 * Set sc and sc->cfg variables from the EEPROM configuration 341 * that was read. 342 * 343 * This is the mapping of EEPROM fields to Adw Library fields. 344 */ 345 sc->wdtr_able = eep_config.wdtr_able; 346 if (sc->chip_type == ADW_CHIP_ASC3550) { 347 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 348 sc->ultra_able = eep_config.sdtr2.ultra_able; 349 } else { 350 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 351 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 352 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 353 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 354 } 355 sc->ppr_able = 0; 356 sc->tagqng_able = eep_config.tagqng_able; 357 sc->cfg.disc_enable = eep_config.disc_enable; 358 sc->max_host_qng = eep_config.max_host_qng; 359 sc->max_dvc_qng = eep_config.max_dvc_qng; 360 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 361 sc->start_motor = eep_config.start_motor; 362 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 363 sc->bios_ctrl = eep_config.bios_ctrl; 364 sc->no_scam = eep_config.scam_tolerant; 365 sc->cfg.serial1 = eep_config.serial_number[0]; 366 sc->cfg.serial2 = eep_config.serial_number[1]; 367 sc->cfg.serial3 = eep_config.serial_number[2]; 368 369 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 370 sc->chip_type == ADW_CHIP_ASC38C1600) { 371 sc->sdtr_able = 0; 372 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 373 if (tid == 0) { 374 sdtr_speed = sc->sdtr_speed1; 375 } else if (tid == 4) { 376 sdtr_speed = sc->sdtr_speed2; 377 } else if (tid == 8) { 378 sdtr_speed = sc->sdtr_speed3; 379 } else if (tid == 12) { 380 sdtr_speed = sc->sdtr_speed4; 381 } 382 if (sdtr_speed & ADW_MAX_TID) { 383 sc->sdtr_able |= (1 << tid); 384 } 385 sdtr_speed >>= 4; 386 } 387 } 388 389 /* 390 * Set the host maximum queuing (max. 253, min. 16) and the per device 391 * maximum queuing (max. 63, min. 4). 392 */ 393 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 394 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 395 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 396 { 397 /* If the value is zero, assume it is uninitialized. */ 398 if (eep_config.max_host_qng == 0) { 399 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 400 } else { 401 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 402 } 403 } 404 405 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 406 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 407 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 408 /* If the value is zero, assume it is uninitialized. */ 409 if (eep_config.max_dvc_qng == 0) { 410 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 411 } else { 412 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 413 } 414 } 415 416 /* 417 * If 'max_dvc_qng' is greater than 'max_host_qng', then 418 * set 'max_dvc_qng' to 'max_host_qng'. 419 */ 420 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 421 eep_config.max_dvc_qng = eep_config.max_host_qng; 422 } 423 424 /* 425 * Set ADW_SOFTC 'max_host_qng' and 'max_dvc_qng' 426 * values based on possibly adjusted EEPROM values. 427 */ 428 sc->max_host_qng = eep_config.max_host_qng; 429 sc->max_dvc_qng = eep_config.max_dvc_qng; 430 431 432 /* 433 * If the EEPROM 'termination' field is set to automatic (0), then set 434 * the ADW_SOFTC.cfg 'termination' field to automatic also. 435 * 436 * If the termination is specified with a non-zero 'termination' 437 * value check that a legal value is set and set the ADW_SOFTC.cfg 438 * 'termination' field appropriately. 439 */ 440 441 switch(sc->chip_type) { 442 case ADW_CHIP_ASC3550: 443 sc->cfg.termination = 0; /* auto termination */ 444 switch(eep_config.termination_se) { 445 case 3: 446 /* Enable manual control with low on / high on. */ 447 sc->cfg.termination |= ADW_TERM_CTL_L; 448 case 2: 449 /* Enable manual control with low off / high on. */ 450 sc->cfg.termination |= ADW_TERM_CTL_H; 451 case 1: 452 /* Enable manual control with low off / high off. */ 453 sc->cfg.termination |= ADW_TERM_CTL_SEL; 454 case 0: 455 break; 456 default: 457 warn_code |= ADW_WARN_EEPROM_TERMINATION; 458 } 459 break; 460 461 case ADW_CHIP_ASC38C0800: 462 case ADW_CHIP_ASC38C1600: 463 switch(eep_config.termination_se) { 464 case 0: 465 /* auto termination for SE */ 466 termination = 0; 467 break; 468 case 1: 469 /* Enable manual control with low off / high off. */ 470 termination = 0; 471 break; 472 case 2: 473 /* Enable manual control with low off / high on. */ 474 termination = ADW_TERM_SE_HI; 475 break; 476 case 3: 477 /* Enable manual control with low on / high on. */ 478 termination = ADW_TERM_SE; 479 break; 480 default: 481 /* 482 * The EEPROM 'termination_se' field contains a 483 * bad value. Use automatic termination instead. 484 */ 485 termination = 0; 486 warn_code |= ADW_WARN_EEPROM_TERMINATION; 487 } 488 489 switch(eep_config.termination_lvd) { 490 case 0: 491 /* auto termination for LVD */ 492 sc->cfg.termination = termination; 493 break; 494 case 1: 495 /* Enable manual control with low off / high off. */ 496 sc->cfg.termination = termination; 497 break; 498 case 2: 499 /* Enable manual control with low off / high on. */ 500 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 501 break; 502 case 3: 503 /* Enable manual control with low on / high on. */ 504 sc->cfg.termination = termination | ADW_TERM_LVD; 505 break; 506 default: 507 /* 508 * The EEPROM 'termination_lvd' field contains a 509 * bad value. Use automatic termination instead. 510 */ 511 sc->cfg.termination = termination; 512 warn_code |= ADW_WARN_EEPROM_TERMINATION; 513 } 514 break; 515 } 516 517 return warn_code; 518 } 519 520 521 /* 522 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 523 * 524 * On failure return the error code. 525 */ 526 int 527 AdwInitDriver(sc) 528 ADW_SOFTC *sc; 529 { 530 bus_space_tag_t iot = sc->sc_iot; 531 bus_space_handle_t ioh = sc->sc_ioh; 532 u_int16_t error_code; 533 int word; 534 int i; 535 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 536 0x40-0x8F. */ 537 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; 538 u_int8_t max_cmd[ADW_MAX_TID + 1]; 539 u_int8_t tid; 540 541 542 error_code = 0; 543 544 /* 545 * Save the RISC memory BIOS region before writing the microcode. 546 * The BIOS may already be loaded and using its RISC LRAM region 547 * so its region must be saved and restored. 548 * 549 * Note: This code makes the assumption, which is currently true, 550 * that a chip reset does not clear RISC LRAM. 551 */ 552 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 553 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 554 } 555 556 /* 557 * Save current per TID negotiated values. 558 */ 559 switch (sc->chip_type) { 560 case ADW_CHIP_ASC3550: 561 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 562 563 u_int16_t bios_version, major, minor; 564 565 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 566 ADW_MC_BIOSMEM) / 2]; 567 major = (bios_version >> 12) & 0xF; 568 minor = (bios_version >> 8) & 0xF; 569 if (major < 3 || (major == 3 && minor == 1)) { 570 /* 571 * BIOS 3.1 and earlier location of 572 * 'wdtr_able' variable. 573 */ 574 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 575 } else { 576 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 577 wdtr_able); 578 } 579 } 580 break; 581 582 case ADW_CHIP_ASC38C1600: 583 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 584 /* FALLTHROUGH */ 585 case ADW_CHIP_ASC38C0800: 586 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 587 break; 588 } 589 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 590 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 591 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 592 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 593 max_cmd[tid]); 594 } 595 596 /* 597 * Perform a RAM Built-In Self Test 598 */ 599 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 600 return error_code; 601 } 602 603 /* 604 * Load the Microcode 605 */ 606 ; 607 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 608 return error_code; 609 } 610 611 /* 612 * Read microcode version and date. 613 */ 614 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 615 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 616 617 /* 618 * If the PCI Configuration Command Register "Parity Error Response 619 * Control" Bit was clear (0), then set the microcode variable 620 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 621 * to ignore DMA parity errors. 622 */ 623 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 624 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 625 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 626 word | CONTROL_FLAG_IGNORE_PERR); 627 } 628 629 switch (sc->chip_type) { 630 case ADW_CHIP_ASC3550: 631 /* 632 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 633 * FIFO threshold of 128 bytes. 634 * This register is only accessible to the host. 635 */ 636 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 637 START_CTL_EMFU | READ_CMD_MRM); 638 break; 639 640 case ADW_CHIP_ASC38C0800: 641 /* 642 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 643 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 644 * cable detection and then we are able to read C_DET[3:0]. 645 * 646 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 647 * Microcode Default Value' section below. 648 */ 649 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 650 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 651 | ADW_DIS_TERM_DRV); 652 653 /* 654 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 655 * START_CTL_TH [3:2] bits for the default FIFO threshold. 656 * 657 * Note: ASC-38C0800 FIFO threshold has been changed to 658 * 256 bytes. 659 * 660 * For DMA Errata #4 set the BC_THRESH_ENB bit. 661 */ 662 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 663 BC_THRESH_ENB | FIFO_THRESH_80B 664 | START_CTL_TH | READ_CMD_MRM); 665 break; 666 667 case ADW_CHIP_ASC38C1600: 668 /* 669 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 670 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 671 * cable detection and then we are able to read C_DET[3:0]. 672 * 673 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 674 * Microcode Default Value' section below. 675 */ 676 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 677 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 678 | ADW_DIS_TERM_DRV); 679 680 /* 681 * If the BIOS control flag AIPP (Asynchronous Information 682 * Phase Protection) disable bit is not set, then set the 683 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 684 * enable AIPP checking and encoding. 685 */ 686 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 687 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 688 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 689 word | CONTROL_FLAG_ENABLE_AIPP); 690 } 691 692 /* 693 * For ASC-38C1600 use DMA_CFG0 default values: 694 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 695 */ 696 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 697 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 698 break; 699 } 700 701 /* 702 * Microcode operating variables for WDTR, SDTR, and command tag 703 * queuing will be set in AdwInquiryHandling() based on what a 704 * device reports it is capable of in Inquiry byte 7. 705 * 706 * If SCSI Bus Resets have been disabled, then directly set 707 * SDTR and WDTR from the EEPROM configuration. This will allow 708 * the BIOS and warm boot to work without a SCSI bus hang on 709 * the Inquiry caused by host and target mismatched DTR values. 710 * Without the SCSI Bus Reset, before an Inquiry a device can't 711 * be assumed to be in Asynchronous, Narrow mode. 712 */ 713 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 714 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 715 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 716 } 717 718 /* 719 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 720 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 721 * bitmask. These values determine the maximum SDTR speed negotiated 722 * with a device. 723 * 724 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 725 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 726 * without determining here whether the device supports SDTR. 727 */ 728 switch (sc->chip_type) { 729 case ADW_CHIP_ASC3550: 730 word = 0; 731 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 732 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 733 /* Set Ultra speed for TID 'tid'. */ 734 word |= (0x3 << (4 * (tid % 4))); 735 } else { 736 /* Set Fast speed for TID 'tid'. */ 737 word |= (0x2 << (4 * (tid % 4))); 738 } 739 /* Check if done with sdtr_speed1. */ 740 if (tid == 3) { 741 ADW_WRITE_WORD_LRAM(iot, ioh, 742 ADW_MC_SDTR_SPEED1, word); 743 word = 0; 744 /* Check if done with sdtr_speed2. */ 745 } else if (tid == 7) { 746 ADW_WRITE_WORD_LRAM(iot, ioh, 747 ADW_MC_SDTR_SPEED2, word); 748 word = 0; 749 /* Check if done with sdtr_speed3. */ 750 } else if (tid == 11) { 751 ADW_WRITE_WORD_LRAM(iot, ioh, 752 ADW_MC_SDTR_SPEED3, word); 753 word = 0; 754 /* Check if done with sdtr_speed4. */ 755 } else if (tid == 15) { 756 ADW_WRITE_WORD_LRAM(iot, ioh, 757 ADW_MC_SDTR_SPEED4, word); 758 /* End of loop. */ 759 } 760 } 761 762 /* 763 * Set microcode operating variable for the 764 * disconnect per TID bitmask. 765 */ 766 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 767 sc->cfg.disc_enable); 768 break; 769 770 case ADW_CHIP_ASC38C0800: 771 /* FALLTHROUGH */ 772 case ADW_CHIP_ASC38C1600: 773 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 774 sc->cfg.disc_enable); 775 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 776 sc->sdtr_speed1); 777 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 778 sc->sdtr_speed2); 779 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 780 sc->sdtr_speed3); 781 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 782 sc->sdtr_speed4); 783 break; 784 } 785 786 787 /* 788 * Set SCSI_CFG0 Microcode Default Value. 789 * 790 * The microcode will set the SCSI_CFG0 register using this value 791 * after it is started below. 792 */ 793 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 794 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 795 ADW_OUR_ID_EN | sc->chip_scsi_id); 796 797 798 switch(sc->chip_type) { 799 case ADW_CHIP_ASC3550: 800 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 801 break; 802 803 case ADW_CHIP_ASC38C0800: 804 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 805 break; 806 807 case ADW_CHIP_ASC38C1600: 808 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 809 break; 810 } 811 if(error_code) { 812 return error_code; 813 } 814 815 /* 816 * Set SEL_MASK Microcode Default Value 817 * 818 * The microcode will set the SEL_MASK register using this value 819 * after it is started below. 820 */ 821 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 822 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 823 824 /* 825 * Create and Initialize Host->RISC Carrier lists 826 */ 827 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 828 sc->sc_control->carriers); 829 830 /* 831 * Set-up the Host->RISC Initiator Command Queue (ICQ). 832 */ 833 834 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 835 return ADW_IERR_NO_CARRIER; 836 } 837 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 838 ADW_GET_CARRP(sc->icq_sp->next_ba)); 839 840 /* 841 * The first command issued will be placed in the stopper carrier. 842 */ 843 sc->icq_sp->next_ba = ADW_CQ_STOPPER; 844 845 /* 846 * Set RISC ICQ physical address start value. 847 */ 848 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); 849 850 /* 851 * Initialize the COMMA register to the same value otherwise 852 * the RISC will prematurely detect a command is available. 853 */ 854 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 855 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 856 sc->icq_sp->carr_ba); 857 } 858 859 /* 860 * Set-up the RISC->Host Initiator Response Queue (IRQ). 861 */ 862 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 863 return ADW_IERR_NO_CARRIER; 864 } 865 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 866 ADW_GET_CARRP(sc->irq_sp->next_ba)); 867 868 /* 869 * The first command completed by the RISC will be placed in 870 * the stopper. 871 * 872 * Note: Set 'next_ba' to ADW_CQ_STOPPER. When the request is 873 * completed the RISC will set the ADW_RQ_DONE bit. 874 */ 875 sc->irq_sp->next_ba = ADW_CQ_STOPPER; 876 877 /* 878 * Set RISC IRQ physical address start value. 879 */ 880 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); 881 sc->carr_pending_cnt = 0; 882 883 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 884 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 885 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 886 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 887 888 /* finally, finally, gentlemen, start your engine */ 889 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 890 891 /* 892 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 893 * Resets should be performed. The RISC has to be running 894 * to issue a SCSI Bus Reset. 895 */ 896 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 897 { 898 /* 899 * If the BIOS Signature is present in memory, restore the 900 * BIOS Handshake Configuration Table and do not perform 901 * a SCSI Bus Reset. 902 */ 903 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 904 0x55AA) { 905 /* 906 * Restore per TID negotiated values. 907 */ 908 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 909 wdtr_able); 910 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 911 sdtr_able); 912 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 913 tagqng_able); 914 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 915 ADW_WRITE_BYTE_LRAM(iot, ioh, 916 ADW_MC_NUMBER_OF_MAX_CMD + tid, 917 max_cmd[tid]); 918 } 919 } else { 920 if (AdwResetCCB(sc) != ADW_TRUE) { 921 error_code = ADW_WARN_BUSRESET_ERROR; 922 } 923 } 924 } 925 926 return error_code; 927 } 928 929 930 int 931 AdwRamSelfTest(iot, ioh, chip_type) 932 bus_space_tag_t iot; 933 bus_space_handle_t ioh; 934 u_int8_t chip_type; 935 { 936 int i; 937 u_int8_t byte; 938 939 940 if ((chip_type == ADW_CHIP_ASC38C0800) || 941 (chip_type == ADW_CHIP_ASC38C1600)) { 942 /* 943 * RAM BIST (RAM Built-In Self Test) 944 * 945 * Address : I/O base + offset 0x38h register (byte). 946 * Function: Bit 7-6(RW) : RAM mode 947 * Normal Mode : 0x00 948 * Pre-test Mode : 0x40 949 * RAM Test Mode : 0x80 950 * Bit 5 : unused 951 * Bit 4(RO) : Done bit 952 * Bit 3-0(RO) : Status 953 * Host Error : 0x08 954 * Int_RAM Error : 0x04 955 * RISC Error : 0x02 956 * SCSI Error : 0x01 957 * No Error : 0x00 958 * 959 * Note: RAM BIST code should be put right here, before loading 960 * the microcode and after saving the RISC memory BIOS region. 961 */ 962 963 /* 964 * LRAM Pre-test 965 * 966 * Write PRE_TEST_MODE (0x40) to register and wait for 967 * 10 milliseconds. 968 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 969 * return an error. Reset to NORMAL_MODE (0x00) and do again. 970 * If cannot reset to NORMAL_MODE, return an error too. 971 */ 972 for (i = 0; i < 2; i++) { 973 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 974 PRE_TEST_MODE); 975 /* Wait for 10ms before reading back. */ 976 AdwSleepMilliSecond(10); 977 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 978 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 979 PRE_TEST_VALUE) { 980 return ADW_IERR_BIST_PRE_TEST; 981 } 982 983 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 984 NORMAL_MODE); 985 /* Wait for 10ms before reading back. */ 986 AdwSleepMilliSecond(10); 987 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 988 != NORMAL_VALUE) { 989 return ADW_IERR_BIST_PRE_TEST; 990 } 991 } 992 993 /* 994 * LRAM Test - It takes about 1.5 ms to run through the test. 995 * 996 * Write RAM_TEST_MODE (0x80) to register and wait for 997 * 10 milliseconds. 998 * If Done bit not set or Status not 0, save register byte, 999 * set the err_code, and return an error. 1000 */ 1001 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1002 /* Wait for 10ms before checking status. */ 1003 AdwSleepMilliSecond(10); 1004 1005 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1006 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1007 /* Get here if Done bit not set or Status not 0. */ 1008 return ADW_IERR_BIST_RAM_TEST; 1009 } 1010 1011 /* We need to reset back to normal mode after LRAM test passes*/ 1012 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1013 } 1014 1015 return 0; 1016 } 1017 1018 1019 int 1020 AdwLoadMCode(iot, ioh, bios_mem, chip_type) 1021 bus_space_tag_t iot; 1022 bus_space_handle_t ioh; 1023 u_int16_t *bios_mem; 1024 u_int8_t chip_type; 1025 { 1026 u_int8_t *mcode_data = NULL; 1027 u_int32_t mcode_chksum = 0; 1028 u_int16_t mcode_size = 0; 1029 u_int32_t sum; 1030 u_int16_t code_sum; 1031 int begin_addr; 1032 int end_addr; 1033 int word; 1034 int adw_memsize = 0; 1035 int adw_mcode_expanded_size; 1036 int i, j; 1037 1038 1039 switch(chip_type) { 1040 case ADW_CHIP_ASC3550: 1041 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1042 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1043 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1044 adw_memsize = ADW_3550_MEMSIZE; 1045 break; 1046 1047 case ADW_CHIP_ASC38C0800: 1048 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1049 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1050 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1051 adw_memsize = ADW_38C0800_MEMSIZE; 1052 break; 1053 1054 case ADW_CHIP_ASC38C1600: 1055 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1056 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1057 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1058 adw_memsize = ADW_38C1600_MEMSIZE; 1059 break; 1060 } 1061 1062 /* 1063 * Write the microcode image to RISC memory starting at address 0. 1064 */ 1065 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1066 1067 /* Assume the following compressed format of the microcode buffer: 1068 * 1069 * 254 word (508 byte) table indexed by byte code followed 1070 * by the following byte codes: 1071 * 1072 * 1-Byte Code: 1073 * 00: Emit word 0 in table. 1074 * 01: Emit word 1 in table. 1075 * . 1076 * FD: Emit word 253 in table. 1077 * 1078 * Multi-Byte Code: 1079 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1080 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1081 */ 1082 word = 0; 1083 for (i = 253 * 2; i < mcode_size; i++) { 1084 if (mcode_data[i] == 0xff) { 1085 for (j = 0; j < mcode_data[i + 1]; j++) { 1086 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1087 (((u_int16_t)mcode_data[i + 3] << 8) | 1088 mcode_data[i + 2])); 1089 word++; 1090 } 1091 i += 3; 1092 } else if (mcode_data[i] == 0xfe) { 1093 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1094 (((u_int16_t)mcode_data[i + 2] << 8) | 1095 mcode_data[i + 1])); 1096 i += 2; 1097 word++; 1098 } else { 1099 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1100 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1101 mcode_data[mcode_data[i] * 2])); 1102 word++; 1103 } 1104 } 1105 1106 /* 1107 * Set 'word' for later use to clear the rest of memory and save 1108 * the expanded mcode size. 1109 */ 1110 word *= 2; 1111 adw_mcode_expanded_size = word; 1112 1113 /* 1114 * Clear the rest of the Internal RAM. 1115 */ 1116 for (; word < adw_memsize; word += 2) { 1117 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1118 } 1119 1120 /* 1121 * Verify the microcode checksum. 1122 */ 1123 sum = 0; 1124 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1125 1126 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1127 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1128 } 1129 1130 if (sum != mcode_chksum) { 1131 return ADW_IERR_MCODE_CHKSUM; 1132 } 1133 1134 /* 1135 * Restore the RISC memory BIOS region. 1136 */ 1137 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1138 if(chip_type == ADW_CHIP_ASC3550) { 1139 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1140 bios_mem[i]); 1141 } else { 1142 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1143 bios_mem[i]); 1144 } 1145 } 1146 1147 /* 1148 * Calculate and write the microcode code checksum to the microcode 1149 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1150 */ 1151 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1152 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1153 code_sum = 0; 1154 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1155 for (word = begin_addr; word < end_addr; word += 2) { 1156 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1157 } 1158 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1159 1160 /* 1161 * Set the chip type. 1162 */ 1163 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1164 1165 return 0; 1166 } 1167 1168 1169 int 1170 AdwASC3550Cabling(iot, ioh, cfg) 1171 bus_space_tag_t iot; 1172 bus_space_handle_t ioh; 1173 ADW_DVC_CFG *cfg; 1174 { 1175 u_int16_t scsi_cfg1; 1176 1177 1178 /* 1179 * Determine SCSI_CFG1 Microcode Default Value. 1180 * 1181 * The microcode will set the SCSI_CFG1 register using this value 1182 * after it is started below. 1183 */ 1184 1185 /* Read current SCSI_CFG1 Register value. */ 1186 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1187 1188 /* 1189 * If all three connectors are in use in ASC3550, return an error. 1190 */ 1191 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1192 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1193 return ADW_IERR_ILLEGAL_CONNECTION; 1194 } 1195 1196 /* 1197 * If the cable is reversed all of the SCSI_CTRL register signals 1198 * will be set. Check for and return an error if this condition is 1199 * found. 1200 */ 1201 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1202 return ADW_IERR_REVERSED_CABLE; 1203 } 1204 1205 /* 1206 * If this is a differential board and a single-ended device 1207 * is attached to one of the connectors, return an error. 1208 */ 1209 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1210 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1211 return ADW_IERR_SINGLE_END_DEVICE; 1212 } 1213 1214 /* 1215 * If automatic termination control is enabled, then set the 1216 * termination value based on a table listed in a_condor.h. 1217 * 1218 * If manual termination was specified with an EEPROM setting 1219 * then 'termination' was set-up in AdwInitFromEEPROM() and 1220 * is ready to be 'ored' into SCSI_CFG1. 1221 */ 1222 if (cfg->termination == 0) { 1223 /* 1224 * The software always controls termination by setting 1225 * TERM_CTL_SEL. 1226 * If TERM_CTL_SEL were set to 0, the hardware would set 1227 * termination. 1228 */ 1229 cfg->termination |= ADW_TERM_CTL_SEL; 1230 1231 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1232 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1233 case 0x3: case 0x7: case 0xB: 1234 case 0xD: case 0xE: case 0xF: 1235 cfg->termination |= 1236 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1237 break; 1238 1239 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1240 case 0x1: case 0x5: case 0x9: 1241 case 0xA: case 0xC: 1242 cfg->termination |= ADW_TERM_CTL_H; 1243 break; 1244 1245 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1246 case 0x2: case 0x6: 1247 break; 1248 } 1249 } 1250 1251 /* 1252 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1253 */ 1254 scsi_cfg1 &= ~ADW_TERM_CTL; 1255 1256 /* 1257 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1258 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1259 * referenced, because the hardware internally inverts 1260 * the Termination High and Low bits if TERM_POL is set. 1261 */ 1262 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1263 1264 /* 1265 * Set SCSI_CFG1 Microcode Default Value 1266 * 1267 * Set filter value and possibly modified termination control 1268 * bits in the Microcode SCSI_CFG1 Register Value. 1269 * 1270 * The microcode will set the SCSI_CFG1 register using this value 1271 * after it is started below. 1272 */ 1273 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1274 ADW_FLTR_DISABLE | scsi_cfg1); 1275 1276 /* 1277 * Set MEM_CFG Microcode Default Value 1278 * 1279 * The microcode will set the MEM_CFG register using this value 1280 * after it is started below. 1281 * 1282 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1283 * are defined. 1284 * 1285 * ASC-3550 has 8KB internal memory. 1286 */ 1287 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1288 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1289 1290 return 0; 1291 } 1292 1293 1294 int 1295 AdwASC38C0800Cabling(iot, ioh, cfg) 1296 bus_space_tag_t iot; 1297 bus_space_handle_t ioh; 1298 ADW_DVC_CFG *cfg; 1299 { 1300 u_int16_t scsi_cfg1; 1301 1302 1303 /* 1304 * Determine SCSI_CFG1 Microcode Default Value. 1305 * 1306 * The microcode will set the SCSI_CFG1 register using this value 1307 * after it is started below. 1308 */ 1309 1310 /* Read current SCSI_CFG1 Register value. */ 1311 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1312 1313 /* 1314 * If the cable is reversed all of the SCSI_CTRL register signals 1315 * will be set. Check for and return an error if this condition is 1316 * found. 1317 */ 1318 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1319 return ADW_IERR_REVERSED_CABLE; 1320 } 1321 1322 /* 1323 * All kind of combinations of devices attached to one of four 1324 * connectors are acceptable except HVD device attached. 1325 * For example, LVD device can be attached to SE connector while 1326 * SE device attached to LVD connector. 1327 * If LVD device attached to SE connector, it only runs up to 1328 * Ultra speed. 1329 * 1330 * If an HVD device is attached to one of LVD connectors, return 1331 * an error. 1332 * However, there is no way to detect HVD device attached to 1333 * SE connectors. 1334 */ 1335 if (scsi_cfg1 & ADW_HVD) { 1336 return ADW_IERR_HVD_DEVICE; 1337 } 1338 1339 /* 1340 * If either SE or LVD automatic termination control is enabled, then 1341 * set the termination value based on a table listed in a_condor.h. 1342 * 1343 * If manual termination was specified with an EEPROM setting then 1344 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1345 * to be 'ored' into SCSI_CFG1. 1346 */ 1347 if ((cfg->termination & ADW_TERM_SE) == 0) { 1348 /* SE automatic termination control is enabled. */ 1349 switch(scsi_cfg1 & ADW_C_DET_SE) { 1350 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1351 case 0x1: case 0x2: case 0x3: 1352 cfg->termination |= ADW_TERM_SE; 1353 break; 1354 1355 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1356 case 0x0: 1357 cfg->termination |= ADW_TERM_SE_HI; 1358 break; 1359 } 1360 } 1361 1362 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1363 /* LVD automatic termination control is enabled. */ 1364 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1365 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1366 case 0x4: case 0x8: case 0xC: 1367 cfg->termination |= ADW_TERM_LVD; 1368 break; 1369 1370 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1371 case 0x0: 1372 break; 1373 } 1374 } 1375 1376 /* 1377 * Clear any set TERM_SE and TERM_LVD bits. 1378 */ 1379 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1380 1381 /* 1382 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1383 */ 1384 scsi_cfg1 |= (~cfg->termination & 0xF0); 1385 1386 /* 1387 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1388 * HVD/LVD/SE bits and set possibly modified termination control bits 1389 * in the Microcode SCSI_CFG1 Register Value. 1390 */ 1391 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1392 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1393 1394 /* 1395 * Set SCSI_CFG1 Microcode Default Value 1396 * 1397 * Set possibly modified termination control and reset DIS_TERM_DRV 1398 * bits in the Microcode SCSI_CFG1 Register Value. 1399 * 1400 * The microcode will set the SCSI_CFG1 register using this value 1401 * after it is started below. 1402 */ 1403 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1404 1405 /* 1406 * Set MEM_CFG Microcode Default Value 1407 * 1408 * The microcode will set the MEM_CFG register using this value 1409 * after it is started below. 1410 * 1411 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1412 * are defined. 1413 * 1414 * ASC-38C0800 has 16KB internal memory. 1415 */ 1416 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1417 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1418 1419 return 0; 1420 } 1421 1422 1423 int 1424 AdwASC38C1600Cabling(iot, ioh, cfg) 1425 bus_space_tag_t iot; 1426 bus_space_handle_t ioh; 1427 ADW_DVC_CFG *cfg; 1428 { 1429 u_int16_t scsi_cfg1; 1430 1431 1432 /* 1433 * Determine SCSI_CFG1 Microcode Default Value. 1434 * 1435 * The microcode will set the SCSI_CFG1 register using this value 1436 * after it is started below. 1437 * Each ASC-38C1600 function has only two cable detect bits. 1438 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1439 */ 1440 1441 /* Read current SCSI_CFG1 Register value. */ 1442 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1443 1444 /* 1445 * If the cable is reversed all of the SCSI_CTRL register signals 1446 * will be set. Check for and return an error if this condition is 1447 * found. 1448 */ 1449 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1450 return ADW_IERR_REVERSED_CABLE; 1451 } 1452 1453 /* 1454 * Each ASC-38C1600 function has two connectors. Only an HVD device 1455 * cannot be connected to either connector. An LVD device or SE device 1456 * may be connected to either connector. If an SE device is connected, 1457 * then at most Ultra speed (20 MHz) can be used on both connectors. 1458 * 1459 * If an HVD device is attached, return an error. 1460 */ 1461 if (scsi_cfg1 & ADW_HVD) { 1462 return ADW_IERR_HVD_DEVICE; 1463 } 1464 1465 /* 1466 * Each function in the ASC-38C1600 uses only the SE cable detect and 1467 * termination because there are two connectors for each function. 1468 * Each function may use either LVD or SE mode. 1469 * Corresponding the SE automatic termination control EEPROM bits are 1470 * used for each function. 1471 * Each function has its own EEPROM. If SE automatic control is enabled 1472 * for the function, then set the termination value based on a table 1473 * listed in adwlib.h. 1474 * 1475 * If manual termination is specified in the EEPROM for the function, 1476 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1477 * ready to be 'ored' into SCSI_CFG1. 1478 */ 1479 if ((cfg->termination & ADW_TERM_SE) == 0) { 1480 /* SE automatic termination control is enabled. */ 1481 switch(scsi_cfg1 & ADW_C_DET_SE) { 1482 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1483 case 0x1: case 0x2: case 0x3: 1484 cfg->termination |= ADW_TERM_SE; 1485 break; 1486 1487 case 0x0: 1488 /* !!!!TODO!!!! */ 1489 // if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1490 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1491 // } 1492 // else 1493 // { 1494 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1495 cfg->termination |= ADW_TERM_SE_HI; 1496 // } 1497 break; 1498 } 1499 } 1500 1501 /* 1502 * Clear any set TERM_SE bits. 1503 */ 1504 scsi_cfg1 &= ~ADW_TERM_SE; 1505 1506 /* 1507 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1508 */ 1509 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1510 1511 /* 1512 * Clear Big Endian and Terminator Polarity bits and set possibly 1513 * modified termination control bits in the Microcode SCSI_CFG1 1514 * Register Value. 1515 */ 1516 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1517 1518 /* 1519 * Set SCSI_CFG1 Microcode Default Value 1520 * 1521 * Set possibly modified termination control bits in the Microcode 1522 * SCSI_CFG1 Register Value. 1523 * 1524 * The microcode will set the SCSI_CFG1 register using this value 1525 * after it is started below. 1526 */ 1527 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1528 1529 /* 1530 * Set MEM_CFG Microcode Default Value 1531 * 1532 * The microcode will set the MEM_CFG register using this value 1533 * after it is started below. 1534 * 1535 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1536 * are defined. 1537 * 1538 * ASC-38C1600 has 32KB internal memory. 1539 */ 1540 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1541 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1542 1543 return 0; 1544 } 1545 1546 1547 /* 1548 * Read EEPROM configuration into the specified buffer. 1549 * 1550 * Return a checksum based on the EEPROM configuration read. 1551 */ 1552 u_int16_t 1553 AdwGetEEPROMConfig(iot, ioh, cfg_buf) 1554 bus_space_tag_t iot; 1555 bus_space_handle_t ioh; 1556 ADW_EEPROM *cfg_buf; 1557 { 1558 u_int16_t wval, chksum; 1559 u_int16_t *wbuf; 1560 int eep_addr; 1561 1562 1563 wbuf = (u_int16_t *) cfg_buf; 1564 chksum = 0; 1565 1566 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN; 1567 eep_addr < ADW_EEP_DVC_CFG_END; 1568 eep_addr++, wbuf++) { 1569 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1570 chksum += wval; 1571 *wbuf = wval; 1572 } 1573 1574 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1575 wbuf++; 1576 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN; 1577 eep_addr < ADW_EEP_MAX_WORD_ADDR; 1578 eep_addr++, wbuf++) { 1579 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1580 } 1581 1582 return chksum; 1583 } 1584 1585 1586 /* 1587 * Read the EEPROM from specified location 1588 */ 1589 u_int16_t 1590 AdwReadEEPWord(iot, ioh, eep_word_addr) 1591 bus_space_tag_t iot; 1592 bus_space_handle_t ioh; 1593 int eep_word_addr; 1594 { 1595 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1596 ADW_EEP_CMD_READ | eep_word_addr); 1597 AdwWaitEEPCmd(iot, ioh); 1598 1599 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1600 } 1601 1602 1603 /* 1604 * Wait for EEPROM command to complete 1605 */ 1606 void 1607 AdwWaitEEPCmd(iot, ioh) 1608 bus_space_tag_t iot; 1609 bus_space_handle_t ioh; 1610 { 1611 int eep_delay_ms; 1612 1613 1614 for (eep_delay_ms = 0; eep_delay_ms < ADW_EEP_DELAY_MS; eep_delay_ms++){ 1615 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1616 ADW_EEP_CMD_DONE) { 1617 break; 1618 } 1619 AdwSleepMilliSecond(1); 1620 } 1621 1622 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1623 } 1624 1625 1626 /* 1627 * Write the EEPROM from 'cfg_buf'. 1628 */ 1629 void 1630 AdwSetEEPROMConfig(iot, ioh, cfg_buf) 1631 bus_space_tag_t iot; 1632 bus_space_handle_t ioh; 1633 ADW_EEPROM *cfg_buf; 1634 { 1635 u_int16_t *wbuf; 1636 u_int16_t addr, chksum; 1637 1638 1639 wbuf = (u_int16_t *) cfg_buf; 1640 chksum = 0; 1641 1642 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ADW_EEP_CMD_WRITE_ABLE); 1643 AdwWaitEEPCmd(iot, ioh); 1644 1645 /* 1646 * Write EEPROM from word 0 to word 20 1647 */ 1648 for (addr = ADW_EEP_DVC_CFG_BEGIN; 1649 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) { 1650 chksum += *wbuf; 1651 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1652 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1653 ADW_EEP_CMD_WRITE | addr); 1654 AdwWaitEEPCmd(iot, ioh); 1655 AdwSleepMilliSecond(ADW_EEP_DELAY_MS); 1656 } 1657 1658 /* 1659 * Write EEPROM checksum at word 21 1660 */ 1661 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1662 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1663 ADW_EEP_CMD_WRITE | addr); 1664 AdwWaitEEPCmd(iot, ioh); 1665 wbuf++; /* skip over check_sum */ 1666 1667 /* 1668 * Write EEPROM OEM name at words 22 to 29 1669 */ 1670 for (addr = ADW_EEP_DVC_CTL_BEGIN; 1671 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1672 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1673 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1674 ADW_EEP_CMD_WRITE | addr); 1675 AdwWaitEEPCmd(iot, ioh); 1676 } 1677 1678 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1679 ADW_EEP_CMD_WRITE_DISABLE); 1680 AdwWaitEEPCmd(iot, ioh); 1681 1682 return; 1683 } 1684 1685 1686 /* 1687 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1688 * 1689 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1690 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1691 * RISC to notify it a new command is ready to be executed. 1692 * 1693 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1694 * set to SCSI_MAX_RETRY. 1695 * 1696 * Return: 1697 * ADW_SUCCESS(1) - The request was successfully queued. 1698 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1699 * request completes. 1700 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1701 * host IC error. 1702 */ 1703 int 1704 AdwExeScsiQueue(sc, scsiq) 1705 ADW_SOFTC *sc; 1706 ADW_SCSI_REQ_Q *scsiq; 1707 { 1708 bus_space_tag_t iot = sc->sc_iot; 1709 bus_space_handle_t ioh = sc->sc_ioh; 1710 ADW_CCB *ccb; 1711 long req_size; 1712 u_int32_t req_paddr; 1713 ADW_CARRIER *new_carrp; 1714 1715 /* 1716 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1717 */ 1718 if (scsiq->target_id > ADW_MAX_TID) { 1719 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1720 scsiq->done_status = QD_WITH_ERROR; 1721 return ADW_ERROR; 1722 } 1723 1724 /* 1725 * Beginning of CRITICAL SECTION: ASSUME splbio() in effect 1726 */ 1727 1728 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1729 1730 /* 1731 * Allocate a carrier and initialize fields. 1732 */ 1733 if ((new_carrp = sc->carr_freelist) == NULL) { 1734 return ADW_BUSY; 1735 } 1736 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1737 ADW_GET_CARRP(new_carrp->next_ba)); 1738 sc->carr_pending_cnt++; 1739 1740 /* 1741 * Set the carrier to be a stopper by setting 'next_ba' 1742 * to the stopper value. The current stopper will be changed 1743 * below to point to the new stopper. 1744 */ 1745 new_carrp->next_ba = ADW_CQ_STOPPER; 1746 1747 req_size = sizeof(ADW_SCSI_REQ_Q); 1748 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1749 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1750 1751 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1752 scsiq->scsiq_rptr = req_paddr; 1753 1754 /* 1755 * Every ADW_SCSI_REQ_Q.carr_ba is byte swapped to little-endian 1756 * order during initialization. 1757 */ 1758 scsiq->carr_ba = sc->icq_sp->carr_ba; 1759 scsiq->carr_va = sc->icq_sp->carr_ba; 1760 1761 /* 1762 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1763 * the microcode. The newly allocated stopper will become the new 1764 * stopper. 1765 */ 1766 sc->icq_sp->areq_ba = req_paddr; 1767 1768 /* 1769 * Set the 'next_ba' pointer for the old stopper to be the 1770 * physical address of the new stopper. The RISC can only 1771 * follow physical addresses. 1772 */ 1773 sc->icq_sp->next_ba = new_carrp->carr_ba; 1774 1775 #if ADW_DEBUG 1776 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1777 sc->icq_sp->carr_id, 1778 sc->icq_sp->carr_ba, 1779 sc->icq_sp->areq_ba, 1780 sc->icq_sp->next_ba); 1781 #endif 1782 /* 1783 * Set the host adapter stopper pointer to point to the new carrier. 1784 */ 1785 sc->icq_sp = new_carrp; 1786 1787 if (sc->chip_type == ADW_CHIP_ASC3550 || 1788 sc->chip_type == ADW_CHIP_ASC38C0800) { 1789 /* 1790 * Tickle the RISC to tell it to read its Command Queue Head 1791 * pointer. 1792 */ 1793 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1794 if (sc->chip_type == ADW_CHIP_ASC3550) { 1795 /* 1796 * Clear the tickle value. In the ASC-3550 the RISC flag 1797 * command 'clr_tickle_a' does not work unless the host 1798 * value is cleared. 1799 */ 1800 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1801 ADW_TICKLE_NOP); 1802 } 1803 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1804 /* 1805 * Notify the RISC a carrier is ready by writing the physical 1806 * address of the new carrier stopper to the COMMA register. 1807 */ 1808 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1809 new_carrp->carr_ba); 1810 } 1811 1812 /* 1813 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1814 */ 1815 1816 return ADW_SUCCESS; 1817 } 1818 1819 1820 void 1821 AdwResetChip(iot, ioh) 1822 bus_space_tag_t iot; 1823 bus_space_handle_t ioh; 1824 { 1825 1826 /* 1827 * Reset Chip. 1828 */ 1829 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1830 ADW_CTRL_REG_CMD_RESET); 1831 AdwSleepMilliSecond(100); 1832 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1833 ADW_CTRL_REG_CMD_WR_IO_REG); 1834 } 1835 1836 1837 /* 1838 * Reset SCSI Bus and purge all outstanding requests. 1839 * 1840 * Return Value: 1841 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1842 * ADW_FALSE(0) - Microcode command failed. 1843 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1844 * may be hung which requires driver recovery. 1845 */ 1846 int 1847 AdwResetCCB(sc) 1848 ADW_SOFTC *sc; 1849 { 1850 int status; 1851 1852 /* 1853 * Send the SCSI Bus Reset idle start idle command which asserts 1854 * the SCSI Bus Reset signal. 1855 */ 1856 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1857 if (status != ADW_TRUE) { 1858 return status; 1859 } 1860 1861 /* 1862 * Delay for the specified SCSI Bus Reset hold time. 1863 * 1864 * The hold time delay is done on the host because the RISC has no 1865 * microsecond accurate timer. 1866 */ 1867 AdwDelayMicroSecond((u_int16_t) ADW_SCSI_RESET_HOLD_TIME_US); 1868 1869 /* 1870 * Send the SCSI Bus Reset end idle command which de-asserts 1871 * the SCSI Bus Reset signal and purges any pending requests. 1872 */ 1873 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1874 if (status != ADW_TRUE) { 1875 return status; 1876 } 1877 1878 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1879 1880 return status; 1881 } 1882 1883 1884 /* 1885 * Reset chip and SCSI Bus. 1886 * 1887 * Return Value: 1888 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1889 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1890 */ 1891 int 1892 AdwResetSCSIBus(sc) 1893 ADW_SOFTC *sc; 1894 { 1895 bus_space_tag_t iot = sc->sc_iot; 1896 bus_space_handle_t ioh = sc->sc_ioh; 1897 int status; 1898 u_int16_t wdtr_able, sdtr_able, ppr_able = 0, tagqng_able; 1899 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1900 u_int16_t bios_sig; 1901 1902 1903 /* 1904 * Save current per TID negotiated values. 1905 */ 1906 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1907 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1908 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1909 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1910 } 1911 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1912 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1913 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1914 max_cmd[tid]); 1915 } 1916 1917 /* 1918 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1919 * by clearing the BIOS signature word. 1920 * The initialization functions assumes a SCSI Bus Reset is not 1921 * needed if the BIOS signature word is present. 1922 */ 1923 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1924 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1925 1926 /* 1927 * Stop chip and reset it. 1928 */ 1929 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1930 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1931 ADW_CTRL_REG_CMD_RESET); 1932 AdwSleepMilliSecond(100); 1933 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1934 ADW_CTRL_REG_CMD_WR_IO_REG); 1935 1936 /* 1937 * Reset Adw Library error code, if any, and try 1938 * re-initializing the chip. 1939 * Then translate initialization return value to status value. 1940 */ 1941 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1942 1943 /* 1944 * Restore the BIOS signature word. 1945 */ 1946 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1947 1948 /* 1949 * Restore per TID negotiated values. 1950 */ 1951 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1952 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1953 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1954 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1955 } 1956 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1957 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1958 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1959 max_cmd[tid]); 1960 } 1961 1962 return status; 1963 } 1964 1965 1966 /* 1967 * Adw Library Interrupt Service Routine 1968 * 1969 * This function is called by a driver's interrupt service routine. 1970 * The function disables and re-enables interrupts. 1971 * 1972 * Note: AdwISR() can be called when interrupts are disabled or even 1973 * when there is no hardware interrupt condition present. It will 1974 * always check for completed idle commands and microcode requests. 1975 * This is an important feature that shouldn't be changed because it 1976 * allows commands to be completed from polling mode loops. 1977 * 1978 * Return: 1979 * ADW_TRUE(1) - interrupt was pending 1980 * ADW_FALSE(0) - no interrupt was pending 1981 */ 1982 int 1983 AdwISR(sc) 1984 ADW_SOFTC *sc; 1985 { 1986 bus_space_tag_t iot = sc->sc_iot; 1987 bus_space_handle_t ioh = sc->sc_ioh; 1988 u_int8_t int_stat; 1989 u_int16_t target_bit; 1990 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 1991 u_int32_t irq_next_pa; 1992 ADW_SCSI_REQ_Q *scsiq; 1993 ADW_CCB *ccb; 1994 int s; 1995 1996 1997 s = splbio(); 1998 1999 /* Reading the register clears the interrupt. */ 2000 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 2001 2002 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 2003 ADW_INTR_STATUS_INTRC)) == 0) { 2004 splx(s); 2005 return ADW_FALSE; 2006 } 2007 2008 /* 2009 * Notify the driver of an asynchronous microcode condition by 2010 * calling the ADW_SOFTC.async_callback function. The function 2011 * is passed the microcode ADW_MC_INTRB_CODE byte value. 2012 */ 2013 if (int_stat & ADW_INTR_STATUS_INTRB) { 2014 u_int8_t intrb_code; 2015 2016 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2017 2018 if (sc->chip_type == ADW_CHIP_ASC3550 || 2019 sc->chip_type == ADW_CHIP_ASC38C0800) { 2020 if (intrb_code == ADW_ASYNC_CARRIER_READY_FAILURE && 2021 sc->carr_pending_cnt != 0) { 2022 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2023 IOPB_TICKLE, ADW_TICKLE_A); 2024 if (sc->chip_type == ADW_CHIP_ASC3550) { 2025 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2026 IOPB_TICKLE, ADW_TICKLE_NOP); 2027 } 2028 } 2029 } 2030 2031 if (sc->async_callback != 0) { 2032 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2033 } 2034 } 2035 2036 /* 2037 * Check if the IRQ stopper carrier contains a completed request. 2038 */ 2039 while (((irq_next_pa = sc->irq_sp->next_ba) & ADW_RQ_DONE) != 0) 2040 { 2041 #if ADW_DEBUG 2042 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2043 sc->irq_sp->carr_id, 2044 sc->irq_sp->carr_ba, 2045 sc->irq_sp->areq_ba, 2046 sc->irq_sp->next_ba); 2047 #endif 2048 /* 2049 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2050 * structure. 2051 * The RISC will have set 'areq_ba' to a virtual address. 2052 * 2053 * The firmware will have copied the ADW_SCSI_REQ_Q.ccb_ptr 2054 * field to the carrier ADW_CARRIER.areq_ba field. 2055 * The conversion below complements the conversion of 2056 * ADW_SCSI_REQ_Q.ccb_ptr' in AdwExeScsiQueue(). 2057 */ 2058 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2059 scsiq = &ccb->scsiq; 2060 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2061 2062 /* 2063 * Request finished with good status and the queue was not 2064 * DMAed to host memory by the firmware. Set all status fields 2065 * to indicate good status. 2066 */ 2067 if ((irq_next_pa & ADW_RQ_GOOD) != 0) { 2068 scsiq->done_status = QD_NO_ERROR; 2069 scsiq->host_status = scsiq->scsi_status = 0; 2070 scsiq->data_cnt = 0L; 2071 } 2072 2073 /* 2074 * Advance the stopper pointer to the next carrier 2075 * ignoring the lower four bits. Free the previous 2076 * stopper carrier. 2077 */ 2078 free_carrp = sc->irq_sp; 2079 sc->irq_sp = ADW_CARRIER_VADDR(sc, ADW_GET_CARRP(irq_next_pa)); 2080 2081 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0 2082 : sc->carr_freelist->carr_ba; 2083 sc->carr_freelist = free_carrp; 2084 sc->carr_pending_cnt--; 2085 2086 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 2087 2088 /* 2089 * Clear request microcode control flag. 2090 */ 2091 scsiq->cntl = 0; 2092 2093 /* 2094 * Check Condition handling 2095 */ 2096 /* 2097 * If the command that completed was a SCSI INQUIRY and 2098 * LUN 0 was sent the command, then process the INQUIRY 2099 * command information for the device. 2100 */ 2101 if (scsiq->done_status == QD_NO_ERROR && 2102 scsiq->cdb[0] == INQUIRY && 2103 scsiq->target_lun == 0) { 2104 AdwInquiryHandling(sc, scsiq); 2105 } 2106 2107 /* 2108 * Notify the driver of the completed request by passing 2109 * the ADW_SCSI_REQ_Q pointer to its callback function. 2110 */ 2111 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2112 /* 2113 * Note: After the driver callback function is called, 'scsiq' 2114 * can no longer be referenced. 2115 * 2116 * Fall through and continue processing other completed 2117 * requests... 2118 */ 2119 } 2120 2121 splx(s); 2122 2123 return ADW_TRUE; 2124 } 2125 2126 2127 /* 2128 * Send an idle command to the chip and wait for completion. 2129 * 2130 * Command completion is polled for once per microsecond. 2131 * 2132 * The function can be called from anywhere including an interrupt handler. 2133 * But the function is not re-entrant, so it uses the splbio/splx() 2134 * functions to prevent reentrancy. 2135 * 2136 * Return Values: 2137 * ADW_TRUE - command completed successfully 2138 * ADW_FALSE - command failed 2139 * ADW_ERROR - command timed out 2140 */ 2141 int 2142 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter) 2143 ADW_SOFTC *sc; 2144 u_int16_t idle_cmd; 2145 u_int32_t idle_cmd_parameter; 2146 { 2147 bus_space_tag_t iot = sc->sc_iot; 2148 bus_space_handle_t ioh = sc->sc_ioh; 2149 u_int16_t result; 2150 u_int32_t i, j, s; 2151 2152 s = splbio(); 2153 2154 /* 2155 * Clear the idle command status which is set by the microcode 2156 * to a non-zero value to indicate when the command is completed. 2157 */ 2158 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2159 2160 /* 2161 * Write the idle command value after the idle command parameter 2162 * has been written to avoid a race condition. If the order is not 2163 * followed, the microcode may process the idle command before the 2164 * parameters have been written to LRAM. 2165 */ 2166 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2167 idle_cmd_parameter); 2168 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2169 2170 /* 2171 * Tickle the RISC to tell it to process the idle command. 2172 */ 2173 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2174 if (sc->chip_type == ADW_CHIP_ASC3550) { 2175 /* 2176 * Clear the tickle value. In the ASC-3550 the RISC flag 2177 * command 'clr_tickle_b' does not work unless the host 2178 * value is cleared. 2179 */ 2180 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2181 } 2182 2183 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2184 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2185 /* Poll once each microsecond for command completion. */ 2186 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2187 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2188 result); 2189 if (result != 0) { 2190 splx(s); 2191 return result; 2192 } 2193 AdwDelayMicroSecond(1); 2194 } 2195 } 2196 2197 splx(s); 2198 return ADW_ERROR; 2199 } 2200 2201 2202 /* 2203 * Inquiry Information Byte 7 Handling 2204 * 2205 * Handle SCSI Inquiry Command information for a device by setting 2206 * microcode operating variables that affect WDTR, SDTR, and Tag 2207 * Queuing. 2208 */ 2209 void 2210 AdwInquiryHandling(sc, scsiq) 2211 ADW_SOFTC *sc; 2212 ADW_SCSI_REQ_Q *scsiq; 2213 { 2214 #ifndef FAILSAFE 2215 bus_space_tag_t iot = sc->sc_iot; 2216 bus_space_handle_t ioh = sc->sc_ioh; 2217 u_int8_t tid; 2218 ADW_SCSI_INQUIRY *inq; 2219 u_int16_t tidmask; 2220 u_int16_t cfg_word; 2221 2222 2223 /* 2224 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2225 * to be available. 2226 * 2227 * If less than 8 bytes of INQUIRY information were requested or less 2228 * than 8 bytes were transferred, then return. cdb[4] is the request 2229 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2230 * microcode to the transfer residual count. 2231 */ 2232 2233 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2234 return; 2235 } 2236 2237 tid = scsiq->target_id; 2238 2239 inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr; 2240 2241 /* 2242 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2243 */ 2244 if ((inq->rsp_data_fmt < 2) /*SCSI-1 | CCS*/ && 2245 (inq->ansi_apr_ver < 2)) { 2246 return; 2247 } else { 2248 /* 2249 * INQUIRY Byte 7 Handling 2250 * 2251 * Use a device's INQUIRY byte 7 to determine whether it 2252 * supports WDTR, SDTR, and Tag Queuing. If the feature 2253 * is enabled in the EEPROM and the device supports the 2254 * feature, then enable it in the microcode. 2255 */ 2256 2257 tidmask = ADW_TID_TO_TIDMASK(tid); 2258 2259 /* 2260 * Wide Transfers 2261 * 2262 * If the EEPROM enabled WDTR for the device and the device 2263 * supports wide bus (16 bit) transfers, then turn on the 2264 * device's 'wdtr_able' bit and write the new value to the 2265 * microcode. 2266 */ 2267 #ifdef SCSI_ADW_WDTR_DISABLE 2268 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2269 #endif /* SCSI_ADW_WDTR_DISABLE */ 2270 if ((sc->wdtr_able & tidmask) && inq->WBus16) { 2271 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2272 cfg_word); 2273 if ((cfg_word & tidmask) == 0) { 2274 cfg_word |= tidmask; 2275 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2276 cfg_word); 2277 2278 /* 2279 * Clear the microcode "SDTR negotiation" and 2280 * "WDTR negotiation" done indicators for the 2281 * target to cause it to negotiate with the new 2282 * setting set above. 2283 * WDTR when accepted causes the target to enter 2284 * asynchronous mode, so SDTR must be negotiated 2285 */ 2286 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2287 cfg_word); 2288 cfg_word &= ~tidmask; 2289 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2290 cfg_word); 2291 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2292 cfg_word); 2293 cfg_word &= ~tidmask; 2294 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2295 cfg_word); 2296 } 2297 } 2298 2299 /* 2300 * Synchronous Transfers 2301 * 2302 * If the EEPROM enabled SDTR for the device and the device 2303 * supports synchronous transfers, then turn on the device's 2304 * 'sdtr_able' bit. Write the new value to the microcode. 2305 */ 2306 #ifdef SCSI_ADW_SDTR_DISABLE 2307 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2308 #endif /* SCSI_ADW_SDTR_DISABLE */ 2309 if ((sc->sdtr_able & tidmask) && inq->Sync) { 2310 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2311 if ((cfg_word & tidmask) == 0) { 2312 cfg_word |= tidmask; 2313 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2314 cfg_word); 2315 2316 /* 2317 * Clear the microcode "SDTR negotiation" 2318 * done indicator for the target to cause it 2319 * to negotiate with the new setting set above. 2320 */ 2321 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2322 cfg_word); 2323 cfg_word &= ~tidmask; 2324 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2325 cfg_word); 2326 } 2327 } 2328 /* 2329 * If the Inquiry data included enough space for the SPI-3 2330 * Clocking field, then check if DT mode is supported. 2331 */ 2332 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2333 (scsiq->cdb[4] >= 57 || 2334 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2335 /* 2336 * PPR (Parallel Protocol Request) Capable 2337 * 2338 * If the device supports DT mode, then it must be 2339 * PPR capable. 2340 * The PPR message will be used in place of the SDTR 2341 * and WDTR messages to negotiate synchronous speed 2342 * and offset, transfer width, and protocol options. 2343 */ 2344 if((inq->Clocking) & INQ_CLOCKING_DT_ONLY){ 2345 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2346 sc->ppr_able); 2347 sc->ppr_able |= tidmask; 2348 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2349 sc->ppr_able); 2350 } 2351 } 2352 2353 /* 2354 * If the EEPROM enabled Tag Queuing for the device and the 2355 * device supports Tag Queueing, then turn on the device's 2356 * 'tagqng_enable' bit in the microcode and set the microcode 2357 * maximum command count to the ADW_SOFTC 'max_dvc_qng' 2358 * value. 2359 * 2360 * Tag Queuing is disabled for the BIOS which runs in polled 2361 * mode and would see no benefit from Tag Queuing. Also by 2362 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2363 * bugs will at least work with the BIOS. 2364 */ 2365 #ifdef SCSI_ADW_TAGQ_DISABLE 2366 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2367 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2368 if ((sc->tagqng_able & tidmask) && inq->CmdQue) { 2369 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2370 cfg_word); 2371 cfg_word |= tidmask; 2372 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2373 cfg_word); 2374 2375 ADW_WRITE_BYTE_LRAM(iot, ioh, 2376 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2377 sc->max_dvc_qng); 2378 } 2379 } 2380 #endif /* FAILSAFE */ 2381 } 2382 2383 2384 void 2385 AdwSleepMilliSecond(n) 2386 u_int32_t n; 2387 { 2388 2389 DELAY(n * 1000); 2390 } 2391 2392 2393 void 2394 AdwDelayMicroSecond(n) 2395 u_int32_t n; 2396 { 2397 2398 DELAY(n); 2399 } 2400 2401