1 /* $OpenBSD: adwlib.c,v 1.24 2012/01/11 16:22:32 dhill Exp $ */ 2 /* $NetBSD: adwlib.c,v 1.20 2000/07/04 04:17:03 itojun Exp $ */ 3 4 /* 5 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from: 35 */ 36 /* 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-2000 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 */ 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/queue.h> 54 #include <sys/device.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <scsi/scsi_all.h> 60 #include <scsi/scsiconf.h> 61 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/ic/adwlib.h> 65 #include <dev/microcode/adw/adwmcode.h> 66 #include <dev/ic/adw.h> 67 68 69 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t); 70 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, 71 u_int8_t); 72 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 73 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, 74 ADW_DVC_CFG *); 75 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, 76 ADW_DVC_CFG *); 77 78 u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 79 ADW_EEPROM *); 80 void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 81 ADW_EEPROM *); 82 u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int); 83 void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t); 84 85 void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 86 87 void AdwSleepMilliSecond(u_int32_t); 88 void AdwDelayMicroSecond(u_int32_t); 89 90 91 /* 92 * EEPROM Configuration. 93 * 94 * All drivers should use this structure to set the default EEPROM 95 * configuration. The BIOS now uses this structure when it is built. 96 * Additional structure information can be found in adwlib.h where 97 * the structure is defined. 98 */ 99 const static ADW_EEPROM adw_3550_Default_EEPROM = { 100 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 101 0x0000, /* 01 cfg_msw */ 102 0xFFFF, /* 02 disc_enable */ 103 0xFFFF, /* 03 wdtr_able */ 104 { 0xFFFF }, /* 04 sdtr_able */ 105 0xFFFF, /* 05 start_motor */ 106 0xFFFF, /* 06 tagqng_able */ 107 0xFFFF, /* 07 bios_scan */ 108 0, /* 08 scam_tolerant */ 109 7, /* 09 adapter_scsi_id */ 110 0, /* bios_boot_delay */ 111 3, /* 10 scsi_reset_delay */ 112 0, /* bios_id_lun */ 113 0, /* 11 termination */ 114 0, /* reserved1 */ 115 0xFFE7, /* 12 bios_ctrl */ 116 { 0xFFFF }, /* 13 ultra_able */ 117 { 0 }, /* 14 reserved2 */ 118 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 119 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 120 0, /* 16 dvc_cntl */ 121 { 0 }, /* 17 bug_fix */ 122 { 0,0,0 }, /* 18-20 serial_number[3] */ 123 0, /* 21 check_sum */ 124 { /* 22-29 oem_name[16] */ 125 0,0,0,0,0,0,0,0, 126 0,0,0,0,0,0,0,0 127 }, 128 0, /* 30 dvc_err_code */ 129 0, /* 31 adw_err_code */ 130 0, /* 32 adw_err_addr */ 131 0, /* 33 saved_dvc_err_code */ 132 0, /* 34 saved_adw_err_code */ 133 0 /* 35 saved_adw_err_addr */ 134 }; 135 136 const static ADW_EEPROM adw_38C0800_Default_EEPROM = { 137 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 138 0x0000, /* 01 cfg_msw */ 139 0xFFFF, /* 02 disc_enable */ 140 0xFFFF, /* 03 wdtr_able */ 141 { 0x4444 }, /* 04 sdtr_speed1 */ 142 0xFFFF, /* 05 start_motor */ 143 0xFFFF, /* 06 tagqng_able */ 144 0xFFFF, /* 07 bios_scan */ 145 0, /* 08 scam_tolerant */ 146 7, /* 09 adapter_scsi_id */ 147 0, /* bios_boot_delay */ 148 3, /* 10 scsi_reset_delay */ 149 0, /* bios_id_lun */ 150 0, /* 11 termination_se */ 151 0, /* termination_lvd */ 152 0xFFE7, /* 12 bios_ctrl */ 153 { 0x4444 }, /* 13 sdtr_speed2 */ 154 { 0x4444 }, /* 14 sdtr_speed3 */ 155 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 156 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 157 0, /* 16 dvc_cntl */ 158 { 0x4444 }, /* 17 sdtr_speed4 */ 159 { 0,0,0 }, /* 18-20 serial_number[3] */ 160 0, /* 21 check_sum */ 161 { /* 22-29 oem_name[16] */ 162 0,0,0,0,0,0,0,0, 163 0,0,0,0,0,0,0,0 164 }, 165 0, /* 30 dvc_err_code */ 166 0, /* 31 adw_err_code */ 167 0, /* 32 adw_err_addr */ 168 0, /* 33 saved_dvc_err_code */ 169 0, /* 34 saved_adw_err_code */ 170 0, /* 35 saved_adw_err_addr */ 171 { /* 36-55 reserved1[16] */ 172 0,0,0,0,0,0,0,0,0,0, 173 0,0,0,0,0,0,0,0,0,0 174 }, 175 0, /* 56 cisptr_lsw */ 176 0, /* 57 cisprt_msw */ 177 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 178 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 179 { 0,0,0,0 } /* 60-63 reserved2[4] */ 180 }; 181 182 const static ADW_EEPROM adw_38C1600_Default_EEPROM = { 183 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 184 0x0000, /* 01 cfg_msw */ 185 0xFFFF, /* 02 disc_enable */ 186 0xFFFF, /* 03 wdtr_able */ 187 { 0x5555 }, /* 04 sdtr_speed1 */ 188 0xFFFF, /* 05 start_motor */ 189 0xFFFF, /* 06 tagqng_able */ 190 0xFFFF, /* 07 bios_scan */ 191 0, /* 08 scam_tolerant */ 192 7, /* 09 adapter_scsi_id */ 193 0, /* bios_boot_delay */ 194 3, /* 10 scsi_reset_delay */ 195 0, /* bios_id_lun */ 196 0, /* 11 termination_se */ 197 0, /* termination_lvd */ 198 0xFFE7, /* 12 bios_ctrl */ 199 { 0x5555 }, /* 13 sdtr_speed2 */ 200 { 0x5555 }, /* 14 sdtr_speed3 */ 201 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 202 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 203 0, /* 16 dvc_cntl */ 204 { 0x5555 }, /* 17 sdtr_speed4 */ 205 { 0,0,0 }, /* 18-20 serial_number[3] */ 206 0, /* 21 check_sum */ 207 { /* 22-29 oem_name[16] */ 208 0,0,0,0,0,0,0,0, 209 0,0,0,0,0,0,0,0 210 }, 211 0, /* 30 dvc_err_code */ 212 0, /* 31 adw_err_code */ 213 0, /* 32 adw_err_addr */ 214 0, /* 33 saved_dvc_err_code */ 215 0, /* 34 saved_adw_err_code */ 216 0, /* 35 saved_adw_err_addr */ 217 { /* 36-55 reserved1[16] */ 218 0,0,0,0,0,0,0,0,0,0, 219 0,0,0,0,0,0,0,0,0,0 220 }, 221 0, /* 56 cisptr_lsw */ 222 0, /* 57 cisprt_msw */ 223 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 224 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 225 { 0,0,0,0 } /* 60-63 reserved2[4] */ 226 }; 227 228 229 /* 230 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 231 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 232 * all of this is done. 233 * 234 * For a non-fatal error return a warning code. If there are no warnings 235 * then 0 is returned. 236 * 237 * Note: Chip is stopped on entry. 238 */ 239 int 240 AdwInitFromEEPROM(ADW_SOFTC *sc) 241 { 242 bus_space_tag_t iot = sc->sc_iot; 243 bus_space_handle_t ioh = sc->sc_ioh; 244 ADW_EEPROM eep_config; 245 u_int16_t warn_code; 246 u_int16_t sdtr_speed = 0; 247 u_int8_t tid, termination; 248 int i, j; 249 250 251 warn_code = 0; 252 253 /* 254 * Read the board's EEPROM configuration. 255 * 256 * Set default values if a bad checksum is found. 257 * 258 * XXX - Don't handle big-endian access to EEPROM yet. 259 */ 260 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 261 warn_code |= ADW_WARN_EEPROM_CHKSUM; 262 263 /* 264 * Set EEPROM default values. 265 */ 266 switch(sc->chip_type) { 267 case ADW_CHIP_ASC3550: 268 eep_config = adw_3550_Default_EEPROM; 269 break; 270 case ADW_CHIP_ASC38C0800: 271 eep_config = adw_38C0800_Default_EEPROM; 272 break; 273 case ADW_CHIP_ASC38C1600: 274 eep_config = adw_38C1600_Default_EEPROM; 275 276 // XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 277 if (sc->cfg.pci_slot_info != 0) { 278 u_int8_t lsw_msb; 279 280 lsw_msb = eep_config.cfg_lsw >> 8; 281 /* 282 * Set Function 1 EEPROM Word 0 MSB 283 * 284 * Clear the BIOS_ENABLE (bit 14) and 285 * INTAB (bit 11) EEPROM bits. 286 * 287 * Disable Bit 14 (BIOS_ENABLE) to fix 288 * SPARC Ultra 60 and old Mac system booting 289 * problem. The Expansion ROM must 290 * be disabled in Function 1 for these systems. 291 */ 292 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 293 ADW_EEPROM_INTAB) >> 8) & 0xFF); 294 /* 295 * Set the INTAB (bit 11) if the GPIO 0 input 296 * indicates the Function 1 interrupt line is 297 * wired to INTA. 298 * 299 * Set/Clear Bit 11 (INTAB) from 300 * the GPIO bit 0 input: 301 * 1 - Function 1 intr line wired to INT A. 302 * 0 - Function 1 intr line wired to INT B. 303 * 304 * Note: Adapter boards always have Function 0 305 * wired to INTA. 306 * Put all 5 GPIO bits in input mode and then 307 * read their input values. 308 */ 309 ADW_WRITE_BYTE_REGISTER(iot, ioh, 310 IOPB_GPIO_CNTL, 0); 311 if (ADW_READ_BYTE_REGISTER(iot, ioh, 312 IOPB_GPIO_DATA) & 0x01) { 313 /* 314 * Function 1 interrupt wired to INTA; 315 * Set EEPROM bit. 316 */ 317 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 318 & 0xFF; 319 } 320 eep_config.cfg_lsw &= 0x00FF; 321 eep_config.cfg_lsw |= lsw_msb << 8; 322 } 323 break; 324 } 325 326 /* 327 * Assume the 6 byte board serial number that was read 328 * from EEPROM is correct even if the EEPROM checksum 329 * failed. 330 */ 331 for (i=2, j=1; i>=0; i--, j++) { 332 eep_config.serial_number[i] = 333 AdwReadEEPWord(iot, ioh, ADW_EEP_DVC_CFG_END - j); 334 } 335 336 AdwSetEEPROMConfig(iot, ioh, &eep_config); 337 } 338 /* 339 * Set sc and sc->cfg variables from the EEPROM configuration 340 * that was read. 341 * 342 * This is the mapping of EEPROM fields to Adw Library fields. 343 */ 344 sc->wdtr_able = eep_config.wdtr_able; 345 if (sc->chip_type == ADW_CHIP_ASC3550) { 346 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 347 sc->ultra_able = eep_config.sdtr2.ultra_able; 348 } else { 349 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 350 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 351 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 352 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 353 } 354 sc->ppr_able = 0; 355 sc->tagqng_able = eep_config.tagqng_able; 356 sc->cfg.disc_enable = eep_config.disc_enable; 357 sc->max_host_qng = eep_config.max_host_qng; 358 sc->max_dvc_qng = eep_config.max_dvc_qng; 359 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 360 sc->start_motor = eep_config.start_motor; 361 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 362 sc->bios_ctrl = eep_config.bios_ctrl; 363 sc->no_scam = eep_config.scam_tolerant; 364 sc->cfg.serial1 = eep_config.serial_number[0]; 365 sc->cfg.serial2 = eep_config.serial_number[1]; 366 sc->cfg.serial3 = eep_config.serial_number[2]; 367 368 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 369 sc->chip_type == ADW_CHIP_ASC38C1600) { 370 sc->sdtr_able = 0; 371 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 372 if (tid == 0) { 373 sdtr_speed = sc->sdtr_speed1; 374 } else if (tid == 4) { 375 sdtr_speed = sc->sdtr_speed2; 376 } else if (tid == 8) { 377 sdtr_speed = sc->sdtr_speed3; 378 } else if (tid == 12) { 379 sdtr_speed = sc->sdtr_speed4; 380 } 381 if (sdtr_speed & ADW_MAX_TID) { 382 sc->sdtr_able |= (1 << tid); 383 } 384 sdtr_speed >>= 4; 385 } 386 } 387 388 /* 389 * Set the host maximum queuing (max. 253, min. 16) and the per device 390 * maximum queuing (max. 63, min. 4). 391 */ 392 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 393 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 394 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 395 { 396 /* If the value is zero, assume it is uninitialized. */ 397 if (eep_config.max_host_qng == 0) { 398 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 399 } else { 400 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 401 } 402 } 403 404 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 405 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 406 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 407 /* If the value is zero, assume it is uninitialized. */ 408 if (eep_config.max_dvc_qng == 0) { 409 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 410 } else { 411 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 412 } 413 } 414 415 /* 416 * If 'max_dvc_qng' is greater than 'max_host_qng', then 417 * set 'max_dvc_qng' to 'max_host_qng'. 418 */ 419 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 420 eep_config.max_dvc_qng = eep_config.max_host_qng; 421 } 422 423 /* 424 * Set ADW_SOFTC 'max_host_qng' and 'max_dvc_qng' 425 * values based on possibly adjusted EEPROM values. 426 */ 427 sc->max_host_qng = eep_config.max_host_qng; 428 sc->max_dvc_qng = eep_config.max_dvc_qng; 429 430 431 /* 432 * If the EEPROM 'termination' field is set to automatic (0), then set 433 * the ADW_SOFTC.cfg 'termination' field to automatic also. 434 * 435 * If the termination is specified with a non-zero 'termination' 436 * value check that a legal value is set and set the ADW_SOFTC.cfg 437 * 'termination' field appropriately. 438 */ 439 440 switch(sc->chip_type) { 441 case ADW_CHIP_ASC3550: 442 sc->cfg.termination = 0; /* auto termination */ 443 switch(eep_config.termination_se) { 444 case 3: 445 /* Enable manual control with low on / high on. */ 446 sc->cfg.termination |= ADW_TERM_CTL_L; 447 case 2: 448 /* Enable manual control with low off / high on. */ 449 sc->cfg.termination |= ADW_TERM_CTL_H; 450 case 1: 451 /* Enable manual control with low off / high off. */ 452 sc->cfg.termination |= ADW_TERM_CTL_SEL; 453 case 0: 454 break; 455 default: 456 warn_code |= ADW_WARN_EEPROM_TERMINATION; 457 } 458 break; 459 460 case ADW_CHIP_ASC38C0800: 461 case ADW_CHIP_ASC38C1600: 462 switch(eep_config.termination_se) { 463 case 0: 464 /* auto termination for SE */ 465 termination = 0; 466 break; 467 case 1: 468 /* Enable manual control with low off / high off. */ 469 termination = 0; 470 break; 471 case 2: 472 /* Enable manual control with low off / high on. */ 473 termination = ADW_TERM_SE_HI; 474 break; 475 case 3: 476 /* Enable manual control with low on / high on. */ 477 termination = ADW_TERM_SE; 478 break; 479 default: 480 /* 481 * The EEPROM 'termination_se' field contains a 482 * bad value. Use automatic termination instead. 483 */ 484 termination = 0; 485 warn_code |= ADW_WARN_EEPROM_TERMINATION; 486 } 487 488 switch(eep_config.termination_lvd) { 489 case 0: 490 /* auto termination for LVD */ 491 sc->cfg.termination = termination; 492 break; 493 case 1: 494 /* Enable manual control with low off / high off. */ 495 sc->cfg.termination = termination; 496 break; 497 case 2: 498 /* Enable manual control with low off / high on. */ 499 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 500 break; 501 case 3: 502 /* Enable manual control with low on / high on. */ 503 sc->cfg.termination = termination | ADW_TERM_LVD; 504 break; 505 default: 506 /* 507 * The EEPROM 'termination_lvd' field contains a 508 * bad value. Use automatic termination instead. 509 */ 510 sc->cfg.termination = termination; 511 warn_code |= ADW_WARN_EEPROM_TERMINATION; 512 } 513 break; 514 } 515 516 return warn_code; 517 } 518 519 520 /* 521 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 522 * 523 * On failure return the error code. 524 */ 525 int 526 AdwInitDriver(ADW_SOFTC *sc) 527 { 528 bus_space_tag_t iot = sc->sc_iot; 529 bus_space_handle_t ioh = sc->sc_ioh; 530 u_int16_t error_code; 531 int word; 532 int i; 533 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 534 0x40-0x8F. */ 535 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able; 536 u_int8_t max_cmd[ADW_MAX_TID + 1]; 537 u_int8_t tid; 538 539 540 error_code = 0; 541 542 /* 543 * Save the RISC memory BIOS region before writing the microcode. 544 * The BIOS may already be loaded and using its RISC LRAM region 545 * so its region must be saved and restored. 546 * 547 * Note: This code makes the assumption, which is currently true, 548 * that a chip reset does not clear RISC LRAM. 549 */ 550 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 551 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 552 } 553 554 /* 555 * Save current per TID negotiated values. 556 */ 557 switch (sc->chip_type) { 558 case ADW_CHIP_ASC3550: 559 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 560 561 u_int16_t bios_version, major, minor; 562 563 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 564 ADW_MC_BIOSMEM) / 2]; 565 major = (bios_version >> 12) & 0xF; 566 minor = (bios_version >> 8) & 0xF; 567 if (major < 3 || (major == 3 && minor == 1)) { 568 /* 569 * BIOS 3.1 and earlier location of 570 * 'wdtr_able' variable. 571 */ 572 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 573 } else { 574 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 575 wdtr_able); 576 } 577 } 578 break; 579 580 case ADW_CHIP_ASC38C1600: 581 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 582 /* FALLTHROUGH */ 583 case ADW_CHIP_ASC38C0800: 584 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 585 break; 586 } 587 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 588 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 589 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 590 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 591 max_cmd[tid]); 592 } 593 594 /* 595 * Perform a RAM Built-In Self Test 596 */ 597 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 598 return error_code; 599 } 600 601 /* 602 * Load the Microcode 603 */ 604 ; 605 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 606 return error_code; 607 } 608 609 /* 610 * Read microcode version and date. 611 */ 612 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 613 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 614 615 /* 616 * If the PCI Configuration Command Register "Parity Error Response 617 * Control" Bit was clear (0), then set the microcode variable 618 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 619 * to ignore DMA parity errors. 620 */ 621 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 622 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 623 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 624 word | CONTROL_FLAG_IGNORE_PERR); 625 } 626 627 switch (sc->chip_type) { 628 case ADW_CHIP_ASC3550: 629 /* 630 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 631 * FIFO threshold of 128 bytes. 632 * This register is only accessible to the host. 633 */ 634 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 635 START_CTL_EMFU | READ_CMD_MRM); 636 break; 637 638 case ADW_CHIP_ASC38C0800: 639 /* 640 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 641 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 642 * cable detection and then we are able to read C_DET[3:0]. 643 * 644 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 645 * Microcode Default Value' section below. 646 */ 647 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 648 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 649 | ADW_DIS_TERM_DRV); 650 651 /* 652 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 653 * START_CTL_TH [3:2] bits for the default FIFO threshold. 654 * 655 * Note: ASC-38C0800 FIFO threshold has been changed to 656 * 256 bytes. 657 * 658 * For DMA Errata #4 set the BC_THRESH_ENB bit. 659 */ 660 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 661 BC_THRESH_ENB | FIFO_THRESH_80B 662 | START_CTL_TH | READ_CMD_MRM); 663 break; 664 665 case ADW_CHIP_ASC38C1600: 666 /* 667 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 668 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 669 * cable detection and then we are able to read C_DET[3:0]. 670 * 671 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 672 * Microcode Default Value' section below. 673 */ 674 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 675 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 676 | ADW_DIS_TERM_DRV); 677 678 /* 679 * If the BIOS control flag AIPP (Asynchronous Information 680 * Phase Protection) disable bit is not set, then set the 681 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 682 * enable AIPP checking and encoding. 683 */ 684 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 685 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 686 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 687 word | CONTROL_FLAG_ENABLE_AIPP); 688 } 689 690 /* 691 * For ASC-38C1600 use DMA_CFG0 default values: 692 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 693 */ 694 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 695 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 696 break; 697 } 698 699 /* 700 * Microcode operating variables for WDTR, SDTR, and command tag 701 * queuing will be set in AdwInquiryHandling() based on what a 702 * device reports it is capable of in Inquiry byte 7. 703 * 704 * If SCSI Bus Resets have been disabled, then directly set 705 * SDTR and WDTR from the EEPROM configuration. This will allow 706 * the BIOS and warm boot to work without a SCSI bus hang on 707 * the Inquiry caused by host and target mismatched DTR values. 708 * Without the SCSI Bus Reset, before an Inquiry a device can't 709 * be assumed to be in Asynchronous, Narrow mode. 710 */ 711 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 712 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 713 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 714 } 715 716 /* 717 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 718 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 719 * bitmask. These values determine the maximum SDTR speed negotiated 720 * with a device. 721 * 722 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 723 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 724 * without determining here whether the device supports SDTR. 725 */ 726 switch (sc->chip_type) { 727 case ADW_CHIP_ASC3550: 728 word = 0; 729 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 730 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 731 /* Set Ultra speed for TID 'tid'. */ 732 word |= (0x3 << (4 * (tid % 4))); 733 } else { 734 /* Set Fast speed for TID 'tid'. */ 735 word |= (0x2 << (4 * (tid % 4))); 736 } 737 /* Check if done with sdtr_speed1. */ 738 if (tid == 3) { 739 ADW_WRITE_WORD_LRAM(iot, ioh, 740 ADW_MC_SDTR_SPEED1, word); 741 word = 0; 742 /* Check if done with sdtr_speed2. */ 743 } else if (tid == 7) { 744 ADW_WRITE_WORD_LRAM(iot, ioh, 745 ADW_MC_SDTR_SPEED2, word); 746 word = 0; 747 /* Check if done with sdtr_speed3. */ 748 } else if (tid == 11) { 749 ADW_WRITE_WORD_LRAM(iot, ioh, 750 ADW_MC_SDTR_SPEED3, word); 751 word = 0; 752 /* Check if done with sdtr_speed4. */ 753 } else if (tid == 15) { 754 ADW_WRITE_WORD_LRAM(iot, ioh, 755 ADW_MC_SDTR_SPEED4, word); 756 /* End of loop. */ 757 } 758 } 759 760 /* 761 * Set microcode operating variable for the 762 * disconnect per TID bitmask. 763 */ 764 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 765 sc->cfg.disc_enable); 766 break; 767 768 case ADW_CHIP_ASC38C0800: 769 /* FALLTHROUGH */ 770 case ADW_CHIP_ASC38C1600: 771 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 772 sc->cfg.disc_enable); 773 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 774 sc->sdtr_speed1); 775 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 776 sc->sdtr_speed2); 777 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 778 sc->sdtr_speed3); 779 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 780 sc->sdtr_speed4); 781 break; 782 } 783 784 785 /* 786 * Set SCSI_CFG0 Microcode Default Value. 787 * 788 * The microcode will set the SCSI_CFG0 register using this value 789 * after it is started below. 790 */ 791 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 792 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 793 ADW_OUR_ID_EN | sc->chip_scsi_id); 794 795 796 switch(sc->chip_type) { 797 case ADW_CHIP_ASC3550: 798 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 799 break; 800 801 case ADW_CHIP_ASC38C0800: 802 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 803 break; 804 805 case ADW_CHIP_ASC38C1600: 806 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 807 break; 808 } 809 if(error_code) { 810 return error_code; 811 } 812 813 /* 814 * Set SEL_MASK Microcode Default Value 815 * 816 * The microcode will set the SEL_MASK register using this value 817 * after it is started below. 818 */ 819 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 820 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 821 822 /* 823 * Create and Initialize Host->RISC Carrier lists 824 */ 825 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 826 sc->sc_control->carriers); 827 828 /* 829 * Set-up the Host->RISC Initiator Command Queue (ICQ). 830 */ 831 832 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 833 return ADW_IERR_NO_CARRIER; 834 } 835 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 836 ADW_GET_CARRP(sc->icq_sp->next_ba)); 837 838 /* 839 * The first command issued will be placed in the stopper carrier. 840 */ 841 sc->icq_sp->next_ba = ADW_CQ_STOPPER; 842 843 /* 844 * Set RISC ICQ physical address start value. 845 */ 846 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, sc->icq_sp->carr_ba); 847 848 /* 849 * Initialize the COMMA register to the same value otherwise 850 * the RISC will prematurely detect a command is available. 851 */ 852 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 853 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 854 sc->icq_sp->carr_ba); 855 } 856 857 /* 858 * Set-up the RISC->Host Initiator Response Queue (IRQ). 859 */ 860 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 861 return ADW_IERR_NO_CARRIER; 862 } 863 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 864 ADW_GET_CARRP(sc->irq_sp->next_ba)); 865 866 /* 867 * The first command completed by the RISC will be placed in 868 * the stopper. 869 * 870 * Note: Set 'next_ba' to ADW_CQ_STOPPER. When the request is 871 * completed the RISC will set the ADW_RQ_DONE bit. 872 */ 873 sc->irq_sp->next_ba = ADW_CQ_STOPPER; 874 875 /* 876 * Set RISC IRQ physical address start value. 877 */ 878 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, sc->irq_sp->carr_ba); 879 sc->carr_pending_cnt = 0; 880 881 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 882 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 883 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 884 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 885 886 /* finally, finally, gentlemen, start your engine */ 887 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 888 889 /* 890 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 891 * Resets should be performed. The RISC has to be running 892 * to issue a SCSI Bus Reset. 893 */ 894 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 895 { 896 /* 897 * If the BIOS Signature is present in memory, restore the 898 * BIOS Handshake Configuration Table and do not perform 899 * a SCSI Bus Reset. 900 */ 901 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 902 0x55AA) { 903 /* 904 * Restore per TID negotiated values. 905 */ 906 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 907 wdtr_able); 908 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 909 sdtr_able); 910 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 911 tagqng_able); 912 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 913 ADW_WRITE_BYTE_LRAM(iot, ioh, 914 ADW_MC_NUMBER_OF_MAX_CMD + tid, 915 max_cmd[tid]); 916 } 917 } else { 918 if (AdwResetCCB(sc) != ADW_TRUE) { 919 error_code = ADW_WARN_BUSRESET_ERROR; 920 } 921 } 922 } 923 924 return error_code; 925 } 926 927 928 int 929 AdwRamSelfTest(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t chip_type) 930 { 931 int i; 932 u_int8_t byte; 933 934 935 if ((chip_type == ADW_CHIP_ASC38C0800) || 936 (chip_type == ADW_CHIP_ASC38C1600)) { 937 /* 938 * RAM BIST (RAM Built-In Self Test) 939 * 940 * Address : I/O base + offset 0x38h register (byte). 941 * Function: Bit 7-6(RW) : RAM mode 942 * Normal Mode : 0x00 943 * Pre-test Mode : 0x40 944 * RAM Test Mode : 0x80 945 * Bit 5 : unused 946 * Bit 4(RO) : Done bit 947 * Bit 3-0(RO) : Status 948 * Host Error : 0x08 949 * Int_RAM Error : 0x04 950 * RISC Error : 0x02 951 * SCSI Error : 0x01 952 * No Error : 0x00 953 * 954 * Note: RAM BIST code should be put right here, before loading 955 * the microcode and after saving the RISC memory BIOS region. 956 */ 957 958 /* 959 * LRAM Pre-test 960 * 961 * Write PRE_TEST_MODE (0x40) to register and wait for 962 * 10 milliseconds. 963 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 964 * return an error. Reset to NORMAL_MODE (0x00) and do again. 965 * If cannot reset to NORMAL_MODE, return an error too. 966 */ 967 for (i = 0; i < 2; i++) { 968 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 969 PRE_TEST_MODE); 970 /* Wait for 10ms before reading back. */ 971 AdwSleepMilliSecond(10); 972 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 973 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 974 PRE_TEST_VALUE) { 975 return ADW_IERR_BIST_PRE_TEST; 976 } 977 978 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 979 NORMAL_MODE); 980 /* Wait for 10ms before reading back. */ 981 AdwSleepMilliSecond(10); 982 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 983 != NORMAL_VALUE) { 984 return ADW_IERR_BIST_PRE_TEST; 985 } 986 } 987 988 /* 989 * LRAM Test - It takes about 1.5 ms to run through the test. 990 * 991 * Write RAM_TEST_MODE (0x80) to register and wait for 992 * 10 milliseconds. 993 * If Done bit not set or Status not 0, save register byte, 994 * set the err_code, and return an error. 995 */ 996 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 997 /* Wait for 10ms before checking status. */ 998 AdwSleepMilliSecond(10); 999 1000 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1001 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1002 /* Get here if Done bit not set or Status not 0. */ 1003 return ADW_IERR_BIST_RAM_TEST; 1004 } 1005 1006 /* We need to reset back to normal mode after LRAM test passes*/ 1007 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1008 } 1009 1010 return 0; 1011 } 1012 1013 1014 int 1015 AdwLoadMCode(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t *bios_mem, 1016 u_int8_t chip_type) 1017 { 1018 u_int8_t *mcode_data = NULL; 1019 u_int32_t mcode_chksum = 0; 1020 u_int16_t mcode_size = 0; 1021 u_int32_t sum; 1022 u_int16_t code_sum; 1023 int begin_addr; 1024 int end_addr; 1025 int word; 1026 int adw_memsize = 0; 1027 int adw_mcode_expanded_size; 1028 int i, j; 1029 1030 1031 switch(chip_type) { 1032 case ADW_CHIP_ASC3550: 1033 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1034 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1035 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1036 adw_memsize = ADW_3550_MEMSIZE; 1037 break; 1038 1039 case ADW_CHIP_ASC38C0800: 1040 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1041 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1042 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1043 adw_memsize = ADW_38C0800_MEMSIZE; 1044 break; 1045 1046 case ADW_CHIP_ASC38C1600: 1047 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1048 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1049 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1050 adw_memsize = ADW_38C1600_MEMSIZE; 1051 break; 1052 } 1053 1054 /* 1055 * Write the microcode image to RISC memory starting at address 0. 1056 */ 1057 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1058 1059 /* Assume the following compressed format of the microcode buffer: 1060 * 1061 * 254 word (508 byte) table indexed by byte code followed 1062 * by the following byte codes: 1063 * 1064 * 1-Byte Code: 1065 * 00: Emit word 0 in table. 1066 * 01: Emit word 1 in table. 1067 * . 1068 * FD: Emit word 253 in table. 1069 * 1070 * Multi-Byte Code: 1071 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1072 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1073 */ 1074 word = 0; 1075 for (i = 253 * 2; i < mcode_size; i++) { 1076 if (mcode_data[i] == 0xff) { 1077 for (j = 0; j < mcode_data[i + 1]; j++) { 1078 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1079 (((u_int16_t)mcode_data[i + 3] << 8) | 1080 mcode_data[i + 2])); 1081 word++; 1082 } 1083 i += 3; 1084 } else if (mcode_data[i] == 0xfe) { 1085 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1086 (((u_int16_t)mcode_data[i + 2] << 8) | 1087 mcode_data[i + 1])); 1088 i += 2; 1089 word++; 1090 } else { 1091 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1092 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1093 mcode_data[mcode_data[i] * 2])); 1094 word++; 1095 } 1096 } 1097 1098 /* 1099 * Set 'word' for later use to clear the rest of memory and save 1100 * the expanded mcode size. 1101 */ 1102 word *= 2; 1103 adw_mcode_expanded_size = word; 1104 1105 /* 1106 * Clear the rest of the Internal RAM. 1107 */ 1108 for (; word < adw_memsize; word += 2) { 1109 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1110 } 1111 1112 /* 1113 * Verify the microcode checksum. 1114 */ 1115 sum = 0; 1116 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1117 1118 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1119 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1120 } 1121 1122 if (sum != mcode_chksum) { 1123 return ADW_IERR_MCODE_CHKSUM; 1124 } 1125 1126 /* 1127 * Restore the RISC memory BIOS region. 1128 */ 1129 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1130 if(chip_type == ADW_CHIP_ASC3550) { 1131 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1132 bios_mem[i]); 1133 } else { 1134 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1135 bios_mem[i]); 1136 } 1137 } 1138 1139 /* 1140 * Calculate and write the microcode code checksum to the microcode 1141 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1142 */ 1143 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1144 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1145 code_sum = 0; 1146 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1147 for (word = begin_addr; word < end_addr; word += 2) { 1148 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1149 } 1150 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1151 1152 /* 1153 * Set the chip type. 1154 */ 1155 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1156 1157 return 0; 1158 } 1159 1160 1161 int 1162 AdwASC3550Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1163 { 1164 u_int16_t scsi_cfg1; 1165 1166 1167 /* 1168 * Determine SCSI_CFG1 Microcode Default Value. 1169 * 1170 * The microcode will set the SCSI_CFG1 register using this value 1171 * after it is started below. 1172 */ 1173 1174 /* Read current SCSI_CFG1 Register value. */ 1175 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1176 1177 /* 1178 * If all three connectors are in use in ASC3550, return an error. 1179 */ 1180 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1181 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1182 return ADW_IERR_ILLEGAL_CONNECTION; 1183 } 1184 1185 /* 1186 * If the cable is reversed all of the SCSI_CTRL register signals 1187 * will be set. Check for and return an error if this condition is 1188 * found. 1189 */ 1190 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1191 return ADW_IERR_REVERSED_CABLE; 1192 } 1193 1194 /* 1195 * If this is a differential board and a single-ended device 1196 * is attached to one of the connectors, return an error. 1197 */ 1198 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1199 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1200 return ADW_IERR_SINGLE_END_DEVICE; 1201 } 1202 1203 /* 1204 * If automatic termination control is enabled, then set the 1205 * termination value based on a table listed in a_condor.h. 1206 * 1207 * If manual termination was specified with an EEPROM setting 1208 * then 'termination' was set-up in AdwInitFromEEPROM() and 1209 * is ready to be 'ored' into SCSI_CFG1. 1210 */ 1211 if (cfg->termination == 0) { 1212 /* 1213 * The software always controls termination by setting 1214 * TERM_CTL_SEL. 1215 * If TERM_CTL_SEL were set to 0, the hardware would set 1216 * termination. 1217 */ 1218 cfg->termination |= ADW_TERM_CTL_SEL; 1219 1220 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1221 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1222 case 0x3: case 0x7: case 0xB: 1223 case 0xD: case 0xE: case 0xF: 1224 cfg->termination |= 1225 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1226 break; 1227 1228 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1229 case 0x1: case 0x5: case 0x9: 1230 case 0xA: case 0xC: 1231 cfg->termination |= ADW_TERM_CTL_H; 1232 break; 1233 1234 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1235 case 0x2: case 0x6: 1236 break; 1237 } 1238 } 1239 1240 /* 1241 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1242 */ 1243 scsi_cfg1 &= ~ADW_TERM_CTL; 1244 1245 /* 1246 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1247 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1248 * referenced, because the hardware internally inverts 1249 * the Termination High and Low bits if TERM_POL is set. 1250 */ 1251 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1252 1253 /* 1254 * Set SCSI_CFG1 Microcode Default Value 1255 * 1256 * Set filter value and possibly modified termination control 1257 * bits in the Microcode SCSI_CFG1 Register Value. 1258 * 1259 * The microcode will set the SCSI_CFG1 register using this value 1260 * after it is started below. 1261 */ 1262 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1263 ADW_FLTR_DISABLE | scsi_cfg1); 1264 1265 /* 1266 * Set MEM_CFG Microcode Default Value 1267 * 1268 * The microcode will set the MEM_CFG register using this value 1269 * after it is started below. 1270 * 1271 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1272 * are defined. 1273 * 1274 * ASC-3550 has 8KB internal memory. 1275 */ 1276 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1277 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1278 1279 return 0; 1280 } 1281 1282 1283 int 1284 AdwASC38C0800Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, 1285 ADW_DVC_CFG *cfg) 1286 { 1287 u_int16_t scsi_cfg1; 1288 1289 1290 /* 1291 * Determine SCSI_CFG1 Microcode Default Value. 1292 * 1293 * The microcode will set the SCSI_CFG1 register using this value 1294 * after it is started below. 1295 */ 1296 1297 /* Read current SCSI_CFG1 Register value. */ 1298 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1299 1300 /* 1301 * If the cable is reversed all of the SCSI_CTRL register signals 1302 * will be set. Check for and return an error if this condition is 1303 * found. 1304 */ 1305 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1306 return ADW_IERR_REVERSED_CABLE; 1307 } 1308 1309 /* 1310 * All kind of combinations of devices attached to one of four 1311 * connectors are acceptable except HVD device attached. 1312 * For example, LVD device can be attached to SE connector while 1313 * SE device attached to LVD connector. 1314 * If LVD device attached to SE connector, it only runs up to 1315 * Ultra speed. 1316 * 1317 * If an HVD device is attached to one of LVD connectors, return 1318 * an error. 1319 * However, there is no way to detect HVD device attached to 1320 * SE connectors. 1321 */ 1322 if (scsi_cfg1 & ADW_HVD) { 1323 return ADW_IERR_HVD_DEVICE; 1324 } 1325 1326 /* 1327 * If either SE or LVD automatic termination control is enabled, then 1328 * set the termination value based on a table listed in a_condor.h. 1329 * 1330 * If manual termination was specified with an EEPROM setting then 1331 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1332 * to be 'ored' into SCSI_CFG1. 1333 */ 1334 if ((cfg->termination & ADW_TERM_SE) == 0) { 1335 /* SE automatic termination control is enabled. */ 1336 switch(scsi_cfg1 & ADW_C_DET_SE) { 1337 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1338 case 0x1: case 0x2: case 0x3: 1339 cfg->termination |= ADW_TERM_SE; 1340 break; 1341 1342 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1343 case 0x0: 1344 cfg->termination |= ADW_TERM_SE_HI; 1345 break; 1346 } 1347 } 1348 1349 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1350 /* LVD automatic termination control is enabled. */ 1351 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1352 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1353 case 0x4: case 0x8: case 0xC: 1354 cfg->termination |= ADW_TERM_LVD; 1355 break; 1356 1357 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1358 case 0x0: 1359 break; 1360 } 1361 } 1362 1363 /* 1364 * Clear any set TERM_SE and TERM_LVD bits. 1365 */ 1366 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1367 1368 /* 1369 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1370 */ 1371 scsi_cfg1 |= (~cfg->termination & 0xF0); 1372 1373 /* 1374 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1375 * HVD/LVD/SE bits and set possibly modified termination control bits 1376 * in the Microcode SCSI_CFG1 Register Value. 1377 */ 1378 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1379 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1380 1381 /* 1382 * Set SCSI_CFG1 Microcode Default Value 1383 * 1384 * Set possibly modified termination control and reset DIS_TERM_DRV 1385 * bits in the Microcode SCSI_CFG1 Register Value. 1386 * 1387 * The microcode will set the SCSI_CFG1 register using this value 1388 * after it is started below. 1389 */ 1390 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1391 1392 /* 1393 * Set MEM_CFG Microcode Default Value 1394 * 1395 * The microcode will set the MEM_CFG register using this value 1396 * after it is started below. 1397 * 1398 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1399 * are defined. 1400 * 1401 * ASC-38C0800 has 16KB internal memory. 1402 */ 1403 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1404 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1405 1406 return 0; 1407 } 1408 1409 1410 int 1411 AdwASC38C1600Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, 1412 ADW_DVC_CFG *cfg) 1413 { 1414 u_int16_t scsi_cfg1; 1415 1416 1417 /* 1418 * Determine SCSI_CFG1 Microcode Default Value. 1419 * 1420 * The microcode will set the SCSI_CFG1 register using this value 1421 * after it is started below. 1422 * Each ASC-38C1600 function has only two cable detect bits. 1423 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1424 */ 1425 1426 /* Read current SCSI_CFG1 Register value. */ 1427 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1428 1429 /* 1430 * If the cable is reversed all of the SCSI_CTRL register signals 1431 * will be set. Check for and return an error if this condition is 1432 * found. 1433 */ 1434 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1435 return ADW_IERR_REVERSED_CABLE; 1436 } 1437 1438 /* 1439 * Each ASC-38C1600 function has two connectors. Only an HVD device 1440 * cannot be connected to either connector. An LVD device or SE device 1441 * may be connected to either connector. If an SE device is connected, 1442 * then at most Ultra speed (20 MHz) can be used on both connectors. 1443 * 1444 * If an HVD device is attached, return an error. 1445 */ 1446 if (scsi_cfg1 & ADW_HVD) { 1447 return ADW_IERR_HVD_DEVICE; 1448 } 1449 1450 /* 1451 * Each function in the ASC-38C1600 uses only the SE cable detect and 1452 * termination because there are two connectors for each function. 1453 * Each function may use either LVD or SE mode. 1454 * Corresponding the SE automatic termination control EEPROM bits are 1455 * used for each function. 1456 * Each function has its own EEPROM. If SE automatic control is enabled 1457 * for the function, then set the termination value based on a table 1458 * listed in adwlib.h. 1459 * 1460 * If manual termination is specified in the EEPROM for the function, 1461 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1462 * ready to be 'ored' into SCSI_CFG1. 1463 */ 1464 if ((cfg->termination & ADW_TERM_SE) == 0) { 1465 /* SE automatic termination control is enabled. */ 1466 switch(scsi_cfg1 & ADW_C_DET_SE) { 1467 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1468 case 0x1: case 0x2: case 0x3: 1469 cfg->termination |= ADW_TERM_SE; 1470 break; 1471 1472 case 0x0: 1473 /* !!!!TODO!!!! */ 1474 // if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1475 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1476 // } 1477 // else 1478 // { 1479 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1480 cfg->termination |= ADW_TERM_SE_HI; 1481 // } 1482 break; 1483 } 1484 } 1485 1486 /* 1487 * Clear any set TERM_SE bits. 1488 */ 1489 scsi_cfg1 &= ~ADW_TERM_SE; 1490 1491 /* 1492 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1493 */ 1494 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1495 1496 /* 1497 * Clear Big Endian and Terminator Polarity bits and set possibly 1498 * modified termination control bits in the Microcode SCSI_CFG1 1499 * Register Value. 1500 */ 1501 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1502 1503 /* 1504 * Set SCSI_CFG1 Microcode Default Value 1505 * 1506 * Set possibly modified termination control bits in the Microcode 1507 * SCSI_CFG1 Register Value. 1508 * 1509 * The microcode will set the SCSI_CFG1 register using this value 1510 * after it is started below. 1511 */ 1512 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1513 1514 /* 1515 * Set MEM_CFG Microcode Default Value 1516 * 1517 * The microcode will set the MEM_CFG register using this value 1518 * after it is started below. 1519 * 1520 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1521 * are defined. 1522 * 1523 * ASC-38C1600 has 32KB internal memory. 1524 */ 1525 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1526 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1527 1528 return 0; 1529 } 1530 1531 1532 /* 1533 * Read EEPROM configuration into the specified buffer. 1534 * 1535 * Return a checksum based on the EEPROM configuration read. 1536 */ 1537 u_int16_t 1538 AdwGetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, 1539 ADW_EEPROM *cfg_buf) 1540 { 1541 u_int16_t wval, chksum; 1542 u_int16_t *wbuf; 1543 int eep_addr; 1544 1545 1546 wbuf = (u_int16_t *) cfg_buf; 1547 chksum = 0; 1548 1549 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN; 1550 eep_addr < ADW_EEP_DVC_CFG_END; 1551 eep_addr++, wbuf++) { 1552 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1553 chksum += wval; 1554 *wbuf = wval; 1555 } 1556 1557 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1558 wbuf++; 1559 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN; 1560 eep_addr < ADW_EEP_MAX_WORD_ADDR; 1561 eep_addr++, wbuf++) { 1562 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1563 } 1564 1565 return chksum; 1566 } 1567 1568 1569 /* 1570 * Read the EEPROM from specified location 1571 */ 1572 u_int16_t 1573 AdwReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, int eep_word_addr) 1574 { 1575 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1576 ADW_EEP_CMD_READ | eep_word_addr); 1577 AdwWaitEEPCmd(iot, ioh); 1578 1579 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1580 } 1581 1582 1583 /* 1584 * Wait for EEPROM command to complete 1585 */ 1586 void 1587 AdwWaitEEPCmd(bus_space_tag_t iot, bus_space_handle_t ioh) 1588 { 1589 int eep_delay_ms; 1590 1591 1592 for (eep_delay_ms = 0; eep_delay_ms < ADW_EEP_DELAY_MS; eep_delay_ms++){ 1593 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1594 ADW_EEP_CMD_DONE) { 1595 break; 1596 } 1597 AdwSleepMilliSecond(1); 1598 } 1599 1600 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1601 } 1602 1603 1604 /* 1605 * Write the EEPROM from 'cfg_buf'. 1606 */ 1607 void 1608 AdwSetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, 1609 ADW_EEPROM *cfg_buf) 1610 { 1611 u_int16_t *wbuf; 1612 u_int16_t addr, chksum; 1613 1614 1615 wbuf = (u_int16_t *) cfg_buf; 1616 chksum = 0; 1617 1618 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ADW_EEP_CMD_WRITE_ABLE); 1619 AdwWaitEEPCmd(iot, ioh); 1620 1621 /* 1622 * Write EEPROM from word 0 to word 20 1623 */ 1624 for (addr = ADW_EEP_DVC_CFG_BEGIN; 1625 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) { 1626 chksum += *wbuf; 1627 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1628 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1629 ADW_EEP_CMD_WRITE | addr); 1630 AdwWaitEEPCmd(iot, ioh); 1631 AdwSleepMilliSecond(ADW_EEP_DELAY_MS); 1632 } 1633 1634 /* 1635 * Write EEPROM checksum at word 21 1636 */ 1637 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1638 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1639 ADW_EEP_CMD_WRITE | addr); 1640 AdwWaitEEPCmd(iot, ioh); 1641 wbuf++; /* skip over check_sum */ 1642 1643 /* 1644 * Write EEPROM OEM name at words 22 to 29 1645 */ 1646 for (addr = ADW_EEP_DVC_CTL_BEGIN; 1647 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1648 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1649 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1650 ADW_EEP_CMD_WRITE | addr); 1651 AdwWaitEEPCmd(iot, ioh); 1652 } 1653 1654 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1655 ADW_EEP_CMD_WRITE_DISABLE); 1656 AdwWaitEEPCmd(iot, ioh); 1657 1658 return; 1659 } 1660 1661 1662 /* 1663 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1664 * 1665 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1666 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1667 * RISC to notify it a new command is ready to be executed. 1668 * 1669 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1670 * set to SCSI_MAX_RETRY. 1671 * 1672 * Return: 1673 * ADW_SUCCESS(1) - The request was successfully queued. 1674 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1675 * request completes. 1676 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1677 * host IC error. 1678 */ 1679 int 1680 AdwExeScsiQueue(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 1681 { 1682 bus_space_tag_t iot = sc->sc_iot; 1683 bus_space_handle_t ioh = sc->sc_ioh; 1684 ADW_CCB *ccb; 1685 long req_size; 1686 u_int32_t req_paddr; 1687 ADW_CARRIER *new_carrp; 1688 1689 /* 1690 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1691 */ 1692 if (scsiq->target_id > ADW_MAX_TID) { 1693 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1694 scsiq->done_status = QD_WITH_ERROR; 1695 return ADW_ERROR; 1696 } 1697 1698 /* 1699 * Beginning of CRITICAL SECTION: ASSUME splbio() in effect 1700 */ 1701 1702 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1703 1704 /* 1705 * Allocate a carrier and initialize fields. 1706 */ 1707 if ((new_carrp = sc->carr_freelist) == NULL) { 1708 return ADW_BUSY; 1709 } 1710 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1711 ADW_GET_CARRP(new_carrp->next_ba)); 1712 sc->carr_pending_cnt++; 1713 1714 /* 1715 * Set the carrier to be a stopper by setting 'next_ba' 1716 * to the stopper value. The current stopper will be changed 1717 * below to point to the new stopper. 1718 */ 1719 new_carrp->next_ba = ADW_CQ_STOPPER; 1720 1721 req_size = sizeof(ADW_SCSI_REQ_Q); 1722 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1723 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1724 1725 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1726 scsiq->scsiq_rptr = req_paddr; 1727 1728 /* 1729 * Every ADW_SCSI_REQ_Q.carr_ba is byte swapped to little-endian 1730 * order during initialization. 1731 */ 1732 scsiq->carr_ba = sc->icq_sp->carr_ba; 1733 scsiq->carr_va = sc->icq_sp->carr_ba; 1734 1735 /* 1736 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1737 * the microcode. The newly allocated stopper will become the new 1738 * stopper. 1739 */ 1740 sc->icq_sp->areq_ba = req_paddr; 1741 1742 /* 1743 * Set the 'next_ba' pointer for the old stopper to be the 1744 * physical address of the new stopper. The RISC can only 1745 * follow physical addresses. 1746 */ 1747 sc->icq_sp->next_ba = new_carrp->carr_ba; 1748 1749 #if ADW_DEBUG 1750 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1751 sc->icq_sp->carr_id, 1752 sc->icq_sp->carr_ba, 1753 sc->icq_sp->areq_ba, 1754 sc->icq_sp->next_ba); 1755 #endif 1756 /* 1757 * Set the host adapter stopper pointer to point to the new carrier. 1758 */ 1759 sc->icq_sp = new_carrp; 1760 1761 if (sc->chip_type == ADW_CHIP_ASC3550 || 1762 sc->chip_type == ADW_CHIP_ASC38C0800) { 1763 /* 1764 * Tickle the RISC to tell it to read its Command Queue Head 1765 * pointer. 1766 */ 1767 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1768 if (sc->chip_type == ADW_CHIP_ASC3550) { 1769 /* 1770 * Clear the tickle value. In the ASC-3550 the RISC flag 1771 * command 'clr_tickle_a' does not work unless the host 1772 * value is cleared. 1773 */ 1774 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1775 ADW_TICKLE_NOP); 1776 } 1777 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1778 /* 1779 * Notify the RISC a carrier is ready by writing the physical 1780 * address of the new carrier stopper to the COMMA register. 1781 */ 1782 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1783 new_carrp->carr_ba); 1784 } 1785 1786 /* 1787 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1788 */ 1789 1790 return ADW_SUCCESS; 1791 } 1792 1793 1794 void 1795 AdwResetChip(bus_space_tag_t iot, bus_space_handle_t ioh) 1796 { 1797 1798 /* 1799 * Reset Chip. 1800 */ 1801 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1802 ADW_CTRL_REG_CMD_RESET); 1803 AdwSleepMilliSecond(100); 1804 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1805 ADW_CTRL_REG_CMD_WR_IO_REG); 1806 } 1807 1808 1809 /* 1810 * Reset SCSI Bus and purge all outstanding requests. 1811 * 1812 * Return Value: 1813 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1814 * ADW_FALSE(0) - Microcode command failed. 1815 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1816 * may be hung which requires driver recovery. 1817 */ 1818 int 1819 AdwResetCCB(ADW_SOFTC *sc) 1820 { 1821 int status; 1822 1823 /* 1824 * Send the SCSI Bus Reset idle start idle command which asserts 1825 * the SCSI Bus Reset signal. 1826 */ 1827 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1828 if (status != ADW_TRUE) { 1829 return status; 1830 } 1831 1832 /* 1833 * Delay for the specified SCSI Bus Reset hold time. 1834 * 1835 * The hold time delay is done on the host because the RISC has no 1836 * microsecond accurate timer. 1837 */ 1838 AdwDelayMicroSecond((u_int16_t) ADW_SCSI_RESET_HOLD_TIME_US); 1839 1840 /* 1841 * Send the SCSI Bus Reset end idle command which de-asserts 1842 * the SCSI Bus Reset signal and purges any pending requests. 1843 */ 1844 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1845 if (status != ADW_TRUE) { 1846 return status; 1847 } 1848 1849 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1850 1851 return status; 1852 } 1853 1854 1855 /* 1856 * Reset chip and SCSI Bus. 1857 * 1858 * Return Value: 1859 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1860 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1861 */ 1862 int 1863 AdwResetSCSIBus(ADW_SOFTC *sc) 1864 { 1865 bus_space_tag_t iot = sc->sc_iot; 1866 bus_space_handle_t ioh = sc->sc_ioh; 1867 int status; 1868 u_int16_t wdtr_able, sdtr_able, ppr_able = 0, tagqng_able; 1869 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1870 u_int16_t bios_sig; 1871 1872 1873 /* 1874 * Save current per TID negotiated values. 1875 */ 1876 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1877 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1878 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1879 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1880 } 1881 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1882 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1883 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1884 max_cmd[tid]); 1885 } 1886 1887 /* 1888 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1889 * by clearing the BIOS signature word. 1890 * The initialization functions assumes a SCSI Bus Reset is not 1891 * needed if the BIOS signature word is present. 1892 */ 1893 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1894 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1895 1896 /* 1897 * Stop chip and reset it. 1898 */ 1899 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1900 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1901 ADW_CTRL_REG_CMD_RESET); 1902 AdwSleepMilliSecond(100); 1903 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1904 ADW_CTRL_REG_CMD_WR_IO_REG); 1905 1906 /* 1907 * Reset Adw Library error code, if any, and try 1908 * re-initializing the chip. 1909 * Then translate initialization return value to status value. 1910 */ 1911 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1912 1913 /* 1914 * Restore the BIOS signature word. 1915 */ 1916 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1917 1918 /* 1919 * Restore per TID negotiated values. 1920 */ 1921 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1922 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1923 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1924 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1925 } 1926 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1927 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1928 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1929 max_cmd[tid]); 1930 } 1931 1932 return status; 1933 } 1934 1935 1936 /* 1937 * Adw Library Interrupt Service Routine 1938 * 1939 * This function is called by a driver's interrupt service routine. 1940 * The function disables and re-enables interrupts. 1941 * 1942 * Note: AdwISR() can be called when interrupts are disabled or even 1943 * when there is no hardware interrupt condition present. It will 1944 * always check for completed idle commands and microcode requests. 1945 * This is an important feature that shouldn't be changed because it 1946 * allows commands to be completed from polling mode loops. 1947 * 1948 * Return: 1949 * ADW_TRUE(1) - interrupt was pending 1950 * ADW_FALSE(0) - no interrupt was pending 1951 */ 1952 int 1953 AdwISR(ADW_SOFTC *sc) 1954 { 1955 bus_space_tag_t iot = sc->sc_iot; 1956 bus_space_handle_t ioh = sc->sc_ioh; 1957 u_int8_t int_stat; 1958 u_int16_t target_bit; 1959 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 1960 u_int32_t irq_next_pa; 1961 ADW_SCSI_REQ_Q *scsiq; 1962 ADW_CCB *ccb; 1963 int s; 1964 1965 1966 s = splbio(); 1967 1968 /* Reading the register clears the interrupt. */ 1969 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 1970 1971 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 1972 ADW_INTR_STATUS_INTRC)) == 0) { 1973 splx(s); 1974 return ADW_FALSE; 1975 } 1976 1977 /* 1978 * Notify the driver of an asynchronous microcode condition by 1979 * calling the ADW_SOFTC.async_callback function. The function 1980 * is passed the microcode ADW_MC_INTRB_CODE byte value. 1981 */ 1982 if (int_stat & ADW_INTR_STATUS_INTRB) { 1983 u_int8_t intrb_code; 1984 1985 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 1986 1987 if (sc->chip_type == ADW_CHIP_ASC3550 || 1988 sc->chip_type == ADW_CHIP_ASC38C0800) { 1989 if (intrb_code == ADW_ASYNC_CARRIER_READY_FAILURE && 1990 sc->carr_pending_cnt != 0) { 1991 ADW_WRITE_BYTE_REGISTER(iot, ioh, 1992 IOPB_TICKLE, ADW_TICKLE_A); 1993 if (sc->chip_type == ADW_CHIP_ASC3550) { 1994 ADW_WRITE_BYTE_REGISTER(iot, ioh, 1995 IOPB_TICKLE, ADW_TICKLE_NOP); 1996 } 1997 } 1998 } 1999 2000 if (sc->async_callback != 0) { 2001 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code); 2002 } 2003 } 2004 2005 /* 2006 * Check if the IRQ stopper carrier contains a completed request. 2007 */ 2008 while (((irq_next_pa = sc->irq_sp->next_ba) & ADW_RQ_DONE) != 0) 2009 { 2010 #if ADW_DEBUG 2011 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2012 sc->irq_sp->carr_id, 2013 sc->irq_sp->carr_ba, 2014 sc->irq_sp->areq_ba, 2015 sc->irq_sp->next_ba); 2016 #endif 2017 /* 2018 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2019 * structure. 2020 * The RISC will have set 'areq_ba' to a virtual address. 2021 * 2022 * The firmware will have copied the ADW_SCSI_REQ_Q.ccb_ptr 2023 * field to the carrier ADW_CARRIER.areq_ba field. 2024 * The conversion below complements the conversion of 2025 * ADW_SCSI_REQ_Q.ccb_ptr' in AdwExeScsiQueue(). 2026 */ 2027 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2028 scsiq = &ccb->scsiq; 2029 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2030 2031 /* 2032 * Request finished with good status and the queue was not 2033 * DMAed to host memory by the firmware. Set all status fields 2034 * to indicate good status. 2035 */ 2036 if ((irq_next_pa & ADW_RQ_GOOD) != 0) { 2037 scsiq->done_status = QD_NO_ERROR; 2038 scsiq->host_status = scsiq->scsi_status = 0; 2039 scsiq->data_cnt = 0L; 2040 } 2041 2042 /* 2043 * Advance the stopper pointer to the next carrier 2044 * ignoring the lower four bits. Free the previous 2045 * stopper carrier. 2046 */ 2047 free_carrp = sc->irq_sp; 2048 sc->irq_sp = ADW_CARRIER_VADDR(sc, ADW_GET_CARRP(irq_next_pa)); 2049 2050 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0 2051 : sc->carr_freelist->carr_ba; 2052 sc->carr_freelist = free_carrp; 2053 sc->carr_pending_cnt--; 2054 2055 target_bit = ADW_TID_TO_TIDMASK(scsiq->target_id); 2056 2057 /* 2058 * Clear request microcode control flag. 2059 */ 2060 scsiq->cntl = 0; 2061 2062 /* 2063 * Check Condition handling 2064 */ 2065 /* 2066 * If the command that completed was a SCSI INQUIRY and 2067 * LUN 0 was sent the command, then process the INQUIRY 2068 * command information for the device. 2069 */ 2070 if (scsiq->done_status == QD_NO_ERROR && 2071 scsiq->cdb[0] == INQUIRY && 2072 scsiq->target_lun == 0) { 2073 AdwInquiryHandling(sc, scsiq); 2074 } 2075 2076 /* 2077 * Notify the driver of the completed request by passing 2078 * the ADW_SCSI_REQ_Q pointer to its callback function. 2079 */ 2080 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq); 2081 /* 2082 * Note: After the driver callback function is called, 'scsiq' 2083 * can no longer be referenced. 2084 * 2085 * Fall through and continue processing other completed 2086 * requests... 2087 */ 2088 } 2089 2090 splx(s); 2091 2092 return ADW_TRUE; 2093 } 2094 2095 2096 /* 2097 * Send an idle command to the chip and wait for completion. 2098 * 2099 * Command completion is polled for once per microsecond. 2100 * 2101 * The function can be called from anywhere including an interrupt handler. 2102 * But the function is not re-entrant, so it uses the splbio/splx() 2103 * functions to prevent reentrancy. 2104 * 2105 * Return Values: 2106 * ADW_TRUE - command completed successfully 2107 * ADW_FALSE - command failed 2108 * ADW_ERROR - command timed out 2109 */ 2110 int 2111 AdwSendIdleCmd(ADW_SOFTC *sc, u_int16_t idle_cmd, u_int32_t idle_cmd_parameter) 2112 { 2113 bus_space_tag_t iot = sc->sc_iot; 2114 bus_space_handle_t ioh = sc->sc_ioh; 2115 u_int16_t result; 2116 u_int32_t i, j, s; 2117 2118 s = splbio(); 2119 2120 /* 2121 * Clear the idle command status which is set by the microcode 2122 * to a non-zero value to indicate when the command is completed. 2123 */ 2124 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2125 2126 /* 2127 * Write the idle command value after the idle command parameter 2128 * has been written to avoid a race condition. If the order is not 2129 * followed, the microcode may process the idle command before the 2130 * parameters have been written to LRAM. 2131 */ 2132 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2133 idle_cmd_parameter); 2134 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2135 2136 /* 2137 * Tickle the RISC to tell it to process the idle command. 2138 */ 2139 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2140 if (sc->chip_type == ADW_CHIP_ASC3550) { 2141 /* 2142 * Clear the tickle value. In the ASC-3550 the RISC flag 2143 * command 'clr_tickle_b' does not work unless the host 2144 * value is cleared. 2145 */ 2146 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2147 } 2148 2149 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2150 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2151 /* Poll once each microsecond for command completion. */ 2152 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2153 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2154 result); 2155 if (result != 0) { 2156 splx(s); 2157 return result; 2158 } 2159 AdwDelayMicroSecond(1); 2160 } 2161 } 2162 2163 splx(s); 2164 return ADW_ERROR; 2165 } 2166 2167 2168 /* 2169 * Inquiry Information Byte 7 Handling 2170 * 2171 * Handle SCSI Inquiry Command information for a device by setting 2172 * microcode operating variables that affect WDTR, SDTR, and Tag 2173 * Queuing. 2174 */ 2175 void 2176 AdwInquiryHandling(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 2177 { 2178 #ifndef FAILSAFE 2179 bus_space_tag_t iot = sc->sc_iot; 2180 bus_space_handle_t ioh = sc->sc_ioh; 2181 u_int8_t tid; 2182 ADW_SCSI_INQUIRY *inq; 2183 u_int16_t tidmask; 2184 u_int16_t cfg_word; 2185 2186 2187 /* 2188 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2189 * to be available. 2190 * 2191 * If less than 8 bytes of INQUIRY information were requested or less 2192 * than 8 bytes were transferred, then return. cdb[4] is the request 2193 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2194 * microcode to the transfer residual count. 2195 */ 2196 2197 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2198 return; 2199 } 2200 2201 tid = scsiq->target_id; 2202 2203 inq = (ADW_SCSI_INQUIRY *) scsiq->vdata_addr; 2204 2205 /* 2206 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2207 */ 2208 if ((inq->rsp_data_fmt < 2) /*SCSI-1 | CCS*/ && 2209 (inq->ansi_apr_ver < 2)) { 2210 return; 2211 } else { 2212 /* 2213 * INQUIRY Byte 7 Handling 2214 * 2215 * Use a device's INQUIRY byte 7 to determine whether it 2216 * supports WDTR, SDTR, and Tag Queuing. If the feature 2217 * is enabled in the EEPROM and the device supports the 2218 * feature, then enable it in the microcode. 2219 */ 2220 2221 tidmask = ADW_TID_TO_TIDMASK(tid); 2222 2223 /* 2224 * Wide Transfers 2225 * 2226 * If the EEPROM enabled WDTR for the device and the device 2227 * supports wide bus (16 bit) transfers, then turn on the 2228 * device's 'wdtr_able' bit and write the new value to the 2229 * microcode. 2230 */ 2231 #ifdef SCSI_ADW_WDTR_DISABLE 2232 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2233 #endif /* SCSI_ADW_WDTR_DISABLE */ 2234 if ((sc->wdtr_able & tidmask) && inq->WBus16) { 2235 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2236 cfg_word); 2237 if ((cfg_word & tidmask) == 0) { 2238 cfg_word |= tidmask; 2239 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2240 cfg_word); 2241 2242 /* 2243 * Clear the microcode "SDTR negotiation" and 2244 * "WDTR negotiation" done indicators for the 2245 * target to cause it to negotiate with the new 2246 * setting set above. 2247 * WDTR when accepted causes the target to enter 2248 * asynchronous mode, so SDTR must be negotiated 2249 */ 2250 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2251 cfg_word); 2252 cfg_word &= ~tidmask; 2253 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2254 cfg_word); 2255 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2256 cfg_word); 2257 cfg_word &= ~tidmask; 2258 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2259 cfg_word); 2260 } 2261 } 2262 2263 /* 2264 * Synchronous Transfers 2265 * 2266 * If the EEPROM enabled SDTR for the device and the device 2267 * supports synchronous transfers, then turn on the device's 2268 * 'sdtr_able' bit. Write the new value to the microcode. 2269 */ 2270 #ifdef SCSI_ADW_SDTR_DISABLE 2271 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2272 #endif /* SCSI_ADW_SDTR_DISABLE */ 2273 if ((sc->sdtr_able & tidmask) && inq->Sync) { 2274 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2275 if ((cfg_word & tidmask) == 0) { 2276 cfg_word |= tidmask; 2277 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2278 cfg_word); 2279 2280 /* 2281 * Clear the microcode "SDTR negotiation" 2282 * done indicator for the target to cause it 2283 * to negotiate with the new setting set above. 2284 */ 2285 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2286 cfg_word); 2287 cfg_word &= ~tidmask; 2288 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2289 cfg_word); 2290 } 2291 } 2292 /* 2293 * If the Inquiry data included enough space for the SPI-3 2294 * Clocking field, then check if DT mode is supported. 2295 */ 2296 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2297 (scsiq->cdb[4] >= 57 || 2298 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2299 /* 2300 * PPR (Parallel Protocol Request) Capable 2301 * 2302 * If the device supports DT mode, then it must be 2303 * PPR capable. 2304 * The PPR message will be used in place of the SDTR 2305 * and WDTR messages to negotiate synchronous speed 2306 * and offset, transfer width, and protocol options. 2307 */ 2308 if((inq->Clocking) & INQ_CLOCKING_DT_ONLY){ 2309 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2310 sc->ppr_able); 2311 sc->ppr_able |= tidmask; 2312 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2313 sc->ppr_able); 2314 } 2315 } 2316 2317 /* 2318 * If the EEPROM enabled Tag Queuing for the device and the 2319 * device supports Tag Queueing, then turn on the device's 2320 * 'tagqng_enable' bit in the microcode and set the microcode 2321 * maximum command count to the ADW_SOFTC 'max_dvc_qng' 2322 * value. 2323 * 2324 * Tag Queuing is disabled for the BIOS which runs in polled 2325 * mode and would see no benefit from Tag Queuing. Also by 2326 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2327 * bugs will at least work with the BIOS. 2328 */ 2329 #ifdef SCSI_ADW_TAGQ_DISABLE 2330 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2331 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2332 if ((sc->tagqng_able & tidmask) && inq->CmdQue) { 2333 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2334 cfg_word); 2335 cfg_word |= tidmask; 2336 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2337 cfg_word); 2338 2339 ADW_WRITE_BYTE_LRAM(iot, ioh, 2340 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2341 sc->max_dvc_qng); 2342 } 2343 } 2344 #endif /* FAILSAFE */ 2345 } 2346 2347 2348 void 2349 AdwSleepMilliSecond(u_int32_t n) 2350 { 2351 2352 DELAY(n * 1000); 2353 } 2354 2355 2356 void 2357 AdwDelayMicroSecond(u_int32_t n) 2358 { 2359 2360 DELAY(n); 2361 } 2362 2363