1 /* $OpenBSD: aic7xxx.c,v 1.84 2010/03/14 14:37:01 krw Exp $ */ 2 /* $NetBSD: aic7xxx.c,v 1.108 2003/11/02 11:07:44 wiz Exp $ */ 3 4 /* 5 * Core routines and tables shareable across OS platforms. 6 * 7 * Copyright (c) 1994-2002 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * $Id: aic7xxx.c,v 1.84 2010/03/14 14:37:01 krw Exp $ 44 */ 45 /* 46 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 47 */ 48 49 #include <sys/cdefs.h> 50 /* __FBSDID("$FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.100 2004/05/11 20:39:46 gibbs Exp $"); */ 51 52 #include <dev/ic/aic7xxx_openbsd.h> 53 #ifdef SMALL_KERNEL 54 #define IO_EXPAND 55 #endif 56 #include <dev/ic/aic7xxx_inline.h> 57 #include <dev/microcode/aic7xxx/aicasm_insformat.h> 58 59 /****************************** Softc Data ************************************/ 60 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 61 62 /***************************** Lookup Tables **********************************/ 63 char *ahc_chip_names[] = 64 { 65 "NONE", 66 "aic7770", 67 "aic7850", 68 "aic7855", 69 "aic7859", 70 "aic7860", 71 "aic7870", 72 "aic7880", 73 "aic7895", 74 "aic7895C", 75 "aic7890/91", 76 "aic7896/97", 77 "aic7892", 78 "aic7899" 79 }; 80 81 /* 82 * Hardware error codes. 83 */ 84 struct ahc_hard_error_entry { 85 uint8_t errno; 86 char *errmesg; 87 }; 88 89 #if !defined(SMALL_KERNEL) 90 static struct ahc_hard_error_entry ahc_hard_errors[] = { 91 { ILLHADDR, "Illegal Host Access" }, 92 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 93 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 94 { SQPARERR, "Sequencer Parity Error" }, 95 { DPARERR, "Data-path Parity Error" }, 96 { MPARERR, "Scratch or SCB Memory Parity Error" }, 97 { PCIERRSTAT, "PCI Error detected" }, 98 { CIOPARERR, "CIOBUS Parity Error" }, 99 }; 100 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 101 #endif /* !defined(SMALL_KERNEL) */ 102 103 static struct ahc_phase_table_entry ahc_phase_table[] = 104 { 105 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 106 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 107 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 108 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 109 { P_COMMAND, MSG_NOOP, "in Command phase" }, 110 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 111 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 112 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 113 { P_BUSFREE, MSG_NOOP, "while idle" }, 114 { 0, MSG_NOOP, "in unknown phase" } 115 }; 116 117 /* 118 * In most cases we only wish to itterate over real phases, so 119 * exclude the last element from the count. 120 */ 121 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 122 123 /* 124 * Valid SCSIRATE values. (p. 3-17) 125 * Provides a mapping of transfer periods in ns to the proper value to 126 * stick in the scsixfer reg. 127 */ 128 static struct ahc_syncrate ahc_syncrates[] = 129 { 130 /* ultra2 fast/ultra period rate */ 131 { 0x42, 0x000, 9, "80.0" }, 132 { 0x03, 0x000, 10, "40.0" }, 133 { 0x04, 0x000, 11, "33.0" }, 134 { 0x05, 0x100, 12, "20.0" }, 135 { 0x06, 0x110, 15, "16.0" }, 136 { 0x07, 0x120, 18, "13.4" }, 137 { 0x08, 0x000, 25, "10.0" }, 138 { 0x19, 0x010, 31, "8.0" }, 139 { 0x1a, 0x020, 37, "6.67" }, 140 { 0x1b, 0x030, 43, "5.7" }, 141 { 0x1c, 0x040, 50, "5.0" }, 142 { 0x00, 0x050, 56, "4.4" }, 143 { 0x00, 0x060, 62, "4.0" }, 144 { 0x00, 0x070, 68, "3.6" }, 145 { 0x00, 0x000, 0, NULL } 146 }; 147 148 /* Our Sequencer Program */ 149 #include <dev/microcode/aic7xxx/aic7xxx_seq.h> 150 151 /**************************** Function Declarations ***************************/ 152 static void ahc_force_renegotiation(struct ahc_softc *ahc, 153 struct ahc_devinfo *devinfo); 154 static struct ahc_tmode_tstate* 155 ahc_alloc_tstate(struct ahc_softc *ahc, 156 u_int scsi_id, char channel); 157 #ifdef AHC_TARGET_MODE 158 static void ahc_free_tstate(struct ahc_softc *ahc, 159 u_int scsi_id, char channel, int force); 160 #endif 161 static struct ahc_syncrate* 162 ahc_devlimited_syncrate(struct ahc_softc *ahc, 163 struct ahc_initiator_tinfo *, 164 u_int *period, 165 u_int *ppr_options, 166 role_t role); 167 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 168 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 169 struct ahc_devinfo *devinfo); 170 static void ahc_assert_atn(struct ahc_softc *ahc); 171 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 172 struct ahc_devinfo *devinfo, 173 struct scb *scb); 174 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo); 176 static void ahc_construct_sdtr(struct ahc_softc *ahc, 177 struct ahc_devinfo *devinfo, 178 u_int period, u_int offset); 179 static void ahc_construct_wdtr(struct ahc_softc *ahc, 180 struct ahc_devinfo *devinfo, 181 u_int bus_width); 182 static void ahc_construct_ppr(struct ahc_softc *ahc, 183 struct ahc_devinfo *devinfo, 184 u_int period, u_int offset, 185 u_int bus_width, u_int ppr_options); 186 static void ahc_clear_msg_state(struct ahc_softc *ahc); 187 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 188 static void ahc_handle_message_phase(struct ahc_softc *ahc); 189 typedef enum { 190 AHCMSG_1B, 191 AHCMSG_2B, 192 AHCMSG_EXT 193 } ahc_msgtype; 194 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 195 u_int msgval, int full); 196 static int ahc_parse_msg(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 201 struct ahc_devinfo *devinfo); 202 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 203 static void ahc_handle_devreset(struct ahc_softc *ahc, 204 struct ahc_devinfo *devinfo, 205 cam_status status, char *message, 206 int verbose_level); 207 #ifdef AHC_TARGET_MODE 208 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 209 struct ahc_devinfo *devinfo, 210 struct scb *scb); 211 #endif 212 213 //static bus_dmamap_callback_t ahc_dmamap_cb; 214 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 215 static int ahc_init_scbdata(struct ahc_softc *ahc); 216 static void ahc_fini_scbdata(struct ahc_softc *ahc); 217 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 218 struct scb *prev_scb, 219 struct scb *scb); 220 static int ahc_qinfifo_count(struct ahc_softc *ahc); 221 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 222 u_int prev, u_int scbptr); 223 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 224 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 225 u_int scbpos, u_int prev); 226 static void ahc_reset_current_bus(struct ahc_softc *ahc); 227 #ifdef AHC_DUMP_SEQ 228 static void ahc_dumpseq(struct ahc_softc *ahc); 229 #endif 230 static int ahc_loadseq(struct ahc_softc *ahc); 231 static int ahc_check_patch(struct ahc_softc *ahc, 232 const struct patch **start_patch, 233 u_int start_instr, u_int *skip_addr); 234 static void ahc_download_instr(struct ahc_softc *ahc, 235 u_int instrptr, uint8_t *dconsts); 236 #ifdef AHC_TARGET_MODE 237 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 238 struct ahc_tmode_lstate *lstate, 239 u_int initiator_id, 240 u_int event_type, 241 u_int event_arg); 242 static void ahc_update_scsiid(struct ahc_softc *ahc, 243 u_int targid_mask); 244 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 245 struct target_cmd *cmd); 246 #endif 247 248 /************************** Added for porting to NetBSD ***********************/ 249 static int ahc_createdmamem(bus_dma_tag_t tag, 250 int size, 251 int flags, 252 bus_dmamap_t *mapp, 253 caddr_t *vaddr, 254 bus_addr_t *baddr, 255 bus_dma_segment_t *seg, 256 int *nseg, 257 const char *myname, const char *what); 258 static void ahc_freedmamem(bus_dma_tag_t tag, 259 int size, 260 bus_dmamap_t map, 261 caddr_t vaddr, 262 bus_dma_segment_t *seg, 263 int nseg); 264 265 /************************* Sequencer Execution Control ************************/ 266 /* 267 * Restart the sequencer program from address zero 268 */ 269 void 270 ahc_restart(struct ahc_softc *ahc) 271 { 272 273 ahc_pause(ahc); 274 275 /* No more pending messages. */ 276 ahc_clear_msg_state(ahc); 277 278 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 279 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 280 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 281 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 282 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 283 ahc_outb(ahc, SAVED_LUN, 0xFF); 284 285 /* 286 * Ensure that the sequencer's idea of TQINPOS 287 * matches our own. The sequencer increments TQINPOS 288 * only after it sees a DMA complete and a reset could 289 * occur before the increment leaving the kernel to believe 290 * the command arrived but the sequencer to not. 291 */ 292 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 293 294 /* Always allow reselection */ 295 ahc_outb(ahc, SCSISEQ, 296 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 297 if ((ahc->features & AHC_CMD_CHAN) != 0) { 298 /* Ensure that no DMA operations are in progress */ 299 ahc_outb(ahc, CCSCBCNT, 0); 300 ahc_outb(ahc, CCSGCTL, 0); 301 ahc_outb(ahc, CCSCBCTL, 0); 302 } 303 /* 304 * If we were in the process of DMA'ing SCB data into 305 * an SCB, replace that SCB on the free list. This prevents 306 * an SCB leak. 307 */ 308 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 309 ahc_add_curscb_to_free_list(ahc); 310 ahc_outb(ahc, SEQ_FLAGS2, 311 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 312 } 313 314 /* 315 * Clear any pending sequencer interrupt. It is no 316 * longer relevant since we're resetting the Program 317 * Counter. 318 */ 319 ahc_outb(ahc, CLRINT, CLRSEQINT); 320 321 ahc_outb(ahc, MWI_RESIDUAL, 0); 322 ahc_outb(ahc, SEQCTL, ahc->seqctl); 323 ahc_outb(ahc, SEQADDR0, 0); 324 ahc_outb(ahc, SEQADDR1, 0); 325 326 ahc_unpause(ahc); 327 } 328 329 /************************* Input/Output Queues ********************************/ 330 void 331 ahc_run_qoutfifo(struct ahc_softc *ahc) 332 { 333 struct scb *scb; 334 u_int scb_index; 335 336 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 337 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 338 339 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 340 #ifdef __sgi__ 341 if ((ahc->qoutfifonext & 0x1f) == 0x1f) { 342 u_int modnext; 343 u_int32_t *nextp; 344 345 /* 346 * Clear 32 bytes of QOUTFIFO at a time 347 * so that we don't clobber an incoming 348 * byte DMA to the array on architectures 349 * non coherent caches. 350 */ 351 modnext = ahc->qoutfifonext & ~0x1f; 352 nextp = (uint32_t *)(&ahc->qoutfifo[modnext]); 353 *nextp++ = 0xFFFFFFFFUL; 354 *nextp++ = 0xFFFFFFFFUL; 355 *nextp++ = 0xFFFFFFFFUL; 356 *nextp++ = 0xFFFFFFFFUL; 357 *nextp++ = 0xFFFFFFFFUL; 358 *nextp++ = 0xFFFFFFFFUL; 359 *nextp++ = 0xFFFFFFFFUL; 360 *nextp++ = 0xFFFFFFFFUL; 361 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, 362 ahc->shared_data_dmamap, 363 /*offset*/modnext, /*len*/32, 364 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 365 } 366 #else 367 if ((ahc->qoutfifonext & 0x03) == 0x03) { 368 u_int modnext; 369 370 /* 371 * Clear 32bits of QOUTFIFO at a time 372 * so that we don't clobber an incoming 373 * byte DMA to the array on architectures 374 * that only support 32bit load and store 375 * operations. 376 */ 377 modnext = ahc->qoutfifonext & ~0x3; 378 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 379 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, 380 ahc->shared_data_dmamap, 381 /*offset*/modnext, /*len*/4, 382 BUS_DMASYNC_PREREAD); 383 } 384 #endif 385 ahc->qoutfifonext++; 386 387 scb = ahc_lookup_scb(ahc, scb_index); 388 if (scb == NULL) { 389 printf("%s: WARNING no command for scb %d " 390 "(cmdcmplt)\nQOUTPOS = %d\n", 391 ahc_name(ahc), scb_index, 392 (ahc->qoutfifonext - 1) & 0xFF); 393 continue; 394 } 395 396 /* 397 * Save off the residual 398 * if there is one. 399 */ 400 ahc_update_residual(ahc, scb); 401 ahc_done(ahc, scb); 402 } 403 } 404 405 void 406 ahc_run_untagged_queues(struct ahc_softc *ahc) 407 { 408 int i; 409 410 for (i = 0; i < 16; i++) 411 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 412 } 413 414 void 415 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 416 { 417 struct scb *scb; 418 419 if (ahc->untagged_queue_lock != 0) 420 return; 421 422 if ((scb = TAILQ_FIRST(queue)) != NULL 423 && (scb->flags & SCB_ACTIVE) == 0) { 424 scb->flags |= SCB_ACTIVE; 425 ahc_queue_scb(ahc, scb); 426 } 427 } 428 429 /************************* Interrupt Handling *********************************/ 430 void 431 ahc_handle_brkadrint(struct ahc_softc *ahc) 432 { 433 /* 434 * We upset the sequencer :-( 435 * Lookup the error message 436 */ 437 #ifndef SMALL_KERNEL 438 int i; 439 int error; 440 441 error = ahc_inb(ahc, ERROR); 442 for (i = 0; error != 1 && i < num_errors; i++) 443 error >>= 1; 444 if (i >= num_errors) 445 panic("invalid error code"); 446 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 447 ahc_name(ahc), ahc_hard_errors[i].errmesg, 448 ahc_inb(ahc, SEQADDR0) | 449 (ahc_inb(ahc, SEQADDR1) << 8)); 450 451 ahc_dump_card_state(ahc); 452 #endif 453 454 /* Tell everyone that this HBA is no longer available */ 455 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 456 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 457 CAM_NO_HBA); 458 459 /* Disable all interrupt sources by resetting the controller */ 460 ahc_shutdown(ahc); 461 } 462 463 void 464 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 465 { 466 struct scb *scb; 467 struct ahc_devinfo devinfo; 468 u_int scb_index; 469 470 ahc_fetch_devinfo(ahc, &devinfo); 471 472 /* 473 * Clear the upper byte that holds SEQINT status 474 * codes and clear the SEQINT bit. We will unpause 475 * the sequencer, if appropriate, after servicing 476 * the request. 477 */ 478 ahc_outb(ahc, CLRINT, CLRSEQINT); 479 switch (intstat & SEQINT_MASK) { 480 case BAD_STATUS: 481 { 482 struct hardware_scb *hscb; 483 484 /* 485 * Set the default return value to 0 (don't 486 * send sense). The sense code will change 487 * this if needed. 488 */ 489 ahc_outb(ahc, RETURN_1, 0); 490 491 /* 492 * The sequencer will notify us when a command 493 * has an error that would be of interest to 494 * the kernel. This allows us to leave the sequencer 495 * running in the common case of command completes 496 * without error. The sequencer will already have 497 * DMA'd the SCB back up to us, so we can reference 498 * the in kernel copy directly. 499 */ 500 scb_index = ahc_inb(ahc, SCB_TAG); 501 scb = ahc_lookup_scb(ahc, scb_index); 502 if (scb == NULL) { 503 ahc_print_devinfo(ahc, &devinfo); 504 printf("ahc_intr - referenced scb " 505 "not valid during seqint 0x%x scb(%d)\n", 506 intstat, scb_index); 507 ahc_dump_card_state(ahc); 508 panic("for safety"); 509 goto unpause; 510 } 511 512 hscb = scb->hscb; 513 514 /* Don't want to clobber the original sense code */ 515 if ((scb->flags & SCB_SENSE) != 0) { 516 /* 517 * Clear the SCB_SENSE Flag and have 518 * the sequencer do a normal command 519 * complete. 520 */ 521 scb->flags &= ~SCB_SENSE; 522 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 523 break; 524 } 525 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 526 /* Freeze the queue until the client sees the error. */ 527 ahc_freeze_devq(ahc, scb); 528 ahc_freeze_scb(scb); 529 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 530 switch (hscb->shared_data.status.scsi_status) { 531 case SCSI_STATUS_OK: 532 printf("%s: Interrupted for status of 0 (?)\n", 533 ahc_name(ahc)); 534 break; 535 case SCSI_STATUS_CMD_TERMINATED: 536 case SCSI_STATUS_CHECK_COND: 537 { 538 struct ahc_dma_seg *sg; 539 struct scsi_sense *sc; 540 struct ahc_initiator_tinfo *targ_info; 541 struct ahc_tmode_tstate *tstate; 542 struct ahc_transinfo *tinfo; 543 #ifdef AHC_DEBUG 544 if (ahc_debug & AHC_SHOW_SENSE) { 545 ahc_print_path(ahc, scb); 546 printf("SCB %d: requests Check Status\n", 547 scb->hscb->tag); 548 } 549 #endif 550 551 if (ahc_perform_autosense(scb) == 0) 552 break; 553 554 targ_info = ahc_fetch_transinfo(ahc, 555 devinfo.channel, 556 devinfo.our_scsiid, 557 devinfo.target, 558 &tstate); 559 tinfo = &targ_info->curr; 560 sg = scb->sg_list; 561 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 562 /* 563 * Save off the residual if there is one. 564 */ 565 ahc_update_residual(ahc, scb); 566 #ifdef AHC_DEBUG 567 if (ahc_debug & AHC_SHOW_SENSE) { 568 ahc_print_path(ahc, scb); 569 printf("Sending Sense\n"); 570 } 571 #endif 572 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 573 sg->len = ahc_get_sense_bufsize(ahc, scb); 574 sg->len |= AHC_DMA_LAST_SEG; 575 576 /* Fixup byte order */ 577 sg->addr = aic_htole32(sg->addr); 578 sg->len = aic_htole32(sg->len); 579 580 sc->opcode = REQUEST_SENSE; 581 sc->byte2 = 0; 582 if (tinfo->protocol_version <= SCSI_REV_2 583 && SCB_GET_LUN(scb) < 8) 584 sc->byte2 = SCB_GET_LUN(scb) << 5; 585 sc->unused[0] = 0; 586 sc->unused[1] = 0; 587 sc->length = sg->len; 588 sc->control = 0; 589 590 /* 591 * We can't allow the target to disconnect. 592 * This will be an untagged transaction and 593 * having the target disconnect will make this 594 * transaction indistinguishable from outstanding 595 * tagged transactions. 596 */ 597 hscb->control = 0; 598 599 /* 600 * This request sense could be because the 601 * the device lost power or in some other 602 * way has lost our transfer negotiations. 603 * Renegotiate if appropriate. Unit attention 604 * errors will be reported before any data 605 * phases occur. 606 */ 607 if (ahc_get_residual(scb) 608 == ahc_get_transfer_length(scb)) { 609 ahc_update_neg_request(ahc, &devinfo, 610 tstate, targ_info, 611 AHC_NEG_IF_NON_ASYNC); 612 } 613 if (tstate->auto_negotiate & devinfo.target_mask) { 614 hscb->control |= MK_MESSAGE; 615 scb->flags &= ~SCB_NEGOTIATE; 616 scb->flags |= SCB_AUTO_NEGOTIATE; 617 } 618 hscb->cdb_len = sizeof(*sc); 619 hscb->dataptr = sg->addr; 620 hscb->datacnt = sg->len; 621 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 622 hscb->sgptr = aic_htole32(hscb->sgptr); 623 #ifdef __OpenBSD__ 624 bus_dmamap_sync(ahc->parent_dmat, 625 ahc->scb_data->sense_dmamap, 626 (scb - ahc->scb_data->scbarray) * 627 sizeof(struct scsi_sense_data), 628 sizeof(struct scsi_sense_data), 629 BUS_DMASYNC_PREREAD); 630 bus_dmamap_sync(ahc->parent_dmat, 631 scb->sg_map->sg_dmamap, 632 0, scb->sg_map->sg_dmamap->dm_mapsize, 633 BUS_DMASYNC_PREWRITE); 634 bus_dmamap_sync(ahc->parent_dmat, 635 ahc->scb_data->hscb_dmamap, 636 0, ahc->scb_data->hscb_dmamap->dm_mapsize, 637 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 638 #endif 639 scb->sg_count = 1; 640 scb->flags |= SCB_SENSE; 641 ahc_qinfifo_requeue_tail(ahc, scb); 642 ahc_outb(ahc, RETURN_1, SEND_SENSE); 643 /* 644 * Ensure we have enough time to actually 645 * retrieve the sense. 646 */ 647 ahc_scb_timer_reset(scb, 5 * 1000000); 648 break; 649 } 650 default: 651 break; 652 } 653 break; 654 } 655 case NO_MATCH: 656 { 657 /* Ensure we don't leave the selection hardware on */ 658 ahc_outb(ahc, SCSISEQ, 659 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 660 661 printf("%s:%c:%d: no active SCB for reconnecting " 662 "target - issuing BUS DEVICE RESET\n", 663 ahc_name(ahc), devinfo.channel, devinfo.target); 664 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 665 "ARG_1 == 0x%x ACCUM = 0x%x\n", 666 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 667 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 668 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 669 "SINDEX == 0x%x\n", 670 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 671 ahc_index_busy_tcl(ahc, 672 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 673 ahc_inb(ahc, SAVED_LUN))), 674 ahc_inb(ahc, SINDEX)); 675 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 676 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 677 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 678 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 679 ahc_inb(ahc, SCB_CONTROL)); 680 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 681 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 682 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 683 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 684 ahc_dump_card_state(ahc); 685 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 686 ahc->msgout_len = 1; 687 ahc->msgout_index = 0; 688 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 689 ahc_outb(ahc, MSG_OUT, HOST_MSG); 690 ahc_assert_atn(ahc); 691 break; 692 } 693 case SEND_REJECT: 694 { 695 u_int rejbyte = ahc_inb(ahc, ACCUM); 696 printf("%s:%c:%d: Warning - unknown message received from " 697 "target (0x%x). Rejecting\n", 698 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 699 break; 700 } 701 case PROTO_VIOLATION: 702 { 703 ahc_handle_proto_violation(ahc); 704 break; 705 } 706 case IGN_WIDE_RES: 707 ahc_handle_ign_wide_residue(ahc, &devinfo); 708 break; 709 case PDATA_REINIT: 710 ahc_reinitialize_dataptrs(ahc); 711 break; 712 case BAD_PHASE: 713 { 714 u_int lastphase; 715 716 lastphase = ahc_inb(ahc, LASTPHASE); 717 printf("%s:%c:%d: unknown scsi bus phase %x, " 718 "lastphase = 0x%x. Attempting to continue\n", 719 ahc_name(ahc), devinfo.channel, devinfo.target, 720 lastphase, ahc_inb(ahc, SCSISIGI)); 721 break; 722 } 723 case MISSED_BUSFREE: 724 { 725 u_int lastphase; 726 727 lastphase = ahc_inb(ahc, LASTPHASE); 728 printf("%s:%c:%d: Missed busfree. " 729 "Lastphase = 0x%x, Curphase = 0x%x\n", 730 ahc_name(ahc), devinfo.channel, devinfo.target, 731 lastphase, ahc_inb(ahc, SCSISIGI)); 732 ahc_restart(ahc); 733 return; 734 } 735 case HOST_MSG_LOOP: 736 { 737 /* 738 * The sequencer has encountered a message phase 739 * that requires host assistance for completion. 740 * While handling the message phase(s), we will be 741 * notified by the sequencer after each byte is 742 * transferred so we can track bus phase changes. 743 * 744 * If this is the first time we've seen a HOST_MSG_LOOP 745 * interrupt, initialize the state of the host message 746 * loop. 747 */ 748 if (ahc->msg_type == MSG_TYPE_NONE) { 749 u_int bus_phase; 750 751 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 752 if (bus_phase != P_MESGIN 753 && bus_phase != P_MESGOUT) { 754 printf("ahc_intr: HOST_MSG_LOOP bad " 755 "phase 0x%x\n", 756 bus_phase); 757 /* 758 * Probably transitioned to bus free before 759 * we got here. Just punt the message. 760 */ 761 ahc_clear_intstat(ahc); 762 ahc_restart(ahc); 763 return; 764 } 765 766 scb_index = ahc_inb(ahc, SCB_TAG); 767 scb = ahc_lookup_scb(ahc, scb_index); 768 if (devinfo.role == ROLE_INITIATOR) { 769 if (scb == NULL) 770 panic("HOST_MSG_LOOP with " 771 "invalid SCB %x\n", scb_index); 772 773 if (bus_phase == P_MESGOUT) 774 ahc_setup_initiator_msgout(ahc, 775 &devinfo, 776 scb); 777 else { 778 ahc->msg_type = 779 MSG_TYPE_INITIATOR_MSGIN; 780 ahc->msgin_index = 0; 781 } 782 } 783 #ifdef AHC_TARGET_MODE 784 else { 785 if (bus_phase == P_MESGOUT) { 786 ahc->msg_type = 787 MSG_TYPE_TARGET_MSGOUT; 788 ahc->msgin_index = 0; 789 } 790 else 791 ahc_setup_target_msgin(ahc, 792 &devinfo, 793 scb); 794 } 795 #endif 796 } 797 798 ahc_handle_message_phase(ahc); 799 break; 800 } 801 case PERR_DETECTED: 802 { 803 /* 804 * If we've cleared the parity error interrupt 805 * but the sequencer still believes that SCSIPERR 806 * is true, it must be that the parity error is 807 * for the currently presented byte on the bus, 808 * and we are not in a phase (data-in) where we will 809 * eventually ack this byte. Ack the byte and 810 * throw it away in the hope that the target will 811 * take us to message out to deliver the appropriate 812 * error message. 813 */ 814 if ((intstat & SCSIINT) == 0 815 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 816 817 if ((ahc->features & AHC_DT) == 0) { 818 u_int curphase; 819 820 /* 821 * The hardware will only let you ack bytes 822 * if the expected phase in SCSISIGO matches 823 * the current phase. Make sure this is 824 * currently the case. 825 */ 826 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 827 ahc_outb(ahc, LASTPHASE, curphase); 828 ahc_outb(ahc, SCSISIGO, curphase); 829 } 830 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 831 int wait; 832 833 /* 834 * In a data phase. Faster to bitbucket 835 * the data than to individually ack each 836 * byte. This is also the only strategy 837 * that will work with AUTOACK enabled. 838 */ 839 ahc_outb(ahc, SXFRCTL1, 840 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 841 wait = 5000; 842 while (--wait != 0) { 843 if ((ahc_inb(ahc, SCSISIGI) 844 & (CDI|MSGI)) != 0) 845 break; 846 aic_delay(100); 847 } 848 ahc_outb(ahc, SXFRCTL1, 849 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 850 if (wait == 0) { 851 ahc_print_devinfo(ahc, &devinfo); 852 printf("Unable to clear parity error. " 853 "Resetting bus.\n"); 854 scb_index = ahc_inb(ahc, SCB_TAG); 855 scb = ahc_lookup_scb(ahc, scb_index); 856 if (scb != NULL) 857 ahc_set_transaction_status(scb, 858 CAM_UNCOR_PARITY); 859 ahc_reset_channel(ahc, devinfo.channel, 860 /*init reset*/TRUE); 861 } 862 } else { 863 ahc_inb(ahc, SCSIDATL); 864 } 865 } 866 break; 867 } 868 case DATA_OVERRUN: 869 { 870 /* 871 * When the sequencer detects an overrun, it 872 * places the controller in "BITBUCKET" mode 873 * and allows the target to complete its transfer. 874 * Unfortunately, none of the counters get updated 875 * when the controller is in this mode, so we have 876 * no way of knowing how large the overrun was. 877 */ 878 u_int scbindex = ahc_inb(ahc, SCB_TAG); 879 u_int lastphase = ahc_inb(ahc, LASTPHASE); 880 u_int i; 881 882 scb = ahc_lookup_scb(ahc, scbindex); 883 for (i = 0; i < num_phases; i++) { 884 if (lastphase == ahc_phase_table[i].phase) 885 break; 886 } 887 #ifdef AHC_DEBUG 888 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 889 ahc_print_path(ahc, scb); 890 printf("data overrun detected %s." 891 " Tag == 0x%x.\n", 892 ahc_phase_table[i].phasemsg, 893 scb->hscb->tag); 894 ahc_print_path(ahc, scb); 895 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 896 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 897 ahc_get_transfer_length(scb), scb->sg_count); 898 if (scb->sg_count > 0) { 899 for (i = 0; i < scb->sg_count; i++) { 900 901 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 902 i, 903 (aic_le32toh(scb->sg_list[i].len) >> 24 904 & SG_HIGH_ADDR_BITS), 905 aic_le32toh(scb->sg_list[i].addr), 906 aic_le32toh(scb->sg_list[i].len) 907 & AHC_SG_LEN_MASK); 908 } 909 } 910 } 911 #endif 912 /* 913 * Set this and it will take effect when the 914 * target does a command complete. 915 */ 916 ahc_freeze_devq(ahc, scb); 917 if ((scb->flags & SCB_SENSE) == 0) { 918 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 919 } else { 920 scb->flags &= ~SCB_SENSE; 921 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 922 } 923 ahc_freeze_scb(scb); 924 925 if ((ahc->features & AHC_ULTRA2) != 0) { 926 /* 927 * Clear the channel in case we return 928 * to data phase later. 929 */ 930 ahc_outb(ahc, SXFRCTL0, 931 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 932 ahc_outb(ahc, SXFRCTL0, 933 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 934 } 935 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 936 u_int dscommand1; 937 938 /* Ensure HHADDR is 0 for future DMA operations. */ 939 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 940 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 941 ahc_outb(ahc, HADDR, 0); 942 ahc_outb(ahc, DSCOMMAND1, dscommand1); 943 } 944 break; 945 } 946 case MKMSG_FAILED: 947 { 948 u_int scbindex; 949 950 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 951 ahc_name(ahc), devinfo.channel, devinfo.target, 952 devinfo.lun); 953 scbindex = ahc_inb(ahc, SCB_TAG); 954 scb = ahc_lookup_scb(ahc, scbindex); 955 if (scb != NULL) 956 /* 957 * Ensure that we didn't put a second instance of this 958 * SCB into the QINFIFO. 959 */ 960 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 961 SCB_GET_CHANNEL(ahc, scb), 962 SCB_GET_LUN(scb), scb->hscb->tag, 963 ROLE_INITIATOR, /*status*/0, 964 SEARCH_REMOVE); 965 break; 966 } 967 case NO_FREE_SCB: 968 { 969 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 970 ahc_dump_card_state(ahc); 971 panic("for safety"); 972 break; 973 } 974 case SCB_MISMATCH: 975 { 976 u_int scbptr; 977 978 scbptr = ahc_inb(ahc, SCBPTR); 979 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 980 scbptr, ahc_inb(ahc, ARG_1), 981 ahc->scb_data->hscbs[scbptr].tag); 982 ahc_dump_card_state(ahc); 983 panic("for safety"); 984 break; 985 } 986 case OUT_OF_RANGE: 987 { 988 #ifndef SMALL_KERNEL 989 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 990 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 991 "ARG_1 == 0x%x ACCUM = 0x%x\n", 992 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 993 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 994 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 995 "SINDEX == 0x%x\n, A == 0x%x\n", 996 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 997 ahc_index_busy_tcl(ahc, 998 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 999 ahc_inb(ahc, SAVED_LUN))), 1000 ahc_inb(ahc, SINDEX), 1001 ahc_inb(ahc, ACCUM)); 1002 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1003 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 1004 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 1005 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 1006 ahc_inb(ahc, SCB_CONTROL)); 1007 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 1008 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 1009 #endif 1010 ahc_dump_card_state(ahc); 1011 panic("for safety"); 1012 break; 1013 } 1014 default: 1015 printf("ahc_intr: seqint, " 1016 "intstat == 0x%x, scsisigi = 0x%x\n", 1017 intstat, ahc_inb(ahc, SCSISIGI)); 1018 break; 1019 } 1020 unpause: 1021 /* 1022 * The sequencer is paused immediately on 1023 * a SEQINT, so we should restart it when 1024 * we're done. 1025 */ 1026 ahc_unpause(ahc); 1027 } 1028 1029 void 1030 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 1031 { 1032 u_int scb_index; 1033 u_int status0; 1034 u_int status; 1035 struct scb *scb; 1036 char cur_channel; 1037 char intr_channel; 1038 1039 if ((ahc->features & AHC_TWIN) != 0 1040 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 1041 cur_channel = 'B'; 1042 else 1043 cur_channel = 'A'; 1044 intr_channel = cur_channel; 1045 1046 if ((ahc->features & AHC_ULTRA2) != 0) 1047 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 1048 else 1049 status0 = 0; 1050 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1051 if (status == 0 && status0 == 0) { 1052 if ((ahc->features & AHC_TWIN) != 0) { 1053 /* Try the other channel */ 1054 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1055 status = ahc_inb(ahc, SSTAT1) 1056 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1057 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 1058 } 1059 if (status == 0) { 1060 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 1061 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1062 ahc_unpause(ahc); 1063 return; 1064 } 1065 } 1066 1067 /* Make sure the sequencer is in a safe location. */ 1068 ahc_clear_critical_section(ahc); 1069 1070 scb_index = ahc_inb(ahc, SCB_TAG); 1071 scb = ahc_lookup_scb(ahc, scb_index); 1072 if (scb != NULL 1073 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1074 scb = NULL; 1075 1076 if ((ahc->features & AHC_ULTRA2) != 0 1077 && (status0 & IOERR) != 0) { 1078 int now_lvd; 1079 1080 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1081 printf("%s: Transceiver State Has Changed to %s mode\n", 1082 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1083 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1084 /* 1085 * When transitioning to SE mode, the reset line 1086 * glitches, triggering an arbitration bug in some 1087 * Ultra2 controllers. This bug is cleared when we 1088 * assert the reset line. Since a reset glitch has 1089 * already occurred with this transition and a 1090 * transceiver state change is handled just like 1091 * a bus reset anyway, asserting the reset line 1092 * ourselves is safe. 1093 */ 1094 ahc_reset_channel(ahc, intr_channel, 1095 /*Initiate Reset*/now_lvd == 0); 1096 } else if ((status & SCSIRSTI) != 0) { 1097 printf("%s: Someone reset channel %c\n", 1098 ahc_name(ahc), intr_channel); 1099 if (intr_channel != cur_channel) 1100 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1101 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1102 } else if ((status & SCSIPERR) != 0) { 1103 /* 1104 * Determine the bus phase and queue an appropriate message. 1105 * SCSIPERR is latched true as soon as a parity error 1106 * occurs. If the sequencer acked the transfer that 1107 * caused the parity error and the currently presented 1108 * transfer on the bus has correct parity, SCSIPERR will 1109 * be cleared by CLRSCSIPERR. Use this to determine if 1110 * we should look at the last phase the sequencer recorded, 1111 * or the current phase presented on the bus. 1112 */ 1113 struct ahc_devinfo devinfo; 1114 u_int mesg_out; 1115 u_int curphase; 1116 u_int errorphase; 1117 u_int lastphase; 1118 u_int scsirate; 1119 u_int i; 1120 u_int sstat2; 1121 int silent; 1122 1123 lastphase = ahc_inb(ahc, LASTPHASE); 1124 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1125 sstat2 = ahc_inb(ahc, SSTAT2); 1126 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1127 /* 1128 * For all phases save DATA, the sequencer won't 1129 * automatically ack a byte that has a parity error 1130 * in it. So the only way that the current phase 1131 * could be 'data-in' is if the parity error is for 1132 * an already acked byte in the data phase. During 1133 * synchronous data-in transfers, we may actually 1134 * ack bytes before latching the current phase in 1135 * LASTPHASE, leading to the discrepancy between 1136 * curphase and lastphase. 1137 */ 1138 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1139 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1140 errorphase = curphase; 1141 else 1142 errorphase = lastphase; 1143 1144 for (i = 0; i < num_phases; i++) { 1145 if (errorphase == ahc_phase_table[i].phase) 1146 break; 1147 } 1148 mesg_out = ahc_phase_table[i].mesg_out; 1149 silent = FALSE; 1150 if (scb != NULL) { 1151 if (SCB_IS_SILENT(scb)) 1152 silent = TRUE; 1153 else 1154 ahc_print_path(ahc, scb); 1155 scb->flags |= SCB_TRANSMISSION_ERROR; 1156 } else 1157 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1158 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1159 scsirate = ahc_inb(ahc, SCSIRATE); 1160 if (silent == FALSE) { 1161 printf("parity error detected %s. " 1162 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1163 ahc_phase_table[i].phasemsg, 1164 ahc_inw(ahc, SEQADDR0), 1165 scsirate); 1166 if ((ahc->features & AHC_DT) != 0) { 1167 if ((sstat2 & CRCVALERR) != 0) 1168 printf("\tCRC Value Mismatch\n"); 1169 if ((sstat2 & CRCENDERR) != 0) 1170 printf("\tNo terminal CRC packet " 1171 "received\n"); 1172 if ((sstat2 & CRCREQERR) != 0) 1173 printf("\tIllegal CRC packet " 1174 "request\n"); 1175 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1176 printf("\tUnexpected %sDT Data Phase\n", 1177 (scsirate & SINGLE_EDGE) 1178 ? "" : "non-"); 1179 } 1180 } 1181 1182 if ((ahc->features & AHC_DT) != 0 1183 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1184 /* 1185 * This error applies regardless of 1186 * data direction, so ignore the value 1187 * in the phase table. 1188 */ 1189 mesg_out = MSG_INITIATOR_DET_ERR; 1190 } 1191 1192 /* 1193 * We've set the hardware to assert ATN if we 1194 * get a parity error on "in" phases, so all we 1195 * need to do is stuff the message buffer with 1196 * the appropriate message. "In" phases have set 1197 * mesg_out to something other than MSG_NOP. 1198 */ 1199 if (mesg_out != MSG_NOOP) { 1200 if (ahc->msg_type != MSG_TYPE_NONE) 1201 ahc->send_msg_perror = TRUE; 1202 else 1203 ahc_outb(ahc, MSG_OUT, mesg_out); 1204 } 1205 /* 1206 * Force a renegotiation with this target just in 1207 * case we are out of sync for some external reason 1208 * unknown (or unreported) by the target. 1209 */ 1210 ahc_fetch_devinfo(ahc, &devinfo); 1211 ahc_force_renegotiation(ahc, &devinfo); 1212 1213 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1214 ahc_unpause(ahc); 1215 } else if ((status & SELTO) != 0) { 1216 u_int scbptr; 1217 1218 /* Stop the selection */ 1219 ahc_outb(ahc, SCSISEQ, 0); 1220 1221 /* No more pending messages */ 1222 ahc_clear_msg_state(ahc); 1223 1224 /* Clear interrupt state */ 1225 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1226 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1227 1228 /* 1229 * Although the driver does not care about the 1230 * 'Selection in Progress' status bit, the busy 1231 * LED does. SELINGO is only cleared by a successful 1232 * selection, so we must manually clear it to insure 1233 * the LED turns off just incase no future successful 1234 * selections occur (e.g. no devices on the bus). 1235 */ 1236 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1237 1238 scbptr = ahc_inb(ahc, WAITING_SCBH); 1239 ahc_outb(ahc, SCBPTR, scbptr); 1240 scb_index = ahc_inb(ahc, SCB_TAG); 1241 1242 scb = ahc_lookup_scb(ahc, scb_index); 1243 if (scb == NULL) { 1244 printf("%s: ahc_intr - referenced scb not " 1245 "valid during SELTO scb(%d, %d)\n", 1246 ahc_name(ahc), scbptr, scb_index); 1247 ahc_dump_card_state(ahc); 1248 } else { 1249 struct ahc_devinfo devinfo; 1250 #ifdef AHC_DEBUG 1251 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1252 ahc_print_path(ahc, scb); 1253 printf("Saw Selection Timeout for SCB 0x%x\n", 1254 scb_index); 1255 } 1256 #endif 1257 ahc_scb_devinfo(ahc, &devinfo, scb); 1258 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1259 ahc_freeze_devq(ahc, scb); 1260 1261 /* 1262 * Cancel any pending transactions on the device 1263 * now that it seems to be missing. This will 1264 * also revert us to async/narrow transfers until 1265 * we can renegotiate with the device. 1266 */ 1267 ahc_handle_devreset(ahc, &devinfo, 1268 CAM_SEL_TIMEOUT, 1269 "Selection Timeout", 1270 /*verbose_level*/1); 1271 } 1272 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1273 ahc_restart(ahc); 1274 } else if ((status & BUSFREE) != 0 1275 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1276 struct ahc_devinfo devinfo; 1277 u_int lastphase; 1278 u_int saved_scsiid; 1279 u_int saved_lun; 1280 u_int target; 1281 u_int initiator_role_id; 1282 char channel; 1283 int printerror; 1284 1285 /* 1286 * Clear our selection hardware as soon as possible. 1287 * We may have an entry in the waiting Q for this target, 1288 * that is affected by this busfree and we don't want to 1289 * go about selecting the target while we handle the event. 1290 */ 1291 ahc_outb(ahc, SCSISEQ, 1292 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1293 1294 /* 1295 * Disable busfree interrupts and clear the busfree 1296 * interrupt status. We do this here so that several 1297 * bus transactions occur prior to clearing the SCSIINT 1298 * latch. It can take a bit for the clearing to take effect. 1299 */ 1300 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1301 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1302 1303 /* 1304 * Look at what phase we were last in. 1305 * If its message out, chances are pretty good 1306 * that the busfree was in response to one of 1307 * our abort requests. 1308 */ 1309 lastphase = ahc_inb(ahc, LASTPHASE); 1310 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1311 saved_lun = ahc_inb(ahc, SAVED_LUN); 1312 target = SCSIID_TARGET(ahc, saved_scsiid); 1313 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1314 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1315 ahc_compile_devinfo(&devinfo, initiator_role_id, 1316 target, saved_lun, channel, ROLE_INITIATOR); 1317 printerror = 1; 1318 1319 if (lastphase == P_MESGOUT) { 1320 u_int tag; 1321 1322 tag = SCB_LIST_NULL; 1323 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1324 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1325 if (ahc->msgout_buf[ahc->msgout_index - 1] 1326 == MSG_ABORT_TAG) 1327 tag = scb->hscb->tag; 1328 ahc_print_path(ahc, scb); 1329 printf("SCB %d - Abort%s Completed.\n", 1330 scb->hscb->tag, tag == SCB_LIST_NULL ? 1331 "" : " Tag"); 1332 ahc_abort_scbs(ahc, target, channel, 1333 saved_lun, tag, 1334 ROLE_INITIATOR, 1335 CAM_REQ_ABORTED); 1336 printerror = 0; 1337 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1338 MSG_BUS_DEV_RESET, TRUE)) { 1339 #ifdef __FreeBSD__ 1340 /* 1341 * Don't mark the user's request for this BDR 1342 * as completing with CAM_BDR_SENT. CAM3 1343 * specifies CAM_REQ_CMP. 1344 */ 1345 if (scb != NULL 1346 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1347 && ahc_match_scb(ahc, scb, target, channel, 1348 CAM_LUN_WILDCARD, 1349 SCB_LIST_NULL, 1350 ROLE_INITIATOR)) { 1351 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1352 } 1353 #endif 1354 ahc_compile_devinfo(&devinfo, 1355 initiator_role_id, 1356 target, 1357 CAM_LUN_WILDCARD, 1358 channel, 1359 ROLE_INITIATOR); 1360 ahc_handle_devreset(ahc, &devinfo, 1361 CAM_BDR_SENT, 1362 "Bus Device Reset", 1363 /*verbose_level*/0); 1364 printerror = 0; 1365 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1366 MSG_EXT_PPR, FALSE)) { 1367 struct ahc_initiator_tinfo *tinfo; 1368 struct ahc_tmode_tstate *tstate; 1369 1370 /* 1371 * PPR Rejected. Try non-ppr negotiation 1372 * and retry command. 1373 */ 1374 tinfo = ahc_fetch_transinfo(ahc, 1375 devinfo.channel, 1376 devinfo.our_scsiid, 1377 devinfo.target, 1378 &tstate); 1379 tinfo->curr.transport_version = 2; 1380 tinfo->goal.transport_version = 2; 1381 tinfo->goal.ppr_options = 0; 1382 ahc_qinfifo_requeue_tail(ahc, scb); 1383 printerror = 0; 1384 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1385 MSG_EXT_WDTR, FALSE)) { 1386 /* 1387 * Negotiation Rejected. Go-narrow and 1388 * retry command. 1389 */ 1390 ahc_set_width(ahc, &devinfo, 1391 MSG_EXT_WDTR_BUS_8_BIT, 1392 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1393 /*paused*/TRUE); 1394 ahc_qinfifo_requeue_tail(ahc, scb); 1395 printerror = 0; 1396 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1397 MSG_EXT_SDTR, FALSE)) { 1398 /* 1399 * Negotiation Rejected. Go-async and 1400 * retry command. 1401 */ 1402 ahc_set_syncrate(ahc, &devinfo, 1403 /*syncrate*/NULL, 1404 /*period*/0, /*offset*/0, 1405 /*ppr_options*/0, 1406 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1407 /*paused*/TRUE); 1408 ahc_qinfifo_requeue_tail(ahc, scb); 1409 printerror = 0; 1410 } 1411 } 1412 if (printerror != 0) { 1413 u_int i; 1414 1415 if (scb != NULL) { 1416 u_int tag; 1417 1418 if ((scb->hscb->control & TAG_ENB) != 0) 1419 tag = scb->hscb->tag; 1420 else 1421 tag = SCB_LIST_NULL; 1422 ahc_print_path(ahc, scb); 1423 ahc_abort_scbs(ahc, target, channel, 1424 SCB_GET_LUN(scb), tag, 1425 ROLE_INITIATOR, 1426 CAM_UNEXP_BUSFREE); 1427 } else { 1428 /* 1429 * We had not fully identified this connection, 1430 * so we cannot abort anything. 1431 */ 1432 printf("%s: ", ahc_name(ahc)); 1433 } 1434 for (i = 0; i < num_phases; i++) { 1435 if (lastphase == ahc_phase_table[i].phase) 1436 break; 1437 } 1438 if (lastphase != P_BUSFREE) { 1439 /* 1440 * Renegotiate with this device at the 1441 * next oportunity just in case this busfree 1442 * is due to a negotiation mismatch with the 1443 * device. 1444 */ 1445 ahc_force_renegotiation(ahc, &devinfo); 1446 } 1447 printf("Unexpected busfree %s\n" 1448 "SEQADDR == 0x%x\n", 1449 ahc_phase_table[i].phasemsg, 1450 ahc_inb(ahc, SEQADDR0) 1451 | (ahc_inb(ahc, SEQADDR1) << 8)); 1452 } 1453 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1454 ahc_restart(ahc); 1455 } else { 1456 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1457 ahc_name(ahc), status); 1458 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1459 } 1460 } 1461 1462 /* 1463 * Force renegotiation to occur the next time we initiate 1464 * a command to the current device. 1465 */ 1466 void 1467 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1468 { 1469 struct ahc_initiator_tinfo *targ_info; 1470 struct ahc_tmode_tstate *tstate; 1471 1472 targ_info = ahc_fetch_transinfo(ahc, 1473 devinfo->channel, 1474 devinfo->our_scsiid, 1475 devinfo->target, 1476 &tstate); 1477 ahc_update_neg_request(ahc, devinfo, tstate, 1478 targ_info, AHC_NEG_IF_NON_ASYNC); 1479 } 1480 1481 #define AHC_MAX_STEPS 2000 1482 void 1483 ahc_clear_critical_section(struct ahc_softc *ahc) 1484 { 1485 int stepping; 1486 int steps; 1487 u_int simode0; 1488 u_int simode1; 1489 1490 if (ahc->num_critical_sections == 0) 1491 return; 1492 1493 stepping = FALSE; 1494 steps = 0; 1495 simode0 = 0; 1496 simode1 = 0; 1497 for (;;) { 1498 struct cs *cs; 1499 u_int seqaddr; 1500 u_int i; 1501 1502 seqaddr = ahc_inb(ahc, SEQADDR0) 1503 | (ahc_inb(ahc, SEQADDR1) << 8); 1504 1505 /* 1506 * Seqaddr represents the next instruction to execute, 1507 * so we are really executing the instruction just 1508 * before it. 1509 */ 1510 cs = ahc->critical_sections; 1511 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1512 1513 if (cs->begin < seqaddr && cs->end >= seqaddr) 1514 break; 1515 } 1516 1517 if (i == ahc->num_critical_sections) 1518 break; 1519 1520 if (steps > AHC_MAX_STEPS) { 1521 printf("%s: Infinite loop in critical section\n", 1522 ahc_name(ahc)); 1523 ahc_dump_card_state(ahc); 1524 panic("critical section loop"); 1525 } 1526 1527 steps++; 1528 if (stepping == FALSE) { 1529 1530 /* 1531 * Disable all interrupt sources so that the 1532 * sequencer will not be stuck by a pausing 1533 * interrupt condition while we attempt to 1534 * leave a critical section. 1535 */ 1536 simode0 = ahc_inb(ahc, SIMODE0); 1537 ahc_outb(ahc, SIMODE0, 0); 1538 simode1 = ahc_inb(ahc, SIMODE1); 1539 if ((ahc->features & AHC_DT) != 0) 1540 /* 1541 * On DT class controllers, we 1542 * use the enhanced busfree logic. 1543 * Unfortunately we cannot re-enable 1544 * busfree detection within the 1545 * current connection, so we must 1546 * leave it on while single stepping. 1547 */ 1548 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE); 1549 else 1550 ahc_outb(ahc, SIMODE1, 0); 1551 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1552 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 1553 stepping = TRUE; 1554 } 1555 if ((ahc->features & AHC_DT) != 0) { 1556 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1557 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1558 } 1559 ahc_outb(ahc, HCNTRL, ahc->unpause); 1560 while (!ahc_is_paused(ahc)) 1561 aic_delay(200); 1562 } 1563 if (stepping) { 1564 ahc_outb(ahc, SIMODE0, simode0); 1565 ahc_outb(ahc, SIMODE1, simode1); 1566 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1567 } 1568 } 1569 1570 /* 1571 * Clear any pending interrupt status. 1572 */ 1573 void 1574 ahc_clear_intstat(struct ahc_softc *ahc) 1575 { 1576 /* Clear any interrupt conditions this may have caused */ 1577 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1578 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1579 CLRREQINIT); 1580 ahc_flush_device_writes(ahc); 1581 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1582 ahc_flush_device_writes(ahc); 1583 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1584 ahc_flush_device_writes(ahc); 1585 } 1586 1587 /**************************** Debugging Routines ******************************/ 1588 #ifdef AHC_DEBUG 1589 uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/ 1590 1591 void 1592 ahc_print_scb(struct scb *scb) 1593 { 1594 int i; 1595 1596 struct hardware_scb *hscb = scb->hscb; 1597 1598 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1599 (void *)scb, 1600 hscb->control, 1601 hscb->scsiid, 1602 hscb->lun, 1603 hscb->cdb_len); 1604 printf("Shared Data: "); 1605 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1606 printf("%#02x", hscb->shared_data.cdb[i]); 1607 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1608 aic_le32toh(hscb->dataptr), 1609 aic_le32toh(hscb->datacnt), 1610 aic_le32toh(hscb->sgptr), 1611 hscb->tag); 1612 if (scb->sg_count > 0) { 1613 for (i = 0; i < scb->sg_count; i++) { 1614 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1615 i, 1616 (aic_le32toh(scb->sg_list[i].len) >> 24 1617 & SG_HIGH_ADDR_BITS), 1618 aic_le32toh(scb->sg_list[i].addr), 1619 aic_le32toh(scb->sg_list[i].len)); 1620 } 1621 } 1622 } 1623 #endif 1624 1625 /************************* Transfer Negotiation *******************************/ 1626 /* 1627 * Allocate per target mode instance (ID we respond to as a target) 1628 * transfer negotiation data structures. 1629 */ 1630 static struct ahc_tmode_tstate * 1631 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1632 { 1633 struct ahc_tmode_tstate *master_tstate; 1634 struct ahc_tmode_tstate *tstate; 1635 int i; 1636 1637 master_tstate = ahc->enabled_targets[ahc->our_id]; 1638 if (channel == 'B') { 1639 scsi_id += 8; 1640 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1641 } 1642 if (ahc->enabled_targets[scsi_id] != NULL 1643 && ahc->enabled_targets[scsi_id] != master_tstate) 1644 panic("%s: ahc_alloc_tstate - Target already allocated", 1645 ahc_name(ahc)); 1646 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO); 1647 if (tstate == NULL) 1648 return (NULL); 1649 1650 /* 1651 * If we have allocated a master tstate, copy user settings from 1652 * the master tstate (taken from SRAM or the EEPROM) for this 1653 * channel, but reset our current and goal settings to async/narrow 1654 * until an initiator talks to us. 1655 */ 1656 if (master_tstate != NULL) { 1657 memcpy(tstate, master_tstate, sizeof(*tstate)); 1658 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1659 tstate->ultraenb = 0; 1660 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1661 memset(&tstate->transinfo[i].curr, 0, 1662 sizeof(tstate->transinfo[i].curr)); 1663 memset(&tstate->transinfo[i].goal, 0, 1664 sizeof(tstate->transinfo[i].goal)); 1665 } 1666 } 1667 ahc->enabled_targets[scsi_id] = tstate; 1668 return (tstate); 1669 } 1670 1671 #ifdef AHC_TARGET_MODE 1672 /* 1673 * Free per target mode instance (ID we respond to as a target) 1674 * transfer negotiation data structures. 1675 */ 1676 static void 1677 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1678 { 1679 struct ahc_tmode_tstate *tstate; 1680 1681 /* 1682 * Don't clean up our "master" tstate. 1683 * It has our default user settings. 1684 */ 1685 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1686 || (channel == 'A' && scsi_id == ahc->our_id)) 1687 && force == FALSE) 1688 return; 1689 1690 if (channel == 'B') 1691 scsi_id += 8; 1692 tstate = ahc->enabled_targets[scsi_id]; 1693 if (tstate != NULL) 1694 free(tstate, M_DEVBUF); 1695 ahc->enabled_targets[scsi_id] = NULL; 1696 } 1697 #endif 1698 1699 /* 1700 * Called when we have an active connection to a target on the bus, 1701 * this function finds the nearest syncrate to the input period limited 1702 * by the capabilities of the bus connectivity of and sync settings for 1703 * the target. 1704 */ 1705 struct ahc_syncrate * 1706 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1707 struct ahc_initiator_tinfo *tinfo, 1708 u_int *period, u_int *ppr_options, role_t role) 1709 { 1710 struct ahc_transinfo *transinfo; 1711 u_int maxsync; 1712 1713 if ((ahc->features & AHC_ULTRA2) != 0) { 1714 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1715 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1716 maxsync = AHC_SYNCRATE_DT; 1717 } else { 1718 maxsync = AHC_SYNCRATE_ULTRA; 1719 /* Can't do DT on an SE bus */ 1720 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1721 } 1722 } else if ((ahc->features & AHC_ULTRA) != 0) { 1723 maxsync = AHC_SYNCRATE_ULTRA; 1724 } else { 1725 maxsync = AHC_SYNCRATE_FAST; 1726 } 1727 /* 1728 * Never allow a value higher than our current goal 1729 * period otherwise we may allow a target initiated 1730 * negotiation to go above the limit as set by the 1731 * user. In the case of an initiator initiated 1732 * sync negotiation, we limit based on the user 1733 * setting. This allows the system to still accept 1734 * incoming negotiations even if target initiated 1735 * negotiation is not performed. 1736 */ 1737 if (role == ROLE_TARGET) 1738 transinfo = &tinfo->user; 1739 else 1740 transinfo = &tinfo->goal; 1741 *ppr_options &= transinfo->ppr_options; 1742 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1743 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1744 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1745 } 1746 if (transinfo->period == 0) { 1747 *period = 0; 1748 *ppr_options = 0; 1749 return (NULL); 1750 } 1751 *period = MAX(*period, transinfo->period); 1752 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1753 } 1754 1755 /* 1756 * Look up the valid period to SCSIRATE conversion in our table. 1757 * Return the period and offset that should be sent to the target 1758 * if this was the beginning of an SDTR. 1759 */ 1760 struct ahc_syncrate * 1761 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1762 u_int *ppr_options, u_int maxsync) 1763 { 1764 struct ahc_syncrate *syncrate; 1765 1766 if ((ahc->features & AHC_DT) == 0) 1767 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1768 1769 /* Skip all DT only entries if DT is not available */ 1770 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1771 && maxsync < AHC_SYNCRATE_ULTRA2) 1772 maxsync = AHC_SYNCRATE_ULTRA2; 1773 1774 for (syncrate = &ahc_syncrates[maxsync]; 1775 syncrate->rate != NULL; 1776 syncrate++) { 1777 1778 /* 1779 * The Ultra2 table doesn't go as low 1780 * as for the Fast/Ultra cards. 1781 */ 1782 if ((ahc->features & AHC_ULTRA2) != 0 1783 && (syncrate->sxfr_u2 == 0)) 1784 break; 1785 1786 if (*period <= syncrate->period) { 1787 /* 1788 * When responding to a target that requests 1789 * sync, the requested rate may fall between 1790 * two rates that we can output, but still be 1791 * a rate that we can receive. Because of this, 1792 * we want to respond to the target with 1793 * the same rate that it sent to us even 1794 * if the period we use to send data to it 1795 * is lower. Only lower the response period 1796 * if we must. 1797 */ 1798 if (syncrate == &ahc_syncrates[maxsync]) 1799 *period = syncrate->period; 1800 1801 /* 1802 * At some speeds, we only support 1803 * ST transfers. 1804 */ 1805 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1806 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1807 break; 1808 } 1809 } 1810 1811 if ((*period == 0) 1812 || (syncrate->rate == NULL) 1813 || ((ahc->features & AHC_ULTRA2) != 0 1814 && (syncrate->sxfr_u2 == 0))) { 1815 /* Use asynchronous transfers. */ 1816 *period = 0; 1817 syncrate = NULL; 1818 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1819 } 1820 return (syncrate); 1821 } 1822 1823 /* 1824 * Convert from an entry in our syncrate table to the SCSI equivalent 1825 * sync "period" factor. 1826 */ 1827 u_int 1828 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1829 { 1830 struct ahc_syncrate *syncrate; 1831 1832 if ((ahc->features & AHC_ULTRA2) != 0) 1833 scsirate &= SXFR_ULTRA2; 1834 else 1835 scsirate &= SXFR; 1836 1837 syncrate = &ahc_syncrates[maxsync]; 1838 while (syncrate->rate != NULL) { 1839 1840 if ((ahc->features & AHC_ULTRA2) != 0) { 1841 if (syncrate->sxfr_u2 == 0) 1842 break; 1843 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1844 return (syncrate->period); 1845 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1846 return (syncrate->period); 1847 } 1848 syncrate++; 1849 } 1850 return (0); /* async */ 1851 } 1852 1853 /* 1854 * Truncate the given synchronous offset to a value the 1855 * current adapter type and syncrate are capable of. 1856 */ 1857 void 1858 ahc_validate_offset(struct ahc_softc *ahc, 1859 struct ahc_initiator_tinfo *tinfo, 1860 struct ahc_syncrate *syncrate, 1861 u_int *offset, int wide, role_t role) 1862 { 1863 u_int maxoffset; 1864 1865 /* Limit offset to what we can do */ 1866 if (syncrate == NULL) { 1867 maxoffset = 0; 1868 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1869 maxoffset = MAX_OFFSET_ULTRA2; 1870 } else { 1871 if (wide) 1872 maxoffset = MAX_OFFSET_16BIT; 1873 else 1874 maxoffset = MAX_OFFSET_8BIT; 1875 } 1876 *offset = MIN(*offset, maxoffset); 1877 if (tinfo != NULL) { 1878 if (role == ROLE_TARGET) 1879 *offset = MIN(*offset, tinfo->user.offset); 1880 else 1881 *offset = MIN(*offset, tinfo->goal.offset); 1882 } 1883 } 1884 1885 /* 1886 * Truncate the given transfer width parameter to a value the 1887 * current adapter type is capable of. 1888 */ 1889 void 1890 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1891 u_int *bus_width, role_t role) 1892 { 1893 switch (*bus_width) { 1894 default: 1895 if (ahc->features & AHC_WIDE) { 1896 /* Respond Wide */ 1897 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1898 break; 1899 } 1900 /* FALLTHROUGH */ 1901 case MSG_EXT_WDTR_BUS_8_BIT: 1902 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1903 break; 1904 } 1905 if (tinfo != NULL) { 1906 if (role == ROLE_TARGET) 1907 *bus_width = MIN(tinfo->user.width, *bus_width); 1908 else 1909 *bus_width = MIN(tinfo->goal.width, *bus_width); 1910 } 1911 } 1912 1913 /* 1914 * Update the bitmask of targets for which the controller should 1915 * negotiate with at the next convenient opportunity. This currently 1916 * means the next time we send the initial identify messages for 1917 * a new transaction. 1918 */ 1919 int 1920 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1921 struct ahc_tmode_tstate *tstate, 1922 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1923 { 1924 u_int auto_negotiate_orig; 1925 1926 auto_negotiate_orig = tstate->auto_negotiate; 1927 if (neg_type == AHC_NEG_ALWAYS) { 1928 /* 1929 * Force our "current" settings to be 1930 * unknown so that unless a bus reset 1931 * occurs the need to renegotiate is 1932 * recorded persistently. 1933 */ 1934 if ((ahc->features & AHC_WIDE) != 0) 1935 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1936 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1937 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1938 } 1939 if (tinfo->curr.period != tinfo->goal.period 1940 || tinfo->curr.width != tinfo->goal.width 1941 || tinfo->curr.offset != tinfo->goal.offset 1942 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1943 || (neg_type == AHC_NEG_IF_NON_ASYNC 1944 && (tinfo->goal.offset != 0 1945 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1946 || tinfo->goal.ppr_options != 0))) 1947 tstate->auto_negotiate |= devinfo->target_mask; 1948 else 1949 tstate->auto_negotiate &= ~devinfo->target_mask; 1950 1951 return (auto_negotiate_orig != tstate->auto_negotiate); 1952 } 1953 1954 /* 1955 * Update the user/goal/curr tables of synchronous negotiation 1956 * parameters as well as, in the case of a current or active update, 1957 * any data structures on the host controller. In the case of an 1958 * active update, the specified target is currently talking to us on 1959 * the bus, so the transfer parameter update must take effect 1960 * immediately. 1961 */ 1962 void 1963 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1964 struct ahc_syncrate *syncrate, u_int period, 1965 u_int offset, u_int ppr_options, u_int type, int paused) 1966 { 1967 struct ahc_initiator_tinfo *tinfo; 1968 struct ahc_tmode_tstate *tstate; 1969 u_int old_period; 1970 u_int old_offset; 1971 u_int old_ppr; 1972 int active; 1973 int update_needed; 1974 1975 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1976 update_needed = 0; 1977 1978 if (syncrate == NULL) { 1979 period = 0; 1980 offset = 0; 1981 } 1982 1983 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1984 devinfo->target, &tstate); 1985 1986 if ((type & AHC_TRANS_USER) != 0) { 1987 tinfo->user.period = period; 1988 tinfo->user.offset = offset; 1989 tinfo->user.ppr_options = ppr_options; 1990 } 1991 1992 if ((type & AHC_TRANS_GOAL) != 0) { 1993 tinfo->goal.period = period; 1994 tinfo->goal.offset = offset; 1995 tinfo->goal.ppr_options = ppr_options; 1996 } 1997 1998 old_period = tinfo->curr.period; 1999 old_offset = tinfo->curr.offset; 2000 old_ppr = tinfo->curr.ppr_options; 2001 2002 if ((type & AHC_TRANS_CUR) != 0 2003 && (old_period != period 2004 || old_offset != offset 2005 || old_ppr != ppr_options)) { 2006 u_int scsirate; 2007 2008 update_needed++; 2009 scsirate = tinfo->scsirate; 2010 if ((ahc->features & AHC_ULTRA2) != 0) { 2011 2012 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 2013 if (syncrate != NULL) { 2014 scsirate |= syncrate->sxfr_u2; 2015 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 2016 scsirate |= ENABLE_CRC; 2017 else 2018 scsirate |= SINGLE_EDGE; 2019 } 2020 } else { 2021 2022 scsirate &= ~(SXFR|SOFS); 2023 /* 2024 * Ensure Ultra mode is set properly for 2025 * this target. 2026 */ 2027 tstate->ultraenb &= ~devinfo->target_mask; 2028 if (syncrate != NULL) { 2029 if (syncrate->sxfr & ULTRA_SXFR) { 2030 tstate->ultraenb |= 2031 devinfo->target_mask; 2032 } 2033 scsirate |= syncrate->sxfr & SXFR; 2034 scsirate |= offset & SOFS; 2035 } 2036 if (active) { 2037 u_int sxfrctl0; 2038 2039 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 2040 sxfrctl0 &= ~FAST20; 2041 if (tstate->ultraenb & devinfo->target_mask) 2042 sxfrctl0 |= FAST20; 2043 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 2044 } 2045 } 2046 if (active) { 2047 ahc_outb(ahc, SCSIRATE, scsirate); 2048 if ((ahc->features & AHC_ULTRA2) != 0) 2049 ahc_outb(ahc, SCSIOFFSET, offset); 2050 } 2051 2052 tinfo->scsirate = scsirate; 2053 tinfo->curr.period = period; 2054 tinfo->curr.offset = offset; 2055 tinfo->curr.ppr_options = ppr_options; 2056 2057 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2058 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2059 if (1 /*bootverbose*/) { 2060 if (offset != 0) { 2061 printf("%s: target %d synchronous at %sMHz%s, " 2062 "offset = 0x%x\n", ahc_name(ahc), 2063 devinfo->target, syncrate->rate, 2064 (ppr_options & MSG_EXT_PPR_DT_REQ) 2065 ? " DT" : "", offset); 2066 } else { 2067 printf("%s: target %d using " 2068 "asynchronous transfers\n", 2069 ahc_name(ahc), devinfo->target); 2070 } 2071 } 2072 } 2073 2074 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2075 tinfo, AHC_NEG_TO_GOAL); 2076 2077 if (update_needed) 2078 ahc_update_pending_scbs(ahc); 2079 } 2080 2081 /* 2082 * Update the user/goal/curr tables of wide negotiation 2083 * parameters as well as, in the case of a current or active update, 2084 * any data structures on the host controller. In the case of an 2085 * active update, the specified target is currently talking to us on 2086 * the bus, so the transfer parameter update must take effect 2087 * immediately. 2088 */ 2089 void 2090 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2091 u_int width, u_int type, int paused) 2092 { 2093 struct ahc_initiator_tinfo *tinfo; 2094 struct ahc_tmode_tstate *tstate; 2095 u_int oldwidth; 2096 int active; 2097 int update_needed; 2098 2099 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2100 update_needed = 0; 2101 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2102 devinfo->target, &tstate); 2103 2104 if ((type & AHC_TRANS_USER) != 0) 2105 tinfo->user.width = width; 2106 2107 if ((type & AHC_TRANS_GOAL) != 0) 2108 tinfo->goal.width = width; 2109 2110 oldwidth = tinfo->curr.width; 2111 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2112 u_int scsirate; 2113 2114 update_needed++; 2115 scsirate = tinfo->scsirate; 2116 scsirate &= ~WIDEXFER; 2117 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2118 scsirate |= WIDEXFER; 2119 2120 tinfo->scsirate = scsirate; 2121 2122 if (active) 2123 ahc_outb(ahc, SCSIRATE, scsirate); 2124 2125 tinfo->curr.width = width; 2126 2127 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2128 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2129 if (1 /*bootverbose*/) { 2130 printf("%s: target %d using %dbit transfers\n", 2131 ahc_name(ahc), devinfo->target, 2132 8 * (0x01 << width)); 2133 } 2134 } 2135 2136 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2137 tinfo, AHC_NEG_TO_GOAL); 2138 if (update_needed) 2139 ahc_update_pending_scbs(ahc); 2140 } 2141 2142 /* 2143 * Update the current state of tagged queuing for a given target. 2144 */ 2145 void 2146 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2147 ahc_queue_alg alg) 2148 { 2149 ahc_platform_set_tags(ahc, devinfo, alg); 2150 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2151 devinfo->lun, AC_TRANSFER_NEG, &alg); 2152 } 2153 2154 /* 2155 * When the transfer settings for a connection change, update any 2156 * in-transit SCBs to contain the new data so the hardware will 2157 * be set correctly during future (re)selections. 2158 */ 2159 static void 2160 ahc_update_pending_scbs(struct ahc_softc *ahc) 2161 { 2162 struct scb *pending_scb; 2163 int pending_scb_count; 2164 int i; 2165 int paused; 2166 u_int saved_scbptr; 2167 2168 /* 2169 * Traverse the pending SCB list and ensure that all of the 2170 * SCBs there have the proper settings. 2171 */ 2172 pending_scb_count = 0; 2173 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2174 struct ahc_devinfo devinfo; 2175 struct hardware_scb *pending_hscb; 2176 struct ahc_initiator_tinfo *tinfo; 2177 struct ahc_tmode_tstate *tstate; 2178 2179 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2180 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2181 devinfo.our_scsiid, 2182 devinfo.target, &tstate); 2183 pending_hscb = pending_scb->hscb; 2184 pending_hscb->control &= ~ULTRAENB; 2185 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2186 pending_hscb->control |= ULTRAENB; 2187 pending_hscb->scsirate = tinfo->scsirate; 2188 pending_hscb->scsioffset = tinfo->curr.offset; 2189 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2190 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2191 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2192 pending_hscb->control &= ~MK_MESSAGE; 2193 } 2194 ahc_sync_scb(ahc, pending_scb, 2195 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2196 pending_scb_count++; 2197 } 2198 2199 if (pending_scb_count == 0) 2200 return; 2201 2202 if (ahc_is_paused(ahc)) { 2203 paused = 1; 2204 } else { 2205 paused = 0; 2206 ahc_pause(ahc); 2207 } 2208 2209 saved_scbptr = ahc_inb(ahc, SCBPTR); 2210 /* Ensure that the hscbs down on the card match the new information */ 2211 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2212 struct hardware_scb *pending_hscb; 2213 u_int control; 2214 u_int scb_tag; 2215 2216 ahc_outb(ahc, SCBPTR, i); 2217 scb_tag = ahc_inb(ahc, SCB_TAG); 2218 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2219 if (pending_scb == NULL) 2220 continue; 2221 2222 pending_hscb = pending_scb->hscb; 2223 control = ahc_inb(ahc, SCB_CONTROL); 2224 control &= ~(ULTRAENB|MK_MESSAGE); 2225 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2226 ahc_outb(ahc, SCB_CONTROL, control); 2227 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2228 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2229 } 2230 ahc_outb(ahc, SCBPTR, saved_scbptr); 2231 2232 if (paused == 0) 2233 ahc_unpause(ahc); 2234 } 2235 2236 /**************************** Pathing Information *****************************/ 2237 static void 2238 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2239 { 2240 u_int saved_scsiid; 2241 role_t role; 2242 int our_id; 2243 2244 if (ahc_inb(ahc, SSTAT0) & TARGET) 2245 role = ROLE_TARGET; 2246 else 2247 role = ROLE_INITIATOR; 2248 2249 if (role == ROLE_TARGET 2250 && (ahc->features & AHC_MULTI_TID) != 0 2251 && (ahc_inb(ahc, SEQ_FLAGS) 2252 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2253 /* We were selected, so pull our id from TARGIDIN */ 2254 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2255 } else if ((ahc->features & AHC_ULTRA2) != 0) 2256 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2257 else 2258 our_id = ahc_inb(ahc, SCSIID) & OID; 2259 2260 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2261 ahc_compile_devinfo(devinfo, 2262 our_id, 2263 SCSIID_TARGET(ahc, saved_scsiid), 2264 ahc_inb(ahc, SAVED_LUN), 2265 SCSIID_CHANNEL(ahc, saved_scsiid), 2266 role); 2267 } 2268 2269 struct ahc_phase_table_entry* 2270 ahc_lookup_phase_entry(int phase) 2271 { 2272 struct ahc_phase_table_entry *entry; 2273 struct ahc_phase_table_entry *last_entry; 2274 2275 /* 2276 * num_phases doesn't include the default entry which 2277 * will be returned if the phase doesn't match. 2278 */ 2279 last_entry = &ahc_phase_table[num_phases]; 2280 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2281 if (phase == entry->phase) 2282 break; 2283 } 2284 return (entry); 2285 } 2286 2287 void 2288 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2289 u_int lun, char channel, role_t role) 2290 { 2291 devinfo->our_scsiid = our_id; 2292 devinfo->target = target; 2293 devinfo->lun = lun; 2294 devinfo->target_offset = target; 2295 devinfo->channel = channel; 2296 devinfo->role = role; 2297 if (channel == 'B') 2298 devinfo->target_offset += 8; 2299 devinfo->target_mask = (0x01 << devinfo->target_offset); 2300 } 2301 2302 void 2303 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2304 { 2305 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2306 devinfo->target, devinfo->lun); 2307 } 2308 2309 void 2310 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2311 struct scb *scb) 2312 { 2313 role_t role; 2314 int our_id; 2315 2316 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2317 role = ROLE_INITIATOR; 2318 if ((scb->flags & SCB_TARGET_SCB) != 0) 2319 role = ROLE_TARGET; 2320 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2321 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2322 } 2323 2324 2325 /************************ Message Phase Processing ****************************/ 2326 static void 2327 ahc_assert_atn(struct ahc_softc *ahc) 2328 { 2329 u_int scsisigo; 2330 2331 scsisigo = ATNO; 2332 if ((ahc->features & AHC_DT) == 0) 2333 scsisigo |= ahc_inb(ahc, SCSISIGI); 2334 ahc_outb(ahc, SCSISIGO, scsisigo); 2335 } 2336 2337 /* 2338 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2339 * or enters the initial message out phase, we are interrupted. Fill our 2340 * outgoing message buffer with the appropriate message and begin handing 2341 * the message phase(s) manually. 2342 */ 2343 static void 2344 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2345 struct scb *scb) 2346 { 2347 /* 2348 * To facilitate adding multiple messages together, 2349 * each routine should increment the index and len 2350 * variables instead of setting them explicitly. 2351 */ 2352 ahc->msgout_index = 0; 2353 ahc->msgout_len = 0; 2354 2355 if ((scb->flags & SCB_DEVICE_RESET) == 0 2356 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2357 u_int identify_msg; 2358 2359 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2360 if ((scb->hscb->control & DISCENB) != 0) 2361 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2362 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2363 ahc->msgout_len++; 2364 2365 if ((scb->hscb->control & TAG_ENB) != 0) { 2366 ahc->msgout_buf[ahc->msgout_index++] = 2367 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2368 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2369 ahc->msgout_len += 2; 2370 } 2371 } 2372 2373 if (scb->flags & SCB_DEVICE_RESET) { 2374 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2375 ahc->msgout_len++; 2376 ahc_print_path(ahc, scb); 2377 printf("Bus Device Reset Message Sent\n"); 2378 /* 2379 * Clear our selection hardware in advance of 2380 * the busfree. We may have an entry in the waiting 2381 * Q for this target, and we don't want to go about 2382 * selecting while we handle the busfree and blow it 2383 * away. 2384 */ 2385 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2386 } else if ((scb->flags & SCB_ABORT) != 0) { 2387 if ((scb->hscb->control & TAG_ENB) != 0) 2388 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2389 else 2390 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2391 ahc->msgout_len++; 2392 ahc_print_path(ahc, scb); 2393 printf("Abort%s Message Sent\n", 2394 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2395 /* 2396 * Clear our selection hardware in advance of 2397 * the busfree. We may have an entry in the waiting 2398 * Q for this target, and we don't want to go about 2399 * selecting while we handle the busfree and blow it 2400 * away. 2401 */ 2402 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2403 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2404 ahc_build_transfer_msg(ahc, devinfo); 2405 } else { 2406 printf("ahc_intr: AWAITING_MSG for an SCB that " 2407 "does not have a waiting message\n"); 2408 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2409 devinfo->target_mask); 2410 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2411 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2412 ahc_inb(ahc, MSG_OUT), scb->flags); 2413 } 2414 2415 /* 2416 * Clear the MK_MESSAGE flag from the SCB so we aren't 2417 * asked to send this message again. 2418 */ 2419 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2420 scb->hscb->control &= ~MK_MESSAGE; 2421 ahc->msgout_index = 0; 2422 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2423 } 2424 2425 /* 2426 * Build an appropriate transfer negotiation message for the 2427 * currently active target. 2428 */ 2429 static void 2430 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2431 { 2432 /* 2433 * We need to initiate transfer negotiations. 2434 * If our current and goal settings are identical, 2435 * we want to renegotiate due to a check condition. 2436 */ 2437 struct ahc_initiator_tinfo *tinfo; 2438 struct ahc_tmode_tstate *tstate; 2439 struct ahc_syncrate *rate; 2440 int dowide; 2441 int dosync; 2442 int doppr; 2443 u_int period; 2444 u_int ppr_options; 2445 u_int offset; 2446 2447 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2448 devinfo->target, &tstate); 2449 /* 2450 * Filter our period based on the current connection. 2451 * If we can't perform DT transfers on this segment (not in LVD 2452 * mode for instance), then our decision to issue a PPR message 2453 * may change. 2454 */ 2455 period = tinfo->goal.period; 2456 offset = tinfo->goal.offset; 2457 ppr_options = tinfo->goal.ppr_options; 2458 /* Target initiated PPR is not allowed in the SCSI spec */ 2459 if (devinfo->role == ROLE_TARGET) 2460 ppr_options = 0; 2461 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2462 &ppr_options, devinfo->role); 2463 dowide = tinfo->curr.width != tinfo->goal.width; 2464 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 2465 /* 2466 * Only use PPR if we have options that need it, even if the device 2467 * claims to support it. There might be an expander in the way 2468 * that doesn't. 2469 */ 2470 doppr = ppr_options != 0; 2471 2472 if (!dowide && !dosync && !doppr) { 2473 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2474 dosync = tinfo->goal.offset != 0; 2475 } 2476 2477 if (!dowide && !dosync && !doppr) { 2478 /* 2479 * Force async with a WDTR message if we have a wide bus, 2480 * or just issue an SDTR with a 0 offset. 2481 */ 2482 if ((ahc->features & AHC_WIDE) != 0) 2483 dowide = 1; 2484 else 2485 dosync = 1; 2486 2487 if (bootverbose) { 2488 ahc_print_devinfo(ahc, devinfo); 2489 printf("Ensuring async\n"); 2490 } 2491 } 2492 2493 /* Target initiated PPR is not allowed in the SCSI spec */ 2494 if (devinfo->role == ROLE_TARGET) 2495 doppr = 0; 2496 2497 /* 2498 * Both the PPR message and SDTR message require the 2499 * goal syncrate to be limited to what the target device 2500 * is capable of handling (based on whether an LVD->SE 2501 * expander is on the bus), so combine these two cases. 2502 * Regardless, guarantee that if we are using WDTR and SDTR 2503 * messages that WDTR comes first. 2504 */ 2505 if (doppr || (dosync && !dowide)) { 2506 2507 offset = tinfo->goal.offset; 2508 ahc_validate_offset(ahc, tinfo, rate, &offset, 2509 doppr ? tinfo->goal.width 2510 : tinfo->curr.width, 2511 devinfo->role); 2512 if (doppr) { 2513 ahc_construct_ppr(ahc, devinfo, period, offset, 2514 tinfo->goal.width, ppr_options); 2515 } else { 2516 ahc_construct_sdtr(ahc, devinfo, period, offset); 2517 } 2518 } else { 2519 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2520 } 2521 } 2522 2523 /* 2524 * Build a synchronous negotiation message in our message 2525 * buffer based on the input parameters. 2526 */ 2527 static void 2528 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2529 u_int period, u_int offset) 2530 { 2531 if (offset == 0) 2532 period = AHC_ASYNC_XFER_PERIOD; 2533 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2534 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2535 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2536 ahc->msgout_buf[ahc->msgout_index++] = period; 2537 ahc->msgout_buf[ahc->msgout_index++] = offset; 2538 ahc->msgout_len += 5; 2539 if (bootverbose) { 2540 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2541 ahc_name(ahc), devinfo->channel, devinfo->target, 2542 devinfo->lun, period, offset); 2543 } 2544 } 2545 2546 /* 2547 * Build a wide negotiation message in our message 2548 * buffer based on the input parameters. 2549 */ 2550 static void 2551 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2552 u_int bus_width) 2553 { 2554 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2555 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2556 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2557 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2558 ahc->msgout_len += 4; 2559 if (bootverbose) { 2560 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2561 ahc_name(ahc), devinfo->channel, devinfo->target, 2562 devinfo->lun, bus_width); 2563 } 2564 } 2565 2566 /* 2567 * Build a parallel protocol request message in our message 2568 * buffer based on the input parameters. 2569 */ 2570 static void 2571 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2572 u_int period, u_int offset, u_int bus_width, 2573 u_int ppr_options) 2574 { 2575 if (offset == 0) 2576 period = AHC_ASYNC_XFER_PERIOD; 2577 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2578 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2579 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2580 ahc->msgout_buf[ahc->msgout_index++] = period; 2581 ahc->msgout_buf[ahc->msgout_index++] = 0; 2582 ahc->msgout_buf[ahc->msgout_index++] = offset; 2583 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2584 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2585 ahc->msgout_len += 8; 2586 if (bootverbose) { 2587 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2588 "offset %x, ppr_options %x\n", ahc_name(ahc), 2589 devinfo->channel, devinfo->target, devinfo->lun, 2590 bus_width, period, offset, ppr_options); 2591 } 2592 } 2593 2594 /* 2595 * Clear any active message state. 2596 */ 2597 static void 2598 ahc_clear_msg_state(struct ahc_softc *ahc) 2599 { 2600 ahc->msgout_len = 0; 2601 ahc->msgin_index = 0; 2602 ahc->msg_type = MSG_TYPE_NONE; 2603 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2604 /* 2605 * The target didn't care to respond to our 2606 * message request, so clear ATN. 2607 */ 2608 ahc_outb(ahc, CLRSINT1, CLRATNO); 2609 } 2610 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2611 ahc_outb(ahc, SEQ_FLAGS2, 2612 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2613 } 2614 2615 static void 2616 ahc_handle_proto_violation(struct ahc_softc *ahc) 2617 { 2618 struct ahc_devinfo devinfo; 2619 struct scb *scb; 2620 u_int scbid; 2621 u_int seq_flags; 2622 u_int curphase; 2623 u_int lastphase; 2624 int found; 2625 2626 ahc_fetch_devinfo(ahc, &devinfo); 2627 scbid = ahc_inb(ahc, SCB_TAG); 2628 scb = ahc_lookup_scb(ahc, scbid); 2629 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2630 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2631 lastphase = ahc_inb(ahc, LASTPHASE); 2632 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2633 2634 /* 2635 * The reconnecting target either did not send an 2636 * identify message, or did, but we didn't find an SCB 2637 * to match. 2638 */ 2639 ahc_print_devinfo(ahc, &devinfo); 2640 printf("Target did not send an IDENTIFY message. " 2641 "LASTPHASE = 0x%x.\n", lastphase); 2642 scb = NULL; 2643 } else if (scb == NULL) { 2644 /* 2645 * We don't seem to have an SCB active for this 2646 * transaction. Print an error and reset the bus. 2647 */ 2648 ahc_print_devinfo(ahc, &devinfo); 2649 printf("No SCB found during protocol violation\n"); 2650 goto proto_violation_reset; 2651 } else { 2652 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2653 if ((seq_flags & NO_CDB_SENT) != 0) { 2654 ahc_print_path(ahc, scb); 2655 printf("No or incomplete CDB sent to device.\n"); 2656 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2657 /* 2658 * The target never bothered to provide status to 2659 * us prior to completing the command. Since we don't 2660 * know the disposition of this command, we must attempt 2661 * to abort it. Assert ATN and prepare to send an abort 2662 * message. 2663 */ 2664 ahc_print_path(ahc, scb); 2665 printf("Completed command without status.\n"); 2666 } else { 2667 ahc_print_path(ahc, scb); 2668 printf("Unknown protocol violation.\n"); 2669 ahc_dump_card_state(ahc); 2670 } 2671 } 2672 if ((lastphase & ~P_DATAIN_DT) == 0 2673 || lastphase == P_COMMAND) { 2674 proto_violation_reset: 2675 /* 2676 * Target either went directly to data/command 2677 * phase or didn't respond to our ATN. 2678 * The only safe thing to do is to blow 2679 * it away with a bus reset. 2680 */ 2681 found = ahc_reset_channel(ahc, 'A', TRUE); 2682 printf("%s: Issued Channel %c Bus Reset. " 2683 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2684 } else { 2685 /* 2686 * Leave the selection hardware off in case 2687 * this abort attempt will affect yet to 2688 * be sent commands. 2689 */ 2690 ahc_outb(ahc, SCSISEQ, 2691 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2692 ahc_assert_atn(ahc); 2693 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2694 if (scb == NULL) { 2695 ahc_print_devinfo(ahc, &devinfo); 2696 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2697 ahc->msgout_len = 1; 2698 ahc->msgout_index = 0; 2699 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2700 } else { 2701 ahc_print_path(ahc, scb); 2702 scb->flags |= SCB_ABORT; 2703 } 2704 printf("Protocol violation %s. Attempting to abort.\n", 2705 ahc_lookup_phase_entry(curphase)->phasemsg); 2706 } 2707 } 2708 2709 /* 2710 * Manual message loop handler. 2711 */ 2712 static void 2713 ahc_handle_message_phase(struct ahc_softc *ahc) 2714 { 2715 struct ahc_devinfo devinfo; 2716 u_int bus_phase; 2717 int end_session; 2718 2719 ahc_fetch_devinfo(ahc, &devinfo); 2720 end_session = FALSE; 2721 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2722 2723 reswitch: 2724 switch (ahc->msg_type) { 2725 case MSG_TYPE_INITIATOR_MSGOUT: 2726 { 2727 int lastbyte; 2728 int phasemis; 2729 int msgdone; 2730 2731 if (ahc->msgout_len == 0) 2732 panic("HOST_MSG_LOOP interrupt with no active message"); 2733 2734 #ifdef AHC_DEBUG 2735 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2736 ahc_print_devinfo(ahc, &devinfo); 2737 printf("INITIATOR_MSG_OUT"); 2738 } 2739 #endif 2740 phasemis = bus_phase != P_MESGOUT; 2741 if (phasemis) { 2742 #ifdef AHC_DEBUG 2743 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2744 printf(" PHASEMIS %s\n", 2745 ahc_lookup_phase_entry(bus_phase) 2746 ->phasemsg); 2747 } 2748 #endif 2749 if (bus_phase == P_MESGIN) { 2750 /* 2751 * Change gears and see if 2752 * this messages is of interest to 2753 * us or should be passed back to 2754 * the sequencer. 2755 */ 2756 ahc_outb(ahc, CLRSINT1, CLRATNO); 2757 ahc->send_msg_perror = FALSE; 2758 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2759 ahc->msgin_index = 0; 2760 goto reswitch; 2761 } 2762 end_session = TRUE; 2763 break; 2764 } 2765 2766 if (ahc->send_msg_perror) { 2767 ahc_outb(ahc, CLRSINT1, CLRATNO); 2768 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2769 #ifdef AHC_DEBUG 2770 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2771 printf(" byte 0x%x\n", ahc->send_msg_perror); 2772 #endif 2773 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2774 break; 2775 } 2776 2777 msgdone = ahc->msgout_index == ahc->msgout_len; 2778 if (msgdone) { 2779 /* 2780 * The target has requested a retry. 2781 * Re-assert ATN, reset our message index to 2782 * 0, and try again. 2783 */ 2784 ahc->msgout_index = 0; 2785 ahc_assert_atn(ahc); 2786 } 2787 2788 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2789 if (lastbyte) { 2790 /* Last byte is signified by dropping ATN */ 2791 ahc_outb(ahc, CLRSINT1, CLRATNO); 2792 } 2793 2794 /* 2795 * Clear our interrupt status and present 2796 * the next byte on the bus. 2797 */ 2798 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2799 #ifdef AHC_DEBUG 2800 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2801 printf(" byte 0x%x\n", 2802 ahc->msgout_buf[ahc->msgout_index]); 2803 #endif 2804 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2805 break; 2806 } 2807 case MSG_TYPE_INITIATOR_MSGIN: 2808 { 2809 int phasemis; 2810 int message_done; 2811 2812 #ifdef AHC_DEBUG 2813 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2814 ahc_print_devinfo(ahc, &devinfo); 2815 printf("INITIATOR_MSG_IN"); 2816 } 2817 #endif 2818 phasemis = bus_phase != P_MESGIN; 2819 if (phasemis) { 2820 #ifdef AHC_DEBUG 2821 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2822 printf(" PHASEMIS %s\n", 2823 ahc_lookup_phase_entry(bus_phase) 2824 ->phasemsg); 2825 } 2826 #endif 2827 ahc->msgin_index = 0; 2828 if (bus_phase == P_MESGOUT 2829 && (ahc->send_msg_perror == TRUE 2830 || (ahc->msgout_len != 0 2831 && ahc->msgout_index == 0))) { 2832 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2833 goto reswitch; 2834 } 2835 end_session = TRUE; 2836 break; 2837 } 2838 2839 /* Pull the byte in without acking it */ 2840 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2841 #ifdef AHC_DEBUG 2842 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2843 printf(" byte 0x%x\n", 2844 ahc->msgin_buf[ahc->msgin_index]); 2845 #endif 2846 2847 message_done = ahc_parse_msg(ahc, &devinfo); 2848 2849 if (message_done) { 2850 /* 2851 * Clear our incoming message buffer in case there 2852 * is another message following this one. 2853 */ 2854 ahc->msgin_index = 0; 2855 2856 /* 2857 * If this message illicited a response, 2858 * assert ATN so the target takes us to the 2859 * message out phase. 2860 */ 2861 if (ahc->msgout_len != 0) { 2862 #ifdef AHC_DEBUG 2863 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2864 ahc_print_devinfo(ahc, &devinfo); 2865 printf("Asserting ATN for response\n"); 2866 } 2867 #endif 2868 ahc_assert_atn(ahc); 2869 } 2870 } else 2871 ahc->msgin_index++; 2872 2873 if (message_done == MSGLOOP_TERMINATED) { 2874 end_session = TRUE; 2875 } else { 2876 /* Ack the byte */ 2877 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2878 ahc_inb(ahc, SCSIDATL); 2879 } 2880 break; 2881 } 2882 case MSG_TYPE_TARGET_MSGIN: 2883 { 2884 int msgdone; 2885 int msgout_request; 2886 2887 if (ahc->msgout_len == 0) 2888 panic("Target MSGIN with no active message"); 2889 2890 /* 2891 * If we interrupted a mesgout session, the initiator 2892 * will not know this until our first REQ. So, we 2893 * only honor mesgout requests after we've sent our 2894 * first byte. 2895 */ 2896 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2897 && ahc->msgout_index > 0) 2898 msgout_request = TRUE; 2899 else 2900 msgout_request = FALSE; 2901 2902 if (msgout_request) { 2903 2904 /* 2905 * Change gears and see if 2906 * this messages is of interest to 2907 * us or should be passed back to 2908 * the sequencer. 2909 */ 2910 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2911 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2912 ahc->msgin_index = 0; 2913 /* Dummy read to REQ for first byte */ 2914 ahc_inb(ahc, SCSIDATL); 2915 ahc_outb(ahc, SXFRCTL0, 2916 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2917 break; 2918 } 2919 2920 msgdone = ahc->msgout_index == ahc->msgout_len; 2921 if (msgdone) { 2922 ahc_outb(ahc, SXFRCTL0, 2923 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2924 end_session = TRUE; 2925 break; 2926 } 2927 2928 /* 2929 * Present the next byte on the bus. 2930 */ 2931 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2932 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2933 break; 2934 } 2935 case MSG_TYPE_TARGET_MSGOUT: 2936 { 2937 int lastbyte; 2938 int msgdone; 2939 2940 /* 2941 * The initiator signals that this is 2942 * the last byte by dropping ATN. 2943 */ 2944 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2945 2946 /* 2947 * Read the latched byte, but turn off SPIOEN first 2948 * so that we don't inadvertently cause a REQ for the 2949 * next byte. 2950 */ 2951 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2952 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2953 msgdone = ahc_parse_msg(ahc, &devinfo); 2954 if (msgdone == MSGLOOP_TERMINATED) { 2955 /* 2956 * The message is *really* done in that it caused 2957 * us to go to bus free. The sequencer has already 2958 * been reset at this point, so pull the ejection 2959 * handle. 2960 */ 2961 return; 2962 } 2963 2964 ahc->msgin_index++; 2965 2966 /* 2967 * XXX Read spec about initiator dropping ATN too soon 2968 * and use msgdone to detect it. 2969 */ 2970 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2971 ahc->msgin_index = 0; 2972 2973 /* 2974 * If this message illicited a response, transition 2975 * to the Message in phase and send it. 2976 */ 2977 if (ahc->msgout_len != 0) { 2978 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2979 ahc_outb(ahc, SXFRCTL0, 2980 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2981 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2982 ahc->msgin_index = 0; 2983 break; 2984 } 2985 } 2986 2987 if (lastbyte) 2988 end_session = TRUE; 2989 else { 2990 /* Ask for the next byte. */ 2991 ahc_outb(ahc, SXFRCTL0, 2992 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2993 } 2994 2995 break; 2996 } 2997 default: 2998 panic("Unknown REQINIT message type"); 2999 } 3000 3001 if (end_session) { 3002 ahc_clear_msg_state(ahc); 3003 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 3004 } else 3005 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 3006 } 3007 3008 /* 3009 * See if we sent a particular extended message to the target. 3010 * If "full" is true, return true only if the target saw the full 3011 * message. If "full" is false, return true if the target saw at 3012 * least the first byte of the message. 3013 */ 3014 static int 3015 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 3016 { 3017 int found; 3018 u_int index; 3019 3020 found = FALSE; 3021 index = 0; 3022 3023 while (index < ahc->msgout_len) { 3024 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 3025 u_int end_index; 3026 3027 end_index = index + 1 + ahc->msgout_buf[index + 1]; 3028 if (ahc->msgout_buf[index+2] == msgval 3029 && type == AHCMSG_EXT) { 3030 3031 if (full) { 3032 if (ahc->msgout_index > end_index) 3033 found = TRUE; 3034 } else if (ahc->msgout_index > index) 3035 found = TRUE; 3036 } 3037 index = end_index; 3038 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 3039 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3040 3041 /* Skip tag type and tag id or residue param*/ 3042 index += 2; 3043 } else { 3044 /* Single byte message */ 3045 if (type == AHCMSG_1B 3046 && ahc->msgout_buf[index] == msgval 3047 && ahc->msgout_index > index) 3048 found = TRUE; 3049 index++; 3050 } 3051 3052 if (found) 3053 break; 3054 } 3055 return (found); 3056 } 3057 3058 /* 3059 * Wait for a complete incoming message, parse it, and respond accordingly. 3060 */ 3061 static int 3062 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3063 { 3064 struct ahc_initiator_tinfo *tinfo; 3065 struct ahc_tmode_tstate *tstate; 3066 int reject; 3067 int done; 3068 int response; 3069 u_int targ_scsirate; 3070 3071 done = MSGLOOP_IN_PROG; 3072 response = FALSE; 3073 reject = FALSE; 3074 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3075 devinfo->target, &tstate); 3076 targ_scsirate = tinfo->scsirate; 3077 3078 /* 3079 * Parse as much of the message as is available, 3080 * rejecting it if we don't support it. When 3081 * the entire message is available and has been 3082 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3083 * that we have parsed an entire message. 3084 * 3085 * In the case of extended messages, we accept the length 3086 * byte outright and perform more checking once we know the 3087 * extended message type. 3088 */ 3089 switch (ahc->msgin_buf[0]) { 3090 case MSG_DISCONNECT: 3091 case MSG_SAVEDATAPOINTER: 3092 case MSG_CMDCOMPLETE: 3093 case MSG_RESTOREPOINTERS: 3094 case MSG_IGN_WIDE_RESIDUE: 3095 /* 3096 * End our message loop as these are messages 3097 * the sequencer handles on its own. 3098 */ 3099 done = MSGLOOP_TERMINATED; 3100 break; 3101 case MSG_MESSAGE_REJECT: 3102 response = ahc_handle_msg_reject(ahc, devinfo); 3103 /* FALLTHROUGH */ 3104 case MSG_NOOP: 3105 done = MSGLOOP_MSGCOMPLETE; 3106 break; 3107 case MSG_EXTENDED: 3108 { 3109 /* Wait for enough of the message to begin validation */ 3110 if (ahc->msgin_index < 2) 3111 break; 3112 switch (ahc->msgin_buf[2]) { 3113 case MSG_EXT_SDTR: 3114 { 3115 struct ahc_syncrate *syncrate; 3116 u_int period; 3117 u_int ppr_options; 3118 u_int offset; 3119 u_int saved_offset; 3120 3121 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3122 reject = TRUE; 3123 break; 3124 } 3125 3126 /* 3127 * Wait until we have both args before validating 3128 * and acting on this message. 3129 * 3130 * Add one to MSG_EXT_SDTR_LEN to account for 3131 * the extended message preamble. 3132 */ 3133 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3134 break; 3135 3136 period = ahc->msgin_buf[3]; 3137 ppr_options = 0; 3138 saved_offset = offset = ahc->msgin_buf[4]; 3139 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3140 &ppr_options, 3141 devinfo->role); 3142 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3143 targ_scsirate & WIDEXFER, 3144 devinfo->role); 3145 if (bootverbose) { 3146 printf("(%s:%c:%d:%d): Received " 3147 "SDTR period %x, offset %x\n\t" 3148 "Filtered to period %x, offset %x\n", 3149 ahc_name(ahc), devinfo->channel, 3150 devinfo->target, devinfo->lun, 3151 ahc->msgin_buf[3], saved_offset, 3152 period, offset); 3153 } 3154 ahc_set_syncrate(ahc, devinfo, 3155 syncrate, period, 3156 offset, ppr_options, 3157 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3158 /*paused*/TRUE); 3159 3160 /* 3161 * See if we initiated Sync Negotiation 3162 * and didn't have to fall down to async 3163 * transfers. 3164 */ 3165 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3166 /* We started it */ 3167 if (saved_offset != offset) { 3168 /* Went too low - force async */ 3169 reject = TRUE; 3170 } 3171 } else { 3172 /* 3173 * Send our own SDTR in reply 3174 */ 3175 if (bootverbose 3176 && devinfo->role == ROLE_INITIATOR) { 3177 printf("(%s:%c:%d:%d): Target " 3178 "Initiated SDTR\n", 3179 ahc_name(ahc), devinfo->channel, 3180 devinfo->target, devinfo->lun); 3181 } 3182 ahc->msgout_index = 0; 3183 ahc->msgout_len = 0; 3184 ahc_construct_sdtr(ahc, devinfo, 3185 period, offset); 3186 ahc->msgout_index = 0; 3187 response = TRUE; 3188 } 3189 done = MSGLOOP_MSGCOMPLETE; 3190 break; 3191 } 3192 case MSG_EXT_WDTR: 3193 { 3194 u_int bus_width; 3195 u_int saved_width; 3196 u_int sending_reply; 3197 3198 sending_reply = FALSE; 3199 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3200 reject = TRUE; 3201 break; 3202 } 3203 3204 /* 3205 * Wait until we have our arg before validating 3206 * and acting on this message. 3207 * 3208 * Add one to MSG_EXT_WDTR_LEN to account for 3209 * the extended message preamble. 3210 */ 3211 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3212 break; 3213 3214 bus_width = ahc->msgin_buf[3]; 3215 saved_width = bus_width; 3216 ahc_validate_width(ahc, tinfo, &bus_width, 3217 devinfo->role); 3218 if (bootverbose) { 3219 printf("(%s:%c:%d:%d): Received WDTR " 3220 "%x filtered to %x\n", 3221 ahc_name(ahc), devinfo->channel, 3222 devinfo->target, devinfo->lun, 3223 saved_width, bus_width); 3224 } 3225 3226 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3227 /* 3228 * Don't send a WDTR back to the 3229 * target, since we asked first. 3230 * If the width went higher than our 3231 * request, reject it. 3232 */ 3233 if (saved_width > bus_width) { 3234 reject = TRUE; 3235 printf("(%s:%c:%d:%d): requested %dBit " 3236 "transfers. Rejecting...\n", 3237 ahc_name(ahc), devinfo->channel, 3238 devinfo->target, devinfo->lun, 3239 8 * (0x01 << bus_width)); 3240 bus_width = 0; 3241 } 3242 } else { 3243 /* 3244 * Send our own WDTR in reply 3245 */ 3246 if (bootverbose 3247 && devinfo->role == ROLE_INITIATOR) { 3248 printf("(%s:%c:%d:%d): Target " 3249 "Initiated WDTR\n", 3250 ahc_name(ahc), devinfo->channel, 3251 devinfo->target, devinfo->lun); 3252 } 3253 ahc->msgout_index = 0; 3254 ahc->msgout_len = 0; 3255 ahc_construct_wdtr(ahc, devinfo, bus_width); 3256 ahc->msgout_index = 0; 3257 response = TRUE; 3258 sending_reply = TRUE; 3259 } 3260 /* 3261 * After a wide message, we are async, but 3262 * some devices don't seem to honor this portion 3263 * of the spec. Force a renegotiation of the 3264 * sync component of our transfer agreement even 3265 * if our goal is async. By updating our width 3266 * after forcing the negotiation, we avoid 3267 * renegotiating for width. 3268 */ 3269 ahc_update_neg_request(ahc, devinfo, tstate, 3270 tinfo, AHC_NEG_ALWAYS); 3271 ahc_set_width(ahc, devinfo, bus_width, 3272 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3273 /*paused*/TRUE); 3274 if (sending_reply == FALSE && reject == FALSE) { 3275 3276 /* 3277 * We will always have an SDTR to send. 3278 */ 3279 ahc->msgout_index = 0; 3280 ahc->msgout_len = 0; 3281 ahc_build_transfer_msg(ahc, devinfo); 3282 ahc->msgout_index = 0; 3283 response = TRUE; 3284 } 3285 done = MSGLOOP_MSGCOMPLETE; 3286 break; 3287 } 3288 case MSG_EXT_PPR: 3289 { 3290 struct ahc_syncrate *syncrate; 3291 u_int period; 3292 u_int offset; 3293 u_int bus_width; 3294 u_int ppr_options; 3295 u_int saved_width; 3296 u_int saved_offset; 3297 u_int saved_ppr_options; 3298 3299 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3300 reject = TRUE; 3301 break; 3302 } 3303 3304 /* 3305 * Wait until we have all args before validating 3306 * and acting on this message. 3307 * 3308 * Add one to MSG_EXT_PPR_LEN to account for 3309 * the extended message preamble. 3310 */ 3311 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3312 break; 3313 3314 period = ahc->msgin_buf[3]; 3315 offset = ahc->msgin_buf[5]; 3316 bus_width = ahc->msgin_buf[6]; 3317 saved_width = bus_width; 3318 ppr_options = ahc->msgin_buf[7]; 3319 /* 3320 * According to the spec, a DT only 3321 * period factor with no DT option 3322 * set implies async. 3323 */ 3324 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3325 && period == 9) 3326 offset = 0; 3327 saved_ppr_options = ppr_options; 3328 saved_offset = offset; 3329 3330 /* 3331 * Mask out any options we don't support 3332 * on any controller. Transfer options are 3333 * only available if we are negotiating wide. 3334 */ 3335 ppr_options &= MSG_EXT_PPR_DT_REQ; 3336 if (bus_width == 0) 3337 ppr_options = 0; 3338 3339 ahc_validate_width(ahc, tinfo, &bus_width, 3340 devinfo->role); 3341 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3342 &ppr_options, 3343 devinfo->role); 3344 ahc_validate_offset(ahc, tinfo, syncrate, 3345 &offset, bus_width, 3346 devinfo->role); 3347 3348 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3349 /* 3350 * If we are unable to do any of the 3351 * requested options (we went too low), 3352 * then we'll have to reject the message. 3353 */ 3354 if (saved_width > bus_width 3355 || saved_offset != offset 3356 || saved_ppr_options != ppr_options) { 3357 reject = TRUE; 3358 period = 0; 3359 offset = 0; 3360 bus_width = 0; 3361 ppr_options = 0; 3362 syncrate = NULL; 3363 } 3364 } else { 3365 if (devinfo->role != ROLE_TARGET) 3366 printf("(%s:%c:%d:%d): Target " 3367 "Initiated PPR\n", 3368 ahc_name(ahc), devinfo->channel, 3369 devinfo->target, devinfo->lun); 3370 else 3371 printf("(%s:%c:%d:%d): Initiator " 3372 "Initiated PPR\n", 3373 ahc_name(ahc), devinfo->channel, 3374 devinfo->target, devinfo->lun); 3375 ahc->msgout_index = 0; 3376 ahc->msgout_len = 0; 3377 ahc_construct_ppr(ahc, devinfo, period, offset, 3378 bus_width, ppr_options); 3379 ahc->msgout_index = 0; 3380 response = TRUE; 3381 } 3382 if (bootverbose) { 3383 printf("(%s:%c:%d:%d): Received PPR width %x, " 3384 "period %x, offset %x,options %x\n" 3385 "\tFiltered to width %x, period %x, " 3386 "offset %x, options %x\n", 3387 ahc_name(ahc), devinfo->channel, 3388 devinfo->target, devinfo->lun, 3389 saved_width, ahc->msgin_buf[3], 3390 saved_offset, saved_ppr_options, 3391 bus_width, period, offset, ppr_options); 3392 } 3393 ahc_set_width(ahc, devinfo, bus_width, 3394 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3395 /*paused*/TRUE); 3396 ahc_set_syncrate(ahc, devinfo, 3397 syncrate, period, 3398 offset, ppr_options, 3399 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3400 /*paused*/TRUE); 3401 done = MSGLOOP_MSGCOMPLETE; 3402 break; 3403 } 3404 default: 3405 /* Unknown extended message. Reject it. */ 3406 reject = TRUE; 3407 break; 3408 } 3409 break; 3410 } 3411 #ifdef AHC_TARGET_MODE 3412 case MSG_BUS_DEV_RESET: 3413 ahc_handle_devreset(ahc, devinfo, 3414 CAM_BDR_SENT, 3415 "Bus Device Reset Received", 3416 /*verbose_level*/0); 3417 ahc_restart(ahc); 3418 done = MSGLOOP_TERMINATED; 3419 break; 3420 case MSG_ABORT_TAG: 3421 case MSG_ABORT: 3422 case MSG_CLEAR_QUEUE: 3423 { 3424 int tag; 3425 3426 /* Target mode messages */ 3427 if (devinfo->role != ROLE_TARGET) { 3428 reject = TRUE; 3429 break; 3430 } 3431 tag = SCB_LIST_NULL; 3432 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3433 tag = ahc_inb(ahc, INITIATOR_TAG); 3434 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3435 devinfo->lun, tag, ROLE_TARGET, 3436 CAM_REQ_ABORTED); 3437 3438 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3439 if (tstate != NULL) { 3440 struct ahc_tmode_lstate* lstate; 3441 3442 lstate = tstate->enabled_luns[devinfo->lun]; 3443 if (lstate != NULL) { 3444 ahc_queue_lstate_event(ahc, lstate, 3445 devinfo->our_scsiid, 3446 ahc->msgin_buf[0], 3447 /*arg*/tag); 3448 ahc_send_lstate_events(ahc, lstate); 3449 } 3450 } 3451 ahc_restart(ahc); 3452 done = MSGLOOP_TERMINATED; 3453 break; 3454 } 3455 #endif 3456 case MSG_TERM_IO_PROC: 3457 default: 3458 reject = TRUE; 3459 break; 3460 } 3461 3462 if (reject) { 3463 /* 3464 * Setup to reject the message. 3465 */ 3466 ahc->msgout_index = 0; 3467 ahc->msgout_len = 1; 3468 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3469 done = MSGLOOP_MSGCOMPLETE; 3470 response = TRUE; 3471 } 3472 3473 if (done != MSGLOOP_IN_PROG && !response) 3474 /* Clear the outgoing message buffer */ 3475 ahc->msgout_len = 0; 3476 3477 return (done); 3478 } 3479 3480 /* 3481 * Process a message reject message. 3482 */ 3483 static int 3484 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3485 { 3486 /* 3487 * What we care about here is if we had an 3488 * outstanding SDTR or WDTR message for this 3489 * target. If we did, this is a signal that 3490 * the target is refusing negotiation. 3491 */ 3492 struct scb *scb; 3493 struct ahc_initiator_tinfo *tinfo; 3494 struct ahc_tmode_tstate *tstate; 3495 u_int scb_index; 3496 u_int last_msg; 3497 int response = 0; 3498 3499 scb_index = ahc_inb(ahc, SCB_TAG); 3500 scb = ahc_lookup_scb(ahc, scb_index); 3501 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3502 devinfo->our_scsiid, 3503 devinfo->target, &tstate); 3504 /* Might be necessary */ 3505 last_msg = ahc_inb(ahc, LAST_MSG); 3506 3507 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3508 /* 3509 * Target does not support the PPR message. 3510 * Attempt to negotiate SPI-2 style. 3511 */ 3512 if (bootverbose) { 3513 printf("(%s:%c:%d:%d): PPR Rejected. " 3514 "Trying WDTR/SDTR\n", 3515 ahc_name(ahc), devinfo->channel, 3516 devinfo->target, devinfo->lun); 3517 } 3518 tinfo->goal.ppr_options = 0; 3519 tinfo->curr.transport_version = 2; 3520 tinfo->goal.transport_version = 2; 3521 ahc->msgout_index = 0; 3522 ahc->msgout_len = 0; 3523 ahc_build_transfer_msg(ahc, devinfo); 3524 ahc->msgout_index = 0; 3525 response = 1; 3526 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3527 3528 /* note 8bit xfers */ 3529 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3530 "8bit transfers\n", ahc_name(ahc), 3531 devinfo->channel, devinfo->target, devinfo->lun); 3532 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3533 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3534 /*paused*/TRUE); 3535 /* 3536 * No need to clear the sync rate. If the target 3537 * did not accept the command, our syncrate is 3538 * unaffected. If the target started the negotiation, 3539 * but rejected our response, we already cleared the 3540 * sync rate before sending our WDTR. 3541 */ 3542 if (tinfo->goal.offset != tinfo->curr.offset) { 3543 3544 /* Start the sync negotiation */ 3545 ahc->msgout_index = 0; 3546 ahc->msgout_len = 0; 3547 ahc_build_transfer_msg(ahc, devinfo); 3548 ahc->msgout_index = 0; 3549 response = 1; 3550 } 3551 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3552 /* note asynch xfers and clear flag */ 3553 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3554 /*offset*/0, /*ppr_options*/0, 3555 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3556 /*paused*/TRUE); 3557 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3558 "Using asynchronous transfers\n", 3559 ahc_name(ahc), devinfo->channel, 3560 devinfo->target, devinfo->lun); 3561 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3562 int tag_type; 3563 int mask; 3564 3565 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3566 3567 if (tag_type == MSG_SIMPLE_TASK) { 3568 printf("(%s:%c:%d:%d): refuses tagged commands. " 3569 "Performing non-tagged I/O\n", ahc_name(ahc), 3570 devinfo->channel, devinfo->target, devinfo->lun); 3571 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3572 mask = ~0x23; 3573 } else { 3574 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3575 "Performing simple queue tagged I/O only\n", 3576 ahc_name(ahc), devinfo->channel, devinfo->target, 3577 devinfo->lun, tag_type == MSG_ORDERED_TASK 3578 ? "ordered" : "head of queue"); 3579 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3580 mask = ~0x03; 3581 } 3582 3583 /* 3584 * Resend the identify for this CCB as the target 3585 * may believe that the selection is invalid otherwise. 3586 */ 3587 ahc_outb(ahc, SCB_CONTROL, 3588 ahc_inb(ahc, SCB_CONTROL) & mask); 3589 scb->hscb->control &= mask; 3590 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3591 /*type*/MSG_SIMPLE_TASK); 3592 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3593 ahc_assert_atn(ahc); 3594 3595 /* 3596 * This transaction is now at the head of 3597 * the untagged queue for this target. 3598 */ 3599 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3600 struct scb_tailq *untagged_q; 3601 3602 untagged_q = 3603 &(ahc->untagged_queues[devinfo->target_offset]); 3604 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3605 scb->flags |= SCB_UNTAGGEDQ; 3606 } 3607 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3608 scb->hscb->tag); 3609 3610 /* 3611 * Requeue all tagged commands for this target 3612 * currently in our possession so they can be 3613 * converted to untagged commands. 3614 */ 3615 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3616 SCB_GET_CHANNEL(ahc, scb), 3617 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3618 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3619 SEARCH_COMPLETE); 3620 } else { 3621 /* 3622 * Otherwise, we ignore it. 3623 */ 3624 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3625 ahc_name(ahc), devinfo->channel, devinfo->target, 3626 last_msg); 3627 } 3628 return (response); 3629 } 3630 3631 /* 3632 * Process an ingnore wide residue message. 3633 */ 3634 static void 3635 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3636 { 3637 u_int scb_index; 3638 struct scb *scb; 3639 3640 scb_index = ahc_inb(ahc, SCB_TAG); 3641 scb = ahc_lookup_scb(ahc, scb_index); 3642 /* 3643 * XXX Actually check data direction in the sequencer? 3644 * Perhaps add datadir to some spare bits in the hscb? 3645 */ 3646 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3647 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3648 /* 3649 * Ignore the message if we haven't 3650 * seen an appropriate data phase yet. 3651 */ 3652 } else { 3653 /* 3654 * If the residual occurred on the last 3655 * transfer and the transfer request was 3656 * expected to end on an odd count, do 3657 * nothing. Otherwise, subtract a byte 3658 * and update the residual count accordingly. 3659 */ 3660 uint32_t sgptr; 3661 3662 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3663 if ((sgptr & SG_LIST_NULL) != 0 3664 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 3665 /* 3666 * If the residual occurred on the last 3667 * transfer and the transfer request was 3668 * expected to end on an odd count, do 3669 * nothing. 3670 */ 3671 } else { 3672 struct ahc_dma_seg *sg; 3673 uint32_t data_cnt; 3674 uint32_t data_addr; 3675 uint32_t sglen; 3676 3677 /* Pull in all of the sgptr */ 3678 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 3679 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 3680 3681 if ((sgptr & SG_LIST_NULL) != 0) { 3682 /* 3683 * The residual data count is not updated 3684 * for the command run to completion case. 3685 * Explicitly zero the count. 3686 */ 3687 data_cnt &= ~AHC_SG_LEN_MASK; 3688 } 3689 3690 data_addr = ahc_inl(ahc, SHADDR); 3691 3692 data_cnt += 1; 3693 data_addr -= 1; 3694 sgptr &= SG_PTR_MASK; 3695 3696 sg = ahc_sg_bus_to_virt(scb, sgptr); 3697 3698 /* 3699 * The residual sg ptr points to the next S/G 3700 * to load so we must go back one. 3701 */ 3702 sg--; 3703 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 3704 if (sg != scb->sg_list 3705 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3706 3707 sg--; 3708 sglen = aic_le32toh(sg->len); 3709 /* 3710 * Preserve High Address and SG_LIST bits 3711 * while setting the count to 1. 3712 */ 3713 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3714 data_addr = aic_le32toh(sg->addr) 3715 + (sglen & AHC_SG_LEN_MASK) - 1; 3716 3717 /* 3718 * Increment sg so it points to the 3719 * "next" sg. 3720 */ 3721 sg++; 3722 sgptr = ahc_sg_virt_to_bus(scb, sg); 3723 } 3724 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3725 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3726 /* 3727 * Toggle the "oddness" of the transfer length 3728 * to handle this mid-transfer ignore wide 3729 * residue. This ensures that the oddness is 3730 * correct for subsequent data transfers. 3731 */ 3732 ahc_outb(ahc, SCB_LUN, 3733 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 3734 } 3735 } 3736 } 3737 3738 3739 /* 3740 * Reinitialize the data pointers for the active transfer 3741 * based on its current residual. 3742 */ 3743 static void 3744 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3745 { 3746 struct scb *scb; 3747 struct ahc_dma_seg *sg; 3748 u_int scb_index; 3749 uint32_t sgptr; 3750 uint32_t resid; 3751 uint32_t dataptr; 3752 3753 scb_index = ahc_inb(ahc, SCB_TAG); 3754 scb = ahc_lookup_scb(ahc, scb_index); 3755 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3756 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3757 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3758 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3759 3760 sgptr &= SG_PTR_MASK; 3761 sg = ahc_sg_bus_to_virt(scb, sgptr); 3762 3763 /* The residual sg_ptr always points to the next sg */ 3764 sg--; 3765 3766 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3767 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3768 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3769 3770 dataptr = aic_le32toh(sg->addr) 3771 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK) 3772 - resid; 3773 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3774 u_int dscommand1; 3775 3776 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3777 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3778 ahc_outb(ahc, HADDR, 3779 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3780 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3781 } 3782 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3783 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3784 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3785 ahc_outb(ahc, HADDR, dataptr); 3786 ahc_outb(ahc, HCNT + 2, resid >> 16); 3787 ahc_outb(ahc, HCNT + 1, resid >> 8); 3788 ahc_outb(ahc, HCNT, resid); 3789 if ((ahc->features & AHC_ULTRA2) == 0) { 3790 ahc_outb(ahc, STCNT + 2, resid >> 16); 3791 ahc_outb(ahc, STCNT + 1, resid >> 8); 3792 ahc_outb(ahc, STCNT, resid); 3793 } 3794 } 3795 3796 /* 3797 * Handle the effects of issuing a bus device reset message. 3798 */ 3799 static void 3800 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3801 cam_status status, char *message, int verbose_level) 3802 { 3803 #ifdef AHC_TARGET_MODE 3804 struct ahc_tmode_tstate* tstate; 3805 u_int lun; 3806 #endif 3807 int found; 3808 3809 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3810 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3811 status); 3812 3813 #ifdef AHC_TARGET_MODE 3814 /* 3815 * Send an immediate notify ccb to all target mord peripheral 3816 * drivers affected by this action. 3817 */ 3818 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3819 if (tstate != NULL) { 3820 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3821 struct ahc_tmode_lstate* lstate; 3822 3823 lstate = tstate->enabled_luns[lun]; 3824 if (lstate == NULL) 3825 continue; 3826 3827 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3828 MSG_BUS_DEV_RESET, /*arg*/0); 3829 ahc_send_lstate_events(ahc, lstate); 3830 } 3831 } 3832 #endif 3833 3834 /* 3835 * Go back to async/narrow transfers and renegotiate. 3836 */ 3837 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3838 AHC_TRANS_CUR, /*paused*/TRUE); 3839 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3840 /*period*/0, /*offset*/0, /*ppr_options*/0, 3841 AHC_TRANS_CUR, /*paused*/TRUE); 3842 3843 if (status != CAM_SEL_TIMEOUT) 3844 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3845 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3846 3847 if (message != NULL 3848 && (verbose_level <= bootverbose)) 3849 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3850 message, devinfo->channel, devinfo->target, found); 3851 } 3852 3853 #ifdef AHC_TARGET_MODE 3854 static void 3855 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3856 struct scb *scb) 3857 { 3858 3859 /* 3860 * To facilitate adding multiple messages together, 3861 * each routine should increment the index and len 3862 * variables instead of setting them explicitly. 3863 */ 3864 ahc->msgout_index = 0; 3865 ahc->msgout_len = 0; 3866 3867 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3868 ahc_build_transfer_msg(ahc, devinfo); 3869 else 3870 panic("ahc_intr: AWAITING target message with no message"); 3871 3872 ahc->msgout_index = 0; 3873 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3874 } 3875 #endif 3876 3877 int 3878 ahc_softc_init(struct ahc_softc *ahc) 3879 { 3880 3881 /* The IRQMS bit is only valid on VL and EISA chips */ 3882 if ((ahc->chip & AHC_PCI) == 0) 3883 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3884 else 3885 ahc->unpause = 0; 3886 ahc->pause = ahc->unpause | PAUSE; 3887 /* XXX The shared scb data stuff should be deprecated */ 3888 if (ahc->scb_data == NULL) { 3889 ahc->scb_data = malloc(sizeof(*ahc->scb_data), M_DEVBUF, 3890 M_NOWAIT | M_ZERO); 3891 if (ahc->scb_data == NULL) 3892 return (ENOMEM); 3893 } 3894 3895 return (0); 3896 } 3897 3898 void 3899 ahc_softc_insert(struct ahc_softc *ahc) 3900 { 3901 struct ahc_softc *list_ahc; 3902 3903 #if AHC_PCI_CONFIG > 0 3904 /* 3905 * Second Function PCI devices need to inherit some 3906 * settings from function 0. 3907 */ 3908 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3909 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3910 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3911 ahc_dev_softc_t list_pci; 3912 ahc_dev_softc_t pci; 3913 3914 list_pci = list_ahc->dev_softc; 3915 pci = ahc->dev_softc; 3916 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3917 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3918 struct ahc_softc *master; 3919 struct ahc_softc *slave; 3920 3921 if (ahc_get_pci_function(list_pci) == 0) { 3922 master = list_ahc; 3923 slave = ahc; 3924 } else { 3925 master = ahc; 3926 slave = list_ahc; 3927 } 3928 slave->flags &= ~AHC_BIOS_ENABLED; 3929 slave->flags |= 3930 master->flags & AHC_BIOS_ENABLED; 3931 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3932 slave->flags |= 3933 master->flags & AHC_PRIMARY_CHANNEL; 3934 break; 3935 } 3936 } 3937 } 3938 #endif 3939 3940 /* 3941 * Insertion sort into our list of softcs. 3942 */ 3943 list_ahc = TAILQ_FIRST(&ahc_tailq); 3944 while (list_ahc != NULL 3945 && ahc_softc_comp(ahc, list_ahc) <= 0) 3946 list_ahc = TAILQ_NEXT(list_ahc, links); 3947 if (list_ahc != NULL) 3948 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3949 else 3950 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3951 ahc->init_level++; 3952 } 3953 3954 void 3955 ahc_set_unit(struct ahc_softc *ahc, int unit) 3956 { 3957 ahc->unit = unit; 3958 } 3959 3960 void 3961 ahc_set_name(struct ahc_softc *ahc, char *name) 3962 { 3963 if (ahc->name != NULL) 3964 free(ahc->name, M_DEVBUF); 3965 ahc->name = name; 3966 } 3967 3968 void 3969 ahc_free(struct ahc_softc *ahc) 3970 { 3971 int i; 3972 3973 switch (ahc->init_level) { 3974 default: 3975 case 2: 3976 ahc_shutdown(ahc); 3977 /* FALLTHROUGH */ 3978 case 1: 3979 bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap); 3980 bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap); 3981 bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size); 3982 bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg); 3983 break; 3984 case 0: 3985 break; 3986 } 3987 3988 ahc_platform_free(ahc); 3989 ahc_fini_scbdata(ahc); 3990 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3991 struct ahc_tmode_tstate *tstate; 3992 3993 tstate = ahc->enabled_targets[i]; 3994 if (tstate != NULL) { 3995 #ifdef AHC_TARGET_MODE 3996 int j; 3997 3998 for (j = 0; j < AHC_NUM_LUNS; j++) { 3999 struct ahc_tmode_lstate *lstate; 4000 4001 lstate = tstate->enabled_luns[j]; 4002 if (lstate != NULL) { 4003 /*xpt_free_path(lstate->path);*/ 4004 free(lstate, M_DEVBUF); 4005 } 4006 } 4007 #endif 4008 free(tstate, M_DEVBUF); 4009 } 4010 } 4011 #ifdef AHC_TARGET_MODE 4012 if (ahc->black_hole != NULL) { 4013 /*xpt_free_path(ahc->black_hole->path);*/ 4014 free(ahc->black_hole, M_DEVBUF); 4015 } 4016 #endif 4017 if (ahc->seep_config != NULL) 4018 free(ahc->seep_config, M_DEVBUF); 4019 return; 4020 } 4021 4022 void 4023 ahc_shutdown(void *arg) 4024 { 4025 struct ahc_softc *ahc; 4026 int i; 4027 4028 ahc = (struct ahc_softc *)arg; 4029 4030 /* This will reset most registers to 0, but not all */ 4031 ahc_reset(ahc, /*reinit*/FALSE); 4032 ahc_outb(ahc, SCSISEQ, 0); 4033 ahc_outb(ahc, SXFRCTL0, 0); 4034 ahc_outb(ahc, DSPCISTATUS, 0); 4035 4036 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4037 ahc_outb(ahc, i, 0); 4038 } 4039 4040 /* 4041 * Reset the controller and record some information about it 4042 * that is only available just after a reset. If "reinit" is 4043 * non-zero, this reset occured after initial configuration 4044 * and the caller requests that the chip be fully reinitialized 4045 * to a runable state. Chip interrupts are *not* enabled after 4046 * a reinitialization. The caller must enable interrupts via 4047 * ahc_intr_enable(). 4048 */ 4049 int 4050 ahc_reset(struct ahc_softc *ahc, int reinit) 4051 { 4052 u_int sblkctl; 4053 u_int sxfrctl1_a, sxfrctl1_b; 4054 int error; 4055 int wait; 4056 4057 /* 4058 * Preserve the value of the SXFRCTL1 register for all channels. 4059 * It contains settings that affect termination and we don't want 4060 * to disturb the integrity of the bus. 4061 */ 4062 ahc_pause(ahc); 4063 sxfrctl1_b = 0; 4064 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4065 /* 4066 * Save channel B's settings in case this chip 4067 * is setup for TWIN channel operation. 4068 */ 4069 sblkctl = ahc_inb(ahc, SBLKCTL); 4070 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4071 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4072 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4073 } 4074 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4075 4076 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4077 4078 /* 4079 * Ensure that the reset has finished. We delay 1000us 4080 * prior to reading the register to make sure the chip 4081 * has sufficiently completed its reset to handle register 4082 * accesses. 4083 */ 4084 wait = 1000; 4085 do { 4086 aic_delay(1000); 4087 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4088 4089 if (wait == 0) { 4090 printf("%s: WARNING - Failed chip reset! " 4091 "Trying to initialize anyway.\n", ahc_name(ahc)); 4092 } 4093 ahc_outb(ahc, HCNTRL, ahc->pause); 4094 4095 /* Determine channel configuration */ 4096 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4097 /* No Twin Channel PCI cards */ 4098 if ((ahc->chip & AHC_PCI) != 0) 4099 sblkctl &= ~SELBUSB; 4100 switch (sblkctl) { 4101 case 0: 4102 /* Single Narrow Channel */ 4103 break; 4104 case 2: 4105 /* Wide Channel */ 4106 ahc->features |= AHC_WIDE; 4107 break; 4108 case 8: 4109 /* Twin Channel */ 4110 ahc->features |= AHC_TWIN; 4111 break; 4112 default: 4113 printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl); 4114 return(-1); 4115 } 4116 4117 /* 4118 * Reload sxfrctl1. 4119 * 4120 * We must always initialize STPWEN to 1 before we 4121 * restore the saved values. STPWEN is initialized 4122 * to a tri-state condition which can only be cleared 4123 * by turning it on. 4124 */ 4125 if ((ahc->features & AHC_TWIN) != 0) { 4126 sblkctl = ahc_inb(ahc, SBLKCTL); 4127 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4128 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4129 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4130 } 4131 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4132 4133 error = 0; 4134 if (reinit != 0) 4135 /* 4136 * If a recovery action has forced a chip reset, 4137 * re-initialize the chip to our liking. 4138 */ 4139 error = ahc->bus_chip_init(ahc); 4140 #ifdef AHC_DUMP_SEQ 4141 else 4142 ahc_dumpseq(ahc); 4143 #endif 4144 4145 return (error); 4146 } 4147 4148 /* 4149 * Determine the number of SCBs available on the controller 4150 */ 4151 int 4152 ahc_probe_scbs(struct ahc_softc *ahc) { 4153 int i; 4154 4155 for (i = 0; i < AHC_SCB_MAX; i++) { 4156 4157 ahc_outb(ahc, SCBPTR, i); 4158 ahc_outb(ahc, SCB_BASE, i); 4159 if (ahc_inb(ahc, SCB_BASE) != i) 4160 break; 4161 ahc_outb(ahc, SCBPTR, 0); 4162 if (ahc_inb(ahc, SCB_BASE) != 0) 4163 break; 4164 } 4165 return (i); 4166 } 4167 4168 #if 0 4169 static void 4170 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4171 { 4172 bus_addr_t *baddr; 4173 4174 baddr = (bus_addr_t *)arg; 4175 *baddr = segs->ds_addr; 4176 } 4177 #endif 4178 4179 static void 4180 ahc_build_free_scb_list(struct ahc_softc *ahc) 4181 { 4182 int scbsize; 4183 int i; 4184 4185 scbsize = 32; 4186 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4187 scbsize = 64; 4188 4189 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4190 int j; 4191 4192 ahc_outb(ahc, SCBPTR, i); 4193 4194 /* 4195 * Touch all SCB bytes to avoid parity errors 4196 * should one of our debugging routines read 4197 * an otherwise uninitiatlized byte. 4198 */ 4199 for (j = 0; j < scbsize; j++) 4200 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4201 4202 /* Clear the control byte. */ 4203 ahc_outb(ahc, SCB_CONTROL, 0); 4204 4205 /* Set the next pointer */ 4206 if ((ahc->flags & AHC_PAGESCBS) != 0) 4207 ahc_outb(ahc, SCB_NEXT, i+1); 4208 else 4209 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4210 4211 /* Make the tag number, SCSIID, and lun invalid */ 4212 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4213 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4214 ahc_outb(ahc, SCB_LUN, 0xFF); 4215 } 4216 4217 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4218 /* SCB 0 heads the free list. */ 4219 ahc_outb(ahc, FREE_SCBH, 0); 4220 } else { 4221 /* No free list. */ 4222 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4223 } 4224 4225 /* Make sure that the last SCB terminates the free list */ 4226 ahc_outb(ahc, SCBPTR, i-1); 4227 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4228 } 4229 4230 static int 4231 ahc_init_scbdata(struct ahc_softc *ahc) 4232 { 4233 struct scb_data *scb_data; 4234 int i; 4235 4236 scb_data = ahc->scb_data; 4237 SLIST_INIT(&scb_data->free_scbs); 4238 SLIST_INIT(&scb_data->sg_maps); 4239 4240 /* Allocate SCB resources */ 4241 scb_data->scbarray = malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4242 M_DEVBUF, M_NOWAIT | M_ZERO); 4243 if (scb_data->scbarray == NULL) 4244 return (ENOMEM); 4245 4246 /* Determine the number of hardware SCBs and initialize them */ 4247 4248 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4249 if (ahc->scb_data->maxhscbs == 0) { 4250 printf("%s: No SCB space found\n", ahc_name(ahc)); 4251 return (ENXIO); 4252 } 4253 4254 /* 4255 * Create our DMA tags. These tags define the kinds of device 4256 * accessible memory allocations and memory mappings we will 4257 * need to perform during normal operation. 4258 * 4259 * Unless we need to further restrict the allocation, we rely 4260 * on the restrictions of the parent dmat, hence the common 4261 * use of MAXADDR and MAXSIZE. 4262 */ 4263 4264 if (ahc_createdmamem(ahc->parent_dmat, 4265 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags, 4266 &scb_data->hscb_dmamap, 4267 (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr, 4268 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc), 4269 "hardware SCB structures") < 0) 4270 goto error_exit; 4271 4272 scb_data->init_level++; 4273 4274 if (ahc_createdmamem(ahc->parent_dmat, 4275 AHC_SCB_MAX * sizeof(struct scsi_sense_data), ahc->sc_dmaflags, 4276 &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense, 4277 &scb_data->sense_busaddr, &scb_data->sense_seg, 4278 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0) 4279 goto error_exit; 4280 4281 scb_data->init_level++; 4282 4283 /* Perform initial CCB allocation */ 4284 memset(scb_data->hscbs, 0, 4285 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4286 do { 4287 i = scb_data->numscbs; 4288 ahc_alloc_scbs(ahc); 4289 } while ((i != scb_data->numscbs) && 4290 (scb_data->numscbs < AHC_SCB_MAX_ALLOC)); 4291 4292 if (scb_data->numscbs != AHC_SCB_MAX_ALLOC) { 4293 printf("%s: ahc_init_scbdata - " 4294 "Unable to allocate initial scbs\n", 4295 ahc_name(ahc)); 4296 goto error_exit; 4297 } 4298 4299 /* 4300 * Reserve the next queued SCB. 4301 */ 4302 ahc->next_queued_scb = ahc_get_scb(ahc); 4303 4304 /* 4305 * Note that we were successful 4306 */ 4307 return (0); 4308 4309 error_exit: 4310 4311 return (ENOMEM); 4312 } 4313 4314 static void 4315 ahc_fini_scbdata(struct ahc_softc *ahc) 4316 { 4317 struct scb_data *scb_data; 4318 4319 scb_data = ahc->scb_data; 4320 if (scb_data == NULL) 4321 return; 4322 4323 switch (scb_data->init_level) { 4324 default: 4325 case 5: 4326 { 4327 struct sg_map_node *sg_map; 4328 4329 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4330 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4331 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE, 4332 sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr, 4333 &sg_map->sg_dmasegs, sg_map->sg_nseg); 4334 free(sg_map, M_DEVBUF); 4335 } 4336 } 4337 /*FALLTHROUGH*/ 4338 case 4: 4339 ahc_freedmamem(ahc->parent_dmat, 4340 AHC_SCB_MAX * sizeof(struct scsipi_sense_data), 4341 scb_data->sense_dmamap, (caddr_t)scb_data->sense, 4342 &scb_data->sense_seg, scb_data->sense_nseg); 4343 /*FALLTHROUGH*/ 4344 case 3: 4345 ahc_freedmamem(ahc->parent_dmat, 4346 AHC_SCB_MAX * sizeof(struct hardware_scb), 4347 scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs, 4348 &scb_data->hscb_seg, scb_data->hscb_nseg); 4349 /*FALLTHROUGH*/ 4350 case 2: 4351 case 1: 4352 case 0: 4353 break; 4354 } 4355 if (scb_data->scbarray != NULL) 4356 free(scb_data->scbarray, M_DEVBUF); 4357 } 4358 4359 void 4360 ahc_alloc_scbs(struct ahc_softc *ahc) 4361 { 4362 struct scb_data *scb_data; 4363 struct scb *next_scb; 4364 struct sg_map_node *sg_map; 4365 bus_addr_t physaddr; 4366 struct ahc_dma_seg *segs; 4367 int newcount; 4368 int i; 4369 4370 scb_data = ahc->scb_data; 4371 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4372 /* Can't allocate any more */ 4373 return; 4374 4375 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4376 4377 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4378 4379 if (sg_map == NULL) 4380 return; 4381 4382 /* Allocate S/G space for the next batch of SCBS */ 4383 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags, 4384 &sg_map->sg_dmamap, 4385 (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr, 4386 &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc), 4387 "SG space") < 0) { 4388 free(sg_map, M_DEVBUF); 4389 return; 4390 } 4391 4392 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4393 4394 segs = sg_map->sg_vaddr; 4395 physaddr = sg_map->sg_physaddr; 4396 4397 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4398 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4399 for (i = 0; i < newcount; i++) { 4400 struct scb_platform_data *pdata = NULL; 4401 int error; 4402 4403 if (sizeof(*pdata) > 0) { 4404 pdata = malloc(sizeof(*pdata), M_DEVBUF, 4405 M_NOWAIT | M_ZERO); 4406 if (pdata == NULL) 4407 break; 4408 } 4409 4410 next_scb->platform_data = pdata; 4411 next_scb->sg_map = sg_map; 4412 next_scb->sg_list = segs; 4413 /* 4414 * The sequencer always starts with the second entry. 4415 * The first entry is embedded in the scb. 4416 */ 4417 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4418 next_scb->ahc_softc = ahc; 4419 next_scb->flags = SCB_FLAG_NONE; 4420 4421 error = bus_dmamap_create(ahc->parent_dmat, 4422 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0, 4423 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags, 4424 &next_scb->dmamap); 4425 if (error != 0) 4426 break; 4427 4428 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4429 next_scb->hscb->tag = ahc->scb_data->numscbs; 4430 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4431 next_scb, links.sle); 4432 segs += AHC_NSEG; 4433 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4434 next_scb++; 4435 ahc->scb_data->numscbs++; 4436 } 4437 } 4438 4439 #ifndef DEBUG 4440 void 4441 ahc_controller_info(struct ahc_softc *ahc, char *buf, size_t buf_len) 4442 { 4443 int len = 0; 4444 4445 snprintf(buf + len, buf_len - len, "%s: ", 4446 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4447 len = strlen(buf); 4448 if ((ahc->features & AHC_TWIN) != 0) 4449 snprintf(buf + len, buf_len - len, 4450 "Twin Channel, primary %c, ", 4451 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4452 else { 4453 const char *speed; 4454 const char *type; 4455 4456 speed = ""; 4457 if ((ahc->features & AHC_ULTRA) != 0) { 4458 speed = "Ultra "; 4459 } else if ((ahc->features & AHC_DT) != 0) { 4460 speed = "Ultra160 "; 4461 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4462 speed = "Ultra2 "; 4463 } 4464 if ((ahc->features & AHC_WIDE) != 0) { 4465 type = "Wide"; 4466 } else { 4467 type = "Single"; 4468 } 4469 snprintf(buf + len, buf_len - len, 4470 "%s%s Channel %c, ", 4471 speed, type, ahc->channel); 4472 } 4473 len = strlen(buf); 4474 4475 if ((ahc->flags & AHC_PAGESCBS) != 0) 4476 snprintf(buf + len, buf_len - len, "%d/%d SCBs", 4477 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4478 else 4479 snprintf(buf + len, buf_len - len, "%d SCBs", 4480 ahc->scb_data->maxhscbs); 4481 } 4482 #endif /* !DEBUG */ 4483 4484 int 4485 ahc_chip_init(struct ahc_softc *ahc) 4486 { 4487 int term; 4488 int error; 4489 u_int i; 4490 u_int scsi_conf; 4491 u_int scsiseq_template; 4492 uint32_t physaddr; 4493 4494 ahc_outb(ahc, SEQ_FLAGS, 0); 4495 ahc_outb(ahc, SEQ_FLAGS2, 0); 4496 4497 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4498 if (ahc->features & AHC_TWIN) { 4499 4500 /* 4501 * Setup Channel B first. 4502 */ 4503 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4504 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4505 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4506 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4507 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4508 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4509 if ((ahc->features & AHC_ULTRA2) != 0) 4510 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4511 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4512 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4513 4514 /* Select Channel A */ 4515 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4516 } 4517 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4518 if ((ahc->features & AHC_ULTRA2) != 0) 4519 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4520 else 4521 ahc_outb(ahc, SCSIID, ahc->our_id); 4522 scsi_conf = ahc_inb(ahc, SCSICONF); 4523 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4524 |term|ahc->seltime 4525 |ENSTIMER|ACTNEGEN); 4526 if ((ahc->features & AHC_ULTRA2) != 0) 4527 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4528 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4529 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4530 4531 /* There are no untagged SCBs active yet. */ 4532 for (i = 0; i < 16; i++) { 4533 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4534 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4535 int lun; 4536 4537 /* 4538 * The SCB based BTT allows an entry per 4539 * target and lun pair. 4540 */ 4541 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4542 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4543 } 4544 } 4545 4546 /* All of our queues are empty */ 4547 for (i = 0; i < 256; i++) 4548 ahc->qoutfifo[i] = SCB_LIST_NULL; 4549 #ifdef __sgi__ 4550 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 4551 #else 4552 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4553 #endif 4554 for (i = 0; i < 256; i++) 4555 ahc->qinfifo[i] = SCB_LIST_NULL; 4556 4557 if ((ahc->features & AHC_MULTI_TID) != 0) { 4558 ahc_outb(ahc, TARGID, 0); 4559 ahc_outb(ahc, TARGID + 1, 0); 4560 } 4561 4562 /* 4563 * Tell the sequencer where it can find our arrays in memory. 4564 */ 4565 physaddr = ahc->scb_data->hscb_busaddr; 4566 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4567 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4568 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4569 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4570 4571 physaddr = ahc->shared_data_busaddr; 4572 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4573 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4574 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4575 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4576 4577 /* 4578 * Initialize the group code to command length table. 4579 * This overrides the values in TARG_SCSIRATE, so only 4580 * setup the table after we have processed that information. 4581 */ 4582 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4583 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4584 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4585 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4586 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4587 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4588 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4589 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4590 4591 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4592 ahc_outb(ahc, HS_MAILBOX, 0); 4593 4594 /* Tell the sequencer of our initial queue positions */ 4595 if ((ahc->features & AHC_TARGETMODE) != 0) { 4596 ahc->tqinfifonext = 1; 4597 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4598 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4599 } 4600 ahc->qinfifonext = 0; 4601 ahc->qoutfifonext = 0; 4602 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4603 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4604 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4605 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4606 ahc_outb(ahc, SDSCB_QOFF, 0); 4607 } else { 4608 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4609 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4610 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4611 } 4612 4613 /* We don't have any waiting selections */ 4614 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4615 4616 /* Our disconnection list is empty too */ 4617 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4618 4619 /* Message out buffer starts empty */ 4620 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4621 4622 /* 4623 * Setup the allowed SCSI Sequences based on operational mode. 4624 * If we are a target, we'll enable select in operations once 4625 * we've had a lun enabled. 4626 */ 4627 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4628 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4629 scsiseq_template |= ENRSELI; 4630 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4631 4632 /* Initialize our list of free SCBs. */ 4633 ahc_build_free_scb_list(ahc); 4634 4635 /* 4636 * Tell the sequencer which SCB will be the next one it receives. 4637 */ 4638 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4639 4640 /* 4641 * Load the Sequencer program and Enable the adapter 4642 * in "fast" mode. 4643 */ 4644 if (bootverbose) 4645 printf("%s: Downloading Sequencer Program...", 4646 ahc_name(ahc)); 4647 4648 error = ahc_loadseq(ahc); 4649 if (error != 0) 4650 return (error); 4651 4652 if ((ahc->features & AHC_ULTRA2) != 0) { 4653 int wait; 4654 4655 /* 4656 * Wait for up to 500ms for our transceivers 4657 * to settle. If the adapter does not have 4658 * a cable attached, the transceivers may 4659 * never settle, so don't complain if we 4660 * fail here. 4661 */ 4662 for (wait = 5000; 4663 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4664 wait--) 4665 aic_delay(100); 4666 } 4667 ahc_restart(ahc); 4668 return (0); 4669 } 4670 4671 /* 4672 * Start the board, ready for normal operation 4673 */ 4674 int 4675 ahc_init(struct ahc_softc *ahc) 4676 { 4677 int max_targ; 4678 u_int i; 4679 u_int scsi_conf; 4680 u_int ultraenb; 4681 u_int discenable; 4682 u_int tagenable; 4683 size_t driver_data_size; 4684 4685 #ifdef AHC_DEBUG 4686 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4687 ahc->flags |= AHC_SEQUENCER_DEBUG; 4688 #endif 4689 4690 #ifdef AHC_PRINT_SRAM 4691 printf("Scratch Ram:"); 4692 for (i = 0x20; i < 0x5f; i++) { 4693 if (((i % 8) == 0) && (i != 0)) { 4694 printf ("\n "); 4695 } 4696 printf (" 0x%x", ahc_inb(ahc, i)); 4697 } 4698 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4699 for (i = 0x70; i < 0x7f; i++) { 4700 if (((i % 8) == 0) && (i != 0)) { 4701 printf ("\n "); 4702 } 4703 printf (" 0x%x", ahc_inb(ahc, i)); 4704 } 4705 } 4706 printf ("\n"); 4707 /* 4708 * Reading uninitialized scratch ram may 4709 * generate parity errors. 4710 */ 4711 ahc_outb(ahc, CLRINT, CLRPARERR); 4712 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4713 #endif 4714 max_targ = 15; 4715 4716 /* 4717 * Assume we have a board at this stage and it has been reset. 4718 */ 4719 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4720 ahc->our_id = ahc->our_id_b = 7; 4721 4722 /* 4723 * Default to allowing initiator operations. 4724 */ 4725 ahc->flags |= AHC_INITIATORROLE; 4726 4727 /* 4728 * Only allow target mode features if this unit has them enabled. 4729 */ 4730 //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4731 ahc->features &= ~AHC_TARGETMODE; 4732 4733 /* 4734 * DMA tag for our command fifos and other data in system memory 4735 * the card's sequencer must be able to access. For initiator 4736 * roles, we need to allocate space for the qinfifo and qoutfifo. 4737 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4738 * When providing for the target mode role, we must additionally 4739 * provide space for the incoming target command fifo and an extra 4740 * byte to deal with a DMA bug in some chip versions. 4741 */ 4742 driver_data_size = 2 * 256 * sizeof(uint8_t); 4743 if ((ahc->features & AHC_TARGETMODE) != 0) 4744 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4745 + /*DMA WideOdd Bug Buffer*/1; 4746 4747 ahc->init_level++; 4748 4749 if (ahc_createdmamem(ahc->parent_dmat, driver_data_size, 4750 ahc->sc_dmaflags, 4751 &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo, 4752 &ahc->shared_data_busaddr, &ahc->shared_data_seg, 4753 &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0) 4754 return (ENOMEM); 4755 4756 ahc->init_level++; 4757 4758 if ((ahc->features & AHC_TARGETMODE) != 0) { 4759 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4760 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4761 ahc->dma_bug_buf = ahc->shared_data_busaddr 4762 + driver_data_size - 1; 4763 /* All target command blocks start out invalid. */ 4764 for (i = 0; i < AHC_TMODE_CMDS; i++) 4765 ahc->targetcmds[i].cmd_valid = 0; 4766 #ifdef __sgi__ 4767 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 4768 #else 4769 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4770 #endif 4771 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4772 } 4773 ahc->qinfifo = &ahc->qoutfifo[256]; 4774 4775 ahc->init_level++; 4776 4777 /* Allocate SCB data now that buffer_dmat is initialized */ 4778 if (ahc->scb_data->maxhscbs == 0) 4779 if (ahc_init_scbdata(ahc) != 0) 4780 return (ENOMEM); 4781 4782 /* 4783 * Allocate a tstate to house information for our 4784 * initiator presence on the bus as well as the user 4785 * data for any target mode initiator. 4786 */ 4787 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4788 printf("%s: unable to allocate ahc_tmode_tstate. " 4789 "Failing attach\n", ahc_name(ahc)); 4790 return (ENOMEM); 4791 } 4792 4793 if ((ahc->features & AHC_TWIN) != 0) { 4794 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4795 printf("%s: unable to allocate ahc_tmode_tstate. " 4796 "Failing attach\n", ahc_name(ahc)); 4797 return (ENOMEM); 4798 } 4799 } 4800 4801 ahc_outb(ahc, SEQ_FLAGS, 0); 4802 ahc_outb(ahc, SEQ_FLAGS2, 0); 4803 4804 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4805 ahc->flags |= AHC_PAGESCBS; 4806 } else { 4807 ahc->flags &= ~AHC_PAGESCBS; 4808 } 4809 4810 #ifdef AHC_DEBUG 4811 if (ahc_debug & AHC_SHOW_MISC) { 4812 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 4813 "ahc_dma %u bytes\n", 4814 ahc_name(ahc), 4815 (u_int)sizeof(struct hardware_scb), 4816 (u_int)sizeof(struct scb), 4817 (u_int)sizeof(struct ahc_dma_seg)); 4818 } 4819 #endif /* AHC_DEBUG */ 4820 4821 /* 4822 * Look at the information that board initialization or 4823 * the board bios has left us. 4824 */ 4825 if (ahc->features & AHC_TWIN) { 4826 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4827 if ((scsi_conf & RESET_SCSI) != 0 4828 && (ahc->flags & AHC_INITIATORROLE) != 0) 4829 ahc->flags |= AHC_RESET_BUS_B; 4830 } 4831 4832 scsi_conf = ahc_inb(ahc, SCSICONF); 4833 if ((scsi_conf & RESET_SCSI) != 0 4834 && (ahc->flags & AHC_INITIATORROLE) != 0) 4835 ahc->flags |= AHC_RESET_BUS_A; 4836 4837 ultraenb = 0; 4838 tagenable = ALL_TARGETS_MASK; 4839 4840 /* Grab the disconnection disable table and invert it for our needs */ 4841 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4842 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4843 "device parameters\n", ahc_name(ahc)); 4844 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4845 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4846 discenable = ALL_TARGETS_MASK; 4847 if ((ahc->features & AHC_ULTRA) != 0) 4848 ultraenb = ALL_TARGETS_MASK; 4849 } else { 4850 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4851 | ahc_inb(ahc, DISC_DSB)); 4852 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4853 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4854 | ahc_inb(ahc, ULTRA_ENB); 4855 } 4856 4857 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4858 max_targ = 7; 4859 4860 for (i = 0; i <= max_targ; i++) { 4861 struct ahc_initiator_tinfo *tinfo; 4862 struct ahc_tmode_tstate *tstate; 4863 u_int our_id; 4864 u_int target_id; 4865 char channel; 4866 4867 channel = 'A'; 4868 our_id = ahc->our_id; 4869 target_id = i; 4870 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4871 channel = 'B'; 4872 our_id = ahc->our_id_b; 4873 target_id = i % 8; 4874 } 4875 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4876 target_id, &tstate); 4877 /* Default to async narrow across the board */ 4878 memset(tinfo, 0, sizeof(*tinfo)); 4879 if (ahc->flags & AHC_USEDEFAULTS) { 4880 if ((ahc->features & AHC_WIDE) != 0) 4881 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4882 4883 /* 4884 * These will be truncated when we determine the 4885 * connection type we have with the target. 4886 */ 4887 tinfo->user.period = ahc_syncrates->period; 4888 tinfo->user.offset = MAX_OFFSET; 4889 } else { 4890 u_int scsirate; 4891 uint16_t mask; 4892 4893 /* Take the settings leftover in scratch RAM. */ 4894 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4895 mask = (0x01 << i); 4896 if ((ahc->features & AHC_ULTRA2) != 0) { 4897 u_int offset; 4898 u_int maxsync; 4899 4900 if ((scsirate & SOFS) == 0x0F) { 4901 /* 4902 * Haven't negotiated yet, 4903 * so the format is different. 4904 */ 4905 scsirate = (scsirate & SXFR) >> 4 4906 | (ultraenb & mask) 4907 ? 0x08 : 0x0 4908 | (scsirate & WIDEXFER); 4909 offset = MAX_OFFSET_ULTRA2; 4910 } else 4911 offset = ahc_inb(ahc, TARG_OFFSET + i); 4912 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4913 /* Set to the lowest sync rate, 5MHz */ 4914 scsirate |= 0x1c; 4915 maxsync = AHC_SYNCRATE_ULTRA2; 4916 if ((ahc->features & AHC_DT) != 0) 4917 maxsync = AHC_SYNCRATE_DT; 4918 tinfo->user.period = 4919 ahc_find_period(ahc, scsirate, maxsync); 4920 if (offset == 0) 4921 tinfo->user.period = 0; 4922 else 4923 tinfo->user.offset = MAX_OFFSET; 4924 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4925 && (ahc->features & AHC_DT) != 0) 4926 tinfo->user.ppr_options = 4927 MSG_EXT_PPR_DT_REQ; 4928 } else if ((scsirate & SOFS) != 0) { 4929 if ((scsirate & SXFR) == 0x40 4930 && (ultraenb & mask) != 0) { 4931 /* Treat 10MHz as a non-ultra speed */ 4932 scsirate &= ~SXFR; 4933 ultraenb &= ~mask; 4934 } 4935 tinfo->user.period = 4936 ahc_find_period(ahc, scsirate, 4937 (ultraenb & mask) 4938 ? AHC_SYNCRATE_ULTRA 4939 : AHC_SYNCRATE_FAST); 4940 if (tinfo->user.period != 0) 4941 tinfo->user.offset = MAX_OFFSET; 4942 } 4943 if (tinfo->user.period == 0) 4944 tinfo->user.offset = 0; 4945 if ((scsirate & WIDEXFER) != 0 4946 && (ahc->features & AHC_WIDE) != 0) 4947 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4948 tinfo->user.protocol_version = 4; 4949 if ((ahc->features & AHC_DT) != 0) 4950 tinfo->user.transport_version = 3; 4951 else 4952 tinfo->user.transport_version = 2; 4953 tinfo->goal.protocol_version = 2; 4954 tinfo->goal.transport_version = 2; 4955 tinfo->curr.protocol_version = 2; 4956 tinfo->curr.transport_version = 2; 4957 } 4958 tstate->ultraenb = 0; 4959 tstate->discenable = discenable; 4960 } 4961 ahc->user_discenable = discenable; 4962 ahc->user_tagenable = tagenable; 4963 4964 return (ahc->bus_chip_init(ahc)); 4965 } 4966 4967 void 4968 ahc_intr_enable(struct ahc_softc *ahc, int enable) 4969 { 4970 u_int hcntrl; 4971 4972 hcntrl = ahc_inb(ahc, HCNTRL); 4973 hcntrl &= ~INTEN; 4974 ahc->pause &= ~INTEN; 4975 ahc->unpause &= ~INTEN; 4976 if (enable) { 4977 hcntrl |= INTEN; 4978 ahc->pause |= INTEN; 4979 ahc->unpause |= INTEN; 4980 } 4981 ahc_outb(ahc, HCNTRL, hcntrl); 4982 } 4983 4984 /************************** Busy Target Table *********************************/ 4985 /* 4986 * Return the untagged transaction id for a given target/channel lun. 4987 * Optionally, clear the entry. 4988 */ 4989 u_int 4990 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 4991 { 4992 u_int scbid; 4993 u_int target_offset; 4994 4995 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4996 u_int saved_scbptr; 4997 4998 saved_scbptr = ahc_inb(ahc, SCBPTR); 4999 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5000 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5001 ahc_outb(ahc, SCBPTR, saved_scbptr); 5002 } else { 5003 target_offset = TCL_TARGET_OFFSET(tcl); 5004 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5005 } 5006 5007 return (scbid); 5008 } 5009 5010 void 5011 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5012 { 5013 u_int target_offset; 5014 5015 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5016 u_int saved_scbptr; 5017 5018 saved_scbptr = ahc_inb(ahc, SCBPTR); 5019 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5020 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5021 ahc_outb(ahc, SCBPTR, saved_scbptr); 5022 } else { 5023 target_offset = TCL_TARGET_OFFSET(tcl); 5024 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5025 } 5026 } 5027 5028 void 5029 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5030 { 5031 u_int target_offset; 5032 5033 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5034 u_int saved_scbptr; 5035 5036 saved_scbptr = ahc_inb(ahc, SCBPTR); 5037 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5038 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5039 ahc_outb(ahc, SCBPTR, saved_scbptr); 5040 } else { 5041 target_offset = TCL_TARGET_OFFSET(tcl); 5042 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5043 } 5044 } 5045 5046 /************************** SCB and SCB queue management **********************/ 5047 int 5048 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5049 char channel, int lun, u_int tag, role_t role) 5050 { 5051 char chan; 5052 int targ, slun, match; 5053 5054 if (scb == NULL) 5055 return 0; 5056 5057 targ = SCB_GET_TARGET(ahc, scb); 5058 chan = SCB_GET_CHANNEL(ahc, scb); 5059 slun = SCB_GET_LUN(scb); 5060 5061 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5062 if (match != 0) 5063 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5064 if (match != 0) 5065 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5066 if (match != 0) { 5067 #ifdef AHC_TARGET_MODE 5068 int group; 5069 5070 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5071 if (role == ROLE_INITIATOR) { 5072 match = (group != XPT_FC_GROUP_TMODE) 5073 && ((tag == scb->hscb->tag) 5074 || (tag == SCB_LIST_NULL)); 5075 } else if (role == ROLE_TARGET) { 5076 match = (group == XPT_FC_GROUP_TMODE) 5077 && ((tag == scb->io_ctx->csio.tag_id) 5078 || (tag == SCB_LIST_NULL)); 5079 } 5080 #else /* !AHC_TARGET_MODE */ 5081 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5082 #endif /* AHC_TARGET_MODE */ 5083 } 5084 5085 return match; 5086 } 5087 5088 void 5089 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5090 { 5091 int target; 5092 char channel; 5093 int lun; 5094 5095 target = SCB_GET_TARGET(ahc, scb); 5096 lun = SCB_GET_LUN(scb); 5097 channel = SCB_GET_CHANNEL(ahc, scb); 5098 5099 ahc_search_qinfifo(ahc, target, channel, lun, 5100 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5101 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5102 5103 ahc_platform_freeze_devq(ahc, scb); 5104 } 5105 5106 void 5107 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5108 { 5109 struct scb *prev_scb; 5110 5111 prev_scb = NULL; 5112 if (ahc_qinfifo_count(ahc) != 0) { 5113 u_int prev_tag; 5114 uint8_t prev_pos; 5115 5116 prev_pos = ahc->qinfifonext - 1; 5117 prev_tag = ahc->qinfifo[prev_pos]; 5118 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5119 } 5120 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5121 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5122 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5123 } else { 5124 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5125 } 5126 } 5127 5128 static void 5129 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5130 struct scb *scb) 5131 { 5132 if (prev_scb == NULL) { 5133 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5134 } else { 5135 prev_scb->hscb->next = scb->hscb->tag; 5136 ahc_sync_scb(ahc, prev_scb, 5137 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5138 } 5139 ahc->qinfifo[ahc->qinfifonext] = scb->hscb->tag; 5140 ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap, 5141 /*offset*/ahc->qinfifonext+256, /*len*/1, 5142 BUS_DMASYNC_PREWRITE); 5143 ahc->qinfifonext++; 5144 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5145 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5146 } 5147 5148 static int 5149 ahc_qinfifo_count(struct ahc_softc *ahc) 5150 { 5151 uint8_t qinpos; 5152 uint8_t diff; 5153 5154 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5155 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5156 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5157 } else 5158 qinpos = ahc_inb(ahc, QINPOS); 5159 diff = ahc->qinfifonext - qinpos; 5160 return (diff); 5161 } 5162 5163 int 5164 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5165 int lun, u_int tag, role_t role, uint32_t status, 5166 ahc_search_action action) 5167 { 5168 struct scb *scb; 5169 struct scb *prev_scb; 5170 uint8_t qinstart; 5171 uint8_t qinpos; 5172 uint8_t qintail; 5173 uint8_t next; 5174 uint8_t prev; 5175 uint8_t curscbptr; 5176 int found; 5177 int have_qregs; 5178 5179 qintail = ahc->qinfifonext; 5180 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5181 if (have_qregs) { 5182 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5183 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5184 } else 5185 qinstart = ahc_inb(ahc, QINPOS); 5186 qinpos = qinstart; 5187 found = 0; 5188 prev_scb = NULL; 5189 5190 if (action == SEARCH_COMPLETE) { 5191 /* 5192 * Don't attempt to run any queued untagged transactions 5193 * until we are done with the abort process. 5194 */ 5195 ahc_freeze_untagged_queues(ahc); 5196 } 5197 5198 /* 5199 * Start with an empty queue. Entries that are not chosen 5200 * for removal will be re-added to the queue as we go. 5201 */ 5202 ahc->qinfifonext = qinpos; 5203 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5204 5205 while (qinpos != qintail) { 5206 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5207 if (scb == NULL) { 5208 printf("qinpos = %d, SCB index = %d\n", 5209 qinpos, ahc->qinfifo[qinpos]); 5210 panic("Loop 1"); 5211 } 5212 5213 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5214 /* 5215 * We found an scb that needs to be acted on. 5216 */ 5217 found++; 5218 switch (action) { 5219 case SEARCH_COMPLETE: 5220 { 5221 cam_status ostat; 5222 cam_status cstat; 5223 5224 ostat = ahc_get_transaction_status(scb); 5225 if (ostat == CAM_REQ_INPROG) 5226 ahc_set_transaction_status(scb, status); 5227 cstat = ahc_get_transaction_status(scb); 5228 if (cstat != CAM_REQ_CMP) 5229 ahc_freeze_scb(scb); 5230 if ((scb->flags & SCB_ACTIVE) == 0) 5231 printf("Inactive SCB in qinfifo\n"); 5232 ahc_done(ahc, scb); 5233 5234 /* FALLTHROUGH */ 5235 } 5236 case SEARCH_REMOVE: 5237 break; 5238 case SEARCH_COUNT: 5239 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5240 prev_scb = scb; 5241 break; 5242 } 5243 } else { 5244 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5245 prev_scb = scb; 5246 } 5247 qinpos++; 5248 } 5249 5250 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5251 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5252 } else { 5253 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5254 } 5255 5256 if (action != SEARCH_COUNT 5257 && (found != 0) 5258 && (qinstart != ahc->qinfifonext)) { 5259 /* 5260 * The sequencer may be in the process of DMA'ing 5261 * down the SCB at the beginning of the queue. 5262 * This could be problematic if either the first, 5263 * or the second SCB is removed from the queue 5264 * (the first SCB includes a pointer to the "next" 5265 * SCB to DMA). If we have removed any entries, swap 5266 * the first element in the queue with the next HSCB 5267 * so the sequencer will notice that NEXT_QUEUED_SCB 5268 * has changed during its DMA attempt and will retry 5269 * the DMA. 5270 */ 5271 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5272 5273 if (scb == NULL) { 5274 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5275 found, qinstart, ahc->qinfifonext); 5276 panic("First/Second Qinfifo fixup"); 5277 } 5278 /* 5279 * ahc_swap_with_next_hscb forces our next pointer to 5280 * point to the reserved SCB for future commands. Save 5281 * and restore our original next pointer to maintain 5282 * queue integrity. 5283 */ 5284 next = scb->hscb->next; 5285 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5286 ahc_swap_with_next_hscb(ahc, scb); 5287 scb->hscb->next = next; 5288 ahc->qinfifo[qinstart] = scb->hscb->tag; 5289 5290 /* Tell the card about the new head of the qinfifo. */ 5291 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5292 5293 /* Fixup the tail "next" pointer. */ 5294 qintail = ahc->qinfifonext - 1; 5295 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5296 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5297 } 5298 5299 /* 5300 * Search waiting for selection list. 5301 */ 5302 curscbptr = ahc_inb(ahc, SCBPTR); 5303 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5304 prev = SCB_LIST_NULL; 5305 5306 while (next != SCB_LIST_NULL) { 5307 uint8_t scb_index; 5308 5309 ahc_outb(ahc, SCBPTR, next); 5310 scb_index = ahc_inb(ahc, SCB_TAG); 5311 if (scb_index >= ahc->scb_data->numscbs) { 5312 printf("Waiting List inconsistency. " 5313 "SCB index == %d, yet numscbs == %d.", 5314 scb_index, ahc->scb_data->numscbs); 5315 ahc_dump_card_state(ahc); 5316 panic("for safety"); 5317 } 5318 scb = ahc_lookup_scb(ahc, scb_index); 5319 if (scb == NULL) { 5320 printf("scb_index = %d, next = %d\n", 5321 scb_index, next); 5322 panic("Waiting List traversal"); 5323 } 5324 if (ahc_match_scb(ahc, scb, target, channel, 5325 lun, SCB_LIST_NULL, role)) { 5326 /* 5327 * We found an scb that needs to be acted on. 5328 */ 5329 found++; 5330 switch (action) { 5331 case SEARCH_COMPLETE: 5332 { 5333 cam_status ostat; 5334 cam_status cstat; 5335 5336 ostat = ahc_get_transaction_status(scb); 5337 if (ostat == CAM_REQ_INPROG) 5338 ahc_set_transaction_status(scb, status); 5339 cstat = ahc_get_transaction_status(scb); 5340 if (cstat != CAM_REQ_CMP) 5341 ahc_freeze_scb(scb); 5342 if ((scb->flags & SCB_ACTIVE) == 0) 5343 printf("Inactive SCB in Wait List\n"); 5344 ahc_done(ahc, scb); 5345 /* FALLTHROUGH */ 5346 } 5347 case SEARCH_REMOVE: 5348 next = ahc_rem_wscb(ahc, next, prev); 5349 break; 5350 case SEARCH_COUNT: 5351 prev = next; 5352 next = ahc_inb(ahc, SCB_NEXT); 5353 break; 5354 } 5355 } else { 5356 5357 prev = next; 5358 next = ahc_inb(ahc, SCB_NEXT); 5359 } 5360 } 5361 ahc_outb(ahc, SCBPTR, curscbptr); 5362 5363 found += ahc_search_untagged_queues(ahc, /*scsi_xfer*/NULL, target, 5364 channel, lun, status, action); 5365 5366 if (action == SEARCH_COMPLETE) 5367 ahc_release_untagged_queues(ahc); 5368 return (found); 5369 } 5370 5371 int 5372 ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsi_xfer *xs, 5373 int target, char channel, int lun, uint32_t status, 5374 ahc_search_action action) 5375 { 5376 struct scb *scb; 5377 int maxtarget; 5378 int found; 5379 int i; 5380 5381 if (action == SEARCH_COMPLETE) { 5382 /* 5383 * Don't attempt to run any queued untagged transactions 5384 * until we are done with the abort process. 5385 */ 5386 ahc_freeze_untagged_queues(ahc); 5387 } 5388 5389 found = 0; 5390 i = 0; 5391 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5392 5393 maxtarget = 16; 5394 if (target != CAM_TARGET_WILDCARD) { 5395 5396 i = target; 5397 if (channel == 'B') 5398 i += 8; 5399 maxtarget = i + 1; 5400 } 5401 } else { 5402 maxtarget = 0; 5403 } 5404 5405 for (; i < maxtarget; i++) { 5406 struct scb_tailq *untagged_q; 5407 struct scb *next_scb; 5408 5409 untagged_q = &(ahc->untagged_queues[i]); 5410 next_scb = TAILQ_FIRST(untagged_q); 5411 while (next_scb != NULL) { 5412 5413 scb = next_scb; 5414 next_scb = TAILQ_NEXT(scb, links.tqe); 5415 5416 /* 5417 * The head of the list may be the currently 5418 * active untagged command for a device. 5419 * We're only searching for commands that 5420 * have not been started. A transaction 5421 * marked active but still in the qinfifo 5422 * is removed by the qinfifo scanning code 5423 * above. 5424 */ 5425 if ((scb->flags & SCB_ACTIVE) != 0) 5426 continue; 5427 5428 if (ahc_match_scb(ahc, scb, target, channel, lun, 5429 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5430 || (xs != NULL && xs != scb->xs)) 5431 continue; 5432 5433 /* 5434 * We found an scb that needs to be acted on. 5435 */ 5436 found++; 5437 switch (action) { 5438 case SEARCH_COMPLETE: 5439 { 5440 cam_status ostat; 5441 cam_status cstat; 5442 5443 ostat = ahc_get_transaction_status(scb); 5444 if (ostat == CAM_REQ_INPROG) 5445 ahc_set_transaction_status(scb, status); 5446 cstat = ahc_get_transaction_status(scb); 5447 if (cstat != CAM_REQ_CMP) 5448 ahc_freeze_scb(scb); 5449 ahc_done(ahc, scb); 5450 break; 5451 } 5452 case SEARCH_REMOVE: 5453 scb->flags &= ~SCB_UNTAGGEDQ; 5454 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5455 break; 5456 case SEARCH_COUNT: 5457 break; 5458 } 5459 } 5460 } 5461 5462 if (action == SEARCH_COMPLETE) 5463 ahc_release_untagged_queues(ahc); 5464 return (found); 5465 } 5466 5467 int 5468 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5469 int lun, u_int tag, int stop_on_first, int remove, 5470 int save_state) 5471 { 5472 struct scb *scbp; 5473 u_int next; 5474 u_int prev; 5475 u_int count; 5476 u_int active_scb; 5477 5478 count = 0; 5479 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5480 prev = SCB_LIST_NULL; 5481 5482 if (save_state) { 5483 /* restore this when we're done */ 5484 active_scb = ahc_inb(ahc, SCBPTR); 5485 } else 5486 /* Silence compiler */ 5487 active_scb = SCB_LIST_NULL; 5488 5489 while (next != SCB_LIST_NULL) { 5490 u_int scb_index; 5491 5492 ahc_outb(ahc, SCBPTR, next); 5493 scb_index = ahc_inb(ahc, SCB_TAG); 5494 if (scb_index >= ahc->scb_data->numscbs) { 5495 printf("Disconnected List inconsistency. " 5496 "SCB index == %d, yet numscbs == %d.", 5497 scb_index, ahc->scb_data->numscbs); 5498 ahc_dump_card_state(ahc); 5499 panic("for safety"); 5500 } 5501 5502 if (next == prev) { 5503 panic("Disconnected List Loop. " 5504 "cur SCBPTR == %x, prev SCBPTR == %x.", 5505 next, prev); 5506 } 5507 scbp = ahc_lookup_scb(ahc, scb_index); 5508 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5509 tag, ROLE_INITIATOR)) { 5510 count++; 5511 if (remove) { 5512 next = 5513 ahc_rem_scb_from_disc_list(ahc, prev, next); 5514 } else { 5515 prev = next; 5516 next = ahc_inb(ahc, SCB_NEXT); 5517 } 5518 if (stop_on_first) 5519 break; 5520 } else { 5521 prev = next; 5522 next = ahc_inb(ahc, SCB_NEXT); 5523 } 5524 } 5525 if (save_state) 5526 ahc_outb(ahc, SCBPTR, active_scb); 5527 return (count); 5528 } 5529 5530 /* 5531 * Remove an SCB from the on chip list of disconnected transactions. 5532 * This is empty/unused if we are not performing SCB paging. 5533 */ 5534 static u_int 5535 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5536 { 5537 u_int next; 5538 5539 ahc_outb(ahc, SCBPTR, scbptr); 5540 next = ahc_inb(ahc, SCB_NEXT); 5541 5542 ahc_outb(ahc, SCB_CONTROL, 0); 5543 5544 ahc_add_curscb_to_free_list(ahc); 5545 5546 if (prev != SCB_LIST_NULL) { 5547 ahc_outb(ahc, SCBPTR, prev); 5548 ahc_outb(ahc, SCB_NEXT, next); 5549 } else 5550 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5551 5552 return (next); 5553 } 5554 5555 /* 5556 * Add the SCB as selected by SCBPTR onto the on chip list of 5557 * free hardware SCBs. This list is empty/unused if we are not 5558 * performing SCB paging. 5559 */ 5560 static void 5561 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5562 { 5563 /* 5564 * Invalidate the tag so that our abort 5565 * routines don't think it's active. 5566 */ 5567 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5568 5569 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5570 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5571 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5572 } 5573 } 5574 5575 /* 5576 * Manipulate the waiting for selection list and return the 5577 * scb that follows the one that we remove. 5578 */ 5579 static u_int 5580 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5581 { 5582 u_int curscb, next; 5583 5584 /* 5585 * Select the SCB we want to abort and 5586 * pull the next pointer out of it. 5587 */ 5588 curscb = ahc_inb(ahc, SCBPTR); 5589 ahc_outb(ahc, SCBPTR, scbpos); 5590 next = ahc_inb(ahc, SCB_NEXT); 5591 5592 /* Clear the necessary fields */ 5593 ahc_outb(ahc, SCB_CONTROL, 0); 5594 5595 ahc_add_curscb_to_free_list(ahc); 5596 5597 /* update the waiting list */ 5598 if (prev == SCB_LIST_NULL) { 5599 /* First in the list */ 5600 ahc_outb(ahc, WAITING_SCBH, next); 5601 5602 /* 5603 * Ensure we aren't attempting to perform 5604 * selection for this entry. 5605 */ 5606 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5607 } else { 5608 /* 5609 * Select the scb that pointed to us 5610 * and update its next pointer. 5611 */ 5612 ahc_outb(ahc, SCBPTR, prev); 5613 ahc_outb(ahc, SCB_NEXT, next); 5614 } 5615 5616 /* 5617 * Point us back at the original scb position. 5618 */ 5619 ahc_outb(ahc, SCBPTR, curscb); 5620 return next; 5621 } 5622 5623 /******************************** Error Handling ******************************/ 5624 /* 5625 * Abort all SCBs that match the given description (target/channel/lun/tag), 5626 * setting their status to the passed in status if the status has not already 5627 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5628 * is paused before it is called. 5629 */ 5630 int 5631 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5632 int lun, u_int tag, role_t role, uint32_t status) 5633 { 5634 struct scb *scbp; 5635 struct scb *scbp_next; 5636 u_int active_scb; 5637 int i, j; 5638 int maxtarget; 5639 int minlun; 5640 int maxlun; 5641 5642 int found; 5643 5644 /* 5645 * Don't attempt to run any queued untagged transactions 5646 * until we are done with the abort process. 5647 */ 5648 ahc_freeze_untagged_queues(ahc); 5649 5650 /* restore this when we're done */ 5651 active_scb = ahc_inb(ahc, SCBPTR); 5652 5653 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5654 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5655 5656 /* 5657 * Clean out the busy target table for any untagged commands. 5658 */ 5659 i = 0; 5660 maxtarget = 16; 5661 if (target != CAM_TARGET_WILDCARD) { 5662 i = target; 5663 if (channel == 'B') 5664 i += 8; 5665 maxtarget = i + 1; 5666 } 5667 5668 if (lun == CAM_LUN_WILDCARD) { 5669 5670 /* 5671 * Unless we are using an SCB based 5672 * busy targets table, there is only 5673 * one table entry for all luns of 5674 * a target. 5675 */ 5676 minlun = 0; 5677 maxlun = 1; 5678 if ((ahc->flags & AHC_SCB_BTT) != 0) 5679 maxlun = AHC_NUM_LUNS; 5680 } else { 5681 minlun = lun; 5682 maxlun = lun + 1; 5683 } 5684 5685 if (role != ROLE_TARGET) { 5686 for (;i < maxtarget; i++) { 5687 for (j = minlun;j < maxlun; j++) { 5688 u_int scbid; 5689 u_int tcl; 5690 5691 tcl = BUILD_TCL(i << 4, j); 5692 scbid = ahc_index_busy_tcl(ahc, tcl); 5693 scbp = ahc_lookup_scb(ahc, scbid); 5694 if (scbp == NULL 5695 || ahc_match_scb(ahc, scbp, target, channel, 5696 lun, tag, role) == 0) 5697 continue; 5698 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5699 } 5700 } 5701 5702 /* 5703 * Go through the disconnected list and remove any entries we 5704 * have queued for completion, 0'ing their control byte too. 5705 * We save the active SCB and restore it ourselves, so there 5706 * is no reason for this search to restore it too. 5707 */ 5708 ahc_search_disc_list(ahc, target, channel, lun, tag, 5709 /*stop_on_first*/FALSE, /*remove*/TRUE, 5710 /*save_state*/FALSE); 5711 } 5712 5713 /* 5714 * Go through the hardware SCB array looking for commands that 5715 * were active but not on any list. In some cases, these remnants 5716 * might not still have mappings in the scbindex array (e.g. unexpected 5717 * bus free with the same scb queued for an abort). Don't hold this 5718 * against them. 5719 */ 5720 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5721 u_int scbid; 5722 5723 ahc_outb(ahc, SCBPTR, i); 5724 scbid = ahc_inb(ahc, SCB_TAG); 5725 scbp = ahc_lookup_scb(ahc, scbid); 5726 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5727 || (scbp != NULL 5728 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5729 ahc_add_curscb_to_free_list(ahc); 5730 } 5731 5732 /* 5733 * Go through the pending CCB list and look for 5734 * commands for this target that are still active. 5735 * These are other tagged commands that were 5736 * disconnected when the reset occurred. 5737 */ 5738 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5739 while (scbp_next != NULL) { 5740 scbp = scbp_next; 5741 scbp_next = LIST_NEXT(scbp, pending_links); 5742 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5743 cam_status ostat; 5744 5745 ostat = ahc_get_transaction_status(scbp); 5746 if (ostat == CAM_REQ_INPROG) 5747 ahc_set_transaction_status(scbp, status); 5748 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5749 ahc_freeze_scb(scbp); 5750 if ((scbp->flags & SCB_ACTIVE) == 0) 5751 printf("Inactive SCB on pending list\n"); 5752 ahc_done(ahc, scbp); 5753 found++; 5754 } 5755 } 5756 ahc_outb(ahc, SCBPTR, active_scb); 5757 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5758 ahc_release_untagged_queues(ahc); 5759 return found; 5760 } 5761 5762 static void 5763 ahc_reset_current_bus(struct ahc_softc *ahc) 5764 { 5765 uint8_t scsiseq; 5766 5767 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5768 scsiseq = ahc_inb(ahc, SCSISEQ); 5769 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5770 ahc_flush_device_writes(ahc); 5771 aic_delay(AHC_BUSRESET_DELAY); 5772 /* Turn off the bus reset */ 5773 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5774 5775 ahc_clear_intstat(ahc); 5776 5777 /* Re-enable reset interrupts */ 5778 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5779 } 5780 5781 int 5782 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5783 { 5784 struct ahc_devinfo devinfo; 5785 u_int initiator, target, max_scsiid; 5786 u_int sblkctl; 5787 u_int scsiseq; 5788 u_int simode1; 5789 int found; 5790 int restart_needed; 5791 char cur_channel; 5792 5793 ahc->pending_device = NULL; 5794 5795 ahc_compile_devinfo(&devinfo, 5796 CAM_TARGET_WILDCARD, 5797 CAM_TARGET_WILDCARD, 5798 CAM_LUN_WILDCARD, 5799 channel, ROLE_UNKNOWN); 5800 ahc_pause(ahc); 5801 5802 /* Make sure the sequencer is in a safe location. */ 5803 ahc_clear_critical_section(ahc); 5804 5805 /* 5806 * Run our command complete fifos to ensure that we perform 5807 * completion processing on any commands that 'completed' 5808 * before the reset occurred. 5809 */ 5810 ahc_run_qoutfifo(ahc); 5811 #ifdef AHC_TARGET_MODE 5812 /* 5813 * XXX - In Twin mode, the tqinfifo may have commands 5814 * for an unaffected channel in it. However, if 5815 * we have run out of ATIO resources to drain that 5816 * queue, we may not get them all out here. Further, 5817 * the blocked transactions for the reset channel 5818 * should just be killed off, irrespecitve of whether 5819 * we are blocked on ATIO resources. Write a routine 5820 * to compact the tqinfifo appropriately. 5821 */ 5822 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5823 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5824 } 5825 #endif 5826 5827 /* 5828 * Reset the bus if we are initiating this reset 5829 */ 5830 sblkctl = ahc_inb(ahc, SBLKCTL); 5831 cur_channel = 'A'; 5832 if ((ahc->features & AHC_TWIN) != 0 5833 && ((sblkctl & SELBUSB) != 0)) 5834 cur_channel = 'B'; 5835 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5836 if (cur_channel != channel) { 5837 /* Case 1: Command for another bus is active 5838 * Stealthily reset the other bus without 5839 * upsetting the current bus. 5840 */ 5841 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5842 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5843 #ifdef AHC_TARGET_MODE 5844 /* 5845 * Bus resets clear ENSELI, so we cannot 5846 * defer re-enabling bus reset interrupts 5847 * if we are in target mode. 5848 */ 5849 if ((ahc->flags & AHC_TARGETROLE) != 0) 5850 simode1 |= ENSCSIRST; 5851 #endif 5852 ahc_outb(ahc, SIMODE1, simode1); 5853 if (initiate_reset) 5854 ahc_reset_current_bus(ahc); 5855 ahc_clear_intstat(ahc); 5856 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5857 ahc_outb(ahc, SBLKCTL, sblkctl); 5858 restart_needed = FALSE; 5859 } else { 5860 /* Case 2: A command from this bus is active or we're idle */ 5861 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5862 #ifdef AHC_TARGET_MODE 5863 /* 5864 * Bus resets clear ENSELI, so we cannot 5865 * defer re-enabling bus reset interrupts 5866 * if we are in target mode. 5867 */ 5868 if ((ahc->flags & AHC_TARGETROLE) != 0) 5869 simode1 |= ENSCSIRST; 5870 #endif 5871 ahc_outb(ahc, SIMODE1, simode1); 5872 if (initiate_reset) 5873 ahc_reset_current_bus(ahc); 5874 ahc_clear_intstat(ahc); 5875 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5876 restart_needed = TRUE; 5877 } 5878 5879 /* 5880 * Clean up all the state information for the 5881 * pending transactions on this bus. 5882 */ 5883 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 5884 CAM_LUN_WILDCARD, SCB_LIST_NULL, 5885 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 5886 5887 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5888 5889 #ifdef AHC_TARGET_MODE 5890 /* 5891 * Send an immediate notify ccb to all target more peripheral 5892 * drivers affected by this action. 5893 */ 5894 for (target = 0; target <= max_scsiid; target++) { 5895 struct ahc_tmode_tstate* tstate; 5896 u_int lun; 5897 5898 tstate = ahc->enabled_targets[target]; 5899 if (tstate == NULL) 5900 continue; 5901 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 5902 struct ahc_tmode_lstate* lstate; 5903 5904 lstate = tstate->enabled_luns[lun]; 5905 if (lstate == NULL) 5906 continue; 5907 5908 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 5909 EVENT_TYPE_BUS_RESET, /*arg*/0); 5910 ahc_send_lstate_events(ahc, lstate); 5911 } 5912 } 5913 #endif 5914 /* Notify the XPT that a bus reset occurred */ 5915 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 5916 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 5917 5918 /* 5919 * Revert to async/narrow transfers until we renegotiate. 5920 */ 5921 for (target = 0; target <= max_scsiid; target++) { 5922 5923 if (ahc->enabled_targets[target] == NULL) 5924 continue; 5925 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5926 ahc_compile_devinfo(&devinfo, target, initiator, 5927 CAM_LUN_WILDCARD, 5928 channel, ROLE_UNKNOWN); 5929 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5930 AHC_TRANS_CUR, /*paused*/TRUE); 5931 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 5932 /*period*/0, /*offset*/0, 5933 /*ppr_options*/0, AHC_TRANS_CUR, 5934 /*paused*/TRUE); 5935 } 5936 } 5937 5938 if (restart_needed) 5939 ahc_restart(ahc); 5940 else 5941 ahc_unpause(ahc); 5942 return found; 5943 } 5944 5945 5946 /***************************** Residual Processing ****************************/ 5947 /* 5948 * Calculate the residual for a just completed SCB. 5949 */ 5950 void 5951 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 5952 { 5953 struct hardware_scb *hscb; 5954 struct status_pkt *spkt; 5955 uint32_t sgptr; 5956 uint32_t resid_sgptr; 5957 uint32_t resid; 5958 5959 /* 5960 * 5 cases. 5961 * 1) No residual. 5962 * SG_RESID_VALID clear in sgptr. 5963 * 2) Transferless command 5964 * 3) Never performed any transfers. 5965 * sgptr has SG_FULL_RESID set. 5966 * 4) No residual but target did not 5967 * save data pointers after the 5968 * last transfer, so sgptr was 5969 * never updated. 5970 * 5) We have a partial residual. 5971 * Use residual_sgptr to determine 5972 * where we are. 5973 */ 5974 5975 hscb = scb->hscb; 5976 sgptr = aic_le32toh(hscb->sgptr); 5977 if ((sgptr & SG_RESID_VALID) == 0) 5978 /* Case 1 */ 5979 return; 5980 sgptr &= ~SG_RESID_VALID; 5981 5982 if ((sgptr & SG_LIST_NULL) != 0) 5983 /* Case 2 */ 5984 return; 5985 5986 spkt = &hscb->shared_data.status; 5987 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr); 5988 if ((sgptr & SG_FULL_RESID) != 0) { 5989 /* Case 3 */ 5990 resid = ahc_get_transfer_length(scb); 5991 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 5992 /* Case 4 */ 5993 return; 5994 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 5995 panic("Bogus resid sgptr value 0x%x", resid_sgptr); 5996 } else { 5997 struct ahc_dma_seg *sg; 5998 5999 /* 6000 * Remainder of the SG where the transfer 6001 * stopped. 6002 */ 6003 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6004 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6005 6006 /* The residual sg_ptr always points to the next sg */ 6007 sg--; 6008 6009 /* 6010 * Add up the contents of all residual 6011 * SG segments that are after the SG where 6012 * the transfer stopped. 6013 */ 6014 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6015 sg++; 6016 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 6017 } 6018 } 6019 if ((scb->flags & SCB_SENSE) == 0) 6020 ahc_set_residual(scb, resid); 6021 else 6022 ahc_set_sense_residual(scb, resid); 6023 6024 #ifdef AHC_DEBUG 6025 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6026 ahc_print_path(ahc, scb); 6027 printf("Handled %sResidual of %d bytes\n", 6028 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6029 } 6030 #endif 6031 } 6032 6033 /******************************* Target Mode **********************************/ 6034 #ifdef AHC_TARGET_MODE 6035 /* 6036 * Add a target mode event to this lun's queue 6037 */ 6038 static void 6039 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6040 u_int initiator_id, u_int event_type, u_int event_arg) 6041 { 6042 struct ahc_tmode_event *event; 6043 int pending; 6044 6045 xpt_freeze_devq(lstate->path, /*count*/1); 6046 if (lstate->event_w_idx >= lstate->event_r_idx) 6047 pending = lstate->event_w_idx - lstate->event_r_idx; 6048 else 6049 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6050 - (lstate->event_r_idx - lstate->event_w_idx); 6051 6052 if (event_type == EVENT_TYPE_BUS_RESET 6053 || event_type == MSG_BUS_DEV_RESET) { 6054 /* 6055 * Any earlier events are irrelevant, so reset our buffer. 6056 * This has the effect of allowing us to deal with reset 6057 * floods (an external device holding down the reset line) 6058 * without losing the event that is really interesting. 6059 */ 6060 lstate->event_r_idx = 0; 6061 lstate->event_w_idx = 0; 6062 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6063 } 6064 6065 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6066 xpt_print_path(lstate->path); 6067 printf("immediate event %x:%x lost\n", 6068 lstate->event_buffer[lstate->event_r_idx].event_type, 6069 lstate->event_buffer[lstate->event_r_idx].event_arg); 6070 lstate->event_r_idx++; 6071 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6072 lstate->event_r_idx = 0; 6073 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6074 } 6075 6076 event = &lstate->event_buffer[lstate->event_w_idx]; 6077 event->initiator_id = initiator_id; 6078 event->event_type = event_type; 6079 event->event_arg = event_arg; 6080 lstate->event_w_idx++; 6081 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6082 lstate->event_w_idx = 0; 6083 } 6084 6085 /* 6086 * Send any target mode events queued up waiting 6087 * for immediate notify resources. 6088 */ 6089 void 6090 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6091 { 6092 struct ccb_hdr *ccbh; 6093 struct ccb_immed_notify *inot; 6094 6095 while (lstate->event_r_idx != lstate->event_w_idx 6096 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6097 struct ahc_tmode_event *event; 6098 6099 event = &lstate->event_buffer[lstate->event_r_idx]; 6100 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6101 inot = (struct ccb_immed_notify *)ccbh; 6102 switch (event->event_type) { 6103 case EVENT_TYPE_BUS_RESET: 6104 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6105 break; 6106 default: 6107 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6108 inot->message_args[0] = event->event_type; 6109 inot->message_args[1] = event->event_arg; 6110 break; 6111 } 6112 inot->initiator_id = event->initiator_id; 6113 inot->sense_len = 0; 6114 xpt_done((union ccb *)inot); 6115 lstate->event_r_idx++; 6116 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6117 lstate->event_r_idx = 0; 6118 } 6119 } 6120 #endif 6121 6122 /******************** Sequencer Program Patching/Download *********************/ 6123 6124 #ifdef AHC_DUMP_SEQ 6125 void 6126 ahc_dumpseq(struct ahc_softc* ahc) 6127 { 6128 int i; 6129 6130 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6131 ahc_outb(ahc, SEQADDR0, 0); 6132 ahc_outb(ahc, SEQADDR1, 0); 6133 for (i = 0; i < ahc->instruction_ram_size; i++) { 6134 uint8_t ins_bytes[4]; 6135 6136 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6137 printf("0x%08x\n", ins_bytes[0] << 24 6138 | ins_bytes[1] << 16 6139 | ins_bytes[2] << 8 6140 | ins_bytes[3]); 6141 } 6142 } 6143 #endif 6144 6145 static int 6146 ahc_loadseq(struct ahc_softc *ahc) 6147 { 6148 struct cs cs_table[NUM_CRITICAL_SECTIONS]; 6149 u_int begin_set[NUM_CRITICAL_SECTIONS]; 6150 u_int end_set[NUM_CRITICAL_SECTIONS]; 6151 const struct patch *cur_patch; 6152 u_int cs_count; 6153 u_int cur_cs; 6154 u_int i; 6155 u_int skip_addr; 6156 u_int sg_prefetch_cnt; 6157 int downloaded; 6158 uint8_t download_consts[7]; 6159 6160 /* 6161 * Start out with 0 critical sections 6162 * that apply to this firmware load. 6163 */ 6164 cs_count = 0; 6165 cur_cs = 0; 6166 memset(begin_set, 0, sizeof(begin_set)); 6167 memset(end_set, 0, sizeof(end_set)); 6168 6169 /* Setup downloadable constant table */ 6170 download_consts[QOUTFIFO_OFFSET] = 0; 6171 if (ahc->targetcmds != NULL) 6172 download_consts[QOUTFIFO_OFFSET] += 32; 6173 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6174 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6175 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6176 sg_prefetch_cnt = ahc->pci_cachesize; 6177 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6178 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6179 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6180 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6181 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6182 6183 cur_patch = patches; 6184 downloaded = 0; 6185 skip_addr = 0; 6186 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6187 ahc_outb(ahc, SEQADDR0, 0); 6188 ahc_outb(ahc, SEQADDR1, 0); 6189 6190 for (i = 0; i < sizeof(seqprog)/4; i++) { 6191 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6192 /* 6193 * Don't download this instruction as it 6194 * is in a patch that was removed. 6195 */ 6196 continue; 6197 } 6198 6199 if (downloaded == ahc->instruction_ram_size) { 6200 /* 6201 * We're about to exceed the instruction 6202 * storage capacity for this chip. Fail 6203 * the load. 6204 */ 6205 printf("\n%s: Program too large for instruction memory " 6206 "size of %d!\n", ahc_name(ahc), 6207 ahc->instruction_ram_size); 6208 return (ENOMEM); 6209 } 6210 6211 /* 6212 * Move through the CS table until we find a CS 6213 * that might apply to this instruction. 6214 */ 6215 for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) { 6216 if (critical_sections[cur_cs].end <= i) { 6217 if (begin_set[cs_count] == TRUE 6218 && end_set[cs_count] == FALSE) { 6219 cs_table[cs_count].end = downloaded; 6220 end_set[cs_count] = TRUE; 6221 cs_count++; 6222 } 6223 continue; 6224 } 6225 if (critical_sections[cur_cs].begin <= i 6226 && begin_set[cs_count] == FALSE) { 6227 cs_table[cs_count].begin = downloaded; 6228 begin_set[cs_count] = TRUE; 6229 } 6230 break; 6231 } 6232 ahc_download_instr(ahc, i, download_consts); 6233 downloaded++; 6234 } 6235 6236 ahc->num_critical_sections = cs_count; 6237 if (cs_count != 0) { 6238 6239 cs_count *= sizeof(struct cs); 6240 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6241 if (ahc->critical_sections == NULL) 6242 panic("ahc_loadseq: Could not malloc"); 6243 memcpy(ahc->critical_sections, cs_table, cs_count); 6244 } 6245 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6246 6247 if (bootverbose) { 6248 printf(" %d instructions downloaded\n", downloaded); 6249 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6250 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6251 } 6252 return (0); 6253 } 6254 6255 static int 6256 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 6257 u_int start_instr, u_int *skip_addr) 6258 { 6259 const struct patch *cur_patch; 6260 const struct patch *last_patch; 6261 u_int num_patches; 6262 6263 num_patches = sizeof(patches)/sizeof(struct patch); 6264 last_patch = &patches[num_patches]; 6265 cur_patch = *start_patch; 6266 6267 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6268 6269 if (cur_patch->patch_func(ahc) == 0) { 6270 6271 /* Start rejecting code */ 6272 *skip_addr = start_instr + cur_patch->skip_instr; 6273 cur_patch += cur_patch->skip_patch; 6274 } else { 6275 /* Accepted this patch. Advance to the next 6276 * one and wait for our intruction pointer to 6277 * hit this point. 6278 */ 6279 cur_patch++; 6280 } 6281 } 6282 6283 *start_patch = cur_patch; 6284 if (start_instr < *skip_addr) 6285 /* Still skipping */ 6286 return (0); 6287 6288 return (1); 6289 } 6290 6291 static void 6292 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6293 { 6294 union ins_formats instr; 6295 struct ins_format1 *fmt1_ins; 6296 struct ins_format3 *fmt3_ins; 6297 u_int opcode; 6298 6299 /* 6300 * The firmware is always compiled into a little endian format. 6301 */ 6302 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6303 6304 fmt1_ins = &instr.format1; 6305 fmt3_ins = NULL; 6306 6307 /* Pull the opcode */ 6308 opcode = instr.format1.opcode; 6309 switch (opcode) { 6310 case AIC_OP_JMP: 6311 case AIC_OP_JC: 6312 case AIC_OP_JNC: 6313 case AIC_OP_CALL: 6314 case AIC_OP_JNE: 6315 case AIC_OP_JNZ: 6316 case AIC_OP_JE: 6317 case AIC_OP_JZ: 6318 { 6319 const struct patch *cur_patch; 6320 int address_offset; 6321 u_int address; 6322 u_int skip_addr; 6323 u_int i; 6324 6325 fmt3_ins = &instr.format3; 6326 address_offset = 0; 6327 address = fmt3_ins->address; 6328 cur_patch = patches; 6329 skip_addr = 0; 6330 6331 for (i = 0; i < address;) { 6332 6333 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6334 6335 if (skip_addr > i) { 6336 int end_addr; 6337 6338 end_addr = MIN(address, skip_addr); 6339 address_offset += end_addr - i; 6340 i = skip_addr; 6341 } else { 6342 i++; 6343 } 6344 } 6345 address -= address_offset; 6346 fmt3_ins->address = address; 6347 /* FALLTHROUGH */ 6348 } 6349 case AIC_OP_OR: 6350 case AIC_OP_AND: 6351 case AIC_OP_XOR: 6352 case AIC_OP_ADD: 6353 case AIC_OP_ADC: 6354 case AIC_OP_BMOV: 6355 if (fmt1_ins->parity != 0) { 6356 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6357 } 6358 fmt1_ins->parity = 0; 6359 if ((ahc->features & AHC_CMD_CHAN) == 0 6360 && opcode == AIC_OP_BMOV) { 6361 /* 6362 * Block move was added at the same time 6363 * as the command channel. Verify that 6364 * this is only a move of a single element 6365 * and convert the BMOV to a MOV 6366 * (AND with an immediate of FF). 6367 */ 6368 if (fmt1_ins->immediate != 1) 6369 panic("%s: BMOV not supported", 6370 ahc_name(ahc)); 6371 fmt1_ins->opcode = AIC_OP_AND; 6372 fmt1_ins->immediate = 0xff; 6373 } 6374 /* FALLTHROUGH */ 6375 case AIC_OP_ROL: 6376 if ((ahc->features & AHC_ULTRA2) != 0) { 6377 int i, count; 6378 6379 /* Calculate odd parity for the instruction */ 6380 for (i = 0, count = 0; i < 31; i++) { 6381 uint32_t mask; 6382 6383 mask = 0x01 << i; 6384 if ((instr.integer & mask) != 0) 6385 count++; 6386 } 6387 if ((count & 0x01) == 0) 6388 instr.format1.parity = 1; 6389 } else { 6390 /* Compress the instruction for older sequencers */ 6391 if (fmt3_ins != NULL) { 6392 instr.integer = 6393 fmt3_ins->immediate 6394 | (fmt3_ins->source << 8) 6395 | (fmt3_ins->address << 16) 6396 | (fmt3_ins->opcode << 25); 6397 } else { 6398 instr.integer = 6399 fmt1_ins->immediate 6400 | (fmt1_ins->source << 8) 6401 | (fmt1_ins->destination << 16) 6402 | (fmt1_ins->ret << 24) 6403 | (fmt1_ins->opcode << 25); 6404 } 6405 } 6406 /* The sequencer is a little endian cpu */ 6407 instr.integer = aic_htole32(instr.integer); 6408 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6409 break; 6410 default: 6411 panic("Unknown opcode encountered in seq program"); 6412 break; 6413 } 6414 } 6415 6416 #ifndef SMALL_KERNEL 6417 int 6418 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6419 const char *name, u_int address, u_int value, 6420 u_int *cur_column, u_int wrap_point) 6421 { 6422 u_int printed_mask; 6423 int entry, printed; 6424 6425 if (cur_column != NULL && *cur_column >= wrap_point) { 6426 printf("\n"); 6427 *cur_column = 0; 6428 } 6429 printed = printf("%s[0x%x]", name, value); 6430 if (table == NULL) { 6431 printed += printf(" "); 6432 if (cur_column != NULL) 6433 *cur_column += printed; 6434 return (printed); 6435 } 6436 6437 printed_mask = 0; 6438 while (printed_mask != 0xFF) { 6439 for (entry = 0; entry < num_entries; entry++) { 6440 if (((value & table[entry].mask) != table[entry].value) 6441 || ((printed_mask & table[entry].mask) == 6442 table[entry].mask)) 6443 continue; 6444 6445 printed += printf("%s%s", 6446 printed_mask == 0 ? ":(" : "|", 6447 table[entry].name); 6448 printed_mask |= table[entry].mask; 6449 6450 break; 6451 } 6452 if (entry >= num_entries) 6453 break; 6454 } 6455 6456 printed += printf("%s", printed_mask == 0 ? " " : ") "); 6457 if (cur_column != NULL) 6458 *cur_column += printed; 6459 6460 return (printed); 6461 } 6462 #endif 6463 6464 void 6465 ahc_dump_card_state(struct ahc_softc *ahc) 6466 { 6467 #ifndef SMALL_KERNEL 6468 struct scb *scb; 6469 struct scb_tailq *untagged_q; 6470 u_int cur_col; 6471 int paused; 6472 int target; 6473 int maxtarget; 6474 int i; 6475 uint8_t last_phase; 6476 uint8_t qinpos; 6477 uint8_t qintail; 6478 uint8_t qoutpos; 6479 uint8_t scb_index; 6480 uint8_t saved_scbptr; 6481 6482 if (ahc_is_paused(ahc)) { 6483 paused = 1; 6484 } else { 6485 paused = 0; 6486 ahc_pause(ahc); 6487 } 6488 6489 saved_scbptr = ahc_inb(ahc, SCBPTR); 6490 last_phase = ahc_inb(ahc, LASTPHASE); 6491 printf("================== Dump Card State Begins =================\n" 6492 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6493 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6494 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6495 if (paused) 6496 printf("Card was paused\n"); 6497 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6498 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6499 ahc_inb(ahc, ARG_2)); 6500 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6501 ahc_inb(ahc, SCBPTR)); 6502 cur_col = 0; 6503 if ((ahc->features & AHC_DT) != 0) 6504 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6505 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6506 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6507 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6508 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6509 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6510 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6511 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6512 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6513 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6514 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6515 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6516 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6517 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6518 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6519 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6520 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6521 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6522 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6523 if (cur_col != 0) 6524 printf("\n"); 6525 printf("STACK:"); 6526 for (i = 0; i < STACK_SIZE; i++) 6527 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6528 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6529 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6530 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6531 /* QINFIFO */ 6532 printf("QINFIFO entries: "); 6533 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6534 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6535 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6536 } else 6537 qinpos = ahc_inb(ahc, QINPOS); 6538 qintail = ahc->qinfifonext; 6539 while (qinpos != qintail) { 6540 printf("%d ", ahc->qinfifo[qinpos]); 6541 qinpos++; 6542 } 6543 printf("\n"); 6544 6545 printf("Waiting Queue entries: "); 6546 scb_index = ahc_inb(ahc, WAITING_SCBH); 6547 i = 0; 6548 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6549 ahc_outb(ahc, SCBPTR, scb_index); 6550 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6551 scb_index = ahc_inb(ahc, SCB_NEXT); 6552 } 6553 printf("\n"); 6554 6555 printf("Disconnected Queue entries: "); 6556 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6557 i = 0; 6558 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6559 ahc_outb(ahc, SCBPTR, scb_index); 6560 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6561 scb_index = ahc_inb(ahc, SCB_NEXT); 6562 } 6563 printf("\n"); 6564 6565 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6566 printf("QOUTFIFO entries: "); 6567 qoutpos = ahc->qoutfifonext; 6568 i = 0; 6569 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6570 printf("%d ", ahc->qoutfifo[qoutpos]); 6571 qoutpos++; 6572 } 6573 printf("\n"); 6574 6575 printf("Sequencer Free SCB List: "); 6576 scb_index = ahc_inb(ahc, FREE_SCBH); 6577 i = 0; 6578 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6579 ahc_outb(ahc, SCBPTR, scb_index); 6580 printf("%d ", scb_index); 6581 scb_index = ahc_inb(ahc, SCB_NEXT); 6582 } 6583 printf("\n"); 6584 6585 printf("Sequencer SCB Info: "); 6586 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6587 ahc_outb(ahc, SCBPTR, i); 6588 /*cur_col =*/ printf("\n%3d ", i); 6589 6590 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6591 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6592 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6593 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6594 } 6595 printf("\n"); 6596 6597 printf("Pending list: "); 6598 i = 0; 6599 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6600 if (i++ > 256) 6601 break; 6602 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag); 6603 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6604 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6605 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6606 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6607 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6608 printf("("); 6609 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6610 &cur_col, 60); 6611 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6612 printf(")"); 6613 } 6614 } 6615 printf("\n"); 6616 6617 printf("Kernel Free SCB list: "); 6618 i = 0; 6619 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6620 if (i++ > 256) 6621 break; 6622 printf("%d ", scb->hscb->tag); 6623 } 6624 printf("\n"); 6625 6626 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6627 for (target = 0; target <= maxtarget; target++) { 6628 untagged_q = &ahc->untagged_queues[target]; 6629 if (TAILQ_FIRST(untagged_q) == NULL) 6630 continue; 6631 printf("Untagged Q(%d): ", target); 6632 i = 0; 6633 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6634 if (i++ > 256) 6635 break; 6636 printf("%d ", scb->hscb->tag); 6637 } 6638 printf("\n"); 6639 } 6640 6641 ahc_platform_dump_card_state(ahc); 6642 printf("\n================= Dump Card State Ends ==================\n"); 6643 ahc_outb(ahc, SCBPTR, saved_scbptr); 6644 if (paused == 0) 6645 ahc_unpause(ahc); 6646 #endif 6647 } 6648 6649 /************************* Target Mode ****************************************/ 6650 #ifdef AHC_TARGET_MODE 6651 cam_status 6652 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6653 struct ahc_tmode_tstate **tstate, 6654 struct ahc_tmode_lstate **lstate, 6655 int notfound_failure) 6656 { 6657 6658 if ((ahc->features & AHC_TARGETMODE) == 0) 6659 return (CAM_REQ_INVALID); 6660 6661 /* 6662 * Handle the 'black hole' device that sucks up 6663 * requests to unattached luns on enabled targets. 6664 */ 6665 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6666 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6667 *tstate = NULL; 6668 *lstate = ahc->black_hole; 6669 } else { 6670 u_int max_id; 6671 6672 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6673 if (ccb->ccb_h.target_id > max_id) 6674 return (CAM_TID_INVALID); 6675 6676 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6677 return (CAM_LUN_INVALID); 6678 6679 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6680 *lstate = NULL; 6681 if (*tstate != NULL) 6682 *lstate = 6683 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6684 } 6685 6686 if (notfound_failure != 0 && *lstate == NULL) 6687 return (CAM_PATH_INVALID); 6688 6689 return (CAM_REQ_CMP); 6690 } 6691 6692 void 6693 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6694 { 6695 struct ahc_tmode_tstate *tstate; 6696 struct ahc_tmode_lstate *lstate; 6697 struct ccb_en_lun *cel; 6698 cam_status status; 6699 u_long s; 6700 u_int target; 6701 u_int lun; 6702 u_int target_mask; 6703 u_int our_id; 6704 int error; 6705 char channel; 6706 6707 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6708 /*notfound_failure*/FALSE); 6709 6710 if (status != CAM_REQ_CMP) { 6711 ccb->ccb_h.status = status; 6712 return; 6713 } 6714 6715 if (cam_sim_bus(sim) == 0) 6716 our_id = ahc->our_id; 6717 else 6718 our_id = ahc->our_id_b; 6719 6720 if (ccb->ccb_h.target_id != our_id) { 6721 /* 6722 * our_id represents our initiator ID, or 6723 * the ID of the first target to have an 6724 * enabled lun in target mode. There are 6725 * two cases that may preclude enabling a 6726 * target id other than our_id. 6727 * 6728 * o our_id is for an active initiator role. 6729 * Since the hardware does not support 6730 * reselections to the initiator role at 6731 * anything other than our_id, and our_id 6732 * is used by the hardware to indicate the 6733 * ID to use for both select-out and 6734 * reselect-out operations, the only target 6735 * ID we can support in this mode is our_id. 6736 * 6737 * o The MULTARGID feature is not available and 6738 * a previous target mode ID has been enabled. 6739 */ 6740 if ((ahc->features & AHC_MULTIROLE) != 0) { 6741 6742 if ((ahc->features & AHC_MULTI_TID) != 0 6743 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6744 /* 6745 * Only allow additional targets if 6746 * the initiator role is disabled. 6747 * The hardware cannot handle a re-select-in 6748 * on the initiator id during a re-select-out 6749 * on a different target id. 6750 */ 6751 status = CAM_TID_INVALID; 6752 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6753 || ahc->enabled_luns > 0) { 6754 /* 6755 * Only allow our target id to change 6756 * if the initiator role is not configured 6757 * and there are no enabled luns which 6758 * are attached to the currently registered 6759 * scsi id. 6760 */ 6761 status = CAM_TID_INVALID; 6762 } 6763 } else if ((ahc->features & AHC_MULTI_TID) == 0 6764 && ahc->enabled_luns > 0) { 6765 6766 status = CAM_TID_INVALID; 6767 } 6768 } 6769 6770 if (status != CAM_REQ_CMP) { 6771 ccb->ccb_h.status = status; 6772 return; 6773 } 6774 6775 /* 6776 * We now have an id that is valid. 6777 * If we aren't in target mode, switch modes. 6778 */ 6779 if ((ahc->flags & AHC_TARGETROLE) == 0 6780 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6781 u_long s; 6782 ahc_flag saved_flags; 6783 6784 printf("Configuring Target Mode\n"); 6785 s = splbio(); 6786 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6787 ccb->ccb_h.status = CAM_BUSY; 6788 splx(s); 6789 return; 6790 } 6791 saved_flags = ahc->flags; 6792 ahc->flags |= AHC_TARGETROLE; 6793 if ((ahc->features & AHC_MULTIROLE) == 0) 6794 ahc->flags &= ~AHC_INITIATORROLE; 6795 ahc_pause(ahc); 6796 error = ahc_loadseq(ahc); 6797 if (error != 0) { 6798 /* 6799 * Restore original configuration and notify 6800 * the caller that we cannot support target mode. 6801 * Since the adapter started out in this 6802 * configuration, the firmware load will succeed, 6803 * so there is no point in checking ahc_loadseq's 6804 * return value. 6805 */ 6806 ahc->flags = saved_flags; 6807 (void)ahc_loadseq(ahc); 6808 ahc_restart(ahc); 6809 splx(s); 6810 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 6811 return; 6812 } 6813 ahc_restart(ahc); 6814 splx(s); 6815 } 6816 cel = &ccb->cel; 6817 target = ccb->ccb_h.target_id; 6818 lun = ccb->ccb_h.target_lun; 6819 channel = SIM_CHANNEL(ahc, sim); 6820 target_mask = 0x01 << target; 6821 if (channel == 'B') 6822 target_mask <<= 8; 6823 6824 if (cel->enable != 0) { 6825 u_int scsiseq; 6826 6827 /* Are we already enabled?? */ 6828 if (lstate != NULL) { 6829 xpt_print_path(ccb->ccb_h.path); 6830 printf("Lun already enabled\n"); 6831 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6832 return; 6833 } 6834 6835 if (cel->grp6_len != 0 6836 || cel->grp7_len != 0) { 6837 /* 6838 * Don't (yet?) support vendor 6839 * specific commands. 6840 */ 6841 ccb->ccb_h.status = CAM_REQ_INVALID; 6842 printf("Non-zero Group Codes\n"); 6843 return; 6844 } 6845 6846 /* 6847 * Seems to be okay. 6848 * Setup our data structures. 6849 */ 6850 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6851 tstate = ahc_alloc_tstate(ahc, target, channel); 6852 if (tstate == NULL) { 6853 xpt_print_path(ccb->ccb_h.path); 6854 printf("Couldn't allocate tstate\n"); 6855 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6856 return; 6857 } 6858 } 6859 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT | M_ZERO); 6860 if (lstate == NULL) { 6861 xpt_print_path(ccb->ccb_h.path); 6862 printf("Couldn't allocate lstate\n"); 6863 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6864 return; 6865 } 6866 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6867 xpt_path_path_id(ccb->ccb_h.path), 6868 xpt_path_target_id(ccb->ccb_h.path), 6869 xpt_path_lun_id(ccb->ccb_h.path)); 6870 if (status != CAM_REQ_CMP) { 6871 free(lstate, M_DEVBUF); 6872 xpt_print_path(ccb->ccb_h.path); 6873 printf("Couldn't allocate path\n"); 6874 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6875 return; 6876 } 6877 SLIST_INIT(&lstate->accept_tios); 6878 SLIST_INIT(&lstate->immed_notifies); 6879 s = splbio(); 6880 ahc_pause(ahc); 6881 if (target != CAM_TARGET_WILDCARD) { 6882 tstate->enabled_luns[lun] = lstate; 6883 ahc->enabled_luns++; 6884 6885 if ((ahc->features & AHC_MULTI_TID) != 0) { 6886 u_int targid_mask; 6887 6888 targid_mask = ahc_inb(ahc, TARGID) 6889 | (ahc_inb(ahc, TARGID + 1) << 8); 6890 6891 targid_mask |= target_mask; 6892 ahc_outb(ahc, TARGID, targid_mask); 6893 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 6894 6895 ahc_update_scsiid(ahc, targid_mask); 6896 } else { 6897 u_int our_id; 6898 char channel; 6899 6900 channel = SIM_CHANNEL(ahc, sim); 6901 our_id = SIM_SCSI_ID(ahc, sim); 6902 6903 /* 6904 * This can only happen if selections 6905 * are not enabled 6906 */ 6907 if (target != our_id) { 6908 u_int sblkctl; 6909 char cur_channel; 6910 int swap; 6911 6912 sblkctl = ahc_inb(ahc, SBLKCTL); 6913 cur_channel = (sblkctl & SELBUSB) 6914 ? 'B' : 'A'; 6915 if ((ahc->features & AHC_TWIN) == 0) 6916 cur_channel = 'A'; 6917 swap = cur_channel != channel; 6918 if (channel == 'A') 6919 ahc->our_id = target; 6920 else 6921 ahc->our_id_b = target; 6922 6923 if (swap) 6924 ahc_outb(ahc, SBLKCTL, 6925 sblkctl ^ SELBUSB); 6926 6927 ahc_outb(ahc, SCSIID, target); 6928 6929 if (swap) 6930 ahc_outb(ahc, SBLKCTL, sblkctl); 6931 } 6932 } 6933 } else 6934 ahc->black_hole = lstate; 6935 /* Allow select-in operations */ 6936 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 6937 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 6938 scsiseq |= ENSELI; 6939 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 6940 scsiseq = ahc_inb(ahc, SCSISEQ); 6941 scsiseq |= ENSELI; 6942 ahc_outb(ahc, SCSISEQ, scsiseq); 6943 } 6944 ahc_unpause(ahc); 6945 splx(s); 6946 ccb->ccb_h.status = CAM_REQ_CMP; 6947 xpt_print_path(ccb->ccb_h.path); 6948 printf("Lun now enabled for target mode\n"); 6949 } else { 6950 struct scb *scb; 6951 int i, empty; 6952 6953 if (lstate == NULL) { 6954 ccb->ccb_h.status = CAM_LUN_INVALID; 6955 return; 6956 } 6957 6958 s = splbio(); 6959 6960 ccb->ccb_h.status = CAM_REQ_CMP; 6961 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6962 struct ccb_hdr *ccbh; 6963 6964 ccbh = &scb->io_ctx->ccb_h; 6965 if (ccbh->func_code == XPT_CONT_TARGET_IO 6966 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 6967 printf("CTIO pending\n"); 6968 ccb->ccb_h.status = CAM_REQ_INVALID; 6969 splx(s); 6970 return; 6971 } 6972 } 6973 6974 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 6975 printf("ATIOs pending\n"); 6976 ccb->ccb_h.status = CAM_REQ_INVALID; 6977 } 6978 6979 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 6980 printf("INOTs pending\n"); 6981 ccb->ccb_h.status = CAM_REQ_INVALID; 6982 } 6983 6984 if (ccb->ccb_h.status != CAM_REQ_CMP) { 6985 splx(s); 6986 return; 6987 } 6988 6989 xpt_print_path(ccb->ccb_h.path); 6990 printf("Target mode disabled\n"); 6991 xpt_free_path(lstate->path); 6992 free(lstate, M_DEVBUF); 6993 6994 ahc_pause(ahc); 6995 /* Can we clean up the target too? */ 6996 if (target != CAM_TARGET_WILDCARD) { 6997 tstate->enabled_luns[lun] = NULL; 6998 ahc->enabled_luns--; 6999 for (empty = 1, i = 0; i < 8; i++) 7000 if (tstate->enabled_luns[i] != NULL) { 7001 empty = 0; 7002 break; 7003 } 7004 7005 if (empty) { 7006 ahc_free_tstate(ahc, target, channel, 7007 /*force*/FALSE); 7008 if (ahc->features & AHC_MULTI_TID) { 7009 u_int targid_mask; 7010 7011 targid_mask = ahc_inb(ahc, TARGID) 7012 | (ahc_inb(ahc, TARGID + 1) 7013 << 8); 7014 7015 targid_mask &= ~target_mask; 7016 ahc_outb(ahc, TARGID, targid_mask); 7017 ahc_outb(ahc, TARGID+1, 7018 (targid_mask >> 8)); 7019 ahc_update_scsiid(ahc, targid_mask); 7020 } 7021 } 7022 } else { 7023 7024 ahc->black_hole = NULL; 7025 7026 /* 7027 * We can't allow selections without 7028 * our black hole device. 7029 */ 7030 empty = TRUE; 7031 } 7032 if (ahc->enabled_luns == 0) { 7033 /* Disallow select-in */ 7034 u_int scsiseq; 7035 7036 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7037 scsiseq &= ~ENSELI; 7038 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7039 scsiseq = ahc_inb(ahc, SCSISEQ); 7040 scsiseq &= ~ENSELI; 7041 ahc_outb(ahc, SCSISEQ, scsiseq); 7042 7043 if ((ahc->features & AHC_MULTIROLE) == 0) { 7044 printf("Configuring Initiator Mode\n"); 7045 ahc->flags &= ~AHC_TARGETROLE; 7046 ahc->flags |= AHC_INITIATORROLE; 7047 /* 7048 * Returning to a configuration that 7049 * fit previously will always succeed. 7050 */ 7051 (void)ahc_loadseq(ahc); 7052 ahc_restart(ahc); 7053 /* 7054 * Unpaused. The extra unpause 7055 * that follows is harmless. 7056 */ 7057 } 7058 } 7059 ahc_unpause(ahc); 7060 splx(s); 7061 } 7062 } 7063 7064 static void 7065 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7066 { 7067 u_int scsiid_mask; 7068 u_int scsiid; 7069 7070 if ((ahc->features & AHC_MULTI_TID) == 0) 7071 panic("ahc_update_scsiid called on non-multitid unit"); 7072 7073 /* 7074 * Since we will rely on the TARGID mask 7075 * for selection enables, ensure that OID 7076 * in SCSIID is not set to some other ID 7077 * that we don't want to allow selections on. 7078 */ 7079 if ((ahc->features & AHC_ULTRA2) != 0) 7080 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7081 else 7082 scsiid = ahc_inb(ahc, SCSIID); 7083 scsiid_mask = 0x1 << (scsiid & OID); 7084 if ((targid_mask & scsiid_mask) == 0) { 7085 u_int our_id; 7086 7087 /* ffs counts from 1 */ 7088 our_id = ffs(targid_mask); 7089 if (our_id == 0) 7090 our_id = ahc->our_id; 7091 else 7092 our_id--; 7093 scsiid &= TID; 7094 scsiid |= our_id; 7095 } 7096 if ((ahc->features & AHC_ULTRA2) != 0) 7097 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7098 else 7099 ahc_outb(ahc, SCSIID, scsiid); 7100 } 7101 7102 #ifdef AHC_TARGET_MODE 7103 void 7104 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7105 { 7106 struct target_cmd *cmd; 7107 7108 /* 7109 * If the card supports auto-access pause, 7110 * we can access the card directly regardless 7111 * of whether it is paused or not. 7112 */ 7113 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7114 paused = TRUE; 7115 7116 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7117 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7118 7119 /* 7120 * Only advance through the queue if we 7121 * have the resources to process the command. 7122 */ 7123 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7124 break; 7125 7126 cmd->cmd_valid = 0; 7127 ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/, 7128 ahc->shared_data_dmamap, 7129 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7130 sizeof(struct target_cmd), 7131 #ifdef __sgi__ 7132 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 7133 #else 7134 BUS_DMASYNC_PREREAD); 7135 #endif 7136 ahc->tqinfifonext++; 7137 7138 /* 7139 * Lazily update our position in the target mode incoming 7140 * command queue as seen by the sequencer. 7141 */ 7142 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7143 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7144 u_int hs_mailbox; 7145 7146 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7147 hs_mailbox &= ~HOST_TQINPOS; 7148 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7149 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7150 } else { 7151 if (!paused) 7152 ahc_pause(ahc); 7153 ahc_outb(ahc, KERNEL_TQINPOS, 7154 ahc->tqinfifonext & HOST_TQINPOS); 7155 if (!paused) 7156 ahc_unpause(ahc); 7157 } 7158 } 7159 } 7160 } 7161 #endif 7162 7163 static int 7164 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7165 { 7166 struct ahc_tmode_tstate *tstate; 7167 struct ahc_tmode_lstate *lstate; 7168 struct ccb_accept_tio *atio; 7169 uint8_t *byte; 7170 int initiator; 7171 int target; 7172 int lun; 7173 7174 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7175 target = SCSIID_OUR_ID(cmd->scsiid); 7176 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7177 7178 byte = cmd->bytes; 7179 tstate = ahc->enabled_targets[target]; 7180 lstate = NULL; 7181 if (tstate != NULL) 7182 lstate = tstate->enabled_luns[lun]; 7183 7184 /* 7185 * Commands for disabled luns go to the black hole driver. 7186 */ 7187 if (lstate == NULL) 7188 lstate = ahc->black_hole; 7189 7190 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7191 if (atio == NULL) { 7192 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7193 /* 7194 * Wait for more ATIOs from the peripheral driver for this lun. 7195 */ 7196 if (bootverbose) 7197 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7198 return (1); 7199 } else 7200 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7201 #if 0 7202 printf("Incoming command from %d for %d:%d%s\n", 7203 initiator, target, lun, 7204 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7205 #endif 7206 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7207 7208 if (lstate == ahc->black_hole) { 7209 /* Fill in the wildcards */ 7210 atio->ccb_h.target_id = target; 7211 atio->ccb_h.target_lun = lun; 7212 } 7213 7214 /* 7215 * Package it up and send it off to 7216 * whomever has this lun enabled. 7217 */ 7218 atio->sense_len = 0; 7219 atio->init_id = initiator; 7220 if (byte[0] != 0xFF) { 7221 /* Tag was included */ 7222 atio->tag_action = *byte++; 7223 atio->tag_id = *byte++; 7224 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7225 } else { 7226 atio->ccb_h.flags = 0; 7227 } 7228 byte++; 7229 7230 /* Okay. Now determine the cdb size based on the command code */ 7231 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7232 case 0: 7233 atio->cdb_len = 6; 7234 break; 7235 case 1: 7236 case 2: 7237 atio->cdb_len = 10; 7238 break; 7239 case 4: 7240 atio->cdb_len = 16; 7241 break; 7242 case 5: 7243 atio->cdb_len = 12; 7244 break; 7245 case 3: 7246 default: 7247 /* Only copy the opcode. */ 7248 atio->cdb_len = 1; 7249 printf("Reserved or VU command code type encountered\n"); 7250 break; 7251 } 7252 7253 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7254 7255 atio->ccb_h.status |= CAM_CDB_RECVD; 7256 7257 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7258 /* 7259 * We weren't allowed to disconnect. 7260 * We're hanging on the bus until a 7261 * continue target I/O comes in response 7262 * to this accept tio. 7263 */ 7264 #if 0 7265 printf("Received Immediate Command %d:%d:%d - %p\n", 7266 initiator, target, lun, ahc->pending_device); 7267 #endif 7268 ahc->pending_device = lstate; 7269 ahc_freeze_ccb((union ccb *)atio); 7270 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7271 } 7272 xpt_done((union ccb*)atio); 7273 return (0); 7274 } 7275 #endif 7276 7277 static int 7278 ahc_createdmamem(bus_dma_tag_t tag, int size, int flags, bus_dmamap_t *mapp, 7279 caddr_t *vaddr, bus_addr_t *baddr, bus_dma_segment_t *seg, int *nseg, 7280 const char *myname, const char *what) 7281 { 7282 int error; 7283 7284 if ((error = bus_dmamap_create(tag, size, 1, size, 0, 7285 BUS_DMA_NOWAIT | flags, mapp)) != 0) { 7286 printf("%s: failed to create DMA map for %s, error = %d\n", 7287 myname, what, error); 7288 return (error); 7289 } 7290 7291 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, 7292 seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) { 7293 printf("%s: failed to allocate DMA mem for %s, error = %d\n", 7294 myname, what, error); 7295 goto destroy; 7296 } 7297 7298 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr, 7299 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 7300 printf("%s: failed to map DMA mem for %s, error = %d\n", 7301 myname, what, error); 7302 goto free; 7303 } 7304 7305 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL, 7306 BUS_DMA_NOWAIT)) != 0) { 7307 printf("%s: failed to load DMA map for %s, error = %d\n", 7308 myname, what, error); 7309 goto unmap; 7310 } 7311 7312 *baddr = (*mapp)->dm_segs[0].ds_addr; 7313 return (0); 7314 7315 unmap: 7316 bus_dmamem_unmap(tag, *vaddr, size); 7317 free: 7318 bus_dmamem_free(tag, seg, *nseg); 7319 destroy: 7320 bus_dmamap_destroy(tag, *mapp); 7321 7322 *vaddr = 0; 7323 bzero(seg, sizeof(*seg)); 7324 return (error); 7325 } 7326 7327 static void 7328 ahc_freedmamem(bus_dma_tag_t tag, int size, bus_dmamap_t map, caddr_t vaddr, 7329 bus_dma_segment_t *seg, int nseg) 7330 { 7331 7332 bus_dmamap_unload(tag, map); 7333 bus_dmamem_unmap(tag, vaddr, size); 7334 bus_dmamem_free(tag, seg, nseg); 7335 bus_dmamap_destroy(tag, map); 7336 } 7337