1 /* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * the GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.15 2000/01/07 23:08:18 gibbs Exp $ 34 * $OpenBSD: aic7xxxvar.h,v 1.13 2000/07/03 22:18:36 smurph Exp $ 35 */ 36 37 #ifndef _AIC7XXXVAR_H_ 38 #define _AIC7XXXVAR_H_ 39 40 #ifndef FALSE 41 #define FALSE 0 42 #endif 43 44 #ifndef TRUE 45 #define TRUE 1 46 #endif 47 48 /* 49 * convert FreeBSD's <sys/queue.h> symbols to NetBSD's 50 */ 51 #define STAILQ_ENTRY SIMPLEQ_ENTRY 52 #define STAILQ_HEAD SIMPLEQ_HEAD 53 #define STAILQ_INIT SIMPLEQ_INIT 54 #define STAILQ_INSERT_HEAD SIMPLEQ_INSERT_HEAD 55 #define STAILQ_INSERT_TAIL SIMPLEQ_INSERT_TAIL 56 #define STAILQ_REMOVE_HEAD(head, field) \ 57 SIMPLEQ_REMOVE_HEAD(head, (head)->sqh_first, field) 58 #define stqh_first sqh_first 59 #define stqe_next sqe_next 60 61 /* 62 * The maximum transfer per S/G segment. 63 */ 64 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 65 66 /* 67 * The number of dma segments supported. The current implementation limits 68 * us to 255 S/G entries (this may change to be unlimited at some point). 69 * To reduce the driver's memory consumption, we further limit the number 70 * supported to be sufficient to handle the largest mapping supported by 71 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 72 * and unaligned, this turns out to be the number of paged sized transfers 73 * in MAXPHYS plus an extra element to handle any unaligned residual. 74 */ 75 #define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 76 77 #define AHC_SCB_MAX 255 /* 78 * Up to 255 SCBs on some types of aic7xxx 79 * based boards. The aic7870 have 16 internal 80 * SCBs, but external SRAM bumps this to 255. 81 * The aic7770 family have only 4, and the 82 * aic7850 has only 3. 83 */ 84 85 #define AHC_TMODE_CMDS 256 /* 86 * Ring Buffer of incoming target commands. 87 * We allocate 256 to simplify the logic 88 * in the sequencer by using the natural 89 * wrap point of an 8bit counter. 90 */ 91 92 struct ahc_dma_seg { 93 u_int32_t addr; 94 u_int32_t len; 95 }; 96 97 typedef enum { 98 AHC_NONE = 0x0000, 99 AHC_CHIPID_MASK = 0x00FF, 100 AHC_AIC7770 = 0x0001, 101 AHC_AIC7850 = 0x0002, 102 AHC_AIC7855 = 0x0003, 103 AHC_AIC7859 = 0x0004, 104 AHC_AIC7860 = 0x0005, 105 AHC_AIC7870 = 0x0006, 106 AHC_AIC7880 = 0x0007, 107 AHC_AIC7890 = 0x0008, 108 AHC_AIC7892 = 0x0009, 109 AHC_AIC7895 = 0x000a, 110 AHC_AIC7896 = 0x000b, 111 AHC_AIC7899 = 0x000c, 112 AHC_VL = 0x0100, /* Bus type VL */ 113 AHC_EISA = 0x0200, /* Bus type EISA */ 114 AHC_PCI = 0x0400, /* Bus type PCI */ 115 AHC_BUS_MASK = 0x0F00 116 } ahc_chip; 117 118 extern char *ahc_chip_names[]; 119 120 typedef enum { 121 AHC_FENONE = 0x0000, 122 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 123 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 124 AHC_WIDE = 0x0004, /* Wide Channel */ 125 AHC_TWIN = 0x0008, /* Twin Channel */ 126 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 127 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 128 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 129 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 130 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 131 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 132 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 133 AHC_DT = 0x0800, /* Double Transition transfers */ 134 AHC_NEW_TERMCTL = 0x1000, 135 AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ 136 AHC_TARG_DMABUG = 0x4000, /* WideOdd Data-In bug in TMODE */ 137 AHC_AIC7770_FE = AHC_TARG_DMABUG, 138 AHC_AIC7850_FE = AHC_TARG_DMABUG|AHC_SPIOCAP, 139 AHC_AIC7855_FE = AHC_AIC7850_FE, 140 AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, 141 AHC_AIC7860_FE = AHC_AIC7859_FE, 142 AHC_AIC7870_FE = AHC_TARG_DMABUG, 143 AHC_AIC7880_FE = AHC_TARG_DMABUG|AHC_ULTRA, 144 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 145 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 146 |AHC_NEW_TERMCTL, 147 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, 148 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM 149 |AHC_CMD_CHAN|AHC_MULTI_FUNC, 150 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 151 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 152 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 153 } ahc_feature; 154 155 typedef enum { 156 AHC_FNONE = 0x000, 157 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 158 AHC_CHANNEL_B_PRIMARY = 0x002,/* 159 * On twin channel adapters, probe 160 * channel B first since it is the 161 * primary bus. 162 */ 163 AHC_USEDEFAULTS = 0x004,/* 164 * For cards without an seeprom 165 * or a BIOS to initialize the chip's 166 * SRAM, we use the default target 167 * settings. 168 */ 169 AHC_SHARED_SRAM = 0x010, 170 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 171 AHC_RESET_BUS_A = 0x040, 172 AHC_RESET_BUS_B = 0x080, 173 AHC_EXTENDED_TRANS_A = 0x100, 174 AHC_EXTENDED_TRANS_B = 0x200, 175 AHC_TERM_ENB_A = 0x400, 176 AHC_TERM_ENB_B = 0x800, 177 AHC_INITIATORMODE = 0x1000,/* 178 * Allow initiator operations on 179 * this controller. 180 */ 181 AHC_TARGETMODE = 0x2000,/* 182 * Allow target operations on this 183 * controller. 184 */ 185 AHC_NEWEEPROM_FMT = 0x4000, 186 AHC_RESOURCE_SHORTAGE = 0x8000, 187 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 188 AHC_INT50_SPEEDFLEX = 0x20000,/* 189 * Internal 50pin connector 190 * sits behind an aic3860 191 */ 192 } ahc_flag; 193 194 typedef enum { 195 SCB_FREE = 0x0000, 196 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 197 * Another device was active 198 * during the first timeout for 199 * this SCB so we gave ourselves 200 * an additional timeout period 201 * in case it was hogging the 202 * bus. 203 */ 204 SCB_DEVICE_RESET = 0x0004, 205 SCB_SENSE = 0x0008, 206 SCB_FREEZE_QUEUE = 0x0010, 207 SCB_REQUEUE = 0x0020, 208 SCB_RECOVERY_SCB = 0x0040, 209 SCB_ABORT = 0x1000, 210 SCB_QUEUED_MSG = 0x2000, 211 SCB_ACTIVE = 0x4000, 212 SCB_TARGET_IMMEDIATE = 0x8000 213 } scb_flag; 214 215 /* 216 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 217 * consists of a "hardware SCB" mirroring the fields availible on the card 218 * and additional information the kernel stores for each transaction. 219 */ 220 struct hardware_scb { 221 /*0*/ u_int8_t control; 222 /*1*/ u_int8_t tcl; /* 4/1/3 bits */ 223 /*2*/ u_int8_t status; 224 /*3*/ u_int8_t SG_count; 225 /*4*/ u_int32_t SG_pointer; 226 /*8*/ u_int8_t residual_SG_count; 227 /*9*/ u_int8_t residual_data_count[3]; 228 /*12*/ u_int32_t data; 229 /*16*/ u_int32_t datalen; /* Really only three bytes, but its 230 * faster to treat it as a long on 231 * a quad boundary. 232 */ 233 /*20*/ u_int32_t cmdpointer; 234 /*24*/ u_int8_t cmdlen; 235 /*25*/ u_int8_t tag; /* Index into our kernel SCB array. 236 * Also used as the tag for tagged I/O 237 */ 238 /*26*/ u_int8_t next; /* Used for threading SCBs in the 239 * "Waiting for Selection" and 240 * "Disconnected SCB" lists down 241 * in the sequencer. 242 */ 243 /*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 244 /*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 245 /*29*/ u_int8_t spare[3]; /* 246 * Spare space available on 247 * all controller types. 248 */ 249 /*32*/ u_int8_t cmdstore[16]; /* 250 * CDB storage for controllers 251 * supporting 64 byte SCBs. 252 */ 253 /*48*/ u_int32_t cmdstore_busaddr; /* 254 * Address of command store for 255 * 32byte SCB adapters 256 */ 257 /*48*/ u_int8_t spare_64[12]; /* 258 * Pad to 64 bytes. 259 */ 260 }; 261 262 struct scb { 263 struct hardware_scb *hscb; 264 SLIST_ENTRY(scb) links; /* for chaining */ 265 LIST_ENTRY(scb) pend_links; /* for pending scbs*/ 266 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 267 scb_flag flags; 268 bus_dmamap_t dmamap; 269 struct ahc_dma_seg *sg_list; 270 bus_addr_t sg_list_phys; 271 u_int sg_count;/* How full ahc_dma_seg is */ 272 }; 273 274 /* 275 * Connection desciptor for select-in requests in target mode. 276 * The first byte is the connecting target, followed by identify 277 * message and optional tag information, terminated by 0xFF. The 278 * remainder is the command to execute. The cmd_valid byte is on 279 * an 8 byte boundary to simplify setting it on aic7880 hardware 280 * which only has limited direct access to the DMA FIFO. 281 */ 282 struct target_cmd { 283 u_int8_t initiator_channel; 284 u_int8_t targ_id; /* Target ID we were selected at */ 285 u_int8_t identify; /* Identify message */ 286 u_int8_t bytes[21]; 287 u_int8_t cmd_valid; 288 u_int8_t pad[7]; 289 }; 290 291 /* 292 * Number of events we can buffer up if we run out 293 * of immediate notify ccbs. 294 */ 295 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 296 struct ahc_tmode_event { 297 u_int8_t initiator_id; 298 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 299 #define EVENT_TYPE_BUS_RESET 0xFF 300 u_int8_t event_arg; 301 }; 302 303 /* 304 * Per lun target mode state including accept TIO CCB 305 * and immediate notify CCB pools. 306 */ 307 struct tmode_lstate { 308 u_int8_t not_yet; 309 }; 310 311 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 312 #define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 313 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 314 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 315 316 struct ahc_transinfo { 317 u_int8_t width; 318 u_int8_t period; 319 u_int8_t offset; 320 u_int8_t ppr_flags; 321 }; 322 323 struct ahc_initiator_tinfo { 324 u_int8_t scsirate; 325 struct ahc_transinfo current; 326 struct ahc_transinfo goal; 327 struct ahc_transinfo user; 328 }; 329 330 /* 331 * Per target mode enabled target state. Esentially just an array of 332 * pointers to lun target state as well as sync/wide negotiation information 333 * for each initiator<->target mapping (including the mapping for when we 334 * are the initiator). 335 */ 336 struct tmode_tstate { 337 struct ahc_initiator_tinfo transinfo[16]; 338 339 /* 340 * Per initiator state bitmasks. 341 */ 342 u_int16_t ultraenb; /* Using ultra sync rate */ 343 u_int16_t discenable; /* Disconnection allowed */ 344 u_int16_t tagenable; /* Tagged Queuing allowed */ 345 u_int16_t tagdisable; /* Tagged Queuing NOT allowed */ 346 }; 347 348 #define ALL_TARGETS -1 349 #define ALL_LUNS -1 350 351 /* 352 * Define the format of the aic7XXX SEEPROM registers (16 bits). 353 */ 354 355 struct seeprom_config { 356 /* 357 * SCSI ID Configuration Flags 358 */ 359 u_int16_t device_flags[16]; /* words 0-15 */ 360 #define CFXFER 0x0007 /* synchronous transfer rate */ 361 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 362 #define CFDISC 0x0010 /* enable disconnection */ 363 #define CFWIDEB 0x0020 /* wide bus device */ 364 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 365 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 366 #define CFSTART 0x0100 /* send start unit SCSI command */ 367 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 368 #define CFRNFOUND 0x0400 /* report even if not found */ 369 #define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 370 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 371 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 372 373 /* 374 * BIOS Control Bits 375 */ 376 u_int16_t bios_control; /* word 16 */ 377 #define CFSUPREM 0x0001 /* support all removeable drives */ 378 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 379 #define CFBIOSEN 0x0004 /* BIOS enabled */ 380 /* UNUSED 0x0008 */ 381 #define CFSM2DRV 0x0010 /* support more than two drives */ 382 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 383 /* UNUSED 0x0040 */ 384 #define CFEXTEND 0x0080 /* extended translation enabled */ 385 /* UNUSED 0xff00 */ 386 387 /* 388 * Host Adapter Control Bits 389 */ 390 u_int16_t adapter_control; /* word 17 */ 391 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 392 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 393 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 394 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 395 #define CFSTERM 0x0004 /* SCSI low byte termination */ 396 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 397 #define CFSPARITY 0x0010 /* SCSI parity */ 398 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 399 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 400 #define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 401 #define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 402 #define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 403 /* UNUSED 0xf280 */ 404 405 /* 406 * Bus Release, Host Adapter ID 407 */ 408 u_int16_t brtime_id; /* word 18 */ 409 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 410 /* UNUSED 0x00f0 */ 411 #define CFBRTIME 0xff00 /* bus release time */ 412 413 /* 414 * Maximum targets 415 */ 416 u_int16_t max_targets; /* word 19 */ 417 #define CFMAXTARG 0x00ff /* maximum targets */ 418 /* UNUSED 0xff00 */ 419 u_int16_t res_1[11]; /* words 20-30 */ 420 u_int16_t checksum; /* word 31 */ 421 }; 422 423 struct ahc_syncrate { 424 int sxfr_u2; 425 int sxfr; 426 /* Rates in Ultra mode have bit 8 of sxfr set */ 427 #define ULTRA_SXFR 0x100 428 #define ST_SXFR 0x010 429 u_int8_t period; /* Period to send to SCSI target */ 430 char *rate; 431 }; 432 433 typedef enum { 434 MSG_TYPE_NONE = 0x00, 435 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 436 MSG_TYPE_INITIATOR_MSGIN = 0x02, 437 MSG_TYPE_TARGET_MSGOUT = 0x03, 438 MSG_TYPE_TARGET_MSGIN = 0x04 439 } ahc_msg_type; 440 441 struct sg_map_node { 442 bus_dmamap_t sg_dmamap; 443 bus_addr_t sg_physaddr; 444 bus_dma_segment_t sg_dmasegs; 445 int sg_nseg; 446 struct ahc_dma_seg* sg_vaddr; 447 SLIST_ENTRY(sg_map_node) links; 448 }; 449 450 struct scb_data { 451 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 452 struct scb *scbarray; /* Array of kernel SCBs */ 453 SLIST_HEAD(, scb) free_scbs; /* 454 * Pool of SCBs ready to be assigned 455 * commands to execute. 456 */ 457 struct scsi_sense_data *sense; /* Per SCB sense data */ 458 459 /* 460 * "Bus" addresses of our data structures. 461 */ 462 bus_dmamap_t hscb_dmamap; 463 bus_addr_t hscb_busaddr; 464 bus_dma_segment_t hscb_seg; 465 int hscb_nseg; 466 int hscb_size; 467 468 bus_dmamap_t sense_dmamap; 469 bus_addr_t sense_busaddr; 470 bus_dma_segment_t sense_seg; 471 int sense_nseg; 472 int sense_size; 473 474 SLIST_HEAD(, sg_map_node) sg_maps; 475 u_int8_t numscbs; 476 u_int8_t maxhscbs; /* Number of SCBs on the card */ 477 u_int8_t init_level; /* 478 * How far we've initialized 479 * this structure. 480 */ 481 }; 482 483 struct ahc_softc { 484 struct device sc_dev; 485 void *sc_ih; 486 bus_space_tag_t sc_iot; 487 bus_space_handle_t sc_ioh; 488 bus_dma_tag_t sc_dmat; 489 bus_dmamap_t sc_dmamap_fifo; /* maps the FIFOs */ 490 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 491 struct scb_data *scb_data; 492 void *pci_data; /* for pci config read/write */ 493 int (*pci_intr_func) __P((struct ahc_softc *)); /* for pci error interrupts */ 494 LIST_HEAD(, scsi_xfer) sc_xxxq; /* XXX software request queue */ 495 struct scsi_xfer *sc_xxxqlast; /* last entry in queue */ 496 497 int queue_blocked; 498 u_int16_t devqueue_blocked[16]; 499 #define AHC_NEG_PENDING 0x01 500 #define AHC_NEG_SDTRDONE 0x02 501 #define AHC_NEG_WDTRDONE 0x04 502 u_int8_t inited_targets[16]; 503 u_int8_t inited_channels[2]; 504 505 /* 506 * SCBs that have been send to the controller 507 */ 508 LIST_HEAD(, scb) pending_scbs; 509 510 /* 511 * Target mode related state kept on a per enabled lun basis. 512 * Targets that are not enabled will have null entries. 513 * As an initiator, we keep one target entry for our initiator 514 * ID to store our sync/wide transfer settings. 515 */ 516 struct tmode_tstate* enabled_targets[16]; 517 518 /* 519 * The black hole device responsible for handling requests for 520 * disabled luns on enabled targets. 521 */ 522 struct tmode_lstate* black_hole; 523 524 /* 525 * Device instance currently on the bus awaiting a continue TIO 526 * for a command that was not given the disconnect priveledge. 527 */ 528 struct tmode_lstate* pending_device; 529 530 /* 531 * Card characteristics 532 */ 533 ahc_chip chip; 534 ahc_feature features; 535 ahc_flag flags; 536 537 /* Values to store in the SEQCTL register for pause and unpause */ 538 u_int8_t unpause; 539 u_int8_t pause; 540 541 /* Command Queues */ 542 u_int8_t qoutfifonext; 543 u_int8_t qinfifonext; 544 u_int8_t *qoutfifo; 545 u_int8_t *qinfifo; 546 547 /* 548 * 256 byte array storing the SCBID of outstanding 549 * untagged SCBs indexed by TCL. 550 */ 551 u_int8_t *untagged_scbs; 552 553 /* 554 * Hooks into the XPT. 555 */ 556 struct scsi_link sc_link; 557 struct scsi_link sc_link_b; /* Second bus for Twin channel cards */ 558 559 int unit; 560 561 /* Channel Names ('A', 'B', etc.) */ 562 char channel; 563 char channel_b; 564 565 /* Initiator Bus ID */ 566 u_int8_t our_id; 567 u_int8_t our_id_b; 568 569 /* Targets that need negotiation messages */ 570 u_int16_t targ_msg_req; 571 572 /* 573 * Target incoming command FIFO. 574 */ 575 struct target_cmd *targetcmds; 576 u_int8_t tqinfifonext; 577 578 /* 579 * Incoming and outgoing message handling. 580 */ 581 u_int8_t send_msg_perror; 582 ahc_msg_type msg_type; 583 u_int8_t msgout_buf[8]; /* Message we are sending */ 584 u_int8_t msgin_buf[8]; /* Message we are receiving */ 585 u_int msgout_len; /* Length of message to send */ 586 u_int msgout_index; /* Current index in msgout */ 587 u_int msgin_index; /* Current index in msgin */ 588 589 void *ih; 590 bus_dmamap_t shared_data_dmamap; 591 bus_addr_t shared_data_busaddr; 592 bus_dma_segment_t shared_data_seg; 593 int shared_data_nseg; 594 int shared_data_size; 595 596 /* Number of enabled target mode device on this card */ 597 u_int enabled_luns; 598 599 /* Initialization level of this data structure */ 600 u_int init_level; 601 602 u_int16_t user_discenable;/* Disconnection allowed */ 603 u_int16_t user_tagenable; /* Tagged Queuing allowed */ 604 605 }; 606 607 /* #define AHC_DEBUG */ 608 #ifdef AHC_DEBUG 609 /* Different debugging levels used when AHC_DEBUG is defined */ 610 #define AHC_SHOWMISC 0x0001 611 #define AHC_SHOWCMDS 0x0002 612 #define AHC_SHOWSCBS 0x0004 613 #define AHC_SHOWABORTS 0x0008 614 #define AHC_SHOWSENSE 0x0010 615 #define AHC_SHOWSCBCNT 0x0020 616 617 extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 618 #endif 619 620 #define ahc_name(ahc) (ahc)->sc_dev.dv_xname 621 622 void ahc_construct __P((struct ahc_softc *ahc, bus_space_tag_t iot, 623 bus_space_handle_t ioh, ahc_chip chip, ahc_flag flags, 624 ahc_feature features, u_char channel)); 625 int ahc_probe_scbs __P((struct ahc_softc *ahc)); 626 void ahc_free __P((struct ahc_softc *)); 627 int ahc_init __P((struct ahc_softc *)); 628 int ahc_attach __P((struct ahc_softc *)); 629 int ahc_intr __P((void *arg)); 630 int ahc_reset __P((struct ahc_softc *ahc)); 631 void ahc_xxx_reset __P((char *devname, bus_space_tag_t iot, bus_space_handle_t ioh)); 632 #define ahc_isa_reset ahc_xxx_reset 633 #define ahc_eisa_reset ahc_xxx_reset 634 635 #define AHC_INB(ahc, port) \ 636 bus_space_read_1((ahc)->sc_iot, (ahc)->sc_ioh, port) 637 #define AHC_INSB(ahc, port, valp, size) \ 638 bus_space_read_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, (u_int8_t *) valp, size) 639 #define AHC_OUTB(ahc, port, val) \ 640 bus_space_write_1((ahc)->sc_iot, (ahc)->sc_ioh, port, val) 641 #define AHC_OUTSB(ahc, port, valp, size) \ 642 bus_space_write_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, (u_int8_t *) valp, size) 643 #define AHC_OUTSL(ahc, port, valp, size) \ 644 bus_space_write_multi_4((ahc)->sc_iot, (ahc)->sc_ioh, port, (u_int32_t *) valp, size) 645 646 #define ahc_inb AHC_INB 647 #define ahc_insb AHC_INSB 648 #define ahc_outb AHC_OUTB 649 #define ahc_outsb AHC_OUTSB 650 #define ahc_outsl AHC_OUTSL 651 652 #endif /* _AIC7XXXVAR_H_ */ 653