1 /* $OpenBSD: ar5210.c,v 1.45 2009/06/02 12:39:02 reyk Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for the Atheros AR5000 Wireless LAN chipset 21 * (AR5210 + AR5110). 22 */ 23 24 #include <dev/ic/ar5xxx.h> 25 #include <dev/ic/ar5210reg.h> 26 #include <dev/ic/ar5210var.h> 27 28 HAL_BOOL ar5k_ar5210_nic_reset(struct ath_hal *, u_int32_t); 29 HAL_BOOL ar5k_ar5210_nic_wakeup(struct ath_hal *, HAL_BOOL, HAL_BOOL); 30 void ar5k_ar5210_init_tx_queue(struct ath_hal *, u_int, HAL_BOOL); 31 void ar5k_ar5210_fill(struct ath_hal *); 32 HAL_BOOL ar5k_ar5210_do_calibrate(struct ath_hal *, HAL_CHANNEL *); 33 HAL_BOOL ar5k_ar5210_noise_floor(struct ath_hal *, HAL_CHANNEL *); 34 35 /* 36 * Initial register setting for the AR5210 37 */ 38 static const struct ar5k_ini ar5210_ini[] = 39 AR5K_AR5210_INI; 40 41 AR5K_HAL_FUNCTIONS(extern, ar5k_ar5210,); 42 43 void 44 ar5k_ar5210_fill(struct ath_hal *hal) 45 { 46 hal->ah_magic = AR5K_AR5210_MAGIC; 47 48 /* 49 * Init/Exit functions 50 */ 51 AR5K_HAL_FUNCTION(hal, ar5210, get_rate_table); 52 AR5K_HAL_FUNCTION(hal, ar5210, detach); 53 54 /* 55 * Reset functions 56 */ 57 AR5K_HAL_FUNCTION(hal, ar5210, reset); 58 AR5K_HAL_FUNCTION(hal, ar5210, set_opmode); 59 AR5K_HAL_FUNCTION(hal, ar5210, calibrate); 60 61 /* 62 * TX functions 63 */ 64 AR5K_HAL_FUNCTION(hal, ar5210, update_tx_triglevel); 65 AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queue); 66 AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_queueprops); 67 AR5K_HAL_FUNCTION(hal, ar5210, release_tx_queue); 68 AR5K_HAL_FUNCTION(hal, ar5210, reset_tx_queue); 69 AR5K_HAL_FUNCTION(hal, ar5210, get_tx_buf); 70 AR5K_HAL_FUNCTION(hal, ar5210, put_tx_buf); 71 AR5K_HAL_FUNCTION(hal, ar5210, tx_start); 72 AR5K_HAL_FUNCTION(hal, ar5210, stop_tx_dma); 73 AR5K_HAL_FUNCTION(hal, ar5210, setup_tx_desc); 74 AR5K_HAL_FUNCTION(hal, ar5210, setup_xtx_desc); 75 AR5K_HAL_FUNCTION(hal, ar5210, fill_tx_desc); 76 AR5K_HAL_FUNCTION(hal, ar5210, proc_tx_desc); 77 AR5K_HAL_FUNCTION(hal, ar5210, has_veol); 78 79 /* 80 * RX functions 81 */ 82 AR5K_HAL_FUNCTION(hal, ar5210, get_rx_buf); 83 AR5K_HAL_FUNCTION(hal, ar5210, put_rx_buf); 84 AR5K_HAL_FUNCTION(hal, ar5210, start_rx); 85 AR5K_HAL_FUNCTION(hal, ar5210, stop_rx_dma); 86 AR5K_HAL_FUNCTION(hal, ar5210, start_rx_pcu); 87 AR5K_HAL_FUNCTION(hal, ar5210, stop_pcu_recv); 88 AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filter); 89 AR5K_HAL_FUNCTION(hal, ar5210, set_mcast_filterindex); 90 AR5K_HAL_FUNCTION(hal, ar5210, clear_mcast_filter_idx); 91 AR5K_HAL_FUNCTION(hal, ar5210, get_rx_filter); 92 AR5K_HAL_FUNCTION(hal, ar5210, set_rx_filter); 93 AR5K_HAL_FUNCTION(hal, ar5210, setup_rx_desc); 94 AR5K_HAL_FUNCTION(hal, ar5210, proc_rx_desc); 95 AR5K_HAL_FUNCTION(hal, ar5210, set_rx_signal); 96 97 /* 98 * Misc functions 99 */ 100 AR5K_HAL_FUNCTION(hal, ar5210, dump_state); 101 AR5K_HAL_FUNCTION(hal, ar5210, get_diag_state); 102 AR5K_HAL_FUNCTION(hal, ar5210, get_lladdr); 103 AR5K_HAL_FUNCTION(hal, ar5210, set_lladdr); 104 AR5K_HAL_FUNCTION(hal, ar5210, set_regdomain); 105 AR5K_HAL_FUNCTION(hal, ar5210, set_ledstate); 106 AR5K_HAL_FUNCTION(hal, ar5210, set_associd); 107 AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_input); 108 AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_output); 109 AR5K_HAL_FUNCTION(hal, ar5210, get_gpio); 110 AR5K_HAL_FUNCTION(hal, ar5210, set_gpio); 111 AR5K_HAL_FUNCTION(hal, ar5210, set_gpio_intr); 112 AR5K_HAL_FUNCTION(hal, ar5210, get_tsf32); 113 AR5K_HAL_FUNCTION(hal, ar5210, get_tsf64); 114 AR5K_HAL_FUNCTION(hal, ar5210, reset_tsf); 115 AR5K_HAL_FUNCTION(hal, ar5210, get_regdomain); 116 AR5K_HAL_FUNCTION(hal, ar5210, detect_card_present); 117 AR5K_HAL_FUNCTION(hal, ar5210, update_mib_counters); 118 AR5K_HAL_FUNCTION(hal, ar5210, get_rf_gain); 119 AR5K_HAL_FUNCTION(hal, ar5210, set_slot_time); 120 AR5K_HAL_FUNCTION(hal, ar5210, get_slot_time); 121 AR5K_HAL_FUNCTION(hal, ar5210, set_ack_timeout); 122 AR5K_HAL_FUNCTION(hal, ar5210, get_ack_timeout); 123 AR5K_HAL_FUNCTION(hal, ar5210, set_cts_timeout); 124 AR5K_HAL_FUNCTION(hal, ar5210, get_cts_timeout); 125 126 /* 127 * Key table (WEP) functions 128 */ 129 AR5K_HAL_FUNCTION(hal, ar5210, is_cipher_supported); 130 AR5K_HAL_FUNCTION(hal, ar5210, get_keycache_size); 131 AR5K_HAL_FUNCTION(hal, ar5210, reset_key); 132 AR5K_HAL_FUNCTION(hal, ar5210, is_key_valid); 133 AR5K_HAL_FUNCTION(hal, ar5210, set_key); 134 AR5K_HAL_FUNCTION(hal, ar5210, set_key_lladdr); 135 AR5K_HAL_FUNCTION(hal, ar5210, softcrypto); 136 137 /* 138 * Power management functions 139 */ 140 AR5K_HAL_FUNCTION(hal, ar5210, set_power); 141 AR5K_HAL_FUNCTION(hal, ar5210, get_power_mode); 142 AR5K_HAL_FUNCTION(hal, ar5210, query_pspoll_support); 143 AR5K_HAL_FUNCTION(hal, ar5210, init_pspoll); 144 AR5K_HAL_FUNCTION(hal, ar5210, enable_pspoll); 145 AR5K_HAL_FUNCTION(hal, ar5210, disable_pspoll); 146 147 /* 148 * Beacon functions 149 */ 150 AR5K_HAL_FUNCTION(hal, ar5210, init_beacon); 151 AR5K_HAL_FUNCTION(hal, ar5210, set_beacon_timers); 152 AR5K_HAL_FUNCTION(hal, ar5210, reset_beacon); 153 AR5K_HAL_FUNCTION(hal, ar5210, wait_for_beacon); 154 155 /* 156 * Interrupt functions 157 */ 158 AR5K_HAL_FUNCTION(hal, ar5210, is_intr_pending); 159 AR5K_HAL_FUNCTION(hal, ar5210, get_isr); 160 AR5K_HAL_FUNCTION(hal, ar5210, get_intr); 161 AR5K_HAL_FUNCTION(hal, ar5210, set_intr); 162 163 /* 164 * Chipset functions (ar5k-specific, non-HAL) 165 */ 166 AR5K_HAL_FUNCTION(hal, ar5210, get_capabilities); 167 AR5K_HAL_FUNCTION(hal, ar5210, radar_alert); 168 169 /* 170 * EEPROM access 171 */ 172 AR5K_HAL_FUNCTION(hal, ar5210, eeprom_is_busy); 173 AR5K_HAL_FUNCTION(hal, ar5210, eeprom_read); 174 AR5K_HAL_FUNCTION(hal, ar5210, eeprom_write); 175 176 /* 177 * Unused functions or functions not implemented 178 */ 179 AR5K_HAL_FUNCTION(hal, ar5210, set_bssid_mask); 180 AR5K_HAL_FUNCTION(hal, ar5210, get_tx_queueprops); 181 AR5K_HAL_FUNCTION(hal, ar5210, num_tx_pending); 182 AR5K_HAL_FUNCTION(hal, ar5210, phy_disable); 183 AR5K_HAL_FUNCTION(hal, ar5210, set_txpower_limit); 184 AR5K_HAL_FUNCTION(hal, ar5210, set_def_antenna); 185 AR5K_HAL_FUNCTION(hal, ar5210, get_def_antenna); 186 #ifdef notyet 187 AR5K_HAL_FUNCTION(hal, ar5210, set_capability); 188 AR5K_HAL_FUNCTION(hal, ar5210, proc_mib_event); 189 AR5K_HAL_FUNCTION(hal, ar5210, get_tx_inter_queue); 190 #endif 191 } 192 193 struct ath_hal * 194 ar5k_ar5210_attach(u_int16_t device, void *sc, bus_space_tag_t st, 195 bus_space_handle_t sh, int *status) 196 { 197 int i; 198 struct ath_hal *hal = (struct ath_hal*) sc; 199 u_int8_t mac[IEEE80211_ADDR_LEN]; 200 u_int32_t srev; 201 202 ar5k_ar5210_fill(hal); 203 204 /* Bring device out of sleep and reset its units */ 205 if (ar5k_ar5210_nic_wakeup(hal, AH_FALSE, AH_TRUE) != AH_TRUE) 206 return (NULL); 207 208 /* Get MAC, PHY and RADIO revisions */ 209 srev = AR5K_REG_READ(AR5K_AR5210_SREV); 210 hal->ah_mac_srev = srev; 211 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5210_SREV_VER); 212 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5210_SREV_REV); 213 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5210_PHY_CHIP_ID) & 214 0x00ffffffff; 215 216 /* ...wait until PHY is ready and read RADIO revision */ 217 AR5K_REG_WRITE(AR5K_AR5210_PHY(0x34), 0x00001c16); 218 for (i = 0; i < 4; i++) 219 AR5K_REG_WRITE(AR5K_AR5210_PHY(0x20), 0x00010000); 220 hal->ah_radio_5ghz_revision = (u_int16_t) 221 (ar5k_bitswap((AR5K_REG_READ(AR5K_AR5210_PHY(256) >> 28) & 0xf), 4) 222 + 1); 223 hal->ah_radio_2ghz_revision = 0; 224 225 /* Identify the chipset */ 226 hal->ah_version = AR5K_AR5210; 227 hal->ah_radio = AR5K_AR5110; 228 hal->ah_phy = AR5K_AR5210_PHY(0); 229 230 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 231 ar5k_ar5210_set_associd(hal, mac, 0, 0); 232 ar5k_ar5210_get_lladdr(hal, mac); 233 ar5k_ar5210_set_opmode(hal); 234 235 return (hal); 236 } 237 238 HAL_BOOL 239 ar5k_ar5210_nic_reset(struct ath_hal *hal, u_int32_t val) 240 { 241 HAL_BOOL ret = AH_FALSE; 242 u_int32_t mask = val ? val : ~0; 243 244 /* 245 * Reset the device and wait until success 246 */ 247 AR5K_REG_WRITE(AR5K_AR5210_RC, val); 248 249 /* Wait at least 128 PCI clocks */ 250 AR5K_DELAY(15); 251 252 val &= 253 AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC | 254 AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA; 255 256 mask &= 257 AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_MAC | 258 AR5K_AR5210_RC_PHY | AR5K_AR5210_RC_DMA; 259 260 ret = ar5k_register_timeout(hal, AR5K_AR5210_RC, mask, val, AH_FALSE); 261 262 /* 263 * Reset configuration register 264 */ 265 if ((val & AR5K_AR5210_RC_MAC) == 0) { 266 AR5K_REG_WRITE(AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG); 267 } 268 269 return (ret); 270 } 271 272 HAL_BOOL 273 ar5k_ar5210_nic_wakeup(struct ath_hal *hal, HAL_BOOL turbo, HAL_BOOL initial) 274 { 275 /* 276 * Reset and wakeup the device 277 */ 278 279 if (initial == AH_TRUE) { 280 /* ...reset hardware */ 281 if (ar5k_ar5210_nic_reset(hal, 282 AR5K_AR5210_RC_PCI) == AH_FALSE) { 283 AR5K_PRINT("failed to reset the PCI chipset\n"); 284 return (AH_FALSE); 285 } 286 287 AR5K_DELAY(1000); 288 } 289 290 /* ...wakeup the device */ 291 if (ar5k_ar5210_set_power(hal, 292 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 293 AR5K_PRINT("failed to resume the AR5210 chipset\n"); 294 return (AH_FALSE); 295 } 296 297 /* ...enable Atheros turbo mode if requested */ 298 AR5K_REG_WRITE(AR5K_AR5210_PHY_FC, 299 turbo == AH_TRUE ? AR5K_AR5210_PHY_FC_TURBO_MODE : 0); 300 301 /* ...reset chipset */ 302 if (ar5k_ar5210_nic_reset(hal, AR5K_AR5210_RC_CHIP) == AH_FALSE) { 303 AR5K_PRINT("failed to reset the AR5210 chipset\n"); 304 return (AH_FALSE); 305 } 306 307 AR5K_DELAY(1000); 308 309 /* ...reset chipset and PCI device */ 310 if (ar5k_ar5210_nic_reset(hal, 311 AR5K_AR5210_RC_CHIP | AR5K_AR5210_RC_PCI) == AH_FALSE) { 312 AR5K_PRINT("failed to reset the AR5210 + PCI chipset\n"); 313 return (AH_FALSE); 314 } 315 316 AR5K_DELAY(2300); 317 318 /* ...wakeup (again) */ 319 if (ar5k_ar5210_set_power(hal, 320 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 321 AR5K_PRINT("failed to resume the AR5210 (again)\n"); 322 return (AH_FALSE); 323 } 324 325 /* ...final warm reset */ 326 if (ar5k_ar5210_nic_reset(hal, 0) == AH_FALSE) { 327 AR5K_PRINT("failed to warm reset the AR5210\n"); 328 return (AH_FALSE); 329 } 330 331 return (AH_TRUE); 332 } 333 334 const HAL_RATE_TABLE * 335 ar5k_ar5210_get_rate_table(struct ath_hal *hal, u_int mode) 336 { 337 switch (mode) { 338 case HAL_MODE_11A: 339 return (&hal->ah_rt_11a); 340 case HAL_MODE_TURBO: 341 return (&hal->ah_rt_turbo); 342 case HAL_MODE_11B: 343 case HAL_MODE_11G: 344 default: 345 return (NULL); 346 } 347 348 return (NULL); 349 } 350 351 void 352 ar5k_ar5210_detach(struct ath_hal *hal) 353 { 354 /* 355 * Free HAL structure, assume interrupts are down 356 */ 357 free(hal, M_DEVBUF); 358 } 359 360 HAL_BOOL 361 ar5k_ar5210_phy_disable(struct ath_hal *hal) 362 { 363 AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); 364 return (AH_TRUE); 365 } 366 367 HAL_BOOL 368 ar5k_ar5210_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, 369 HAL_BOOL change_channel, HAL_STATUS *status) 370 { 371 int i; 372 373 /* Not used, keep for HAL compatibility */ 374 *status = HAL_OK; 375 376 if (ar5k_ar5210_nic_wakeup(hal, 377 channel->c_channel_flags & IEEE80211_CHAN_T ? 378 AH_TRUE : AH_FALSE, AH_FALSE) == AH_FALSE) 379 return (AH_FALSE); 380 381 /* 382 * Initialize operating mode 383 */ 384 hal->ah_op_mode = op_mode; 385 ar5k_ar5210_set_opmode(hal); 386 387 /* 388 * Write initial mode register settings 389 */ 390 for (i = 0; i < nitems(ar5210_ini); i++) { 391 if (change_channel == AH_TRUE && 392 ar5210_ini[i].ini_register >= AR5K_AR5210_PCU_MIN && 393 ar5210_ini[i].ini_register <= AR5K_AR5210_PCU_MAX) 394 continue; 395 396 switch (ar5210_ini[i].ini_mode) { 397 case AR5K_INI_READ: 398 /* Cleared on read */ 399 AR5K_REG_READ(ar5210_ini[i].ini_register); 400 break; 401 402 case AR5K_INI_WRITE: 403 default: 404 AR5K_REG_WRITE(ar5210_ini[i].ini_register, 405 ar5210_ini[i].ini_value); 406 } 407 } 408 409 AR5K_DELAY(1000); 410 411 /* 412 * Set channel and calibrate the PHY 413 */ 414 415 /* Disable phy and wait */ 416 AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); 417 AR5K_DELAY(1000); 418 419 if (ar5k_channel(hal, channel) == AH_FALSE) 420 return (AH_FALSE); 421 422 /* 423 * Activate phy and wait 424 */ 425 AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE); 426 AR5K_DELAY(1000); 427 428 ar5k_ar5210_do_calibrate(hal, channel); 429 if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE) 430 return (AH_FALSE); 431 432 /* 433 * Set RF kill flags if supported by the device (read from the EEPROM) 434 */ 435 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { 436 ar5k_ar5210_set_gpio_input(hal, 0); 437 if ((hal->ah_gpio[0] = ar5k_ar5210_get_gpio(hal, 0)) == 0) { 438 ar5k_ar5210_set_gpio_intr(hal, 0, 1); 439 } else { 440 ar5k_ar5210_set_gpio_intr(hal, 0, 0); 441 } 442 } 443 444 /* 445 * Reset queues and start beacon timers at the end of the reset routine 446 */ 447 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { 448 if (ar5k_ar5210_reset_tx_queue(hal, i) == AH_FALSE) { 449 AR5K_PRINTF("failed to reset TX queue #%d\n", i); 450 return (AH_FALSE); 451 } 452 } 453 454 AR5K_REG_DISABLE_BITS(AR5K_AR5210_BEACON, 455 AR5K_AR5210_BEACON_EN | AR5K_AR5210_BEACON_RESET_TSF); 456 457 return (AH_TRUE); 458 } 459 460 void 461 ar5k_ar5210_set_def_antenna(struct ath_hal *hal, u_int ant) 462 { 463 /* Not available */ 464 return; 465 } 466 467 u_int 468 ar5k_ar5210_get_def_antenna(struct ath_hal *hal) 469 { 470 return (0); 471 } 472 473 void 474 ar5k_ar5210_set_opmode(struct ath_hal *hal) 475 { 476 u_int32_t pcu_reg, beacon_reg, low_id, high_id; 477 478 beacon_reg = 0; 479 pcu_reg = 0; 480 481 switch (hal->ah_op_mode) { 482 case IEEE80211_M_STA: 483 pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL | 484 AR5K_AR5210_STA_ID1_DESC_ANTENNA | 485 AR5K_AR5210_STA_ID1_PWR_SV; 486 break; 487 488 #ifndef IEEE80211_STA_ONLY 489 case IEEE80211_M_IBSS: 490 pcu_reg |= AR5K_AR5210_STA_ID1_ADHOC | 491 AR5K_AR5210_STA_ID1_NO_PSPOLL | 492 AR5K_AR5210_STA_ID1_DESC_ANTENNA; 493 beacon_reg |= AR5K_AR5210_BCR_ADHOC; 494 break; 495 496 case IEEE80211_M_HOSTAP: 497 pcu_reg |= AR5K_AR5210_STA_ID1_AP | 498 AR5K_AR5210_STA_ID1_NO_PSPOLL | 499 AR5K_AR5210_STA_ID1_DESC_ANTENNA; 500 beacon_reg |= AR5K_AR5210_BCR_AP; 501 break; 502 #endif 503 504 case IEEE80211_M_MONITOR: 505 pcu_reg |= AR5K_AR5210_STA_ID1_NO_PSPOLL; 506 break; 507 508 default: 509 return; 510 } 511 512 /* 513 * Set PCU and BCR registers 514 */ 515 low_id = AR5K_LOW_ID(hal->ah_sta_id); 516 high_id = AR5K_HIGH_ID(hal->ah_sta_id); 517 AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id); 518 AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, pcu_reg | high_id); 519 AR5K_REG_WRITE(AR5K_AR5210_BCR, beacon_reg); 520 521 return; 522 } 523 524 HAL_BOOL 525 ar5k_ar5210_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 526 { 527 HAL_BOOL ret = AH_TRUE; 528 u_int32_t phy_sig, phy_agc, phy_sat, beacon; 529 530 #define AGC_DISABLE { \ 531 AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGC, \ 532 AR5K_AR5210_PHY_AGC_DISABLE); \ 533 AR5K_DELAY(10); \ 534 } 535 536 #define AGC_ENABLE { \ 537 AR5K_REG_DISABLE_BITS(AR5K_AR5210_PHY_AGC, \ 538 AR5K_AR5210_PHY_AGC_DISABLE); \ 539 } 540 541 /* 542 * Disable beacons and RX/TX queues, wait 543 */ 544 AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, 545 AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX); 546 beacon = AR5K_REG_READ(AR5K_AR5210_BEACON); 547 AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon & ~AR5K_AR5210_BEACON_EN); 548 549 AR5K_DELAY(2300); 550 551 /* 552 * Set the channel (with AGC turned off) 553 */ 554 AGC_DISABLE; 555 ret = ar5k_channel(hal, channel); 556 557 /* 558 * Activate PHY and wait 559 */ 560 AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE); 561 AR5K_DELAY(1000); 562 563 AGC_ENABLE; 564 565 if (ret == AH_FALSE) 566 return (ret); 567 568 /* 569 * Calibrate the radio chip 570 */ 571 572 /* Remember normal state */ 573 phy_sig = AR5K_REG_READ(AR5K_AR5210_PHY_SIG); 574 phy_agc = AR5K_REG_READ(AR5K_AR5210_PHY_AGCCOARSE); 575 phy_sat = AR5K_REG_READ(AR5K_AR5210_PHY_ADCSAT); 576 577 /* Update radio registers */ 578 AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG, 579 (phy_sig & ~(AR5K_AR5210_PHY_SIG_FIRPWR)) | 580 AR5K_REG_SM(-1, AR5K_AR5210_PHY_SIG_FIRPWR)); 581 582 AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, 583 (phy_agc & ~(AR5K_AR5210_PHY_AGCCOARSE_HI | 584 AR5K_AR5210_PHY_AGCCOARSE_LO)) | 585 AR5K_REG_SM(-1, AR5K_AR5210_PHY_AGCCOARSE_HI) | 586 AR5K_REG_SM(-127, AR5K_AR5210_PHY_AGCCOARSE_LO)); 587 588 AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, 589 (phy_sat & ~(AR5K_AR5210_PHY_ADCSAT_ICNT | 590 AR5K_AR5210_PHY_ADCSAT_THR)) | 591 AR5K_REG_SM(2, AR5K_AR5210_PHY_ADCSAT_ICNT) | 592 AR5K_REG_SM(12, AR5K_AR5210_PHY_ADCSAT_THR)); 593 594 AR5K_DELAY(20); 595 596 AGC_DISABLE; 597 AR5K_REG_WRITE(AR5K_AR5210_PHY_RFSTG, AR5K_AR5210_PHY_RFSTG_DISABLE); 598 AGC_ENABLE; 599 600 AR5K_DELAY(1000); 601 602 ret = ar5k_ar5210_do_calibrate(hal, channel); 603 604 /* Reset to normal state */ 605 AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG, phy_sig); 606 AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, phy_agc); 607 AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, phy_sat); 608 609 if (ret == AH_FALSE) 610 return (AH_FALSE); 611 612 if (ar5k_ar5210_noise_floor(hal, channel) == AH_FALSE) 613 return (AH_FALSE); 614 615 /* 616 * Re-enable RX/TX and beacons 617 */ 618 AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, 619 AR5K_AR5210_DIAG_SW_DIS_TX | AR5K_AR5210_DIAG_SW_DIS_RX); 620 AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon); 621 622 #undef AGC_ENABLE 623 #undef AGC_DISABLE 624 625 return (AH_TRUE); 626 } 627 628 HAL_BOOL 629 ar5k_ar5210_do_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 630 { 631 /* 632 * Enable calibration and wait until completion 633 */ 634 AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL, 635 AR5K_AR5210_PHY_AGCCTL_CAL); 636 637 if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, 638 AR5K_AR5210_PHY_AGCCTL_CAL, 0, AH_FALSE) == AH_FALSE) { 639 AR5K_PRINTF("calibration timeout (%uMHz)\n", 640 channel->c_channel); 641 return (AH_FALSE); 642 } 643 644 return (AH_TRUE); 645 } 646 647 HAL_BOOL 648 ar5k_ar5210_noise_floor(struct ath_hal *hal, HAL_CHANNEL *channel) 649 { 650 int i; 651 u_int32_t noise_floor; 652 653 /* 654 * Enable noise floor calibration and wait until completion 655 */ 656 AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL, 657 AR5K_AR5210_PHY_AGCCTL_NF); 658 659 if (ar5k_register_timeout(hal, AR5K_AR5210_PHY_AGCCTL, 660 AR5K_AR5210_PHY_AGCCTL_NF, 0, AH_FALSE) == AH_FALSE) { 661 AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n", 662 channel->c_channel); 663 return (AH_FALSE); 664 } 665 666 /* wait until the noise floor is calibrated */ 667 for (i = 20; i > 0; i--) { 668 AR5K_DELAY(1000); 669 noise_floor = AR5K_REG_READ(AR5K_AR5210_PHY_NF); 670 if (AR5K_AR5210_PHY_NF_RVAL(noise_floor) & 671 AR5K_AR5210_PHY_NF_ACTIVE) 672 noise_floor = AR5K_AR5210_PHY_NF_AVAL(noise_floor); 673 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) 674 break; 675 } 676 677 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { 678 AR5K_PRINTF("noise floor calibration failed (%uMHz)\n", 679 channel->c_channel); 680 return (AH_FALSE); 681 } 682 683 return (AH_TRUE); 684 } 685 686 /* 687 * Transmit functions 688 */ 689 690 HAL_BOOL 691 ar5k_ar5210_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) 692 { 693 u_int32_t trigger_level; 694 HAL_BOOL status = AH_FALSE; 695 696 /* 697 * Disable interrupts by setting the mask 698 */ 699 AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL); 700 701 trigger_level = AR5K_REG_READ(AR5K_AR5210_TRIG_LVL); 702 703 if (increase == AH_FALSE) { 704 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 705 goto done; 706 } else { 707 trigger_level += 708 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 709 } 710 711 /* 712 * Update trigger level on success 713 */ 714 AR5K_REG_WRITE(AR5K_AR5210_TRIG_LVL, trigger_level); 715 status = AH_TRUE; 716 717 done: 718 /* 719 * Restore interrupt mask 720 */ 721 AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL); 722 723 return (status); 724 } 725 726 int 727 ar5k_ar5210_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, 728 const HAL_TXQ_INFO *queue_info) 729 { 730 u_int queue; 731 732 /* 733 * Get queue by type 734 */ 735 switch (queue_type) { 736 case HAL_TX_QUEUE_DATA: 737 queue = 0; 738 break; 739 case HAL_TX_QUEUE_BEACON: 740 case HAL_TX_QUEUE_CAB: 741 queue = 1; 742 break; 743 default: 744 return (-1); 745 } 746 747 /* 748 * Setup internal queue structure 749 */ 750 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 751 hal->ah_txq[queue].tqi_type = queue_type; 752 753 if (queue_info != NULL) { 754 if (ar5k_ar5210_setup_tx_queueprops(hal, 755 queue, queue_info) != AH_TRUE) 756 return (-1); 757 } 758 759 return (queue); 760 } 761 762 HAL_BOOL 763 ar5k_ar5210_setup_tx_queueprops(struct ath_hal *hal, int queue, 764 const HAL_TXQ_INFO *queue_info) 765 { 766 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 767 768 if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) 769 return (AH_FALSE); 770 771 hal->ah_txq[queue].tqi_aifs = queue_info->tqi_aifs; 772 hal->ah_txq[queue].tqi_cw_max = queue_info->tqi_cw_max; 773 hal->ah_txq[queue].tqi_cw_min = queue_info->tqi_cw_min; 774 hal->ah_txq[queue].tqi_flags = queue_info->tqi_flags; 775 776 return (AH_TRUE); 777 } 778 779 HAL_BOOL 780 ar5k_ar5210_get_tx_queueprops(struct ath_hal *hal, int queue, 781 HAL_TXQ_INFO *queue_info) 782 { 783 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 784 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO)); 785 return (AH_TRUE); 786 } 787 788 HAL_BOOL 789 ar5k_ar5210_release_tx_queue(struct ath_hal *hal, u_int queue) 790 { 791 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 792 793 /* This queue will be skipped in further operations */ 794 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; 795 796 return (AH_FALSE); 797 } 798 799 void 800 ar5k_ar5210_init_tx_queue(struct ath_hal *hal, u_int aifs, HAL_BOOL turbo) 801 { 802 int i; 803 struct { 804 u_int16_t mode_register; 805 u_int32_t mode_base, mode_turbo; 806 } initial[] = AR5K_AR5210_INI_MODE(aifs); 807 808 /* 809 * Write initial mode register settings 810 */ 811 for (i = 0; i < nitems(initial); i++) 812 AR5K_REG_WRITE((u_int32_t)initial[i].mode_register, 813 turbo == AH_TRUE ? 814 initial[i].mode_turbo : initial[i].mode_base); 815 } 816 817 HAL_BOOL 818 ar5k_ar5210_reset_tx_queue(struct ath_hal *hal, u_int queue) 819 { 820 u_int32_t cw_min, retry_lg, retry_sh; 821 HAL_TXQ_INFO *tq; 822 823 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 824 825 tq = &hal->ah_txq[queue]; 826 827 /* Only handle data queues, others will be ignored */ 828 if (tq->tqi_type != HAL_TX_QUEUE_DATA) 829 return (AH_TRUE); 830 831 /* Set turbo/base mode parameters */ 832 ar5k_ar5210_init_tx_queue(hal, hal->ah_aifs + tq->tqi_aifs, 833 hal->ah_turbo == AH_TRUE ? AH_TRUE : AH_FALSE); 834 835 /* 836 * Set retry limits 837 */ 838 if (hal->ah_software_retry == AH_TRUE) { 839 /* XXX Need to test this */ 840 retry_lg = hal->ah_limit_tx_retries; 841 retry_sh = retry_lg = 842 retry_lg > AR5K_AR5210_RETRY_LMT_SH_RETRY ? 843 AR5K_AR5210_RETRY_LMT_SH_RETRY : retry_lg; 844 } else { 845 retry_lg = AR5K_INIT_LG_RETRY; 846 retry_sh = AR5K_INIT_SH_RETRY; 847 } 848 849 /* 850 * Set initial content window (cw_min/cw_max) 851 */ 852 cw_min = 1; 853 while (cw_min < hal->ah_cw_min) 854 cw_min = (cw_min << 1) | 1; 855 856 cw_min = tq->tqi_cw_min < 0 ? 857 (cw_min >> (-tq->tqi_cw_min)) : 858 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 859 860 /* Commit values */ 861 AR5K_REG_WRITE(AR5K_AR5210_RETRY_LMT, 862 (cw_min << AR5K_AR5210_RETRY_LMT_CW_MIN_S) 863 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_AR5210_RETRY_LMT_SLG_RETRY) 864 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_AR5210_RETRY_LMT_SSH_RETRY) 865 | AR5K_REG_SM(retry_lg, AR5K_AR5210_RETRY_LMT_LG_RETRY) 866 | AR5K_REG_SM(retry_sh, AR5K_AR5210_RETRY_LMT_SH_RETRY)); 867 868 return (AH_TRUE); 869 } 870 871 u_int32_t 872 ar5k_ar5210_get_tx_buf(struct ath_hal *hal, u_int queue) 873 { 874 u_int16_t tx_reg; 875 876 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 877 878 /* 879 * Get the transmit queue descriptor pointer register by type 880 */ 881 switch (hal->ah_txq[queue].tqi_type) { 882 case HAL_TX_QUEUE_DATA: 883 tx_reg = AR5K_AR5210_TXDP0; 884 break; 885 case HAL_TX_QUEUE_BEACON: 886 case HAL_TX_QUEUE_CAB: 887 tx_reg = AR5K_AR5210_TXDP1; 888 break; 889 default: 890 return (0xffffffff); 891 } 892 893 return (AR5K_REG_READ(tx_reg)); 894 } 895 896 HAL_BOOL 897 ar5k_ar5210_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) 898 { 899 u_int16_t tx_reg; 900 901 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 902 903 /* 904 * Get the transmit queue descriptor pointer register by type 905 */ 906 switch (hal->ah_txq[queue].tqi_type) { 907 case HAL_TX_QUEUE_DATA: 908 tx_reg = AR5K_AR5210_TXDP0; 909 break; 910 case HAL_TX_QUEUE_BEACON: 911 case HAL_TX_QUEUE_CAB: 912 tx_reg = AR5K_AR5210_TXDP1; 913 break; 914 default: 915 return (AH_FALSE); 916 } 917 918 /* Set descriptor pointer */ 919 AR5K_REG_WRITE(tx_reg, phys_addr); 920 921 return (AH_TRUE); 922 } 923 924 u_int32_t 925 ar5k_ar5210_num_tx_pending(struct ath_hal *hal, u_int queue) 926 { 927 return (AH_FALSE); 928 } 929 930 HAL_BOOL 931 ar5k_ar5210_tx_start(struct ath_hal *hal, u_int queue) 932 { 933 u_int32_t tx_queue; 934 935 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 936 937 tx_queue = AR5K_REG_READ(AR5K_AR5210_CR); 938 939 /* 940 * Set the queue type 941 */ 942 switch (hal->ah_txq[queue].tqi_type) { 943 case HAL_TX_QUEUE_DATA: 944 tx_queue |= AR5K_AR5210_CR_TXE0 & ~AR5K_AR5210_CR_TXD0; 945 break; 946 947 case HAL_TX_QUEUE_BEACON: 948 tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1; 949 AR5K_REG_WRITE(AR5K_AR5210_BSR, 950 AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE); 951 break; 952 953 case HAL_TX_QUEUE_CAB: 954 tx_queue |= AR5K_AR5210_CR_TXE1 & ~AR5K_AR5210_CR_TXD1; 955 AR5K_REG_WRITE(AR5K_AR5210_BSR, 956 AR5K_AR5210_BCR_TQ1FV | AR5K_AR5210_BCR_TQ1V | 957 AR5K_AR5210_BCR_BDMAE); 958 break; 959 960 default: 961 return (AH_FALSE); 962 } 963 964 /* Start queue */ 965 AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); 966 967 return (AH_TRUE); 968 } 969 970 HAL_BOOL 971 ar5k_ar5210_stop_tx_dma(struct ath_hal *hal, u_int queue) 972 { 973 u_int32_t tx_queue; 974 975 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 976 977 tx_queue = AR5K_REG_READ(AR5K_AR5210_CR); 978 979 /* 980 * Set by queue type 981 */ 982 switch (hal->ah_txq[queue].tqi_type) { 983 case HAL_TX_QUEUE_DATA: 984 tx_queue |= AR5K_AR5210_CR_TXD0 & ~AR5K_AR5210_CR_TXE0; 985 break; 986 987 case HAL_TX_QUEUE_BEACON: 988 case HAL_TX_QUEUE_CAB: 989 /* XXX Fix me... */ 990 tx_queue |= AR5K_AR5210_CR_TXD1 & ~AR5K_AR5210_CR_TXD1; 991 AR5K_REG_WRITE(AR5K_AR5210_BSR, 0); 992 break; 993 994 default: 995 return (AH_FALSE); 996 } 997 998 /* Stop queue */ 999 AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); 1000 1001 return (AH_TRUE); 1002 } 1003 1004 HAL_BOOL 1005 ar5k_ar5210_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1006 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, 1007 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, 1008 u_int flags, u_int rtscts_rate, u_int rtscts_duration) 1009 { 1010 u_int32_t frame_type; 1011 struct ar5k_ar5210_tx_desc *tx_desc; 1012 1013 tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0; 1014 1015 /* 1016 * Validate input 1017 */ 1018 if (tx_tries0 == 0) 1019 return (AH_FALSE); 1020 1021 if ((tx_desc->tx_control_0 = (packet_length & 1022 AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN)) != packet_length) 1023 return (AH_FALSE); 1024 1025 if ((tx_desc->tx_control_0 = (header_length & 1026 AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN)) != header_length) 1027 return (AH_FALSE); 1028 1029 if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP) 1030 frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY; 1031 else if (type == HAL_PKT_TYPE_PIFS) 1032 frame_type = AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS; 1033 else 1034 frame_type = type; 1035 1036 tx_desc->tx_control_0 = 1037 AR5K_REG_SM(frame_type, AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE); 1038 tx_desc->tx_control_0 |= 1039 AR5K_REG_SM(tx_rate0, AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE); 1040 1041 #define _TX_FLAGS(_c, _flag) \ 1042 if (flags & HAL_TXDESC_##_flag) \ 1043 tx_desc->tx_control_##_c |= \ 1044 AR5K_AR5210_DESC_TX_CTL##_c##_##_flag 1045 1046 _TX_FLAGS(0, CLRDMASK); 1047 _TX_FLAGS(0, INTREQ); 1048 _TX_FLAGS(0, RTSENA); 1049 1050 #undef _TX_FLAGS 1051 1052 /* 1053 * WEP crap 1054 */ 1055 if (key_index != HAL_TXKEYIX_INVALID) { 1056 tx_desc->tx_control_0 |= 1057 AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID; 1058 tx_desc->tx_control_1 |= 1059 AR5K_REG_SM(key_index, 1060 AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); 1061 } 1062 1063 /* 1064 * RTS/CTS 1065 */ 1066 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 1067 tx_desc->tx_control_1 |= 1068 rtscts_duration & AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION; 1069 } 1070 1071 return (AH_TRUE); 1072 } 1073 1074 HAL_BOOL 1075 ar5k_ar5210_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1076 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment) 1077 { 1078 struct ar5k_ar5210_tx_desc *tx_desc; 1079 1080 tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0; 1081 1082 /* Clear status descriptor */ 1083 bzero(desc->ds_hw, sizeof(desc->ds_hw)); 1084 1085 /* Validate segment length and initialize the descriptor */ 1086 if (segment_length & ~AR5K_AR5210_DESC_TX_CTL1_BUF_LEN) 1087 return (AH_FALSE); 1088 tx_desc->tx_control_1 = 1089 #if 0 1090 (tx_desc->tx_control_1 & ~AR5K_AR5210_DESC_TX_CTL1_BUF_LEN) | 1091 #endif 1092 segment_length; 1093 1094 if (first_segment != AH_TRUE) 1095 tx_desc->tx_control_0 &= ~AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN; 1096 1097 if (last_segment != AH_TRUE) 1098 tx_desc->tx_control_1 |= AR5K_AR5210_DESC_TX_CTL1_MORE; 1099 1100 return (AH_TRUE); 1101 } 1102 1103 HAL_BOOL 1104 ar5k_ar5210_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, 1105 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 1106 u_int tx_rate3, u_int tx_tries3) 1107 { 1108 /* 1109 * Does this function is for setting up XR? Not sure... 1110 * Nevertheless, I didn't find any information about XR support 1111 * by the AR5210. This seems to be a slightly new feature. 1112 */ 1113 return (AH_FALSE); 1114 } 1115 1116 HAL_STATUS 1117 ar5k_ar5210_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) 1118 { 1119 struct ar5k_ar5210_tx_status *tx_status; 1120 struct ar5k_ar5210_tx_desc *tx_desc; 1121 1122 tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0; 1123 tx_status = (struct ar5k_ar5210_tx_status*)&desc->ds_hw[0]; 1124 1125 /* No frame has been send or error */ 1126 if ((tx_status->tx_status_1 & AR5K_AR5210_DESC_TX_STATUS1_DONE) == 0) 1127 return (HAL_EINPROGRESS); 1128 1129 /* 1130 * Get descriptor status 1131 */ 1132 desc->ds_us.tx.ts_tstamp = 1133 AR5K_REG_MS(tx_status->tx_status_0, 1134 AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP); 1135 desc->ds_us.tx.ts_shortretry = 1136 AR5K_REG_MS(tx_status->tx_status_0, 1137 AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT); 1138 desc->ds_us.tx.ts_longretry = 1139 AR5K_REG_MS(tx_status->tx_status_0, 1140 AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT); 1141 desc->ds_us.tx.ts_seqnum = 1142 AR5K_REG_MS(tx_status->tx_status_1, 1143 AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM); 1144 desc->ds_us.tx.ts_rssi = 1145 AR5K_REG_MS(tx_status->tx_status_1, 1146 AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 1147 desc->ds_us.tx.ts_antenna = 1; 1148 desc->ds_us.tx.ts_status = 0; 1149 desc->ds_us.tx.ts_rate = 1150 AR5K_REG_MS(tx_desc->tx_control_0, 1151 AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE); 1152 1153 if ((tx_status->tx_status_0 & 1154 AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { 1155 if (tx_status->tx_status_0 & 1156 AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 1157 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; 1158 1159 if (tx_status->tx_status_0 & 1160 AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN) 1161 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; 1162 1163 if (tx_status->tx_status_0 & 1164 AR5K_AR5210_DESC_TX_STATUS0_FILTERED) 1165 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; 1166 } 1167 1168 return (HAL_OK); 1169 } 1170 1171 HAL_BOOL 1172 ar5k_ar5210_has_veol(struct ath_hal *hal) 1173 { 1174 return (AH_FALSE); 1175 } 1176 1177 /* 1178 * Receive functions 1179 */ 1180 1181 u_int32_t 1182 ar5k_ar5210_get_rx_buf(struct ath_hal *hal) 1183 { 1184 return (AR5K_REG_READ(AR5K_AR5210_RXDP)); 1185 } 1186 1187 void 1188 ar5k_ar5210_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) 1189 { 1190 AR5K_REG_WRITE(AR5K_AR5210_RXDP, phys_addr); 1191 } 1192 1193 void 1194 ar5k_ar5210_start_rx(struct ath_hal *hal) 1195 { 1196 AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXE); 1197 } 1198 1199 HAL_BOOL 1200 ar5k_ar5210_stop_rx_dma(struct ath_hal *hal) 1201 { 1202 int i; 1203 1204 AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXD); 1205 1206 /* 1207 * It may take some time to disable the DMA receive unit 1208 */ 1209 for (i = 2000; 1210 i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0; 1211 i--) 1212 AR5K_DELAY(10); 1213 1214 return (i > 0 ? AH_TRUE : AH_FALSE); 1215 } 1216 1217 void 1218 ar5k_ar5210_start_rx_pcu(struct ath_hal *hal) 1219 { 1220 AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX); 1221 } 1222 1223 void 1224 ar5k_ar5210_stop_pcu_recv(struct ath_hal *hal) 1225 { 1226 AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX); 1227 } 1228 1229 void 1230 ar5k_ar5210_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, 1231 u_int32_t filter1) 1232 { 1233 /* Set the multicat filter */ 1234 AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL0, filter0); 1235 AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL1, filter1); 1236 } 1237 1238 HAL_BOOL 1239 ar5k_ar5210_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) 1240 { 1241 if (index >= 64) { 1242 return (AH_FALSE); 1243 } else if (index >= 32) { 1244 AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL1, 1245 (1 << (index - 32))); 1246 } else { 1247 AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL0, 1248 (1 << index)); 1249 } 1250 1251 return (AH_TRUE); 1252 } 1253 1254 HAL_BOOL 1255 ar5k_ar5210_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) 1256 { 1257 if (index >= 64) { 1258 return (AH_FALSE); 1259 } else if (index >= 32) { 1260 AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL1, 1261 (1 << (index - 32))); 1262 } else { 1263 AR5K_REG_DISABLE_BITS(AR5K_AR5210_MCAST_FIL0, 1264 (1 << index)); 1265 } 1266 1267 return (AH_TRUE); 1268 } 1269 1270 u_int32_t 1271 ar5k_ar5210_get_rx_filter(struct ath_hal *hal) 1272 { 1273 return (AR5K_REG_READ(AR5K_AR5210_RX_FILTER)); 1274 } 1275 1276 void 1277 ar5k_ar5210_set_rx_filter(struct ath_hal *hal, u_int32_t filter) 1278 { 1279 /* 1280 * The AR5210 uses promiscous mode to detect radar activity 1281 */ 1282 if (filter & HAL_RX_FILTER_PHYRADAR) { 1283 filter &= ~HAL_RX_FILTER_PHYRADAR; 1284 filter |= AR5K_AR5210_RX_FILTER_PROMISC; 1285 } 1286 1287 AR5K_REG_WRITE(AR5K_AR5210_RX_FILTER, filter); 1288 } 1289 1290 HAL_BOOL 1291 ar5k_ar5210_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1292 u_int32_t size, u_int flags) 1293 { 1294 struct ar5k_ar5210_rx_desc *rx_desc; 1295 1296 rx_desc = (struct ar5k_ar5210_rx_desc*)&desc->ds_ctl0; 1297 1298 if ((rx_desc->rx_control_1 = (size & 1299 AR5K_AR5210_DESC_RX_CTL1_BUF_LEN)) != size) 1300 return (AH_FALSE); 1301 1302 if (flags & HAL_RXDESC_INTREQ) 1303 rx_desc->rx_control_1 |= AR5K_AR5210_DESC_RX_CTL1_INTREQ; 1304 1305 return (AH_TRUE); 1306 } 1307 1308 HAL_STATUS 1309 ar5k_ar5210_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1310 u_int32_t phys_addr, struct ath_desc *next) 1311 { 1312 struct ar5k_ar5210_rx_status *rx_status; 1313 1314 rx_status = (struct ar5k_ar5210_rx_status*)&desc->ds_hw[0]; 1315 1316 /* No frame received / not ready */ 1317 if ((rx_status->rx_status_1 & AR5K_AR5210_DESC_RX_STATUS1_DONE) == 0) 1318 return (HAL_EINPROGRESS); 1319 1320 /* 1321 * Frame receive status 1322 */ 1323 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 1324 AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN; 1325 desc->ds_us.rx.rs_rssi = 1326 AR5K_REG_MS(rx_status->rx_status_0, 1327 AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL); 1328 desc->ds_us.rx.rs_rate = 1329 AR5K_REG_MS(rx_status->rx_status_0, 1330 AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE); 1331 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 1332 AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA; 1333 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 1334 AR5K_AR5210_DESC_RX_STATUS0_MORE; 1335 desc->ds_us.rx.rs_tstamp = 1336 AR5K_REG_MS(rx_status->rx_status_1, 1337 AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); 1338 desc->ds_us.rx.rs_status = 0; 1339 1340 /* 1341 * Key table status 1342 */ 1343 if (rx_status->rx_status_1 & 1344 AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID) { 1345 desc->ds_us.rx.rs_keyix = 1346 AR5K_REG_MS(rx_status->rx_status_1, 1347 AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX); 1348 } else { 1349 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; 1350 } 1351 1352 /* 1353 * Receive/descriptor errors 1354 */ 1355 if ((rx_status->rx_status_1 & 1356 AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { 1357 if (rx_status->rx_status_1 & 1358 AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR) 1359 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; 1360 1361 if (rx_status->rx_status_1 & 1362 AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN) 1363 desc->ds_us.rx.rs_status |= HAL_RXERR_FIFO; 1364 1365 if (rx_status->rx_status_1 & 1366 AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR) { 1367 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; 1368 desc->ds_us.rx.rs_phyerr = 1369 AR5K_REG_MS(rx_status->rx_status_1, 1370 AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR); 1371 } 1372 1373 if (rx_status->rx_status_1 & 1374 AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) 1375 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; 1376 } 1377 1378 return (HAL_OK); 1379 } 1380 1381 void 1382 ar5k_ar5210_set_rx_signal(struct ath_hal *hal) 1383 { 1384 /* Signal state monitoring is not yet supported */ 1385 } 1386 1387 /* 1388 * Misc functions 1389 */ 1390 1391 void 1392 ar5k_ar5210_dump_state(struct ath_hal *hal) 1393 { 1394 #ifdef AR5K_DEBUG 1395 #define AR5K_PRINT_REGISTER(_x) \ 1396 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5210_##_x)); 1397 1398 printf("DMA registers:\n"); 1399 AR5K_PRINT_REGISTER(TXDP0); 1400 AR5K_PRINT_REGISTER(TXDP1); 1401 AR5K_PRINT_REGISTER(CR); 1402 AR5K_PRINT_REGISTER(RXDP); 1403 AR5K_PRINT_REGISTER(CFG); 1404 AR5K_PRINT_REGISTER(ISR); 1405 AR5K_PRINT_REGISTER(IMR); 1406 AR5K_PRINT_REGISTER(IER); 1407 AR5K_PRINT_REGISTER(BCR); 1408 AR5K_PRINT_REGISTER(BSR); 1409 AR5K_PRINT_REGISTER(TXCFG); 1410 AR5K_PRINT_REGISTER(RXCFG); 1411 AR5K_PRINT_REGISTER(MIBC); 1412 AR5K_PRINT_REGISTER(TOPS); 1413 AR5K_PRINT_REGISTER(RXNOFRM); 1414 AR5K_PRINT_REGISTER(TXNOFRM); 1415 AR5K_PRINT_REGISTER(RPGTO); 1416 AR5K_PRINT_REGISTER(RFCNT); 1417 AR5K_PRINT_REGISTER(MISC); 1418 AR5K_PRINT_REGISTER(RC); 1419 AR5K_PRINT_REGISTER(SCR); 1420 AR5K_PRINT_REGISTER(INTPEND); 1421 AR5K_PRINT_REGISTER(SFR); 1422 AR5K_PRINT_REGISTER(PCICFG); 1423 AR5K_PRINT_REGISTER(GPIOCR); 1424 AR5K_PRINT_REGISTER(GPIODO); 1425 AR5K_PRINT_REGISTER(GPIODI); 1426 AR5K_PRINT_REGISTER(SREV); 1427 printf("\n"); 1428 1429 printf("PCU registers:\n"); 1430 AR5K_PRINT_REGISTER(STA_ID0); 1431 AR5K_PRINT_REGISTER(STA_ID1); 1432 AR5K_PRINT_REGISTER(BSS_ID0); 1433 AR5K_PRINT_REGISTER(BSS_ID1); 1434 AR5K_PRINT_REGISTER(SLOT_TIME); 1435 AR5K_PRINT_REGISTER(TIME_OUT); 1436 AR5K_PRINT_REGISTER(RSSI_THR); 1437 AR5K_PRINT_REGISTER(RETRY_LMT); 1438 AR5K_PRINT_REGISTER(USEC); 1439 AR5K_PRINT_REGISTER(BEACON); 1440 AR5K_PRINT_REGISTER(CFP_PERIOD); 1441 AR5K_PRINT_REGISTER(TIMER0); 1442 AR5K_PRINT_REGISTER(TIMER1); 1443 AR5K_PRINT_REGISTER(TIMER2); 1444 AR5K_PRINT_REGISTER(TIMER3); 1445 AR5K_PRINT_REGISTER(IFS0); 1446 AR5K_PRINT_REGISTER(IFS1); 1447 AR5K_PRINT_REGISTER(CFP_DUR); 1448 AR5K_PRINT_REGISTER(RX_FILTER); 1449 AR5K_PRINT_REGISTER(MCAST_FIL0); 1450 AR5K_PRINT_REGISTER(MCAST_FIL1); 1451 AR5K_PRINT_REGISTER(TX_MASK0); 1452 AR5K_PRINT_REGISTER(TX_MASK1); 1453 AR5K_PRINT_REGISTER(CLR_TMASK); 1454 AR5K_PRINT_REGISTER(TRIG_LVL); 1455 AR5K_PRINT_REGISTER(DIAG_SW); 1456 AR5K_PRINT_REGISTER(TSF_L32); 1457 AR5K_PRINT_REGISTER(TSF_U32); 1458 AR5K_PRINT_REGISTER(LAST_TSTP); 1459 AR5K_PRINT_REGISTER(RETRY_CNT); 1460 AR5K_PRINT_REGISTER(BACKOFF); 1461 AR5K_PRINT_REGISTER(NAV); 1462 AR5K_PRINT_REGISTER(RTS_OK); 1463 AR5K_PRINT_REGISTER(RTS_FAIL); 1464 AR5K_PRINT_REGISTER(ACK_FAIL); 1465 AR5K_PRINT_REGISTER(FCS_FAIL); 1466 AR5K_PRINT_REGISTER(BEACON_CNT); 1467 AR5K_PRINT_REGISTER(KEYTABLE_0); 1468 printf("\n"); 1469 1470 printf("PHY registers:\n"); 1471 AR5K_PRINT_REGISTER(PHY(0)); 1472 AR5K_PRINT_REGISTER(PHY_FC); 1473 AR5K_PRINT_REGISTER(PHY_AGC); 1474 AR5K_PRINT_REGISTER(PHY_CHIP_ID); 1475 AR5K_PRINT_REGISTER(PHY_ACTIVE); 1476 AR5K_PRINT_REGISTER(PHY_AGCCTL); 1477 printf("\n"); 1478 #endif 1479 } 1480 1481 HAL_BOOL 1482 ar5k_ar5210_get_diag_state(struct ath_hal *hal, int id, void **device, 1483 u_int *size) 1484 { 1485 /* 1486 * We'll ignore this right now. This seems to be some kind of an obscure 1487 * debugging interface for the binary-only HAL. 1488 */ 1489 return (AH_FALSE); 1490 } 1491 1492 void 1493 ar5k_ar5210_get_lladdr(struct ath_hal *hal, u_int8_t *mac) 1494 { 1495 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); 1496 } 1497 1498 HAL_BOOL 1499 ar5k_ar5210_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) 1500 { 1501 u_int32_t low_id, high_id; 1502 1503 /* Set new station ID */ 1504 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); 1505 1506 low_id = AR5K_LOW_ID(mac); 1507 high_id = 0x0000ffff & AR5K_HIGH_ID(mac); 1508 1509 AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id); 1510 AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, high_id); 1511 1512 return (AH_TRUE); 1513 } 1514 1515 HAL_BOOL 1516 ar5k_ar5210_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, 1517 HAL_STATUS *status) 1518 { 1519 ieee80211_regdomain_t ieee_regdomain; 1520 1521 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); 1522 1523 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, 1524 &ieee_regdomain) == AH_TRUE) { 1525 *status = HAL_OK; 1526 return (AH_TRUE); 1527 } 1528 1529 *status = EIO; 1530 1531 return (AH_FALSE); 1532 } 1533 1534 void 1535 ar5k_ar5210_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) 1536 { 1537 u_int32_t led; 1538 1539 led = AR5K_REG_READ(AR5K_AR5210_PCICFG); 1540 1541 /* 1542 * Some blinking values, define at your wish 1543 */ 1544 switch (state) { 1545 case IEEE80211_S_SCAN: 1546 case IEEE80211_S_INIT: 1547 led |= 1548 AR5K_AR5210_PCICFG_LED_PEND | 1549 AR5K_AR5210_PCICFG_LED_BCTL; 1550 break; 1551 case IEEE80211_S_RUN: 1552 led |= 1553 AR5K_AR5210_PCICFG_LED_ACT; 1554 break; 1555 default: 1556 led |= 1557 AR5K_AR5210_PCICFG_LED_ACT | 1558 AR5K_AR5210_PCICFG_LED_BCTL; 1559 break; 1560 } 1561 1562 AR5K_REG_WRITE(AR5K_AR5210_PCICFG, led); 1563 } 1564 1565 void 1566 ar5k_ar5210_set_associd(struct ath_hal *hal, const u_int8_t *bssid, 1567 u_int16_t assoc_id, u_int16_t tim_offset) 1568 { 1569 u_int32_t low_id, high_id; 1570 1571 /* 1572 * Set BSSID which triggers the "SME Join" operation 1573 */ 1574 low_id = AR5K_LOW_ID(bssid); 1575 high_id = AR5K_HIGH_ID(bssid); 1576 AR5K_REG_WRITE(AR5K_AR5210_BSS_ID0, low_id); 1577 AR5K_REG_WRITE(AR5K_AR5210_BSS_ID1, high_id | 1578 ((assoc_id & 0x3fff) << AR5K_AR5210_BSS_ID1_AID_S)); 1579 bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN); 1580 1581 if (assoc_id == 0) { 1582 ar5k_ar5210_disable_pspoll(hal); 1583 return; 1584 } 1585 1586 AR5K_REG_WRITE_BITS(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_TIM, 1587 tim_offset ? tim_offset + 4 : 0); 1588 1589 ar5k_ar5210_enable_pspoll(hal, NULL, 0); 1590 } 1591 1592 HAL_BOOL 1593 ar5k_ar5210_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) 1594 { 1595 /* Not supported in 5210 */ 1596 return (AH_FALSE); 1597 } 1598 1599 HAL_BOOL 1600 ar5k_ar5210_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) 1601 { 1602 if (gpio > AR5K_AR5210_NUM_GPIO) 1603 return (AH_FALSE); 1604 1605 AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, 1606 (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) 1607 | AR5K_AR5210_GPIOCR_OUT1(gpio)); 1608 1609 return (AH_TRUE); 1610 } 1611 1612 HAL_BOOL 1613 ar5k_ar5210_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) 1614 { 1615 if (gpio > AR5K_AR5210_NUM_GPIO) 1616 return (AH_FALSE); 1617 1618 AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, 1619 (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio)) 1620 | AR5K_AR5210_GPIOCR_IN(gpio)); 1621 1622 return (AH_TRUE); 1623 } 1624 1625 u_int32_t 1626 ar5k_ar5210_get_gpio(struct ath_hal *hal, u_int32_t gpio) 1627 { 1628 if (gpio > AR5K_AR5210_NUM_GPIO) 1629 return (0xffffffff); 1630 1631 /* GPIO input magic */ 1632 return (((AR5K_REG_READ(AR5K_AR5210_GPIODI) & 1633 AR5K_AR5210_GPIOD_MASK) >> gpio) & 0x1); 1634 } 1635 1636 HAL_BOOL 1637 ar5k_ar5210_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) 1638 { 1639 u_int32_t data; 1640 1641 if (gpio > AR5K_AR5210_NUM_GPIO) 1642 return (0xffffffff); 1643 1644 /* GPIO output magic */ 1645 data = AR5K_REG_READ(AR5K_AR5210_GPIODO); 1646 1647 data &= ~(1 << gpio); 1648 data |= (val&1) << gpio; 1649 1650 AR5K_REG_WRITE(AR5K_AR5210_GPIODO, data); 1651 1652 return (AH_TRUE); 1653 } 1654 1655 void 1656 ar5k_ar5210_set_gpio_intr(struct ath_hal *hal, u_int gpio, 1657 u_int32_t interrupt_level) 1658 { 1659 u_int32_t data; 1660 1661 if (gpio > AR5K_AR5210_NUM_GPIO) 1662 return; 1663 1664 /* 1665 * Set the GPIO interrupt 1666 */ 1667 data = (AR5K_REG_READ(AR5K_AR5210_GPIOCR) & 1668 ~(AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_SELH | 1669 AR5K_AR5210_GPIOCR_INT_ENA | AR5K_AR5210_GPIOCR_ALL(gpio))) | 1670 (AR5K_AR5210_GPIOCR_INT_SEL(gpio) | AR5K_AR5210_GPIOCR_INT_ENA); 1671 1672 AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, 1673 interrupt_level ? data : (data | AR5K_AR5210_GPIOCR_INT_SELH)); 1674 1675 hal->ah_imr |= AR5K_AR5210_IMR_GPIO; 1676 1677 /* Enable GPIO interrupts */ 1678 AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_AR5210_IMR_GPIO); 1679 } 1680 1681 u_int32_t 1682 ar5k_ar5210_get_tsf32(struct ath_hal *hal) 1683 { 1684 return (AR5K_REG_READ(AR5K_AR5210_TSF_L32)); 1685 } 1686 1687 u_int64_t 1688 ar5k_ar5210_get_tsf64(struct ath_hal *hal) 1689 { 1690 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32); 1691 return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32)); 1692 } 1693 1694 void 1695 ar5k_ar5210_reset_tsf(struct ath_hal *hal) 1696 { 1697 AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON, 1698 AR5K_AR5210_BEACON_RESET_TSF); 1699 } 1700 1701 u_int16_t 1702 ar5k_ar5210_get_regdomain(struct ath_hal *hal) 1703 { 1704 return (ar5k_get_regdomain(hal)); 1705 } 1706 1707 HAL_BOOL 1708 ar5k_ar5210_detect_card_present(struct ath_hal *hal) 1709 { 1710 u_int16_t magic; 1711 1712 /* 1713 * Checking the EEPROM's magic value could be an indication 1714 * if the card is still present. I didn't find another suitable 1715 * way to do this. 1716 */ 1717 if (ar5k_ar5210_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) 1718 return (AH_FALSE); 1719 1720 return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); 1721 } 1722 1723 void 1724 ar5k_ar5210_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) 1725 { 1726 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5210_ACK_FAIL); 1727 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5210_RTS_FAIL); 1728 statistics->rts_good += AR5K_REG_READ(AR5K_AR5210_RTS_OK); 1729 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5210_FCS_FAIL); 1730 statistics->beacons += AR5K_REG_READ(AR5K_AR5210_BEACON_CNT); 1731 } 1732 1733 HAL_RFGAIN 1734 ar5k_ar5210_get_rf_gain(struct ath_hal *hal) 1735 { 1736 return (HAL_RFGAIN_INACTIVE); 1737 } 1738 1739 HAL_BOOL 1740 ar5k_ar5210_set_slot_time(struct ath_hal *hal, u_int slot_time) 1741 { 1742 if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) 1743 return (AH_FALSE); 1744 1745 AR5K_REG_WRITE(AR5K_AR5210_SLOT_TIME, 1746 ar5k_htoclock(slot_time, hal->ah_turbo)); 1747 1748 return (AH_TRUE); 1749 } 1750 1751 u_int 1752 ar5k_ar5210_get_slot_time(struct ath_hal *hal) 1753 { 1754 return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) & 1755 0xffff, hal->ah_turbo)); 1756 } 1757 1758 HAL_BOOL 1759 ar5k_ar5210_set_ack_timeout(struct ath_hal *hal, u_int timeout) 1760 { 1761 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_ACK), 1762 hal->ah_turbo) <= timeout) 1763 return (AH_FALSE); 1764 1765 AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_ACK, 1766 ar5k_htoclock(timeout, hal->ah_turbo)); 1767 1768 return (AH_TRUE); 1769 } 1770 1771 u_int 1772 ar5k_ar5210_get_ack_timeout(struct ath_hal *hal) 1773 { 1774 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), 1775 AR5K_AR5210_TIME_OUT_ACK), hal->ah_turbo)); 1776 } 1777 1778 HAL_BOOL 1779 ar5k_ar5210_set_cts_timeout(struct ath_hal *hal, u_int timeout) 1780 { 1781 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5210_TIME_OUT_CTS), 1782 hal->ah_turbo) <= timeout) 1783 return (AH_FALSE); 1784 1785 AR5K_REG_WRITE_BITS(AR5K_AR5210_TIME_OUT, AR5K_AR5210_TIME_OUT_CTS, 1786 ar5k_htoclock(timeout, hal->ah_turbo)); 1787 1788 return (AH_TRUE); 1789 } 1790 1791 u_int 1792 ar5k_ar5210_get_cts_timeout(struct ath_hal *hal) 1793 { 1794 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT), 1795 AR5K_AR5210_TIME_OUT_CTS), hal->ah_turbo)); 1796 } 1797 1798 /* 1799 * Key table (WEP) functions 1800 */ 1801 1802 HAL_BOOL 1803 ar5k_ar5210_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) 1804 { 1805 /* 1806 * The AR5210 only supports WEP 1807 */ 1808 if (cipher == HAL_CIPHER_WEP) 1809 return (AH_TRUE); 1810 1811 return (AH_FALSE); 1812 } 1813 1814 u_int32_t 1815 ar5k_ar5210_get_keycache_size(struct ath_hal *hal) 1816 { 1817 return (AR5K_AR5210_KEYCACHE_SIZE); 1818 } 1819 1820 HAL_BOOL 1821 ar5k_ar5210_reset_key(struct ath_hal *hal, u_int16_t entry) 1822 { 1823 int i; 1824 1825 AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); 1826 1827 for (i = 0; i < AR5K_AR5210_KEYCACHE_SIZE; i++) 1828 AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), 0); 1829 1830 return (AH_FALSE); 1831 } 1832 1833 HAL_BOOL 1834 ar5k_ar5210_is_key_valid(struct ath_hal *hal, u_int16_t entry) 1835 { 1836 AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); 1837 1838 /* 1839 * Check the validation flag at the end of the entry 1840 */ 1841 if (AR5K_REG_READ(AR5K_AR5210_KEYTABLE_MAC1(entry)) & 1842 AR5K_AR5210_KEYTABLE_VALID) 1843 return (AH_TRUE); 1844 1845 return (AH_FALSE); 1846 } 1847 1848 HAL_BOOL 1849 ar5k_ar5210_set_key(struct ath_hal *hal, u_int16_t entry, 1850 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) 1851 { 1852 int i; 1853 u_int32_t key_v[AR5K_AR5210_KEYCACHE_SIZE - 2]; 1854 1855 AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); 1856 1857 bzero(&key_v, sizeof(key_v)); 1858 1859 switch (keyval->wk_len) { 1860 case AR5K_KEYVAL_LENGTH_40: 1861 bcopy(keyval->wk_key, &key_v[0], 4); 1862 bcopy(keyval->wk_key + 4, &key_v[1], 1); 1863 key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_40; 1864 break; 1865 1866 case AR5K_KEYVAL_LENGTH_104: 1867 bcopy(keyval->wk_key, &key_v[0], 4); 1868 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1869 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1870 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1871 bcopy(keyval->wk_key + 12, &key_v[4], 1); 1872 key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_104; 1873 break; 1874 1875 case AR5K_KEYVAL_LENGTH_128: 1876 bcopy(keyval->wk_key, &key_v[0], 4); 1877 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1878 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1879 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1880 bcopy(keyval->wk_key + 12, &key_v[4], 4); 1881 key_v[5] = AR5K_AR5210_KEYTABLE_TYPE_128; 1882 break; 1883 1884 default: 1885 /* Unsupported key length (not WEP40/104/128) */ 1886 return (AH_FALSE); 1887 } 1888 1889 for (i = 0; i < nitems(key_v); i++) 1890 AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), key_v[i]); 1891 1892 return (ar5k_ar5210_set_key_lladdr(hal, entry, mac)); 1893 } 1894 1895 HAL_BOOL 1896 ar5k_ar5210_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, 1897 const u_int8_t *mac) 1898 { 1899 u_int32_t low_id, high_id; 1900 const u_int8_t *mac_v; 1901 1902 /* 1903 * Invalid entry (key table overflow) 1904 */ 1905 AR5K_ASSERT_ENTRY(entry, AR5K_AR5210_KEYTABLE_SIZE); 1906 1907 /* MAC may be NULL if it's a broadcast key */ 1908 mac_v = mac == NULL ? etherbroadcastaddr : mac; 1909 1910 low_id = AR5K_LOW_ID(mac_v); 1911 high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5210_KEYTABLE_VALID; 1912 1913 AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC0(entry), low_id); 1914 AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC1(entry), high_id); 1915 1916 return (AH_TRUE); 1917 } 1918 1919 HAL_BOOL 1920 ar5k_ar5210_softcrypto(struct ath_hal *hal, HAL_BOOL enable) 1921 { 1922 u_int32_t bits; 1923 int i; 1924 1925 bits = AR5K_AR5210_DIAG_SW_DIS_ENC | AR5K_AR5210_DIAG_SW_DIS_DEC; 1926 if (enable == AH_TRUE) { 1927 /* Disable the hardware crypto engine */ 1928 AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, bits); 1929 } else { 1930 /* Enable the hardware crypto engine */ 1931 AR5K_REG_DISABLE_BITS(AR5K_AR5210_DIAG_SW, bits); 1932 } 1933 1934 /* Reset the key cache */ 1935 for (i = 0; i < AR5K_AR5210_KEYTABLE_SIZE; i++) 1936 ar5k_ar5210_reset_key(hal, i); 1937 1938 return (AH_TRUE); 1939 } 1940 1941 /* 1942 * Power management functions 1943 */ 1944 1945 HAL_BOOL 1946 ar5k_ar5210_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, 1947 HAL_BOOL set_chip, u_int16_t sleep_duration) 1948 { 1949 u_int32_t staid; 1950 int i; 1951 1952 staid = AR5K_REG_READ(AR5K_AR5210_STA_ID1); 1953 1954 switch (mode) { 1955 case HAL_PM_AUTO: 1956 staid &= ~AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA; 1957 /* FALLTHROUGH */ 1958 case HAL_PM_NETWORK_SLEEP: 1959 if (set_chip == AH_TRUE) { 1960 AR5K_REG_WRITE(AR5K_AR5210_SCR, 1961 AR5K_AR5210_SCR_SLE | sleep_duration); 1962 } 1963 staid |= AR5K_AR5210_STA_ID1_PWR_SV; 1964 break; 1965 1966 case HAL_PM_FULL_SLEEP: 1967 if (set_chip == AH_TRUE) { 1968 AR5K_REG_WRITE(AR5K_AR5210_SCR, 1969 AR5K_AR5210_SCR_SLE_SLP); 1970 } 1971 staid |= AR5K_AR5210_STA_ID1_PWR_SV; 1972 break; 1973 1974 case HAL_PM_AWAKE: 1975 if (set_chip == AH_FALSE) 1976 goto commit; 1977 1978 AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_WAKE); 1979 1980 for (i = 5000; i > 0; i--) { 1981 /* Check if the AR5210 did wake up */ 1982 if ((AR5K_REG_READ(AR5K_AR5210_PCICFG) & 1983 AR5K_AR5210_PCICFG_SPWR_DN) == 0) 1984 break; 1985 1986 /* Wait a bit and retry */ 1987 AR5K_DELAY(200); 1988 AR5K_REG_WRITE(AR5K_AR5210_SCR, 1989 AR5K_AR5210_SCR_SLE_WAKE); 1990 } 1991 1992 /* Fail if the AR5210 didn't wake up */ 1993 if (i <= 0) 1994 return (AH_FALSE); 1995 1996 staid &= ~AR5K_AR5210_STA_ID1_PWR_SV; 1997 break; 1998 1999 default: 2000 return (AH_FALSE); 2001 } 2002 2003 commit: 2004 hal->ah_power_mode = mode; 2005 2006 AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, staid); 2007 2008 return (AH_TRUE); 2009 } 2010 2011 HAL_POWER_MODE 2012 ar5k_ar5210_get_power_mode(struct ath_hal *hal) 2013 { 2014 return (hal->ah_power_mode); 2015 } 2016 2017 HAL_BOOL 2018 ar5k_ar5210_query_pspoll_support(struct ath_hal *hal) 2019 { 2020 /* I think so, why not? */ 2021 return (AH_TRUE); 2022 } 2023 2024 HAL_BOOL 2025 ar5k_ar5210_init_pspoll(struct ath_hal *hal) 2026 { 2027 /* 2028 * Not used on the AR5210 2029 */ 2030 return (AH_FALSE); 2031 } 2032 2033 HAL_BOOL 2034 ar5k_ar5210_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, 2035 u_int16_t assoc_id) 2036 { 2037 AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, 2038 AR5K_AR5210_STA_ID1_NO_PSPOLL | 2039 AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); 2040 2041 return (AH_TRUE); 2042 } 2043 2044 HAL_BOOL 2045 ar5k_ar5210_disable_pspoll(struct ath_hal *hal) 2046 { 2047 AR5K_REG_ENABLE_BITS(AR5K_AR5210_STA_ID1, 2048 AR5K_AR5210_STA_ID1_NO_PSPOLL | 2049 AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA); 2050 2051 return (AH_TRUE); 2052 } 2053 2054 /* 2055 * Beacon functions 2056 */ 2057 2058 void 2059 ar5k_ar5210_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, 2060 u_int32_t interval) 2061 { 2062 u_int32_t timer1, timer2, timer3; 2063 2064 /* 2065 * Set the additional timers by mode 2066 */ 2067 switch (hal->ah_op_mode) { 2068 case HAL_M_STA: 2069 timer1 = 0xffffffff; 2070 timer2 = 0xffffffff; 2071 timer3 = 1; 2072 break; 2073 2074 default: 2075 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 2076 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 2077 timer3 = next_beacon + hal->ah_atim_window; 2078 break; 2079 } 2080 2081 /* 2082 * Enable all timers and set the beacon register 2083 * (next beacon, DMA beacon, software beacon, ATIM window time) 2084 */ 2085 AR5K_REG_WRITE(AR5K_AR5210_TIMER0, next_beacon); 2086 AR5K_REG_WRITE(AR5K_AR5210_TIMER1, timer1); 2087 AR5K_REG_WRITE(AR5K_AR5210_TIMER2, timer2); 2088 AR5K_REG_WRITE(AR5K_AR5210_TIMER3, timer3); 2089 2090 AR5K_REG_WRITE(AR5K_AR5210_BEACON, interval & 2091 (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_RESET_TSF | 2092 AR5K_AR5210_BEACON_EN)); 2093 } 2094 2095 void 2096 ar5k_ar5210_set_beacon_timers(struct ath_hal *hal, 2097 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, 2098 u_int32_t cfp_count) 2099 { 2100 u_int32_t cfp_period, next_cfp; 2101 2102 /* Return on an invalid beacon state */ 2103 if (state->bs_interval < 1) 2104 return; 2105 2106 /* 2107 * PCF support? 2108 */ 2109 if (state->bs_cfp_period > 0) { 2110 /* Enable CFP mode and set the CFP and timer registers */ 2111 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 2112 state->bs_interval; 2113 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 2114 state->bs_interval; 2115 2116 AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, 2117 AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA | 2118 AR5K_AR5210_STA_ID1_PCF); 2119 AR5K_REG_WRITE(AR5K_AR5210_CFP_PERIOD, cfp_period); 2120 AR5K_REG_WRITE(AR5K_AR5210_CFP_DUR, state->bs_cfp_max_duration); 2121 AR5K_REG_WRITE(AR5K_AR5210_TIMER2, 2122 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); 2123 } else { 2124 /* Disable PCF mode */ 2125 AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, 2126 AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA | 2127 AR5K_AR5210_STA_ID1_PCF); 2128 } 2129 2130 /* 2131 * Enable the beacon timer register 2132 */ 2133 AR5K_REG_WRITE(AR5K_AR5210_TIMER0, state->bs_next_beacon); 2134 2135 /* 2136 * Start the beacon timers 2137 */ 2138 AR5K_REG_WRITE(AR5K_AR5210_BEACON, 2139 (AR5K_REG_READ(AR5K_AR5210_BEACON) &~ 2140 (AR5K_AR5210_BEACON_PERIOD | AR5K_AR5210_BEACON_TIM)) | 2141 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 2142 AR5K_AR5210_BEACON_TIM) | 2143 AR5K_REG_SM(state->bs_interval, AR5K_AR5210_BEACON_PERIOD)); 2144 2145 /* 2146 * Write new beacon miss threshold, if it appears to be valid 2147 */ 2148 if (state->bs_bmiss_threshold <= 2149 (AR5K_AR5210_RSSI_THR_BM_THR >> AR5K_AR5210_RSSI_THR_BM_THR_S)) { 2150 AR5K_REG_WRITE_BITS(AR5K_AR5210_RSSI_THR, 2151 AR5K_AR5210_RSSI_THR_BM_THR, state->bs_bmiss_threshold); 2152 } 2153 } 2154 2155 void 2156 ar5k_ar5210_reset_beacon(struct ath_hal *hal) 2157 { 2158 /* 2159 * Disable beacon timer 2160 */ 2161 AR5K_REG_WRITE(AR5K_AR5210_TIMER0, 0); 2162 2163 /* 2164 * Disable some beacon register values 2165 */ 2166 AR5K_REG_DISABLE_BITS(AR5K_AR5210_STA_ID1, 2167 AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5210_STA_ID1_PCF); 2168 AR5K_REG_WRITE(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_PERIOD); 2169 } 2170 2171 HAL_BOOL 2172 ar5k_ar5210_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr) 2173 { 2174 int i; 2175 2176 /* 2177 * Wait for beaconn queue to be done 2178 */ 2179 for (i = (AR5K_TUNE_BEACON_INTERVAL / 2); i > 0 && 2180 (AR5K_REG_READ(AR5K_AR5210_BSR) & 2181 AR5K_AR5210_BSR_TXQ1F) != 0 && 2182 (AR5K_REG_READ(AR5K_AR5210_CR) & 2183 AR5K_AR5210_CR_TXE1) != 0; i--); 2184 2185 /* Timeout... */ 2186 if (i <= 0) { 2187 /* 2188 * Re-schedule the beacon queue 2189 */ 2190 AR5K_REG_WRITE(AR5K_AR5210_TXDP1, (u_int32_t)phys_addr); 2191 AR5K_REG_WRITE(AR5K_AR5210_BCR, 2192 AR5K_AR5210_BCR_TQ1V | AR5K_AR5210_BCR_BDMAE); 2193 2194 return (AH_FALSE); 2195 } 2196 2197 return (AH_TRUE); 2198 } 2199 2200 /* 2201 * Interrupt handling 2202 */ 2203 2204 HAL_BOOL 2205 ar5k_ar5210_is_intr_pending(struct ath_hal *hal) 2206 { 2207 return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE); 2208 } 2209 2210 HAL_BOOL 2211 ar5k_ar5210_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) 2212 { 2213 u_int32_t data; 2214 2215 if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == HAL_INT_NOCARD) { 2216 *interrupt_mask = data; 2217 return (AH_FALSE); 2218 } 2219 2220 /* 2221 * Get abstract interrupt mask (HAL-compatible) 2222 */ 2223 *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; 2224 2225 if (data & (AR5K_AR5210_ISR_RXOK | AR5K_AR5210_ISR_RXERR)) 2226 *interrupt_mask |= HAL_INT_RX; 2227 if (data & (AR5K_AR5210_ISR_TXOK | AR5K_AR5210_ISR_TXERR)) 2228 *interrupt_mask |= HAL_INT_TX; 2229 if (data & AR5K_AR5210_ISR_FATAL) 2230 *interrupt_mask |= HAL_INT_FATAL; 2231 2232 /* 2233 * Special interrupt handling (not caught by the driver) 2234 */ 2235 if (((*interrupt_mask) & AR5K_AR5210_ISR_RXPHY) && 2236 hal->ah_radar.r_enabled == AH_TRUE) 2237 ar5k_radar_alert(hal); 2238 2239 /* XXX BMISS interrupts may occur after association */ 2240 *interrupt_mask &= ~HAL_INT_BMISS; 2241 2242 return (AH_TRUE); 2243 } 2244 2245 u_int32_t 2246 ar5k_ar5210_get_intr(struct ath_hal *hal) 2247 { 2248 /* Return the interrupt mask stored previously */ 2249 return (hal->ah_imr); 2250 } 2251 2252 HAL_INT 2253 ar5k_ar5210_set_intr(struct ath_hal *hal, HAL_INT new_mask) 2254 { 2255 HAL_INT old_mask, int_mask; 2256 2257 /* 2258 * Disable card interrupts to prevent any race conditions 2259 * (they will be re-enabled afterwards). 2260 */ 2261 AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); 2262 2263 old_mask = hal->ah_imr; 2264 2265 /* 2266 * Add additional, chipset-dependent interrupt mask flags 2267 * and write them to the IMR (interrupt mask register). 2268 */ 2269 int_mask = new_mask & HAL_INT_COMMON; 2270 2271 if (new_mask & HAL_INT_RX) 2272 int_mask |= 2273 AR5K_AR5210_IMR_RXOK | 2274 AR5K_AR5210_IMR_RXERR | 2275 AR5K_AR5210_IMR_RXORN; 2276 2277 if (new_mask & HAL_INT_TX) 2278 int_mask |= 2279 AR5K_AR5210_IMR_TXOK | 2280 AR5K_AR5210_IMR_TXERR | 2281 AR5K_AR5210_IMR_TXURN; 2282 2283 AR5K_REG_WRITE(AR5K_AR5210_IMR, int_mask); 2284 2285 /* Store new interrupt mask */ 2286 hal->ah_imr = new_mask; 2287 2288 /* ..re-enable interrupts */ 2289 if (int_mask) { 2290 AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE); 2291 } 2292 2293 return (old_mask); 2294 } 2295 2296 /* 2297 * Misc internal functions 2298 */ 2299 2300 HAL_BOOL 2301 ar5k_ar5210_get_capabilities(struct ath_hal *hal) 2302 { 2303 /* Set number of supported TX queues */ 2304 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5210_TX_NUM_QUEUES; 2305 2306 /* 2307 * Set radio capabilities 2308 * (The AR5210 only supports the middle 5GHz band) 2309 */ 2310 hal->ah_capabilities.cap_range.range_5ghz_min = 5120; 2311 hal->ah_capabilities.cap_range.range_5ghz_max = 5430; 2312 hal->ah_capabilities.cap_range.range_2ghz_min = 0; 2313 hal->ah_capabilities.cap_range.range_2ghz_max = 0; 2314 2315 /* Set supported modes */ 2316 hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; 2317 2318 /* Set number of GPIO pins */ 2319 hal->ah_gpio_npins = AR5K_AR5210_NUM_GPIO; 2320 2321 return (AH_TRUE); 2322 } 2323 2324 void 2325 ar5k_ar5210_radar_alert(struct ath_hal *hal, HAL_BOOL enable) 2326 { 2327 /* 2328 * Set the RXPHY interrupt to be able to detect 2329 * possible radar activity. 2330 */ 2331 AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); 2332 2333 if (enable == AH_TRUE) { 2334 AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, 2335 AR5K_AR5210_IMR_RXPHY); 2336 } else { 2337 AR5K_REG_DISABLE_BITS(AR5K_AR5210_IMR, 2338 AR5K_AR5210_IMR_RXPHY); 2339 } 2340 2341 AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE); 2342 } 2343 2344 /* 2345 * EEPROM access functions 2346 */ 2347 2348 HAL_BOOL 2349 ar5k_ar5210_eeprom_is_busy(struct ath_hal *hal) 2350 { 2351 return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ? 2352 AH_TRUE : AH_FALSE); 2353 } 2354 2355 int 2356 ar5k_ar5210_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) 2357 { 2358 u_int32_t status, timeout; 2359 2360 /* Enable eeprom access */ 2361 AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE); 2362 2363 /* 2364 * Prime read pump 2365 */ 2366 (void)AR5K_REG_READ(AR5K_AR5210_EEPROM_BASE + (4 * offset)); 2367 2368 for (timeout = 10000; timeout > 0; timeout--) { 2369 AR5K_DELAY(1); 2370 status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS); 2371 if (status & AR5K_AR5210_EEPROM_STAT_RDDONE) { 2372 if (status & AR5K_AR5210_EEPROM_STAT_RDERR) 2373 return (EIO); 2374 *data = (u_int16_t) 2375 (AR5K_REG_READ(AR5K_AR5210_EEPROM_RDATA) & 0xffff); 2376 return (0); 2377 } 2378 } 2379 2380 return (ETIMEDOUT); 2381 } 2382 2383 int 2384 ar5k_ar5210_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) 2385 { 2386 u_int32_t status, timeout; 2387 2388 /* Enable eeprom access */ 2389 AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE); 2390 2391 /* 2392 * Prime write pump 2393 */ 2394 AR5K_REG_WRITE(AR5K_AR5210_EEPROM_BASE + (4 * offset), data); 2395 2396 for (timeout = 10000; timeout > 0; timeout--) { 2397 AR5K_DELAY(1); 2398 status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS); 2399 if (status & AR5K_AR5210_EEPROM_STAT_WRDONE) { 2400 if (status & AR5K_AR5210_EEPROM_STAT_WRERR) 2401 return (EIO); 2402 return (0); 2403 } 2404 } 2405 2406 return (ETIMEDOUT); 2407 } 2408 2409 HAL_BOOL 2410 ar5k_ar5210_set_txpower_limit(struct ath_hal *hal, u_int power) 2411 { 2412 /* Not implemented */ 2413 return (AH_FALSE); 2414 } 2415