1 /* $OpenBSD: ar5211.c,v 1.48 2016/01/12 09:28:09 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for the Atheros AR5001 Wireless LAN chipset 21 * (AR5211 + AR5111). 22 */ 23 24 #include <dev/ic/ar5xxx.h> 25 #include <dev/ic/ar5211reg.h> 26 #include <dev/ic/ar5211var.h> 27 28 HAL_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t); 29 HAL_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t); 30 u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, HAL_CHIP); 31 void ar5k_ar5211_fill(struct ath_hal *); 32 HAL_BOOL ar5k_ar5211_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int, 33 u_int); 34 35 /* 36 * Initial register setting for the AR5211 37 */ 38 static const struct ar5k_ini ar5211_ini[] = 39 AR5K_AR5211_INI; 40 static const struct ar5k_ar5211_ini_mode ar5211_mode[] = 41 AR5K_AR5211_INI_MODE; 42 static const struct ar5k_ar5211_ini_rf ar5211_rf[] = 43 AR5K_AR5211_INI_RF; 44 45 AR5K_HAL_FUNCTIONS(extern, ar5k_ar5211,); 46 47 void 48 ar5k_ar5211_fill(struct ath_hal *hal) 49 { 50 hal->ah_magic = AR5K_AR5211_MAGIC; 51 52 /* 53 * Init/Exit functions 54 */ 55 AR5K_HAL_FUNCTION(hal, ar5211, get_rate_table); 56 AR5K_HAL_FUNCTION(hal, ar5211, detach); 57 58 /* 59 * Reset functions 60 */ 61 AR5K_HAL_FUNCTION(hal, ar5211, reset); 62 AR5K_HAL_FUNCTION(hal, ar5211, set_opmode); 63 AR5K_HAL_FUNCTION(hal, ar5211, calibrate); 64 65 /* 66 * TX functions 67 */ 68 AR5K_HAL_FUNCTION(hal, ar5211, update_tx_triglevel); 69 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queue); 70 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queueprops); 71 AR5K_HAL_FUNCTION(hal, ar5211, release_tx_queue); 72 AR5K_HAL_FUNCTION(hal, ar5211, reset_tx_queue); 73 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_buf); 74 AR5K_HAL_FUNCTION(hal, ar5211, put_tx_buf); 75 AR5K_HAL_FUNCTION(hal, ar5211, tx_start); 76 AR5K_HAL_FUNCTION(hal, ar5211, stop_tx_dma); 77 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc); 78 AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc); 79 AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc); 80 AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc); 81 AR5K_HAL_FUNCTION(hal, ar5211, has_veol); 82 83 /* 84 * RX functions 85 */ 86 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_buf); 87 AR5K_HAL_FUNCTION(hal, ar5211, put_rx_buf); 88 AR5K_HAL_FUNCTION(hal, ar5211, start_rx); 89 AR5K_HAL_FUNCTION(hal, ar5211, stop_rx_dma); 90 AR5K_HAL_FUNCTION(hal, ar5211, start_rx_pcu); 91 AR5K_HAL_FUNCTION(hal, ar5211, stop_pcu_recv); 92 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filter); 93 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filterindex); 94 AR5K_HAL_FUNCTION(hal, ar5211, clear_mcast_filter_idx); 95 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_filter); 96 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_filter); 97 AR5K_HAL_FUNCTION(hal, ar5211, setup_rx_desc); 98 AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc); 99 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_signal); 100 101 /* 102 * Misc functions 103 */ 104 AR5K_HAL_FUNCTION(hal, ar5211, dump_state); 105 AR5K_HAL_FUNCTION(hal, ar5211, get_diag_state); 106 AR5K_HAL_FUNCTION(hal, ar5211, get_lladdr); 107 AR5K_HAL_FUNCTION(hal, ar5211, set_lladdr); 108 AR5K_HAL_FUNCTION(hal, ar5211, set_regdomain); 109 AR5K_HAL_FUNCTION(hal, ar5211, set_ledstate); 110 AR5K_HAL_FUNCTION(hal, ar5211, set_associd); 111 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_input); 112 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_output); 113 AR5K_HAL_FUNCTION(hal, ar5211, get_gpio); 114 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio); 115 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_intr); 116 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf32); 117 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf64); 118 AR5K_HAL_FUNCTION(hal, ar5211, reset_tsf); 119 AR5K_HAL_FUNCTION(hal, ar5211, get_regdomain); 120 AR5K_HAL_FUNCTION(hal, ar5211, detect_card_present); 121 AR5K_HAL_FUNCTION(hal, ar5211, update_mib_counters); 122 AR5K_HAL_FUNCTION(hal, ar5211, get_rf_gain); 123 AR5K_HAL_FUNCTION(hal, ar5211, set_slot_time); 124 AR5K_HAL_FUNCTION(hal, ar5211, get_slot_time); 125 AR5K_HAL_FUNCTION(hal, ar5211, set_ack_timeout); 126 AR5K_HAL_FUNCTION(hal, ar5211, get_ack_timeout); 127 AR5K_HAL_FUNCTION(hal, ar5211, set_cts_timeout); 128 AR5K_HAL_FUNCTION(hal, ar5211, get_cts_timeout); 129 130 /* 131 * Key table (WEP) functions 132 */ 133 AR5K_HAL_FUNCTION(hal, ar5211, is_cipher_supported); 134 AR5K_HAL_FUNCTION(hal, ar5211, get_keycache_size); 135 AR5K_HAL_FUNCTION(hal, ar5211, reset_key); 136 AR5K_HAL_FUNCTION(hal, ar5211, is_key_valid); 137 AR5K_HAL_FUNCTION(hal, ar5211, set_key); 138 AR5K_HAL_FUNCTION(hal, ar5211, set_key_lladdr); 139 AR5K_HAL_FUNCTION(hal, ar5211, softcrypto); 140 141 /* 142 * Power management functions 143 */ 144 AR5K_HAL_FUNCTION(hal, ar5211, set_power); 145 AR5K_HAL_FUNCTION(hal, ar5211, get_power_mode); 146 AR5K_HAL_FUNCTION(hal, ar5211, query_pspoll_support); 147 AR5K_HAL_FUNCTION(hal, ar5211, init_pspoll); 148 AR5K_HAL_FUNCTION(hal, ar5211, enable_pspoll); 149 AR5K_HAL_FUNCTION(hal, ar5211, disable_pspoll); 150 151 /* 152 * Beacon functions 153 */ 154 AR5K_HAL_FUNCTION(hal, ar5211, init_beacon); 155 AR5K_HAL_FUNCTION(hal, ar5211, set_beacon_timers); 156 AR5K_HAL_FUNCTION(hal, ar5211, reset_beacon); 157 AR5K_HAL_FUNCTION(hal, ar5211, wait_for_beacon); 158 159 /* 160 * Interrupt functions 161 */ 162 AR5K_HAL_FUNCTION(hal, ar5211, is_intr_pending); 163 AR5K_HAL_FUNCTION(hal, ar5211, get_isr); 164 AR5K_HAL_FUNCTION(hal, ar5211, get_intr); 165 AR5K_HAL_FUNCTION(hal, ar5211, set_intr); 166 167 /* 168 * Chipset functions (ar5k-specific, non-HAL) 169 */ 170 AR5K_HAL_FUNCTION(hal, ar5211, get_capabilities); 171 AR5K_HAL_FUNCTION(hal, ar5211, radar_alert); 172 173 /* 174 * EEPROM access 175 */ 176 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_is_busy); 177 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_read); 178 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_write); 179 180 /* 181 * Unused functions or functions not implemented 182 */ 183 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_queueprops); 184 AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending); 185 AR5K_HAL_FUNCTION(hal, ar5211, phy_disable); 186 AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit); 187 AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna); 188 AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna); 189 AR5K_HAL_FUNCTION(hal, ar5211, set_bssid_mask); 190 #ifdef notyet 191 AR5K_HAL_FUNCTION(hal, ar5211, set_capability); 192 AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event); 193 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue); 194 #endif 195 } 196 197 struct ath_hal * 198 ar5k_ar5211_attach(u_int16_t device, void *sc, bus_space_tag_t st, 199 bus_space_handle_t sh, int *status) 200 { 201 struct ath_hal *hal = (struct ath_hal*) sc; 202 u_int8_t mac[IEEE80211_ADDR_LEN]; 203 u_int32_t srev; 204 205 ar5k_ar5211_fill(hal); 206 207 /* Bring device out of sleep and reset its units */ 208 if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) 209 return (NULL); 210 211 /* Get MAC, PHY and RADIO revisions */ 212 srev = AR5K_REG_READ(AR5K_AR5211_SREV); 213 hal->ah_mac_srev = srev; 214 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5211_SREV_VER); 215 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5211_SREV_REV); 216 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) & 217 0x00ffffffff; 218 hal->ah_radio_5ghz_revision = 219 ar5k_ar5211_radio_revision(hal, HAL_CHIP_5GHZ); 220 hal->ah_radio_2ghz_revision = 0; 221 222 /* Identify the chipset (this has to be done in an early step) */ 223 hal->ah_version = AR5K_AR5211; 224 hal->ah_radio = AR5K_AR5111; 225 hal->ah_phy = AR5K_AR5211_PHY(0); 226 227 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 228 ar5k_ar5211_set_associd(hal, mac, 0, 0); 229 ar5k_ar5211_get_lladdr(hal, mac); 230 ar5k_ar5211_set_opmode(hal); 231 232 return (hal); 233 } 234 235 HAL_BOOL 236 ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val) 237 { 238 HAL_BOOL ret = AH_FALSE; 239 u_int32_t mask = val ? val : ~0; 240 241 /* Read-and-clear */ 242 AR5K_REG_READ(AR5K_AR5211_RXDP); 243 244 /* 245 * Reset the device and wait until success 246 */ 247 AR5K_REG_WRITE(AR5K_AR5211_RC, val); 248 249 /* Wait at least 128 PCI clocks */ 250 AR5K_DELAY(15); 251 252 val &= 253 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 254 255 mask &= 256 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 257 258 ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE); 259 260 /* 261 * Reset configuration register 262 */ 263 if ((val & AR5K_AR5211_RC_PCU) == 0) 264 AR5K_REG_WRITE(AR5K_AR5211_CFG, AR5K_AR5211_INIT_CFG); 265 266 return (ret); 267 } 268 269 HAL_BOOL 270 ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags) 271 { 272 u_int32_t turbo, mode, clock; 273 274 turbo = 0; 275 mode = 0; 276 clock = 0; 277 278 /* 279 * Get channel mode flags 280 */ 281 282 if (flags & IEEE80211_CHAN_2GHZ) { 283 mode |= AR5K_AR5211_PHY_MODE_FREQ_2GHZ; 284 clock |= AR5K_AR5211_PHY_PLL_44MHZ; 285 } else if (flags & IEEE80211_CHAN_5GHZ) { 286 mode |= AR5K_AR5211_PHY_MODE_FREQ_5GHZ; 287 clock |= AR5K_AR5211_PHY_PLL_40MHZ; 288 } else { 289 AR5K_PRINT("invalid radio frequency mode\n"); 290 return (AH_FALSE); 291 } 292 293 if ((flags & IEEE80211_CHAN_CCK) || 294 (flags & IEEE80211_CHAN_DYN)) { 295 /* Dynamic OFDM/CCK is not supported by the AR5211 */ 296 mode |= AR5K_AR5211_PHY_MODE_MOD_CCK; 297 } else if (flags & IEEE80211_CHAN_OFDM) { 298 mode |= AR5K_AR5211_PHY_MODE_MOD_OFDM; 299 } else { 300 AR5K_PRINT("invalid radio frequency mode\n"); 301 return (AH_FALSE); 302 } 303 304 /* 305 * Reset and wakeup the device 306 */ 307 308 /* ...reset chipset and PCI device */ 309 if (ar5k_ar5211_nic_reset(hal, 310 AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == AH_FALSE) { 311 AR5K_PRINT("failed to reset the AR5211 + PCI chipset\n"); 312 return (AH_FALSE); 313 } 314 315 /* ...wakeup */ 316 if (ar5k_ar5211_set_power(hal, 317 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 318 AR5K_PRINT("failed to resume the AR5211 (again)\n"); 319 return (AH_FALSE); 320 } 321 322 /* ...final warm reset */ 323 if (ar5k_ar5211_nic_reset(hal, 0) == AH_FALSE) { 324 AR5K_PRINT("failed to warm reset the AR5211\n"); 325 return (AH_FALSE); 326 } 327 328 /* ...set the PHY operating mode */ 329 AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock); 330 AR5K_DELAY(300); 331 332 AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode); 333 AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo); 334 335 return (AH_TRUE); 336 } 337 338 u_int16_t 339 ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip) 340 { 341 int i; 342 u_int32_t srev; 343 u_int16_t ret; 344 345 /* 346 * Set the radio chip access register 347 */ 348 switch (chip) { 349 case HAL_CHIP_2GHZ: 350 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ); 351 break; 352 case HAL_CHIP_5GHZ: 353 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 354 break; 355 default: 356 return (0); 357 } 358 359 AR5K_DELAY(2000); 360 361 /* ...wait until PHY is ready and read the selected radio revision */ 362 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16); 363 364 for (i = 0; i < 8; i++) 365 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000); 366 srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff; 367 368 ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); 369 370 /* Reset to the 5GHz mode */ 371 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 372 373 return (ret); 374 } 375 376 const HAL_RATE_TABLE * 377 ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode) 378 { 379 switch (mode) { 380 case HAL_MODE_11A: 381 return (&hal->ah_rt_11a); 382 case HAL_MODE_11B: 383 return (&hal->ah_rt_11b); 384 case HAL_MODE_11G: 385 case HAL_MODE_PUREG: 386 return (&hal->ah_rt_11g); 387 default: 388 return (NULL); 389 } 390 391 return (NULL); 392 } 393 394 void 395 ar5k_ar5211_detach(struct ath_hal *hal) 396 { 397 /* 398 * Free HAL structure, assume interrupts are down 399 */ 400 free(hal, M_DEVBUF, 0); 401 } 402 403 HAL_BOOL 404 ar5k_ar5211_phy_disable(struct ath_hal *hal) 405 { 406 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE); 407 return (AH_TRUE); 408 } 409 410 HAL_BOOL 411 ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, 412 HAL_BOOL change_channel, HAL_STATUS *status) 413 { 414 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 415 u_int8_t mac[IEEE80211_ADDR_LEN]; 416 u_int32_t data, s_seq, s_ant, s_led[3]; 417 u_int i, mode, freq, ee_mode, ant[2]; 418 419 /* 420 * Save some registers before a reset 421 */ 422 if (change_channel == AH_TRUE) { 423 s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0)); 424 s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 425 } else { 426 s_seq = 0; 427 s_ant = 1; 428 } 429 430 s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) & 431 AR5K_AR5211_PCICFG_LEDSTATE; 432 s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR); 433 s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO); 434 435 if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) 436 return (AH_FALSE); 437 438 /* 439 * Initialize operating mode 440 */ 441 hal->ah_op_mode = op_mode; 442 443 switch (channel->c_channel_flags & CHANNEL_MODES) { 444 case CHANNEL_A: 445 mode = AR5K_INI_VAL_11A; 446 freq = AR5K_INI_RFGAIN_5GHZ; 447 ee_mode = AR5K_EEPROM_MODE_11A; 448 break; 449 case CHANNEL_B: 450 mode = AR5K_INI_VAL_11B; 451 freq = AR5K_INI_RFGAIN_2GHZ; 452 ee_mode = AR5K_EEPROM_MODE_11B; 453 break; 454 case CHANNEL_G: 455 case CHANNEL_PUREG: 456 mode = AR5K_INI_VAL_11G; 457 freq = AR5K_INI_RFGAIN_2GHZ; 458 ee_mode = AR5K_EEPROM_MODE_11G; 459 break; 460 default: 461 AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); 462 return (AH_FALSE); 463 } 464 465 /* PHY access enable */ 466 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 467 468 /* 469 * Write initial RF registers 470 */ 471 if (ar5k_ar5211_rfregs(hal, channel, freq, ee_mode) == AH_FALSE) 472 return (AH_FALSE); 473 474 /* 475 * Write initial mode settings 476 */ 477 for (i = 0; i < nitems(ar5211_mode); i++) { 478 AR5K_REG_WAIT(i); 479 AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, 480 ar5211_mode[i].mode_value[mode]); 481 } 482 483 /* 484 * Write initial register settings 485 */ 486 for (i = 0; i < nitems(ar5211_ini); i++) { 487 if (change_channel == AH_TRUE && 488 ar5211_ini[i].ini_register >= AR5K_AR5211_PCU_MIN && 489 ar5211_ini[i].ini_register <= AR5K_AR5211_PCU_MAX) 490 continue; 491 492 AR5K_REG_WAIT(i); 493 AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, 494 ar5211_ini[i].ini_value); 495 } 496 497 /* 498 * Write initial RF gain settings 499 */ 500 if (ar5k_rfgain(hal, freq) == AH_FALSE) 501 return (AH_FALSE); 502 503 AR5K_DELAY(1000); 504 505 /* 506 * Configure additional registers 507 */ 508 509 if (hal->ah_radio == AR5K_AR5111) { 510 if (channel->c_channel_flags & IEEE80211_CHAN_B) 511 AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG, 512 AR5K_AR5211_TXCFG_B_MODE); 513 else 514 AR5K_REG_DISABLE_BITS(AR5K_AR5211_TXCFG, 515 AR5K_AR5211_TXCFG_B_MODE); 516 } 517 518 /* Set antenna mode */ 519 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44), 520 hal->ah_antenna[ee_mode][0], 0xfffffc06); 521 522 if (freq == AR5K_INI_RFGAIN_2GHZ) 523 ant[0] = ant[1] = HAL_ANT_FIXED_B; 524 else 525 ant[0] = ant[1] = HAL_ANT_FIXED_A; 526 527 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0, 528 hal->ah_antenna[ee_mode][ant[0]]); 529 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1, 530 hal->ah_antenna[ee_mode][ant[1]]); 531 532 /* Commit values from EEPROM */ 533 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_FC, 534 AR5K_AR5211_PHY_FC_TX_CLIP, ee->ee_tx_clip); 535 536 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a), 537 AR5K_AR5211_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); 538 539 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x11), 540 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); 541 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x12), 542 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); 543 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x14), 544 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | 545 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); 546 547 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d), 548 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 549 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 550 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 551 (ee->ee_tx_frm2xpa_enable[ee_mode])); 552 553 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x0a), 554 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); 555 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x19), 556 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); 557 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x49), 4, 0xffffff01); 558 559 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 560 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 561 (ee->ee_i_cal[ee_mode] << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S) | 562 ee->ee_q_cal[ee_mode]); 563 564 /* 565 * Restore saved values 566 */ 567 AR5K_REG_WRITE(AR5K_AR5211_DCU_SEQNUM(0), s_seq); 568 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, s_ant); 569 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, s_led[0]); 570 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, s_led[1]); 571 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, s_led[2]); 572 573 /* 574 * Misc 575 */ 576 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 577 ar5k_ar5211_set_associd(hal, mac, 0, 0); 578 ar5k_ar5211_set_opmode(hal); 579 AR5K_REG_WRITE(AR5K_AR5211_PISR, 0xffffffff); 580 AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES); 581 582 /* 583 * Set Rx/Tx DMA Configuration 584 */ 585 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_SDMAMR, 586 AR5K_AR5211_DMASIZE_512B | AR5K_AR5211_TXCFG_DMASIZE); 587 AR5K_REG_WRITE_BITS(AR5K_AR5211_RXCFG, AR5K_AR5211_RXCFG_SDMAMW, 588 AR5K_AR5211_DMASIZE_512B); 589 590 /* 591 * Set channel and calibrate the PHY 592 */ 593 if (ar5k_channel(hal, channel) == AH_FALSE) 594 return (AH_FALSE); 595 596 /* 597 * Enable the PHY and wait until completion 598 */ 599 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_ENABLE); 600 601 data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) & 602 AR5K_AR5211_PHY_RX_DELAY_M; 603 data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? 604 ((data << 2) / 22) : (data / 10); 605 606 AR5K_DELAY(100 + data); 607 608 /* 609 * Start calibration 610 */ 611 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 612 AR5K_AR5211_PHY_AGCCTL_NF | 613 AR5K_AR5211_PHY_AGCCTL_CAL); 614 615 if (channel->c_channel_flags & IEEE80211_CHAN_B) { 616 hal->ah_calibration = AH_FALSE; 617 } else { 618 hal->ah_calibration = AH_TRUE; 619 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_IQ, 620 AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX, 15); 621 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 622 AR5K_AR5211_PHY_IQ_RUN); 623 } 624 625 /* 626 * Reset queues and start beacon timers at the end of the reset routine 627 */ 628 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { 629 AR5K_REG_WRITE_Q(AR5K_AR5211_DCU_QCUMASK(i), i); 630 if (ar5k_ar5211_reset_tx_queue(hal, i) == AH_FALSE) { 631 AR5K_PRINTF("failed to reset TX queue #%d\n", i); 632 return (AH_FALSE); 633 } 634 } 635 636 /* Pre-enable interrupts */ 637 ar5k_ar5211_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); 638 639 /* 640 * Set RF kill flags if supported by the device (read from the EEPROM) 641 */ 642 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { 643 ar5k_ar5211_set_gpio_input(hal, 0); 644 if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0) 645 ar5k_ar5211_set_gpio_intr(hal, 0, 1); 646 else 647 ar5k_ar5211_set_gpio_intr(hal, 0, 0); 648 } 649 650 /* 651 * Disable beacons and reset the register 652 */ 653 AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON, 654 AR5K_AR5211_BEACON_ENABLE | AR5K_AR5211_BEACON_RESET_TSF); 655 656 return (AH_TRUE); 657 } 658 659 void 660 ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant) 661 { 662 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant); 663 } 664 665 u_int 666 ar5k_ar5211_get_def_antenna(struct ath_hal *hal) 667 { 668 return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 669 } 670 671 void 672 ar5k_ar5211_set_opmode(struct ath_hal *hal) 673 { 674 u_int32_t pcu_reg, low_id, high_id; 675 676 pcu_reg = 0; 677 678 switch (hal->ah_op_mode) { 679 #ifndef IEEE80211_STA_ONLY 680 case IEEE80211_M_IBSS: 681 pcu_reg |= AR5K_AR5211_STA_ID1_ADHOC | 682 AR5K_AR5211_STA_ID1_DESC_ANTENNA; 683 break; 684 685 case IEEE80211_M_HOSTAP: 686 pcu_reg |= AR5K_AR5211_STA_ID1_AP | 687 AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA; 688 break; 689 #endif 690 691 case IEEE80211_M_STA: 692 case IEEE80211_M_MONITOR: 693 pcu_reg |= AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 694 break; 695 696 default: 697 return; 698 } 699 700 /* 701 * Set PCU registers 702 */ 703 low_id = AR5K_LOW_ID(hal->ah_sta_id); 704 high_id = AR5K_HIGH_ID(hal->ah_sta_id); 705 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 706 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, pcu_reg | high_id); 707 708 return; 709 } 710 711 HAL_BOOL 712 ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 713 { 714 u_int32_t i_pwr, q_pwr; 715 int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; 716 717 if (hal->ah_calibration == AH_FALSE || 718 AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN) 719 goto done; 720 721 hal->ah_calibration = AH_FALSE; 722 723 iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR); 724 i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I); 725 q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q); 726 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 727 q_coffd = q_pwr >> 6; 728 729 if (i_coffd == 0 || q_coffd == 0) 730 goto done; 731 732 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 733 q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; 734 735 /* Commit new IQ value */ 736 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 737 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 738 ((u_int32_t)q_coff) | 739 ((u_int32_t)i_coff << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S)); 740 741 done: 742 /* Start noise floor calibration */ 743 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 744 AR5K_AR5211_PHY_AGCCTL_NF); 745 746 return (AH_TRUE); 747 } 748 749 /* 750 * Transmit functions 751 */ 752 753 HAL_BOOL 754 ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) 755 { 756 u_int32_t trigger_level, imr; 757 HAL_BOOL status = AH_FALSE; 758 759 /* 760 * Disable interrupts by setting the mask 761 */ 762 imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); 763 764 trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG), 765 AR5K_AR5211_TXCFG_TXFULL); 766 767 if (increase == AH_FALSE) { 768 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 769 goto done; 770 } else 771 trigger_level += 772 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 773 774 /* 775 * Update trigger level on success 776 */ 777 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, 778 AR5K_AR5211_TXCFG_TXFULL, trigger_level); 779 status = AH_TRUE; 780 781 done: 782 /* 783 * Restore interrupt mask 784 */ 785 ar5k_ar5211_set_intr(hal, imr); 786 787 return (status); 788 } 789 790 int 791 ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, 792 const HAL_TXQ_INFO *queue_info) 793 { 794 u_int queue; 795 796 /* 797 * Get queue by type 798 */ 799 if (queue_type == HAL_TX_QUEUE_DATA) { 800 for (queue = HAL_TX_QUEUE_ID_DATA_MIN; 801 hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; 802 queue++) 803 if (queue > HAL_TX_QUEUE_ID_DATA_MAX) 804 return (-1); 805 } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { 806 queue = HAL_TX_QUEUE_ID_PSPOLL; 807 } else if (queue_type == HAL_TX_QUEUE_BEACON) { 808 queue = HAL_TX_QUEUE_ID_BEACON; 809 } else if (queue_type == HAL_TX_QUEUE_CAB) { 810 queue = HAL_TX_QUEUE_ID_CAB; 811 } else 812 return (-1); 813 814 /* 815 * Setup internal queue structure 816 */ 817 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 818 hal->ah_txq[queue].tqi_type = queue_type; 819 820 if (queue_info != NULL) { 821 if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info) 822 != AH_TRUE) 823 return (-1); 824 } 825 826 AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); 827 828 return (queue); 829 } 830 831 HAL_BOOL 832 ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue, 833 const HAL_TXQ_INFO *queue_info) 834 { 835 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 836 837 if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) 838 return (AH_FALSE); 839 840 bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 841 842 if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && 843 (queue_info->tqi_subtype >= HAL_WME_AC_VI) && 844 (queue_info->tqi_subtype <= HAL_WME_UPSD)) 845 hal->ah_txq[queue].tqi_flags |= 846 AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 847 848 return (AH_TRUE); 849 } 850 851 HAL_BOOL 852 ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue, 853 HAL_TXQ_INFO *queue_info) 854 { 855 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 856 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO)); 857 return (AH_TRUE); 858 } 859 860 HAL_BOOL 861 ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue) 862 { 863 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 864 865 /* This queue will be skipped in further operations */ 866 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; 867 AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); 868 869 return (AH_FALSE); 870 } 871 872 HAL_BOOL 873 ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue) 874 { 875 u_int32_t cw_min, cw_max, retry_lg, retry_sh; 876 struct ieee80211_channel *channel = (struct ieee80211_channel*) 877 &hal->ah_current_channel; 878 HAL_TXQ_INFO *tq; 879 880 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 881 882 tq = &hal->ah_txq[queue]; 883 884 if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) 885 return (AH_TRUE); 886 887 /* 888 * Set registers by channel mode 889 */ 890 if (IEEE80211_IS_CHAN_B(channel)) { 891 hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; 892 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; 893 hal->ah_aifs = AR5K_TUNE_AIFS_11B; 894 } else { 895 hal->ah_cw_min = AR5K_TUNE_CWMIN; 896 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; 897 hal->ah_aifs = AR5K_TUNE_AIFS; 898 } 899 900 /* 901 * Set retry limits 902 */ 903 if (hal->ah_software_retry == AH_TRUE) { 904 /* XXX Need to test this */ 905 retry_lg = hal->ah_limit_tx_retries; 906 retry_sh = retry_lg = 907 retry_lg > AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY ? 908 AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY : retry_lg; 909 } else { 910 retry_lg = AR5K_INIT_LG_RETRY; 911 retry_sh = AR5K_INIT_SH_RETRY; 912 } 913 914 AR5K_REG_WRITE(AR5K_AR5211_DCU_RETRY_LMT(queue), 915 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 916 AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY) | 917 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 918 AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY) | 919 AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) | 920 AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY)); 921 922 /* 923 * Set initial content window (cw_min/cw_max) 924 */ 925 cw_min = 1; 926 while (cw_min < hal->ah_cw_min) 927 cw_min = (cw_min << 1) | 1; 928 929 cw_min = tq->tqi_cw_min < 0 ? 930 (cw_min >> (-tq->tqi_cw_min)) : 931 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 932 cw_max = tq->tqi_cw_max < 0 ? 933 (cw_max >> (-tq->tqi_cw_max)) : 934 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 935 936 AR5K_REG_WRITE(AR5K_AR5211_DCU_LCL_IFS(queue), 937 AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) | 938 AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) | 939 AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, 940 AR5K_AR5211_DCU_LCL_IFS_AIFS)); 941 942 /* 943 * Set misc registers 944 */ 945 AR5K_REG_WRITE(AR5K_AR5211_QCU_MISC(queue), 946 AR5K_AR5211_QCU_MISC_DCU_EARLY); 947 948 if (tq->tqi_cbr_period) { 949 AR5K_REG_WRITE(AR5K_AR5211_QCU_CBRCFG(queue), 950 AR5K_REG_SM(tq->tqi_cbr_period, 951 AR5K_AR5211_QCU_CBRCFG_INTVAL) | 952 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 953 AR5K_AR5211_QCU_CBRCFG_ORN_THRES)); 954 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 955 AR5K_AR5211_QCU_MISC_FRSHED_CBR); 956 if (tq->tqi_cbr_overflow_limit) 957 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 958 AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE); 959 } 960 961 if (tq->tqi_ready_time) { 962 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 963 AR5K_REG_SM(tq->tqi_ready_time, 964 AR5K_AR5211_QCU_RDYTIMECFG_INTVAL) | 965 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 966 } 967 968 if (tq->tqi_burst_time) { 969 AR5K_REG_WRITE(AR5K_AR5211_DCU_CHAN_TIME(queue), 970 AR5K_REG_SM(tq->tqi_burst_time, 971 AR5K_AR5211_DCU_CHAN_TIME_DUR) | 972 AR5K_AR5211_DCU_CHAN_TIME_ENABLE); 973 974 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { 975 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 976 AR5K_AR5211_QCU_MISC_TXE); 977 } 978 } 979 980 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { 981 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 982 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS); 983 } 984 985 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 986 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 987 AR5K_AR5211_DCU_MISC_BACKOFF_FRAG); 988 } 989 990 /* 991 * Set registers by queue type 992 */ 993 switch (tq->tqi_type) { 994 case HAL_TX_QUEUE_BEACON: 995 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 996 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 997 AR5K_AR5211_QCU_MISC_CBREXP_BCN | 998 AR5K_AR5211_QCU_MISC_BCN_ENABLE); 999 1000 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1001 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1002 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL) | 1003 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS | 1004 AR5K_AR5211_DCU_MISC_BCN_ENABLE); 1005 1006 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 1007 ((AR5K_TUNE_BEACON_INTERVAL - 1008 (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - 1009 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | 1010 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 1011 break; 1012 1013 case HAL_TX_QUEUE_CAB: 1014 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1015 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 1016 AR5K_AR5211_QCU_MISC_CBREXP | 1017 AR5K_AR5211_QCU_MISC_CBREXP_BCN); 1018 1019 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1020 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1021 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL)); 1022 break; 1023 1024 case HAL_TX_QUEUE_PSPOLL: 1025 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1026 AR5K_AR5211_QCU_MISC_CBREXP); 1027 break; 1028 1029 case HAL_TX_QUEUE_DATA: 1030 default: 1031 break; 1032 } 1033 1034 /* 1035 * Enable tx queue in the secondary interrupt mask registers 1036 */ 1037 AR5K_REG_WRITE(AR5K_AR5211_SIMR0, 1038 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) | 1039 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC)); 1040 AR5K_REG_WRITE(AR5K_AR5211_SIMR1, 1041 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR)); 1042 AR5K_REG_WRITE(AR5K_AR5211_SIMR2, 1043 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN)); 1044 1045 return (AH_TRUE); 1046 } 1047 1048 u_int32_t 1049 ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue) 1050 { 1051 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1052 1053 /* 1054 * Get the transmit queue descriptor pointer from the selected queue 1055 */ 1056 return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue))); 1057 } 1058 1059 HAL_BOOL 1060 ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) 1061 { 1062 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1063 1064 /* 1065 * Set the transmit queue descriptor pointer for the selected queue 1066 * (this won't work if the queue is still active) 1067 */ 1068 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue)) 1069 return (AH_FALSE); 1070 1071 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr); 1072 1073 return (AH_TRUE); 1074 } 1075 1076 u_int32_t 1077 ar5k_ar5211_num_tx_pending(struct ath_hal *hal, u_int queue) 1078 { 1079 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1080 return (AR5K_AR5211_QCU_STS(queue) & AR5K_AR5211_QCU_STS_FRMPENDCNT); 1081 } 1082 1083 HAL_BOOL 1084 ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue) 1085 { 1086 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1087 1088 /* Return if queue is disabled */ 1089 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXD, queue)) 1090 return (AH_FALSE); 1091 1092 /* Start queue */ 1093 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXE, queue); 1094 1095 return (AH_TRUE); 1096 } 1097 1098 HAL_BOOL 1099 ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue) 1100 { 1101 int i = 100, pending; 1102 1103 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1104 1105 /* 1106 * Schedule TX disable and wait until queue is empty 1107 */ 1108 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue); 1109 1110 do { 1111 pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) & 1112 AR5K_AR5211_QCU_STS_FRMPENDCNT; 1113 delay(100); 1114 } while (--i && pending); 1115 1116 /* Clear register */ 1117 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0); 1118 1119 return (AH_TRUE); 1120 } 1121 1122 HAL_BOOL 1123 ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1124 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, 1125 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, 1126 u_int flags, u_int rtscts_rate, u_int rtscts_duration) 1127 { 1128 struct ar5k_ar5211_tx_desc *tx_desc; 1129 1130 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1131 1132 /* 1133 * Validate input 1134 */ 1135 if (tx_tries0 == 0) 1136 return (AH_FALSE); 1137 1138 if ((tx_desc->tx_control_0 = (packet_length & 1139 AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) 1140 return (AH_FALSE); 1141 1142 tx_desc->tx_control_0 |= 1143 AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | 1144 AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); 1145 tx_desc->tx_control_1 = 1146 AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); 1147 1148 #define _TX_FLAGS(_c, _flag) \ 1149 if (flags & HAL_TXDESC_##_flag) \ 1150 tx_desc->tx_control_##_c |= \ 1151 AR5K_AR5211_DESC_TX_CTL##_c##_##_flag 1152 1153 _TX_FLAGS(0, CLRDMASK); 1154 _TX_FLAGS(0, VEOL); 1155 _TX_FLAGS(0, INTREQ); 1156 _TX_FLAGS(0, RTSENA); 1157 _TX_FLAGS(1, NOACK); 1158 1159 #undef _TX_FLAGS 1160 1161 /* 1162 * WEP crap 1163 */ 1164 if (key_index != HAL_TXKEYIX_INVALID) { 1165 tx_desc->tx_control_0 |= 1166 AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; 1167 tx_desc->tx_control_1 |= 1168 AR5K_REG_SM(key_index, 1169 AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); 1170 } 1171 1172 return (AH_TRUE); 1173 } 1174 1175 HAL_BOOL 1176 ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1177 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment) 1178 { 1179 struct ar5k_ar5211_tx_desc *tx_desc; 1180 1181 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1182 1183 /* Clear status descriptor */ 1184 bzero(desc->ds_hw, sizeof(desc->ds_hw)); 1185 1186 /* Validate segment length and initialize the descriptor */ 1187 if (segment_length & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) 1188 return (AH_FALSE); 1189 tx_desc->tx_control_1 = 1190 #if 0 1191 (tx_desc->tx_control_1 & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) | 1192 #endif 1193 segment_length; 1194 1195 if (first_segment != AH_TRUE) 1196 tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; 1197 1198 if (last_segment != AH_TRUE) 1199 tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; 1200 1201 return (AH_TRUE); 1202 } 1203 1204 HAL_BOOL 1205 ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, 1206 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 1207 u_int tx_rate3, u_int tx_tries3) 1208 { 1209 return (AH_FALSE); 1210 } 1211 1212 HAL_STATUS 1213 ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) 1214 { 1215 struct ar5k_ar5211_tx_status *tx_status; 1216 struct ar5k_ar5211_tx_desc *tx_desc; 1217 1218 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1219 tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0]; 1220 1221 /* No frame has been send or error */ 1222 if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0) 1223 return (HAL_EINPROGRESS); 1224 1225 /* 1226 * Get descriptor status 1227 */ 1228 desc->ds_us.tx.ts_tstamp = 1229 AR5K_REG_MS(tx_status->tx_status_0, 1230 AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP); 1231 desc->ds_us.tx.ts_shortretry = 1232 AR5K_REG_MS(tx_status->tx_status_0, 1233 AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT); 1234 desc->ds_us.tx.ts_longretry = 1235 AR5K_REG_MS(tx_status->tx_status_0, 1236 AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT); 1237 desc->ds_us.tx.ts_seqnum = 1238 AR5K_REG_MS(tx_status->tx_status_1, 1239 AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM); 1240 desc->ds_us.tx.ts_rssi = 1241 AR5K_REG_MS(tx_status->tx_status_1, 1242 AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 1243 desc->ds_us.tx.ts_antenna = 1; 1244 desc->ds_us.tx.ts_status = 0; 1245 desc->ds_us.tx.ts_rate = 1246 AR5K_REG_MS(tx_desc->tx_control_0, 1247 AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE); 1248 1249 if ((tx_status->tx_status_0 & 1250 AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { 1251 if (tx_status->tx_status_0 & 1252 AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 1253 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; 1254 1255 if (tx_status->tx_status_0 & 1256 AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN) 1257 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; 1258 1259 if (tx_status->tx_status_0 & 1260 AR5K_AR5211_DESC_TX_STATUS0_FILTERED) 1261 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; 1262 } 1263 1264 return (HAL_OK); 1265 } 1266 1267 HAL_BOOL 1268 ar5k_ar5211_has_veol(struct ath_hal *hal) 1269 { 1270 return (AH_TRUE); 1271 } 1272 1273 /* 1274 * Receive functions 1275 */ 1276 1277 u_int32_t 1278 ar5k_ar5211_get_rx_buf(struct ath_hal *hal) 1279 { 1280 return (AR5K_REG_READ(AR5K_AR5211_RXDP)); 1281 } 1282 1283 void 1284 ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) 1285 { 1286 AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr); 1287 } 1288 1289 void 1290 ar5k_ar5211_start_rx(struct ath_hal *hal) 1291 { 1292 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE); 1293 } 1294 1295 HAL_BOOL 1296 ar5k_ar5211_stop_rx_dma(struct ath_hal *hal) 1297 { 1298 int i; 1299 1300 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXD); 1301 1302 /* 1303 * It may take some time to disable the DMA receive unit 1304 */ 1305 for (i = 2000; 1306 i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0; 1307 i--) 1308 AR5K_DELAY(10); 1309 1310 return (i > 0 ? AH_TRUE : AH_FALSE); 1311 } 1312 1313 void 1314 ar5k_ar5211_start_rx_pcu(struct ath_hal *hal) 1315 { 1316 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1317 } 1318 1319 void 1320 ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal) 1321 { 1322 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1323 } 1324 1325 void 1326 ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, 1327 u_int32_t filter1) 1328 { 1329 /* Set the multicat filter */ 1330 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0); 1331 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1); 1332 } 1333 1334 HAL_BOOL 1335 ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) 1336 { 1337 if (index >= 64) { 1338 return (AH_FALSE); 1339 } else if (index >= 32) { 1340 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1341 (1 << (index - 32))); 1342 } else { 1343 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1344 (1 << index)); 1345 } 1346 1347 return (AH_TRUE); 1348 } 1349 1350 HAL_BOOL 1351 ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) 1352 { 1353 1354 if (index >= 64) { 1355 return (AH_FALSE); 1356 } else if (index >= 32) { 1357 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1358 (1 << (index - 32))); 1359 } else { 1360 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1361 (1 << index)); 1362 } 1363 1364 return (AH_TRUE); 1365 } 1366 1367 u_int32_t 1368 ar5k_ar5211_get_rx_filter(struct ath_hal *hal) 1369 { 1370 return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER)); 1371 } 1372 1373 void 1374 ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter) 1375 { 1376 AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter); 1377 } 1378 1379 HAL_BOOL 1380 ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1381 u_int32_t size, u_int flags) 1382 { 1383 struct ar5k_ar5211_rx_desc *rx_desc; 1384 1385 rx_desc = (struct ar5k_ar5211_rx_desc*)&desc->ds_ctl0; 1386 1387 if ((rx_desc->rx_control_1 = (size & 1388 AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size) 1389 return (AH_FALSE); 1390 1391 if (flags & HAL_RXDESC_INTREQ) 1392 rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ; 1393 1394 return (AH_TRUE); 1395 } 1396 1397 HAL_STATUS 1398 ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1399 u_int32_t phys_addr, struct ath_desc *next) 1400 { 1401 struct ar5k_ar5211_rx_status *rx_status; 1402 1403 rx_status = (struct ar5k_ar5211_rx_status*)&desc->ds_hw[0]; 1404 1405 /* No frame received / not ready */ 1406 if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) 1407 return (HAL_EINPROGRESS); 1408 1409 /* 1410 * Frame receive status 1411 */ 1412 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 1413 AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN; 1414 desc->ds_us.rx.rs_rssi = 1415 AR5K_REG_MS(rx_status->rx_status_0, 1416 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL); 1417 desc->ds_us.rx.rs_rate = 1418 AR5K_REG_MS(rx_status->rx_status_0, 1419 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE); 1420 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 1421 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA; 1422 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 1423 AR5K_AR5211_DESC_RX_STATUS0_MORE; 1424 desc->ds_us.rx.rs_tstamp = 1425 AR5K_REG_MS(rx_status->rx_status_1, 1426 AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); 1427 desc->ds_us.rx.rs_status = 0; 1428 1429 /* 1430 * Key table status 1431 */ 1432 if (rx_status->rx_status_1 & 1433 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) { 1434 desc->ds_us.rx.rs_keyix = 1435 AR5K_REG_MS(rx_status->rx_status_1, 1436 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); 1437 } else { 1438 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; 1439 } 1440 1441 /* 1442 * Receive/descriptor errors 1443 */ 1444 if ((rx_status->rx_status_1 & 1445 AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { 1446 if (rx_status->rx_status_1 & 1447 AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) 1448 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; 1449 1450 if (rx_status->rx_status_1 & 1451 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { 1452 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; 1453 desc->ds_us.rx.rs_phyerr = 1454 AR5K_REG_MS(rx_status->rx_status_1, 1455 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); 1456 } 1457 1458 if (rx_status->rx_status_1 & 1459 AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) 1460 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; 1461 } 1462 1463 return (HAL_OK); 1464 } 1465 1466 void 1467 ar5k_ar5211_set_rx_signal(struct ath_hal *hal) 1468 { 1469 /* Signal state monitoring is not yet supported */ 1470 } 1471 1472 /* 1473 * Misc functions 1474 */ 1475 1476 void 1477 ar5k_ar5211_dump_state(struct ath_hal *hal) 1478 { 1479 #ifdef AR5K_DEBUG 1480 #define AR5K_PRINT_REGISTER(_x) \ 1481 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x)); 1482 1483 printf("MAC registers:\n"); 1484 AR5K_PRINT_REGISTER(CR); 1485 AR5K_PRINT_REGISTER(CFG); 1486 AR5K_PRINT_REGISTER(IER); 1487 AR5K_PRINT_REGISTER(RTSD0); 1488 AR5K_PRINT_REGISTER(TXCFG); 1489 AR5K_PRINT_REGISTER(RXCFG); 1490 AR5K_PRINT_REGISTER(RXJLA); 1491 AR5K_PRINT_REGISTER(MIBC); 1492 AR5K_PRINT_REGISTER(TOPS); 1493 AR5K_PRINT_REGISTER(RXNOFRM); 1494 AR5K_PRINT_REGISTER(RPGTO); 1495 AR5K_PRINT_REGISTER(RFCNT); 1496 AR5K_PRINT_REGISTER(MISC); 1497 AR5K_PRINT_REGISTER(PISR); 1498 AR5K_PRINT_REGISTER(SISR0); 1499 AR5K_PRINT_REGISTER(SISR1); 1500 AR5K_PRINT_REGISTER(SISR3); 1501 AR5K_PRINT_REGISTER(SISR4); 1502 AR5K_PRINT_REGISTER(QCU_TXE); 1503 AR5K_PRINT_REGISTER(QCU_TXD); 1504 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); 1505 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); 1506 AR5K_PRINT_REGISTER(DCU_FP); 1507 AR5K_PRINT_REGISTER(DCU_TXP); 1508 AR5K_PRINT_REGISTER(DCU_TX_FILTER); 1509 AR5K_PRINT_REGISTER(RC); 1510 AR5K_PRINT_REGISTER(SCR); 1511 AR5K_PRINT_REGISTER(INTPEND); 1512 AR5K_PRINT_REGISTER(PCICFG); 1513 AR5K_PRINT_REGISTER(GPIOCR); 1514 AR5K_PRINT_REGISTER(GPIODO); 1515 AR5K_PRINT_REGISTER(SREV); 1516 AR5K_PRINT_REGISTER(EEPROM_BASE); 1517 AR5K_PRINT_REGISTER(EEPROM_DATA); 1518 AR5K_PRINT_REGISTER(EEPROM_CMD); 1519 AR5K_PRINT_REGISTER(EEPROM_CFG); 1520 AR5K_PRINT_REGISTER(PCU_MIN); 1521 AR5K_PRINT_REGISTER(STA_ID0); 1522 AR5K_PRINT_REGISTER(STA_ID1); 1523 AR5K_PRINT_REGISTER(BSS_ID0); 1524 AR5K_PRINT_REGISTER(SLOT_TIME); 1525 AR5K_PRINT_REGISTER(TIME_OUT); 1526 AR5K_PRINT_REGISTER(RSSI_THR); 1527 AR5K_PRINT_REGISTER(BEACON); 1528 AR5K_PRINT_REGISTER(CFP_PERIOD); 1529 AR5K_PRINT_REGISTER(TIMER0); 1530 AR5K_PRINT_REGISTER(TIMER2); 1531 AR5K_PRINT_REGISTER(TIMER3); 1532 AR5K_PRINT_REGISTER(CFP_DUR); 1533 AR5K_PRINT_REGISTER(MCAST_FIL0); 1534 AR5K_PRINT_REGISTER(MCAST_FIL1); 1535 AR5K_PRINT_REGISTER(DIAG_SW); 1536 AR5K_PRINT_REGISTER(TSF_U32); 1537 AR5K_PRINT_REGISTER(ADDAC_TEST); 1538 AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); 1539 AR5K_PRINT_REGISTER(LAST_TSTP); 1540 AR5K_PRINT_REGISTER(NAV); 1541 AR5K_PRINT_REGISTER(RTS_OK); 1542 AR5K_PRINT_REGISTER(ACK_FAIL); 1543 AR5K_PRINT_REGISTER(FCS_FAIL); 1544 AR5K_PRINT_REGISTER(BEACON_CNT); 1545 AR5K_PRINT_REGISTER(KEYTABLE_0); 1546 printf("\n"); 1547 1548 printf("PHY registers:\n"); 1549 AR5K_PRINT_REGISTER(PHY_TURBO); 1550 AR5K_PRINT_REGISTER(PHY_AGC); 1551 AR5K_PRINT_REGISTER(PHY_CHIP_ID); 1552 AR5K_PRINT_REGISTER(PHY_AGCCTL); 1553 AR5K_PRINT_REGISTER(PHY_NF); 1554 AR5K_PRINT_REGISTER(PHY_RX_DELAY); 1555 AR5K_PRINT_REGISTER(PHY_IQ); 1556 AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); 1557 AR5K_PRINT_REGISTER(PHY_FC); 1558 AR5K_PRINT_REGISTER(PHY_RADAR); 1559 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); 1560 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); 1561 printf("\n"); 1562 #endif 1563 } 1564 1565 HAL_BOOL 1566 ar5k_ar5211_get_diag_state(struct ath_hal *hal, int id, void **device, 1567 u_int *size) 1568 { 1569 /* 1570 * We'll ignore this right now. This seems to be some kind of an obscure 1571 * debugging interface for the binary-only HAL. 1572 */ 1573 return (AH_FALSE); 1574 } 1575 1576 void 1577 ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac) 1578 { 1579 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); 1580 } 1581 1582 HAL_BOOL 1583 ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) 1584 { 1585 u_int32_t low_id, high_id; 1586 1587 /* Set new station ID */ 1588 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); 1589 1590 low_id = AR5K_LOW_ID(mac); 1591 high_id = 0x0000ffff & AR5K_HIGH_ID(mac); 1592 1593 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 1594 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id); 1595 1596 return (AH_TRUE); 1597 } 1598 1599 HAL_BOOL 1600 ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, 1601 HAL_STATUS *status) 1602 { 1603 ieee80211_regdomain_t ieee_regdomain; 1604 1605 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); 1606 1607 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, 1608 &ieee_regdomain) == AH_TRUE) { 1609 *status = HAL_OK; 1610 return (AH_TRUE); 1611 } 1612 1613 *status = EIO; 1614 1615 return (AH_FALSE); 1616 } 1617 1618 void 1619 ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) 1620 { 1621 u_int32_t led; 1622 1623 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PCICFG, 1624 AR5K_AR5211_PCICFG_LEDMODE | AR5K_AR5211_PCICFG_LED); 1625 1626 /* 1627 * Some blinking values, define at your wish 1628 */ 1629 switch (state) { 1630 case IEEE80211_S_SCAN: 1631 case IEEE80211_S_AUTH: 1632 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1633 AR5K_AR5211_PCICFG_LED_PEND; 1634 break; 1635 1636 case IEEE80211_S_INIT: 1637 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1638 AR5K_AR5211_PCICFG_LED_NONE; 1639 break; 1640 1641 case IEEE80211_S_ASSOC: 1642 case IEEE80211_S_RUN: 1643 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1644 AR5K_AR5211_PCICFG_LED_ASSOC; 1645 break; 1646 1647 default: 1648 led = AR5K_AR5211_PCICFG_LEDMODE_PROM | 1649 AR5K_AR5211_PCICFG_LED_NONE; 1650 break; 1651 } 1652 1653 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, led); 1654 } 1655 1656 void 1657 ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid, 1658 u_int16_t assoc_id, u_int16_t tim_offset) 1659 { 1660 u_int32_t low_id, high_id; 1661 1662 /* 1663 * Set BSSID which triggers the "SME Join" operation 1664 */ 1665 low_id = AR5K_LOW_ID(bssid); 1666 high_id = AR5K_HIGH_ID(bssid); 1667 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID0, low_id); 1668 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID1, high_id | 1669 ((assoc_id & 0x3fff) << AR5K_AR5211_BSS_ID1_AID_S)); 1670 bcopy(bssid, hal->ah_bssid, IEEE80211_ADDR_LEN); 1671 1672 if (assoc_id == 0) { 1673 ar5k_ar5211_disable_pspoll(hal); 1674 return; 1675 } 1676 1677 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 1678 (AR5K_REG_READ(AR5K_AR5211_BEACON) & 1679 ~AR5K_AR5211_BEACON_TIM) | 1680 (((tim_offset ? tim_offset + 4 : 0) << 1681 AR5K_AR5211_BEACON_TIM_S) & 1682 AR5K_AR5211_BEACON_TIM)); 1683 1684 ar5k_ar5211_enable_pspoll(hal, NULL, 0); 1685 } 1686 1687 HAL_BOOL 1688 ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) 1689 { 1690 /* Not supported in 5211 */ 1691 return (AH_FALSE); 1692 } 1693 1694 HAL_BOOL 1695 ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) 1696 { 1697 if (gpio > AR5K_AR5211_NUM_GPIO) 1698 return (AH_FALSE); 1699 1700 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1701 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1702 | AR5K_AR5211_GPIOCR_ALL(gpio)); 1703 1704 return (AH_TRUE); 1705 } 1706 1707 HAL_BOOL 1708 ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) 1709 { 1710 if (gpio > AR5K_AR5211_NUM_GPIO) 1711 return (AH_FALSE); 1712 1713 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1714 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1715 | AR5K_AR5211_GPIOCR_NONE(gpio)); 1716 1717 return (AH_TRUE); 1718 } 1719 1720 u_int32_t 1721 ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio) 1722 { 1723 if (gpio > AR5K_AR5211_NUM_GPIO) 1724 return (0xffffffff); 1725 1726 /* GPIO input magic */ 1727 return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) & 1728 AR5K_AR5211_GPIODI_M) >> gpio) & 0x1); 1729 } 1730 1731 HAL_BOOL 1732 ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) 1733 { 1734 u_int32_t data; 1735 1736 if (gpio > AR5K_AR5211_NUM_GPIO) 1737 return (0xffffffff); 1738 1739 /* GPIO output magic */ 1740 data = AR5K_REG_READ(AR5K_AR5211_GPIODO); 1741 1742 data &= ~(1 << gpio); 1743 data |= (val&1) << gpio; 1744 1745 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data); 1746 1747 return (AH_TRUE); 1748 } 1749 1750 void 1751 ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio, 1752 u_int32_t interrupt_level) 1753 { 1754 u_int32_t data; 1755 1756 if (gpio > AR5K_AR5211_NUM_GPIO) 1757 return; 1758 1759 /* 1760 * Set the GPIO interrupt 1761 */ 1762 data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) & 1763 ~(AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_SELH | 1764 AR5K_AR5211_GPIOCR_INT_ENA | AR5K_AR5211_GPIOCR_ALL(gpio))) | 1765 (AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_ENA); 1766 1767 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1768 interrupt_level ? data : (data | AR5K_AR5211_GPIOCR_INT_SELH)); 1769 1770 hal->ah_imr |= AR5K_AR5211_PIMR_GPIO; 1771 1772 /* Enable GPIO interrupts */ 1773 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_AR5211_PIMR_GPIO); 1774 } 1775 1776 u_int32_t 1777 ar5k_ar5211_get_tsf32(struct ath_hal *hal) 1778 { 1779 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32)); 1780 } 1781 1782 u_int64_t 1783 ar5k_ar5211_get_tsf64(struct ath_hal *hal) 1784 { 1785 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32); 1786 1787 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32)); 1788 } 1789 1790 void 1791 ar5k_ar5211_reset_tsf(struct ath_hal *hal) 1792 { 1793 AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON, 1794 AR5K_AR5211_BEACON_RESET_TSF); 1795 } 1796 1797 u_int16_t 1798 ar5k_ar5211_get_regdomain(struct ath_hal *hal) 1799 { 1800 return (ar5k_get_regdomain(hal)); 1801 } 1802 1803 HAL_BOOL 1804 ar5k_ar5211_detect_card_present(struct ath_hal *hal) 1805 { 1806 u_int16_t magic; 1807 1808 /* 1809 * Checking the EEPROM's magic value could be an indication 1810 * if the card is still present. I didn't find another suitable 1811 * way to do this. 1812 */ 1813 if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) 1814 return (AH_FALSE); 1815 1816 return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); 1817 } 1818 1819 void 1820 ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) 1821 { 1822 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL); 1823 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL); 1824 statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK); 1825 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL); 1826 statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT); 1827 } 1828 1829 HAL_RFGAIN 1830 ar5k_ar5211_get_rf_gain(struct ath_hal *hal) 1831 { 1832 return (HAL_RFGAIN_INACTIVE); 1833 } 1834 1835 HAL_BOOL 1836 ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time) 1837 { 1838 if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) 1839 return (AH_FALSE); 1840 1841 AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time); 1842 1843 return (AH_TRUE); 1844 } 1845 1846 u_int 1847 ar5k_ar5211_get_slot_time(struct ath_hal *hal) 1848 { 1849 return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff); 1850 } 1851 1852 HAL_BOOL 1853 ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout) 1854 { 1855 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK)) 1856 <= timeout) 1857 return (AH_FALSE); 1858 1859 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_ACK, 1860 ar5k_htoclock(timeout)); 1861 1862 return (AH_TRUE); 1863 } 1864 1865 u_int 1866 ar5k_ar5211_get_ack_timeout(struct ath_hal *hal) 1867 { 1868 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1869 AR5K_AR5211_TIME_OUT_ACK))); 1870 } 1871 1872 HAL_BOOL 1873 ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout) 1874 { 1875 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS)) 1876 <= timeout) 1877 return (AH_FALSE); 1878 1879 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_CTS, 1880 ar5k_htoclock(timeout)); 1881 1882 return (AH_TRUE); 1883 } 1884 1885 u_int 1886 ar5k_ar5211_get_cts_timeout(struct ath_hal *hal) 1887 { 1888 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1889 AR5K_AR5211_TIME_OUT_CTS))); 1890 } 1891 1892 /* 1893 * Key table (WEP) functions 1894 */ 1895 1896 HAL_BOOL 1897 ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) 1898 { 1899 /* 1900 * The AR5211 only supports WEP 1901 */ 1902 if (cipher == HAL_CIPHER_WEP) 1903 return (AH_TRUE); 1904 1905 return (AH_FALSE); 1906 } 1907 1908 u_int32_t 1909 ar5k_ar5211_get_keycache_size(struct ath_hal *hal) 1910 { 1911 return (AR5K_AR5211_KEYCACHE_SIZE); 1912 } 1913 1914 HAL_BOOL 1915 ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry) 1916 { 1917 int i; 1918 1919 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1920 1921 for (i = 0; i < AR5K_AR5211_KEYCACHE_SIZE; i++) 1922 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0); 1923 1924 /* Set NULL encryption */ 1925 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_TYPE(entry), 1926 AR5K_AR5211_KEYTABLE_TYPE_NULL); 1927 1928 return (AH_FALSE); 1929 } 1930 1931 HAL_BOOL 1932 ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry) 1933 { 1934 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1935 1936 /* 1937 * Check the validation flag at the end of the entry 1938 */ 1939 if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) & 1940 AR5K_AR5211_KEYTABLE_VALID) 1941 return (AH_TRUE); 1942 1943 return (AH_FALSE); 1944 } 1945 1946 HAL_BOOL 1947 ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry, 1948 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) 1949 { 1950 int i; 1951 u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2]; 1952 1953 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1954 1955 bzero(&key_v, sizeof(key_v)); 1956 1957 switch (keyval->wk_len) { 1958 case AR5K_KEYVAL_LENGTH_40: 1959 bcopy(keyval->wk_key, &key_v[0], 4); 1960 bcopy(keyval->wk_key + 4, &key_v[1], 1); 1961 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_40; 1962 break; 1963 1964 case AR5K_KEYVAL_LENGTH_104: 1965 bcopy(keyval->wk_key, &key_v[0], 4); 1966 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1967 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1968 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1969 bcopy(keyval->wk_key + 12, &key_v[4], 1); 1970 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_104; 1971 break; 1972 1973 case AR5K_KEYVAL_LENGTH_128: 1974 bcopy(keyval->wk_key, &key_v[0], 4); 1975 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1976 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1977 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1978 bcopy(keyval->wk_key + 12, &key_v[4], 4); 1979 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_128; 1980 break; 1981 1982 default: 1983 /* Unsupported key length (not WEP40/104/128) */ 1984 return (AH_FALSE); 1985 } 1986 1987 for (i = 0; i < nitems(key_v); i++) 1988 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), key_v[i]); 1989 1990 return (ar5k_ar5211_set_key_lladdr(hal, entry, mac)); 1991 } 1992 1993 HAL_BOOL 1994 ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, 1995 const u_int8_t *mac) 1996 { 1997 u_int32_t low_id, high_id; 1998 const u_int8_t *mac_v; 1999 2000 /* 2001 * Invalid entry (key table overflow) 2002 */ 2003 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 2004 2005 /* MAC may be NULL if it's a broadcast key */ 2006 mac_v = mac == NULL ? etherbroadcastaddr : mac; 2007 2008 low_id = AR5K_LOW_ID(mac_v); 2009 high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5211_KEYTABLE_VALID; 2010 2011 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id); 2012 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id); 2013 2014 return (AH_TRUE); 2015 } 2016 2017 HAL_BOOL 2018 ar5k_ar5211_softcrypto(struct ath_hal *hal, HAL_BOOL enable) 2019 { 2020 u_int32_t bits; 2021 int i; 2022 2023 bits = AR5K_AR5211_DIAG_SW_DIS_ENC | AR5K_AR5211_DIAG_SW_DIS_DEC; 2024 if (enable == AH_TRUE) { 2025 /* Disable the hardware crypto engine */ 2026 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2027 } else { 2028 /* Enable the hardware crypto engine */ 2029 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2030 } 2031 2032 /* Reset the key cache */ 2033 for (i = 0; i < AR5K_AR5211_KEYTABLE_SIZE; i++) 2034 ar5k_ar5211_reset_key(hal, i); 2035 2036 return (AH_TRUE); 2037 } 2038 2039 /* 2040 * Power management functions 2041 */ 2042 2043 HAL_BOOL 2044 ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, 2045 HAL_BOOL set_chip, u_int16_t sleep_duration) 2046 { 2047 u_int32_t staid; 2048 int i; 2049 2050 staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1); 2051 2052 switch (mode) { 2053 case HAL_PM_AUTO: 2054 staid &= ~AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 2055 /* FALLTHROUGH */ 2056 case HAL_PM_NETWORK_SLEEP: 2057 if (set_chip == AH_TRUE) { 2058 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2059 AR5K_AR5211_SCR_SLE | sleep_duration); 2060 } 2061 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2062 break; 2063 2064 case HAL_PM_FULL_SLEEP: 2065 if (set_chip == AH_TRUE) { 2066 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2067 AR5K_AR5211_SCR_SLE_SLP); 2068 } 2069 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2070 break; 2071 2072 case HAL_PM_AWAKE: 2073 if (set_chip == AH_FALSE) 2074 goto commit; 2075 2076 AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE); 2077 2078 for (i = 5000; i > 0; i--) { 2079 /* Check if the AR5211 did wake up */ 2080 if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) & 2081 AR5K_AR5211_PCICFG_SPWR_DN) == 0) 2082 break; 2083 2084 /* Wait a bit and retry */ 2085 AR5K_DELAY(200); 2086 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2087 AR5K_AR5211_SCR_SLE_WAKE); 2088 } 2089 2090 /* Fail if the AR5211 didn't wake up */ 2091 if (i <= 0) 2092 return (AH_FALSE); 2093 2094 staid &= ~AR5K_AR5211_STA_ID1_PWR_SV; 2095 break; 2096 2097 default: 2098 return (AH_FALSE); 2099 } 2100 2101 commit: 2102 hal->ah_power_mode = mode; 2103 2104 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid); 2105 2106 return (AH_TRUE); 2107 } 2108 2109 HAL_POWER_MODE 2110 ar5k_ar5211_get_power_mode(struct ath_hal *hal) 2111 { 2112 return (hal->ah_power_mode); 2113 } 2114 2115 HAL_BOOL 2116 ar5k_ar5211_query_pspoll_support(struct ath_hal *hal) 2117 { 2118 /* nope */ 2119 return (AH_FALSE); 2120 } 2121 2122 HAL_BOOL 2123 ar5k_ar5211_init_pspoll(struct ath_hal *hal) 2124 { 2125 /* 2126 * Not used on the AR5211 2127 */ 2128 return (AH_FALSE); 2129 } 2130 2131 HAL_BOOL 2132 ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, 2133 u_int16_t assoc_id) 2134 { 2135 return (AH_FALSE); 2136 } 2137 2138 HAL_BOOL 2139 ar5k_ar5211_disable_pspoll(struct ath_hal *hal) 2140 { 2141 return (AH_FALSE); 2142 } 2143 2144 /* 2145 * Beacon functions 2146 */ 2147 2148 void 2149 ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, 2150 u_int32_t interval) 2151 { 2152 u_int32_t timer1, timer2, timer3; 2153 2154 /* 2155 * Set the additional timers by mode 2156 */ 2157 switch (hal->ah_op_mode) { 2158 case HAL_M_STA: 2159 timer1 = 0x0000ffff; 2160 timer2 = 0x0007ffff; 2161 break; 2162 2163 default: 2164 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 2165 0x00000003; 2166 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 2167 0x00000003; 2168 } 2169 2170 timer3 = next_beacon + 2171 (hal->ah_atim_window ? hal->ah_atim_window : 1); 2172 2173 /* 2174 * Enable all timers and set the beacon register 2175 * (next beacon, DMA beacon, software beacon, ATIM window time) 2176 */ 2177 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, next_beacon); 2178 AR5K_REG_WRITE(AR5K_AR5211_TIMER1, timer1); 2179 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, timer2); 2180 AR5K_REG_WRITE(AR5K_AR5211_TIMER3, timer3); 2181 2182 AR5K_REG_WRITE(AR5K_AR5211_BEACON, interval & 2183 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_RESET_TSF | 2184 AR5K_AR5211_BEACON_ENABLE)); 2185 } 2186 2187 void 2188 ar5k_ar5211_set_beacon_timers(struct ath_hal *hal, 2189 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, 2190 u_int32_t cfp_count) 2191 { 2192 u_int32_t cfp_period, next_cfp; 2193 2194 /* Return on an invalid beacon state */ 2195 if (state->bs_interval < 1) 2196 return; 2197 2198 /* 2199 * PCF support? 2200 */ 2201 if (state->bs_cfp_period > 0) { 2202 /* Enable CFP mode and set the CFP and timer registers */ 2203 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 2204 state->bs_interval; 2205 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 2206 state->bs_interval; 2207 2208 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2209 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2210 AR5K_AR5211_STA_ID1_PCF); 2211 AR5K_REG_WRITE(AR5K_AR5211_CFP_PERIOD, cfp_period); 2212 AR5K_REG_WRITE(AR5K_AR5211_CFP_DUR, state->bs_cfp_max_duration); 2213 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, 2214 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); 2215 } else { 2216 /* Disable PCF mode */ 2217 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2218 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2219 AR5K_AR5211_STA_ID1_PCF); 2220 } 2221 2222 /* 2223 * Enable the beacon timer register 2224 */ 2225 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, state->bs_next_beacon); 2226 2227 /* 2228 * Start the beacon timers 2229 */ 2230 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 2231 (AR5K_REG_READ(AR5K_AR5211_BEACON) &~ 2232 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_TIM)) | 2233 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 2234 AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 2235 AR5K_AR5211_BEACON_PERIOD)); 2236 2237 /* 2238 * Write new beacon miss threshold, if it appears to be valid 2239 */ 2240 if ((AR5K_AR5211_RSSI_THR_BMISS >> AR5K_AR5211_RSSI_THR_BMISS_S) < 2241 state->bs_bmiss_threshold) 2242 return; 2243 2244 AR5K_REG_WRITE_BITS(AR5K_AR5211_RSSI_THR_M, 2245 AR5K_AR5211_RSSI_THR_BMISS, state->bs_bmiss_threshold); 2246 AR5K_REG_WRITE_BITS(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLDUR, 2247 (state->bs_sleepduration - 3) << 3); 2248 } 2249 2250 void 2251 ar5k_ar5211_reset_beacon(struct ath_hal *hal) 2252 { 2253 /* 2254 * Disable beacon timer 2255 */ 2256 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, 0); 2257 2258 /* 2259 * Disable some beacon register values 2260 */ 2261 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2262 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5211_STA_ID1_PCF); 2263 AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD); 2264 } 2265 2266 HAL_BOOL 2267 ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr) 2268 { 2269 HAL_BOOL ret; 2270 2271 /* 2272 * Wait for beaconn queue to be done 2273 */ 2274 ret = ar5k_register_timeout(hal, 2275 AR5K_AR5211_QCU_STS(HAL_TX_QUEUE_ID_BEACON), 2276 AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE); 2277 2278 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) 2279 return (AH_FALSE); 2280 2281 return (ret); 2282 } 2283 2284 /* 2285 * Interrupt handling 2286 */ 2287 2288 HAL_BOOL 2289 ar5k_ar5211_is_intr_pending(struct ath_hal *hal) 2290 { 2291 return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE); 2292 } 2293 2294 HAL_BOOL 2295 ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) 2296 { 2297 u_int32_t data; 2298 2299 /* 2300 * Read interrupt status from the Read-And-Clear shadow register 2301 */ 2302 data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR); 2303 2304 /* 2305 * Get abstract interrupt mask (HAL-compatible) 2306 */ 2307 *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; 2308 2309 if (data == HAL_INT_NOCARD) 2310 return (AH_FALSE); 2311 2312 if (data & (AR5K_AR5211_PISR_RXOK | AR5K_AR5211_PISR_RXERR)) 2313 *interrupt_mask |= HAL_INT_RX; 2314 2315 if (data & (AR5K_AR5211_PISR_TXOK | AR5K_AR5211_PISR_TXERR)) 2316 *interrupt_mask |= HAL_INT_TX; 2317 2318 if (data & (AR5K_AR5211_PISR_HIUERR)) 2319 *interrupt_mask |= HAL_INT_FATAL; 2320 2321 /* 2322 * Special interrupt handling (not caught by the driver) 2323 */ 2324 if (((*interrupt_mask) & AR5K_AR5211_PISR_RXPHY) && 2325 hal->ah_radar.r_enabled == AH_TRUE) 2326 ar5k_radar_alert(hal); 2327 2328 return (AH_TRUE); 2329 } 2330 2331 u_int32_t 2332 ar5k_ar5211_get_intr(struct ath_hal *hal) 2333 { 2334 /* Return the interrupt mask stored previously */ 2335 return (hal->ah_imr); 2336 } 2337 2338 HAL_INT 2339 ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask) 2340 { 2341 HAL_INT old_mask, int_mask; 2342 2343 /* 2344 * Disable card interrupts to prevent any race conditions 2345 * (they will be re-enabled afterwards). 2346 */ 2347 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2348 2349 old_mask = hal->ah_imr; 2350 2351 /* 2352 * Add additional, chipset-dependent interrupt mask flags 2353 * and write them to the IMR (interrupt mask register). 2354 */ 2355 int_mask = new_mask & HAL_INT_COMMON; 2356 2357 if (new_mask & HAL_INT_RX) 2358 int_mask |= 2359 AR5K_AR5211_PIMR_RXOK | 2360 AR5K_AR5211_PIMR_RXERR | 2361 AR5K_AR5211_PIMR_RXORN | 2362 AR5K_AR5211_PIMR_RXDESC; 2363 2364 if (new_mask & HAL_INT_TX) 2365 int_mask |= 2366 AR5K_AR5211_PIMR_TXOK | 2367 AR5K_AR5211_PIMR_TXERR | 2368 AR5K_AR5211_PIMR_TXDESC | 2369 AR5K_AR5211_PIMR_TXURN; 2370 2371 if (new_mask & HAL_INT_FATAL) { 2372 int_mask |= AR5K_AR5211_PIMR_HIUERR; 2373 AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2, 2374 AR5K_AR5211_SIMR2_MCABT | 2375 AR5K_AR5211_SIMR2_SSERR | 2376 AR5K_AR5211_SIMR2_DPERR); 2377 } 2378 2379 AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask); 2380 2381 /* Store new interrupt mask */ 2382 hal->ah_imr = new_mask; 2383 2384 /* ..re-enable interrupts */ 2385 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2386 2387 return (old_mask); 2388 } 2389 2390 /* 2391 * Misc internal functions 2392 */ 2393 2394 HAL_BOOL 2395 ar5k_ar5211_get_capabilities(struct ath_hal *hal) 2396 { 2397 u_int16_t ee_header; 2398 u_int a, b, g; 2399 2400 /* Capabilities stored in the EEPROM */ 2401 ee_header = hal->ah_capabilities.cap_eeprom.ee_header; 2402 2403 a = AR5K_EEPROM_HDR_11A(ee_header); 2404 b = AR5K_EEPROM_HDR_11B(ee_header); 2405 g = AR5K_EEPROM_HDR_11G(ee_header); 2406 2407 /* 2408 * If the EEPROM is not reporting any mode, we try 11b. 2409 * This might fix a few broken devices with invalid EEPROM. 2410 */ 2411 if (!a && !b && !g) 2412 b = 1; 2413 2414 /* 2415 * XXX The AR5211 tranceiver supports frequencies from 4920 to 6100GHz 2416 * XXX and from 2312 to 2732GHz. There are problems with the current 2417 * XXX ieee80211 implementation because the IEEE channel mapping 2418 * XXX does not support negative channel numbers (2312MHz is channel 2419 * XXX -19). Of course, this doesn't matter because these channels 2420 * XXX are out of range but some regulation domains like MKK (Japan) 2421 * XXX will support frequencies somewhere around 4.8GHz. 2422 */ 2423 2424 /* 2425 * Set radio capabilities 2426 */ 2427 2428 if (a) { 2429 hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ 2430 hal->ah_capabilities.cap_range.range_5ghz_max = 6100; 2431 2432 /* Set supported modes */ 2433 hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; 2434 } 2435 2436 /* This chip will support 802.11b if the 2GHz radio is connected */ 2437 if (b || g) { 2438 hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ 2439 hal->ah_capabilities.cap_range.range_2ghz_max = 2732; 2440 2441 if (b) 2442 hal->ah_capabilities.cap_mode |= HAL_MODE_11B; 2443 #if 0 2444 if (g) 2445 hal->ah_capabilities.cap_mode |= HAL_MODE_11G; 2446 #endif 2447 } 2448 2449 /* GPIO */ 2450 hal->ah_gpio_npins = AR5K_AR5211_NUM_GPIO; 2451 2452 /* Set number of supported TX queues */ 2453 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES; 2454 2455 return (AH_TRUE); 2456 } 2457 2458 void 2459 ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable) 2460 { 2461 /* 2462 * Enable radar detection 2463 */ 2464 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2465 2466 if (enable == AH_TRUE) { 2467 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2468 AR5K_AR5211_PHY_RADAR_ENABLE); 2469 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, 2470 AR5K_AR5211_PIMR_RXPHY); 2471 } else { 2472 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2473 AR5K_AR5211_PHY_RADAR_DISABLE); 2474 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PIMR, 2475 AR5K_AR5211_PIMR_RXPHY); 2476 } 2477 2478 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2479 } 2480 2481 /* 2482 * EEPROM access functions 2483 */ 2484 2485 HAL_BOOL 2486 ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal) 2487 { 2488 return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ? 2489 AH_TRUE : AH_FALSE); 2490 } 2491 2492 int 2493 ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) 2494 { 2495 u_int32_t status, i; 2496 2497 /* 2498 * Initialize EEPROM access 2499 */ 2500 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset); 2501 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2502 AR5K_AR5211_EEPROM_CMD_READ); 2503 2504 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 2505 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2506 if (status & AR5K_AR5211_EEPROM_STAT_RDDONE) { 2507 if (status & AR5K_AR5211_EEPROM_STAT_RDERR) 2508 return (EIO); 2509 *data = (u_int16_t) 2510 (AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff); 2511 return (0); 2512 } 2513 AR5K_DELAY(15); 2514 } 2515 2516 return (ETIMEDOUT); 2517 } 2518 2519 int 2520 ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) 2521 { 2522 u_int32_t status, timeout; 2523 2524 /* Enable eeprom access */ 2525 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2526 AR5K_AR5211_EEPROM_CMD_RESET); 2527 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2528 AR5K_AR5211_EEPROM_CMD_WRITE); 2529 2530 /* 2531 * Prime write pump 2532 */ 2533 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset - 1); 2534 2535 for (timeout = 10000; timeout > 0; timeout--) { 2536 AR5K_DELAY(1); 2537 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2538 if (status & AR5K_AR5211_EEPROM_STAT_WRDONE) { 2539 if (status & AR5K_AR5211_EEPROM_STAT_WRERR) 2540 return (EIO); 2541 return (0); 2542 } 2543 } 2544 2545 return (ETIMEDOUT); 2546 } 2547 2548 /* 2549 * RF register settings 2550 */ 2551 2552 HAL_BOOL 2553 ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq, 2554 u_int ee_mode) 2555 { 2556 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 2557 struct ar5k_ar5211_ini_rf rf[nitems(ar5211_rf)]; 2558 u_int32_t ob, db, xpds, xpdp, x_gain; 2559 u_int i; 2560 int obdb; 2561 2562 bcopy(ar5211_rf, rf, sizeof(rf)); 2563 obdb = 0; 2564 2565 if (freq == AR5K_INI_RFGAIN_2GHZ && 2566 hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { 2567 ob = ar5k_bitswap(ee->ee_ob[ee_mode][0], 3); 2568 db = ar5k_bitswap(ee->ee_db[ee_mode][0], 3); 2569 rf[25].rf_value[freq] = 2570 ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); 2571 rf[26].rf_value[freq] = 2572 (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | 2573 (rf[26].rf_value[freq] & ~0xf); 2574 } 2575 2576 if (freq == AR5K_INI_RFGAIN_5GHZ) { 2577 /* For 11a and Turbo */ 2578 obdb = channel->c_channel >= 5725 ? 3 : 2579 (channel->c_channel >= 5500 ? 2 : 2580 (channel->c_channel >= 5260 ? 1 : 2581 (channel->c_channel > 4000 ? 0 : -1))); 2582 } 2583 2584 /* bogus channel: bad beacon? */ 2585 if (obdb < 0) 2586 return (AH_FALSE); 2587 2588 ob = ee->ee_ob[ee_mode][obdb]; 2589 db = ee->ee_db[ee_mode][obdb]; 2590 x_gain = ee->ee_x_gain[ee_mode]; 2591 xpds = ee->ee_xpd[ee_mode]; 2592 xpdp = !xpds; 2593 2594 rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | 2595 (((ar5k_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); 2596 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | 2597 ((ar5k_bitswap(x_gain, 4) >> 1) & 0x7); 2598 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | 2599 ((ar5k_bitswap(ob, 3) << 7) & 0x80); 2600 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | 2601 ((ar5k_bitswap(ob, 3) >> 1) & 0x3); 2602 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | 2603 ((ar5k_bitswap(db, 3) << 2) & 0x1c); 2604 rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | 2605 ((xpds << 3) & 0x8); 2606 2607 for (i = 0; i < nitems(rf); i++) { 2608 AR5K_REG_WAIT(i); 2609 AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, 2610 rf[i].rf_value[freq]); 2611 } 2612 2613 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 2614 2615 return (AH_TRUE); 2616 } 2617 2618 HAL_BOOL 2619 ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int power) 2620 { 2621 /* Not implemented */ 2622 return (AH_FALSE); 2623 } 2624