1 /* $OpenBSD: ar5212.c,v 1.47 2008/08/29 10:05:00 reyk Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for the Atheros AR5001 Wireless LAN chipset 21 * (AR5212 + AR5111/AR5112). 22 */ 23 24 #include <dev/ic/ar5xxx.h> 25 #include <dev/ic/ar5212reg.h> 26 #include <dev/ic/ar5212var.h> 27 28 HAL_BOOL ar5k_ar5212_nic_reset(struct ath_hal *, u_int32_t); 29 HAL_BOOL ar5k_ar5212_nic_wakeup(struct ath_hal *, u_int16_t); 30 u_int16_t ar5k_ar5212_radio_revision(struct ath_hal *, HAL_CHIP); 31 const void ar5k_ar5212_fill(struct ath_hal *); 32 HAL_BOOL ar5k_ar5212_txpower(struct ath_hal *, HAL_CHANNEL *, u_int); 33 34 /* 35 * Initial register setting for the AR5212 36 */ 37 static const struct ar5k_ini ar5212_ini[] = AR5K_AR5212_INI; 38 static const struct ar5k_mode ar5212_mode[] = AR5K_AR5212_MODE; 39 static const struct ar5k_mode ar5212_ar5111_mode[] = AR5K_AR5212_AR5111_MODE; 40 static const struct ar5k_mode ar5212_ar5112_mode[] = AR5K_AR5212_AR5112_MODE; 41 static const struct ar5k_mode ar5413_mode[] = AR5K_AR5413_MODE; 42 static const struct ar5k_mode ar2413_mode[] = AR5K_AR2413_MODE; 43 static const struct ar5k_mode ar2425_mode[] = AR5K_AR2425_MODE; 44 static const struct ar5k_ini ar5111_bbgain[] = AR5K_AR5111_INI_BBGAIN; 45 static const struct ar5k_ini ar5112_bbgain[] = AR5K_AR5112_INI_BBGAIN; 46 static const struct ar5k_ini ar5212_pcie[] = AR5K_AR5212_PCIE; 47 48 AR5K_HAL_FUNCTIONS(extern, ar5k_ar5212,); 49 50 const void 51 ar5k_ar5212_fill(struct ath_hal *hal) 52 { 53 hal->ah_magic = AR5K_AR5212_MAGIC; 54 55 /* 56 * Init/Exit functions 57 */ 58 AR5K_HAL_FUNCTION(hal, ar5212, get_rate_table); 59 AR5K_HAL_FUNCTION(hal, ar5212, detach); 60 61 /* 62 * Reset functions 63 */ 64 AR5K_HAL_FUNCTION(hal, ar5212, reset); 65 AR5K_HAL_FUNCTION(hal, ar5212, set_opmode); 66 AR5K_HAL_FUNCTION(hal, ar5212, calibrate); 67 68 /* 69 * TX functions 70 */ 71 AR5K_HAL_FUNCTION(hal, ar5212, update_tx_triglevel); 72 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queue); 73 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queueprops); 74 AR5K_HAL_FUNCTION(hal, ar5212, release_tx_queue); 75 AR5K_HAL_FUNCTION(hal, ar5212, reset_tx_queue); 76 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_buf); 77 AR5K_HAL_FUNCTION(hal, ar5212, put_tx_buf); 78 AR5K_HAL_FUNCTION(hal, ar5212, tx_start); 79 AR5K_HAL_FUNCTION(hal, ar5212, stop_tx_dma); 80 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_desc); 81 AR5K_HAL_FUNCTION(hal, ar5212, setup_xtx_desc); 82 AR5K_HAL_FUNCTION(hal, ar5212, fill_tx_desc); 83 AR5K_HAL_FUNCTION(hal, ar5212, proc_tx_desc); 84 AR5K_HAL_FUNCTION(hal, ar5212, has_veol); 85 86 /* 87 * RX functions 88 */ 89 AR5K_HAL_FUNCTION(hal, ar5212, get_rx_buf); 90 AR5K_HAL_FUNCTION(hal, ar5212, put_rx_buf); 91 AR5K_HAL_FUNCTION(hal, ar5212, start_rx); 92 AR5K_HAL_FUNCTION(hal, ar5212, stop_rx_dma); 93 AR5K_HAL_FUNCTION(hal, ar5212, start_rx_pcu); 94 AR5K_HAL_FUNCTION(hal, ar5212, stop_pcu_recv); 95 AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filter); 96 AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filterindex); 97 AR5K_HAL_FUNCTION(hal, ar5212, clear_mcast_filter_idx); 98 AR5K_HAL_FUNCTION(hal, ar5212, get_rx_filter); 99 AR5K_HAL_FUNCTION(hal, ar5212, set_rx_filter); 100 AR5K_HAL_FUNCTION(hal, ar5212, setup_rx_desc); 101 AR5K_HAL_FUNCTION(hal, ar5212, proc_rx_desc); 102 AR5K_HAL_FUNCTION(hal, ar5212, set_rx_signal); 103 104 /* 105 * Misc functions 106 */ 107 AR5K_HAL_FUNCTION(hal, ar5212, dump_state); 108 AR5K_HAL_FUNCTION(hal, ar5212, get_diag_state); 109 AR5K_HAL_FUNCTION(hal, ar5212, get_lladdr); 110 AR5K_HAL_FUNCTION(hal, ar5212, set_lladdr); 111 AR5K_HAL_FUNCTION(hal, ar5212, set_regdomain); 112 AR5K_HAL_FUNCTION(hal, ar5212, set_ledstate); 113 AR5K_HAL_FUNCTION(hal, ar5212, set_associd); 114 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_input); 115 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_output); 116 AR5K_HAL_FUNCTION(hal, ar5212, get_gpio); 117 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio); 118 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_intr); 119 AR5K_HAL_FUNCTION(hal, ar5212, get_tsf32); 120 AR5K_HAL_FUNCTION(hal, ar5212, get_tsf64); 121 AR5K_HAL_FUNCTION(hal, ar5212, reset_tsf); 122 AR5K_HAL_FUNCTION(hal, ar5212, get_regdomain); 123 AR5K_HAL_FUNCTION(hal, ar5212, detect_card_present); 124 AR5K_HAL_FUNCTION(hal, ar5212, update_mib_counters); 125 AR5K_HAL_FUNCTION(hal, ar5212, get_rf_gain); 126 AR5K_HAL_FUNCTION(hal, ar5212, set_slot_time); 127 AR5K_HAL_FUNCTION(hal, ar5212, get_slot_time); 128 AR5K_HAL_FUNCTION(hal, ar5212, set_ack_timeout); 129 AR5K_HAL_FUNCTION(hal, ar5212, get_ack_timeout); 130 AR5K_HAL_FUNCTION(hal, ar5212, set_cts_timeout); 131 AR5K_HAL_FUNCTION(hal, ar5212, get_cts_timeout); 132 133 /* 134 * Key table (WEP) functions 135 */ 136 AR5K_HAL_FUNCTION(hal, ar5212, is_cipher_supported); 137 AR5K_HAL_FUNCTION(hal, ar5212, get_keycache_size); 138 AR5K_HAL_FUNCTION(hal, ar5212, reset_key); 139 AR5K_HAL_FUNCTION(hal, ar5212, is_key_valid); 140 AR5K_HAL_FUNCTION(hal, ar5212, set_key); 141 AR5K_HAL_FUNCTION(hal, ar5212, set_key_lladdr); 142 AR5K_HAL_FUNCTION(hal, ar5212, softcrypto); 143 144 /* 145 * Power management functions 146 */ 147 AR5K_HAL_FUNCTION(hal, ar5212, set_power); 148 AR5K_HAL_FUNCTION(hal, ar5212, get_power_mode); 149 AR5K_HAL_FUNCTION(hal, ar5212, query_pspoll_support); 150 AR5K_HAL_FUNCTION(hal, ar5212, init_pspoll); 151 AR5K_HAL_FUNCTION(hal, ar5212, enable_pspoll); 152 AR5K_HAL_FUNCTION(hal, ar5212, disable_pspoll); 153 154 /* 155 * Beacon functions 156 */ 157 AR5K_HAL_FUNCTION(hal, ar5212, init_beacon); 158 AR5K_HAL_FUNCTION(hal, ar5212, set_beacon_timers); 159 AR5K_HAL_FUNCTION(hal, ar5212, reset_beacon); 160 AR5K_HAL_FUNCTION(hal, ar5212, wait_for_beacon); 161 162 /* 163 * Interrupt functions 164 */ 165 AR5K_HAL_FUNCTION(hal, ar5212, is_intr_pending); 166 AR5K_HAL_FUNCTION(hal, ar5212, get_isr); 167 AR5K_HAL_FUNCTION(hal, ar5212, get_intr); 168 AR5K_HAL_FUNCTION(hal, ar5212, set_intr); 169 170 /* 171 * Chipset functions (ar5k-specific, non-HAL) 172 */ 173 AR5K_HAL_FUNCTION(hal, ar5212, get_capabilities); 174 AR5K_HAL_FUNCTION(hal, ar5212, radar_alert); 175 176 /* 177 * EEPROM access 178 */ 179 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_is_busy); 180 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_read); 181 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_write); 182 183 /* 184 * Unused functions or functions not implemented 185 */ 186 AR5K_HAL_FUNCTION(hal, ar5212, set_bssid_mask); 187 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_queueprops); 188 AR5K_HAL_FUNCTION(hal, ar5212, num_tx_pending); 189 AR5K_HAL_FUNCTION(hal, ar5212, phy_disable); 190 AR5K_HAL_FUNCTION(hal, ar5212, set_txpower_limit); 191 AR5K_HAL_FUNCTION(hal, ar5212, set_def_antenna); 192 AR5K_HAL_FUNCTION(hal, ar5212, get_def_antenna); 193 #ifdef notyet 194 AR5K_HAL_FUNCTION(hal, ar5212, set_capability); 195 AR5K_HAL_FUNCTION(hal, ar5212, proc_mib_event); 196 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_inter_queue); 197 #endif 198 } 199 200 struct ath_hal * 201 ar5k_ar5212_attach(u_int16_t device, void *sc, bus_space_tag_t st, 202 bus_space_handle_t sh, int *status) 203 { 204 struct ath_hal *hal = (struct ath_hal*) sc; 205 u_int8_t mac[IEEE80211_ADDR_LEN]; 206 u_int32_t srev; 207 208 ar5k_ar5212_fill(hal); 209 210 /* Bring device out of sleep and reset its units */ 211 if (ar5k_ar5212_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) 212 return (NULL); 213 214 /* Get MAC, PHY and RADIO revisions */ 215 srev = AR5K_REG_READ(AR5K_AR5212_SREV); 216 hal->ah_mac_srev = srev; 217 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5212_SREV_VER); 218 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5212_SREV_REV); 219 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID) & 220 0x00ffffffff; 221 hal->ah_radio_5ghz_revision = 222 ar5k_ar5212_radio_revision(hal, HAL_CHIP_5GHZ); 223 hal->ah_radio_2ghz_revision = 224 ar5k_ar5212_radio_revision(hal, HAL_CHIP_2GHZ); 225 226 /* Single chip radio */ 227 if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) 228 hal->ah_radio_2ghz_revision = 0; 229 230 /* Identify the chipset (this has to be done in an early step) */ 231 hal->ah_version = AR5K_AR5212; 232 if (srev == AR5K_SREV_VER_AR2425) { 233 hal->ah_radio = AR5K_AR2425; 234 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112; 235 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) { 236 hal->ah_radio = AR5K_AR5111; 237 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5111; 238 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) { 239 hal->ah_radio = AR5K_AR5112; 240 if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) 241 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112; 242 else 243 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 244 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) { 245 hal->ah_radio = AR5K_AR2413; 246 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 247 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) { 248 hal->ah_radio = AR5K_AR5413; 249 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 250 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133 && 251 srev < AR5K_SREV_VER_AR5424) { 252 hal->ah_radio = AR5K_AR2413; 253 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 254 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) { 255 hal->ah_radio = AR5K_AR5413; 256 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5424; 257 } 258 hal->ah_phy = AR5K_AR5212_PHY(0); 259 260 if (hal->ah_pci_express == AH_TRUE) { 261 /* PCI-Express based devices need some extra initialization */ 262 ar5k_write_ini(hal, ar5212_pcie, AR5K_ELEMENTS(ar5212_pcie), 0); 263 } 264 265 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 266 ar5k_ar5212_set_associd(hal, mac, 0, 0); 267 ar5k_ar5212_get_lladdr(hal, mac); 268 ar5k_ar5212_set_opmode(hal); 269 270 return (hal); 271 } 272 273 HAL_BOOL 274 ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val) 275 { 276 HAL_BOOL ret = AH_FALSE; 277 u_int32_t mask = val ? val : ~0; 278 279 /* Read-and-clear */ 280 AR5K_REG_READ(AR5K_AR5212_RXDP); 281 282 /* 283 * Reset the device and wait until success 284 */ 285 AR5K_REG_WRITE(AR5K_AR5212_RC, val); 286 287 /* Wait at least 128 PCI clocks */ 288 AR5K_DELAY(15); 289 290 val &= 291 AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; 292 293 mask &= 294 AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; 295 296 ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, AH_FALSE); 297 298 /* 299 * Reset configuration register 300 */ 301 if ((val & AR5K_AR5212_RC_PCU) == 0) 302 AR5K_REG_WRITE(AR5K_AR5212_CFG, AR5K_AR5212_INIT_CFG); 303 304 return (ret); 305 } 306 307 HAL_BOOL 308 ar5k_ar5212_nic_wakeup(struct ath_hal *hal, u_int16_t flags) 309 { 310 u_int32_t turbo, mode, clock; 311 312 turbo = 0; 313 mode = 0; 314 clock = 0; 315 316 /* 317 * Get channel mode flags 318 */ 319 320 if (hal->ah_radio >= AR5K_AR5112) { 321 mode = AR5K_AR5212_PHY_MODE_RAD_AR5112; 322 clock = AR5K_AR5212_PHY_PLL_AR5112; 323 } else { 324 mode = AR5K_AR5212_PHY_MODE_RAD_AR5111; 325 clock = AR5K_AR5212_PHY_PLL_AR5111; 326 } 327 328 if (flags & IEEE80211_CHAN_2GHZ) { 329 mode |= AR5K_AR5212_PHY_MODE_FREQ_2GHZ; 330 clock |= AR5K_AR5212_PHY_PLL_44MHZ; 331 } else if (flags & IEEE80211_CHAN_5GHZ) { 332 mode |= AR5K_AR5212_PHY_MODE_FREQ_5GHZ; 333 clock |= AR5K_AR5212_PHY_PLL_40MHZ; 334 } else { 335 AR5K_PRINT("invalid radio frequency mode\n"); 336 return (AH_FALSE); 337 } 338 339 if (flags & IEEE80211_CHAN_CCK) { 340 mode |= AR5K_AR5212_PHY_MODE_MOD_CCK; 341 } else if (flags & IEEE80211_CHAN_OFDM) { 342 mode |= AR5K_AR5212_PHY_MODE_MOD_OFDM; 343 } else if (flags & IEEE80211_CHAN_DYN) { 344 mode |= AR5K_AR5212_PHY_MODE_MOD_DYN; 345 } else { 346 AR5K_PRINT("invalid radio frequency mode\n"); 347 return (AH_FALSE); 348 } 349 350 if (flags & IEEE80211_CHAN_TURBO) { 351 turbo = AR5K_AR5212_PHY_TURBO_MODE | 352 AR5K_AR5212_PHY_TURBO_SHORT; 353 } 354 355 /* 356 * Reset and wakeup the device 357 */ 358 359 /* ...reset chipset and PCI device (if not PCI-E) */ 360 if (hal->ah_pci_express == AH_FALSE && 361 ar5k_ar5212_nic_reset(hal, AR5K_AR5212_RC_CHIP) == AH_FALSE) { 362 AR5K_PRINT("failed to reset the AR5212 + PCI chipset\n"); 363 return (AH_FALSE); 364 } 365 366 /* ...wakeup */ 367 if (ar5k_ar5212_set_power(hal, 368 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 369 AR5K_PRINT("failed to resume the AR5212 (again)\n"); 370 return (AH_FALSE); 371 } 372 373 /* ...final warm reset */ 374 if (ar5k_ar5212_nic_reset(hal, 0) == AH_FALSE) { 375 AR5K_PRINT("failed to warm reset the AR5212\n"); 376 return (AH_FALSE); 377 } 378 379 /* ...set the PHY operating mode */ 380 AR5K_REG_WRITE(AR5K_AR5212_PHY_PLL, clock); 381 AR5K_DELAY(300); 382 383 AR5K_REG_WRITE(AR5K_AR5212_PHY_MODE, mode); 384 AR5K_REG_WRITE(AR5K_AR5212_PHY_TURBO, turbo); 385 386 return (AH_TRUE); 387 } 388 389 u_int16_t 390 ar5k_ar5212_radio_revision(struct ath_hal *hal, HAL_CHIP chip) 391 { 392 int i; 393 u_int32_t srev; 394 u_int16_t ret; 395 396 /* 397 * Set the radio chip access register 398 */ 399 switch (chip) { 400 case HAL_CHIP_2GHZ: 401 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_2GHZ); 402 break; 403 case HAL_CHIP_5GHZ: 404 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); 405 break; 406 default: 407 return (0); 408 } 409 410 AR5K_DELAY(2000); 411 412 /* ...wait until PHY is ready and read the selected radio revision */ 413 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x34), 0x00001c16); 414 415 for (i = 0; i < 8; i++) 416 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x20), 0x00010000); 417 srev = (AR5K_REG_READ(AR5K_AR5212_PHY(0x100)) >> 24) & 0xff; 418 419 ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); 420 421 /* Reset to the 5GHz mode */ 422 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); 423 424 return (ret); 425 } 426 427 const HAL_RATE_TABLE * 428 ar5k_ar5212_get_rate_table(struct ath_hal *hal, u_int mode) 429 { 430 switch (mode) { 431 case HAL_MODE_11A: 432 return (&hal->ah_rt_11a); 433 case HAL_MODE_TURBO: 434 return (&hal->ah_rt_turbo); 435 case HAL_MODE_11B: 436 return (&hal->ah_rt_11b); 437 case HAL_MODE_11G: 438 case HAL_MODE_PUREG: 439 return (&hal->ah_rt_11g); 440 case HAL_MODE_XR: 441 return (&hal->ah_rt_xr); 442 default: 443 return (NULL); 444 } 445 446 return (NULL); 447 } 448 449 void 450 ar5k_ar5212_detach(struct ath_hal *hal) 451 { 452 if (hal->ah_rf_banks != NULL) 453 free(hal->ah_rf_banks, M_DEVBUF); 454 455 /* 456 * Free HAL structure, assume interrupts are down 457 */ 458 free(hal, M_DEVBUF); 459 } 460 461 HAL_BOOL 462 ar5k_ar5212_phy_disable(struct ath_hal *hal) 463 { 464 AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_DISABLE); 465 return (AH_TRUE); 466 } 467 468 HAL_BOOL 469 ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, 470 HAL_BOOL chanchange, HAL_STATUS *status) 471 { 472 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 473 u_int8_t mac[IEEE80211_ADDR_LEN]; 474 u_int32_t data, s_seq, s_ant, s_led[3], dmasize; 475 u_int i, mode, freq, ee_mode, ant[2]; 476 const HAL_RATE_TABLE *rt; 477 478 /* 479 * Save some registers before a reset 480 */ 481 if (chanchange == AH_TRUE) { 482 s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0)); 483 s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA); 484 } else { 485 s_seq = 0; 486 s_ant = 1; 487 } 488 489 s_led[0] = AR5K_REG_READ(AR5K_AR5212_PCICFG) & 490 AR5K_AR5212_PCICFG_LEDSTATE; 491 s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR); 492 s_led[2] = AR5K_REG_READ(AR5K_AR5212_GPIODO); 493 494 if (chanchange == AH_TRUE && hal->ah_rf_banks != NULL) 495 ar5k_ar5212_get_rf_gain(hal); 496 497 if (ar5k_ar5212_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) 498 return (AH_FALSE); 499 500 /* 501 * Initialize operating mode 502 */ 503 hal->ah_op_mode = op_mode; 504 505 switch (channel->c_channel_flags & CHANNEL_MODES) { 506 case CHANNEL_A: 507 mode = AR5K_INI_VAL_11A; 508 freq = AR5K_INI_RFGAIN_5GHZ; 509 ee_mode = AR5K_EEPROM_MODE_11A; 510 break; 511 case CHANNEL_B: 512 mode = AR5K_INI_VAL_11B; 513 freq = AR5K_INI_RFGAIN_2GHZ; 514 ee_mode = AR5K_EEPROM_MODE_11B; 515 break; 516 case CHANNEL_G: 517 case CHANNEL_PUREG: 518 mode = AR5K_INI_VAL_11G; 519 freq = AR5K_INI_RFGAIN_2GHZ; 520 ee_mode = AR5K_EEPROM_MODE_11G; 521 break; 522 case CHANNEL_T: 523 mode = AR5K_INI_VAL_11A_TURBO; 524 freq = AR5K_INI_RFGAIN_5GHZ; 525 ee_mode = AR5K_EEPROM_MODE_11A; 526 break; 527 case CHANNEL_TG: 528 mode = AR5K_INI_VAL_11G_TURBO; 529 freq = AR5K_INI_RFGAIN_2GHZ; 530 ee_mode = AR5K_EEPROM_MODE_11G; 531 break; 532 case CHANNEL_XR: 533 mode = AR5K_INI_VAL_XR; 534 freq = AR5K_INI_RFGAIN_5GHZ; 535 ee_mode = AR5K_EEPROM_MODE_11A; 536 break; 537 default: 538 AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); 539 return (AH_FALSE); 540 } 541 542 /* PHY access enable */ 543 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); 544 545 /* 546 * Write initial mode and register settings 547 */ 548 ar5k_write_mode(hal, ar5212_mode, AR5K_ELEMENTS(ar5212_mode), mode); 549 ar5k_write_ini(hal, ar5212_ini, AR5K_ELEMENTS(ar5212_ini), chanchange); 550 551 switch (hal->ah_radio) { 552 case AR5K_AR5111: 553 ar5k_write_mode(hal, ar5212_ar5111_mode, 554 AR5K_ELEMENTS(ar5212_ar5111_mode), mode); 555 break; 556 case AR5K_AR5112: 557 ar5k_write_mode(hal, ar5212_ar5112_mode, 558 AR5K_ELEMENTS(ar5212_ar5112_mode), mode); 559 break; 560 case AR5K_AR5413: 561 ar5k_write_mode(hal, ar5413_mode, 562 AR5K_ELEMENTS(ar5413_mode), mode); 563 break; 564 case AR5K_AR2413: 565 AR5K_REG_WRITE(AR5K_AR5212_PHY(648), 0x018830c6); 566 ar5k_write_mode(hal, ar2413_mode, 567 AR5K_ELEMENTS(ar2413_mode), mode); 568 break; 569 case AR5K_AR2425: 570 AR5K_REG_WRITE(AR5K_AR5212_PHY(648), 0x018830c6); 571 if (mode == AR5K_INI_VAL_11B) 572 mode = AR5K_INI_VAL_11G; 573 ar5k_write_mode(hal, ar2425_mode, 574 AR5K_ELEMENTS(ar2425_mode), mode); 575 break; 576 default: 577 AR5K_PRINTF("invalid radio: %d\n", hal->ah_radio); 578 return (AH_FALSE); 579 } 580 581 if (hal->ah_radio == AR5K_AR5111) 582 ar5k_write_ini(hal, ar5111_bbgain, 583 AR5K_ELEMENTS(ar5111_bbgain), chanchange); 584 else 585 ar5k_write_ini(hal, ar5112_bbgain, 586 AR5K_ELEMENTS(ar5112_bbgain), chanchange); 587 588 /* 589 * Write initial RF gain settings 590 */ 591 if (ar5k_rfgain(hal, freq) == AH_FALSE) 592 return (AH_FALSE); 593 594 AR5K_DELAY(1000); 595 596 /* 597 * Set rate duration table 598 */ 599 rt = ar5k_ar5212_get_rate_table(hal, 600 channel->c_channel_flags & IEEE80211_CHAN_TURBO ? 601 HAL_MODE_TURBO : HAL_MODE_XR); 602 603 for (i = 0; i < rt->rt_rate_count; i++) { 604 AR5K_REG_WRITE(AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code), 605 ath_hal_computetxtime(hal, rt, 14, 606 rt->rt_info[i].r_control_rate, AH_FALSE)); 607 } 608 609 if ((channel->c_channel_flags & IEEE80211_CHAN_TURBO) == 0) { 610 rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_11B); 611 for (i = 0; i < rt->rt_rate_count; i++) { 612 data = AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code); 613 AR5K_REG_WRITE(data, 614 ath_hal_computetxtime(hal, rt, 14, 615 rt->rt_info[i].r_control_rate, AH_FALSE)); 616 if (rt->rt_info[i].r_short_preamble) { 617 AR5K_REG_WRITE(data + 618 (rt->rt_info[i].r_short_preamble << 2), 619 ath_hal_computetxtime(hal, rt, 14, 620 rt->rt_info[i].r_control_rate, AH_FALSE)); 621 } 622 } 623 } 624 625 /* Fix for first revision of the AR5112 RF chipset */ 626 if (hal->ah_radio >= AR5K_AR5112 && 627 hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 628 AR5K_REG_WRITE(AR5K_AR5212_PHY_CCKTXCTL, 629 AR5K_AR5212_PHY_CCKTXCTL_WORLD); 630 if (channel->c_channel_flags & IEEE80211_CHAN_OFDM) 631 data = 0xffb81020; 632 else 633 data = 0xffb80d20; 634 AR5K_REG_WRITE(AR5K_AR5212_PHY_FC, data); 635 } 636 637 /* 638 * Set TX power (XXX use txpower from net80211) 639 */ 640 if (ar5k_ar5212_txpower(hal, channel, 641 AR5K_TUNE_DEFAULT_TXPOWER) == AH_FALSE) 642 return (AH_FALSE); 643 644 /* 645 * Write RF registers 646 */ 647 if (ar5k_rfregs(hal, channel, mode) == AH_FALSE) 648 return (AH_FALSE); 649 650 /* 651 * Configure additional registers 652 */ 653 654 /* OFDM timings */ 655 if (channel->c_channel_flags & IEEE80211_CHAN_OFDM) { 656 u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, 657 ds_coef_man, clock; 658 659 clock = channel->c_channel_flags & IEEE80211_CHAN_T ? 80 : 40; 660 coef_scaled = ((5 * (clock << 24)) / 2) / channel->c_channel; 661 662 for (coef_exp = 31; coef_exp > 0; coef_exp--) 663 if ((coef_scaled >> coef_exp) & 0x1) 664 break; 665 666 if (!coef_exp) 667 return (AH_FALSE); 668 669 coef_exp = 14 - (coef_exp - 24); 670 coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); 671 ds_coef_man = coef_man >> (24 - coef_exp); 672 ds_coef_exp = coef_exp - 16; 673 674 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3, 675 AR5K_AR5212_PHY_TIMING_3_DSC_MAN, ds_coef_man); 676 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3, 677 AR5K_AR5212_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 678 } 679 680 if (hal->ah_radio == AR5K_AR5111) { 681 if (channel->c_channel_flags & IEEE80211_CHAN_B) 682 AR5K_REG_ENABLE_BITS(AR5K_AR5212_TXCFG, 683 AR5K_AR5212_TXCFG_B_MODE); 684 else 685 AR5K_REG_DISABLE_BITS(AR5K_AR5212_TXCFG, 686 AR5K_AR5212_TXCFG_B_MODE); 687 } 688 689 /* Set antenna mode */ 690 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x44), 691 hal->ah_antenna[ee_mode][0], 0xfffffc06); 692 693 if (freq == AR5K_INI_RFGAIN_2GHZ) 694 ant[0] = ant[1] = HAL_ANT_FIXED_B; 695 else 696 ant[0] = ant[1] = HAL_ANT_FIXED_A; 697 698 AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0, 699 hal->ah_antenna[ee_mode][ant[0]]); 700 AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1, 701 hal->ah_antenna[ee_mode][ant[1]]); 702 703 /* Commit values from EEPROM */ 704 if (hal->ah_radio == AR5K_AR5111) 705 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_FC, 706 AR5K_AR5212_PHY_FC_TX_CLIP, ee->ee_tx_clip); 707 708 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x5a), 709 AR5K_AR5212_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); 710 711 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x11), 712 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); 713 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x12), 714 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); 715 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x14), 716 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | 717 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); 718 719 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x0d), 720 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 721 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 722 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 723 (ee->ee_tx_frm2xpa_enable[ee_mode])); 724 725 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x0a), 726 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); 727 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x19), 728 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); 729 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49), 4, 0xffffff01); 730 731 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, 732 AR5K_AR5212_PHY_IQ_CORR_ENABLE | 733 (ee->ee_i_cal[ee_mode] << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S) | 734 ee->ee_q_cal[ee_mode]); 735 736 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 737 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_GAIN_2GHZ, 738 AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX, 739 ee->ee_margin_tx_rx[ee_mode]); 740 } 741 742 /* 743 * Restore saved values 744 */ 745 AR5K_REG_WRITE(AR5K_AR5212_DCU_SEQNUM(0), s_seq); 746 AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, s_ant); 747 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, s_led[0]); 748 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, s_led[1]); 749 AR5K_REG_WRITE(AR5K_AR5212_GPIODO, s_led[2]); 750 751 /* 752 * Misc 753 */ 754 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 755 ar5k_ar5212_set_associd(hal, mac, 0, 0); 756 ar5k_ar5212_set_opmode(hal); 757 AR5K_REG_WRITE(AR5K_AR5212_PISR, 0xffffffff); 758 AR5K_REG_WRITE(AR5K_AR5212_RSSI_THR, AR5K_TUNE_RSSI_THRES); 759 760 /* 761 * Set Rx/Tx DMA Configuration 762 * 763 * XXX Limit DMA size on PCI-E chipsets to 128 bytes because 764 * XXX we saw RX overruns and TX errors with higher values. 765 */ 766 dmasize = hal->ah_pci_express == AH_TRUE ? 767 AR5K_AR5212_DMASIZE_128B : AR5K_AR5212_DMASIZE_512B; 768 AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, AR5K_AR5212_TXCFG_SDMAMR, 769 dmasize | AR5K_AR5212_TXCFG_DMASIZE); 770 AR5K_REG_WRITE_BITS(AR5K_AR5212_RXCFG, AR5K_AR5212_RXCFG_SDMAMW, 771 dmasize); 772 773 /* 774 * Set channel and calibrate the PHY 775 */ 776 if (ar5k_channel(hal, channel) == AH_FALSE) 777 return (AH_FALSE); 778 779 /* 780 * Enable the PHY and wait until completion 781 */ 782 AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_ENABLE); 783 784 data = AR5K_REG_READ(AR5K_AR5212_PHY_RX_DELAY) & 785 AR5K_AR5212_PHY_RX_DELAY_M; 786 data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? 787 ((data << 2) / 22) : (data / 10); 788 789 AR5K_DELAY(100 + data); 790 791 /* 792 * Start calibration 793 */ 794 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, 795 AR5K_AR5212_PHY_AGCCTL_NF | 796 AR5K_AR5212_PHY_AGCCTL_CAL); 797 798 hal->ah_calibration = AH_FALSE; 799 if ((channel->c_channel_flags & IEEE80211_CHAN_B) == 0) { 800 hal->ah_calibration = AH_TRUE; 801 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_IQ, 802 AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX, 15); 803 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, 804 AR5K_AR5212_PHY_IQ_RUN); 805 } 806 807 /* 808 * Reset queues and start beacon timers at the end of the reset routine 809 */ 810 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { 811 AR5K_REG_WRITE_Q(AR5K_AR5212_DCU_QCUMASK(i), i); 812 if (ar5k_ar5212_reset_tx_queue(hal, i) == AH_FALSE) { 813 AR5K_PRINTF("failed to reset TX queue #%d\n", i); 814 return (AH_FALSE); 815 } 816 } 817 818 /* Pre-enable interrupts */ 819 ar5k_ar5212_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); 820 821 /* 822 * Set RF kill flags if supported by the device (read from the EEPROM) 823 */ 824 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { 825 ar5k_ar5212_set_gpio_input(hal, 0); 826 if ((hal->ah_gpio[0] = ar5k_ar5212_get_gpio(hal, 0)) == 0) 827 ar5k_ar5212_set_gpio_intr(hal, 0, 1); 828 else 829 ar5k_ar5212_set_gpio_intr(hal, 0, 0); 830 } 831 832 /* 833 * Set the 32MHz reference clock 834 */ 835 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCR, AR5K_AR5212_PHY_SCR_32MHZ); 836 AR5K_REG_WRITE(AR5K_AR5212_PHY_SLMT, AR5K_AR5212_PHY_SLMT_32MHZ); 837 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCAL, AR5K_AR5212_PHY_SCAL_32MHZ); 838 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCLOCK, AR5K_AR5212_PHY_SCLOCK_32MHZ); 839 AR5K_REG_WRITE(AR5K_AR5212_PHY_SDELAY, AR5K_AR5212_PHY_SDELAY_32MHZ); 840 AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, hal->ah_phy_spending); 841 842 /* 843 * Disable beacons and reset the register 844 */ 845 AR5K_REG_DISABLE_BITS(AR5K_AR5212_BEACON, 846 AR5K_AR5212_BEACON_ENABLE | AR5K_AR5212_BEACON_RESET_TSF); 847 848 return (AH_TRUE); 849 } 850 851 void 852 ar5k_ar5212_set_def_antenna(struct ath_hal *hal, u_int ant) 853 { 854 AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, ant); 855 } 856 857 u_int 858 ar5k_ar5212_get_def_antenna(struct ath_hal *hal) 859 { 860 return AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA); 861 } 862 863 void 864 ar5k_ar5212_set_opmode(struct ath_hal *hal) 865 { 866 u_int32_t pcu_reg, low_id, high_id; 867 868 pcu_reg = 0; 869 870 switch (hal->ah_op_mode) { 871 #ifndef IEEE80211_STA_ONLY 872 case IEEE80211_M_IBSS: 873 pcu_reg |= AR5K_AR5212_STA_ID1_ADHOC | 874 AR5K_AR5212_STA_ID1_DESC_ANTENNA; 875 break; 876 877 case IEEE80211_M_HOSTAP: 878 pcu_reg |= AR5K_AR5212_STA_ID1_AP | 879 AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA; 880 break; 881 #endif 882 883 case IEEE80211_M_STA: 884 case IEEE80211_M_MONITOR: 885 pcu_reg |= AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; 886 break; 887 888 default: 889 return; 890 } 891 892 /* 893 * Set PCU registers 894 */ 895 low_id = AR5K_LOW_ID(hal->ah_sta_id); 896 high_id = AR5K_HIGH_ID(hal->ah_sta_id); 897 AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); 898 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, pcu_reg | high_id); 899 900 return; 901 } 902 903 HAL_BOOL 904 ar5k_ar5212_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 905 { 906 u_int32_t i_pwr, q_pwr; 907 int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; 908 909 if (hal->ah_calibration == AH_FALSE || 910 AR5K_REG_READ(AR5K_AR5212_PHY_IQ) & AR5K_AR5212_PHY_IQ_RUN) 911 goto done; 912 913 hal->ah_calibration = AH_FALSE; 914 915 iq_corr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_CORR); 916 i_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_I); 917 q_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_Q); 918 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 919 q_coffd = q_pwr >> 6; 920 921 if (i_coffd == 0 || q_coffd == 0) 922 goto done; 923 924 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 925 q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; 926 927 /* Commit new IQ value */ 928 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, 929 AR5K_AR5212_PHY_IQ_CORR_ENABLE | 930 ((u_int32_t)q_coff) | 931 ((u_int32_t)i_coff << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S)); 932 933 done: 934 /* Start noise floor calibration */ 935 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, 936 AR5K_AR5212_PHY_AGCCTL_NF); 937 938 /* Request RF gain */ 939 if (channel->c_channel_flags & IEEE80211_CHAN_5GHZ) { 940 AR5K_REG_WRITE(AR5K_AR5212_PHY_PAPD_PROBE, 941 AR5K_REG_SM(hal->ah_txpower.txp_max, 942 AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER) | 943 AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT); 944 hal->ah_rf_gain = HAL_RFGAIN_READ_REQUESTED; 945 } 946 947 return (AH_TRUE); 948 } 949 950 /* 951 * Transmit functions 952 */ 953 954 HAL_BOOL 955 ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) 956 { 957 u_int32_t trigger_level, imr; 958 HAL_BOOL status = AH_FALSE; 959 960 /* 961 * Disable interrupts by setting the mask 962 */ 963 imr = ar5k_ar5212_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); 964 965 trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TXCFG), 966 AR5K_AR5212_TXCFG_TXFULL); 967 968 if (increase == AH_FALSE) { 969 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 970 goto done; 971 } else 972 trigger_level += 973 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 974 975 /* 976 * Update trigger level on success 977 */ 978 AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, 979 AR5K_AR5212_TXCFG_TXFULL, trigger_level); 980 status = AH_TRUE; 981 982 done: 983 /* 984 * Restore interrupt mask 985 */ 986 ar5k_ar5212_set_intr(hal, imr); 987 988 return (status); 989 } 990 991 int 992 ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, 993 const HAL_TXQ_INFO *queue_info) 994 { 995 u_int queue; 996 997 /* 998 * Get queue by type 999 */ 1000 if (queue_type == HAL_TX_QUEUE_DATA) { 1001 for (queue = HAL_TX_QUEUE_ID_DATA_MIN; 1002 hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; 1003 queue++) 1004 if (queue > HAL_TX_QUEUE_ID_DATA_MAX) 1005 return (-1); 1006 } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { 1007 queue = HAL_TX_QUEUE_ID_PSPOLL; 1008 } else if (queue_type == HAL_TX_QUEUE_BEACON) { 1009 queue = HAL_TX_QUEUE_ID_BEACON; 1010 } else if (queue_type == HAL_TX_QUEUE_CAB) { 1011 queue = HAL_TX_QUEUE_ID_CAB; 1012 } else 1013 return (-1); 1014 1015 /* 1016 * Setup internal queue structure 1017 */ 1018 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 1019 if (queue_info != NULL) { 1020 if (ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info) 1021 != AH_TRUE) 1022 return (-1); 1023 } 1024 hal->ah_txq[queue].tqi_type = queue_type; 1025 1026 AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); 1027 1028 return (queue); 1029 } 1030 1031 HAL_BOOL 1032 ar5k_ar5212_setup_tx_queueprops(struct ath_hal *hal, int queue, 1033 const HAL_TXQ_INFO *queue_info) 1034 { 1035 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1036 1037 if (hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE) 1038 return (AH_FALSE); 1039 1040 bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 1041 1042 if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && 1043 (queue_info->tqi_subtype >= HAL_WME_AC_VI) && 1044 (queue_info->tqi_subtype <= HAL_WME_UPSD)) 1045 hal->ah_txq[queue].tqi_flags |= 1046 AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 1047 1048 return (AH_TRUE); 1049 } 1050 1051 HAL_BOOL 1052 ar5k_ar5212_get_tx_queueprops(struct ath_hal *hal, int queue, 1053 HAL_TXQ_INFO *queue_info) 1054 { 1055 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1056 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO)); 1057 return (AH_TRUE); 1058 } 1059 1060 HAL_BOOL 1061 ar5k_ar5212_release_tx_queue(struct ath_hal *hal, u_int queue) 1062 { 1063 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1064 1065 /* This queue will be skipped in further operations */ 1066 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; 1067 AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); 1068 1069 return (AH_FALSE); 1070 } 1071 1072 HAL_BOOL 1073 ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue) 1074 { 1075 u_int32_t cw_min, cw_max, retry_lg, retry_sh; 1076 struct ieee80211_channel *channel = (struct ieee80211_channel*) 1077 &hal->ah_current_channel; 1078 HAL_TXQ_INFO *tq; 1079 1080 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1081 1082 tq = &hal->ah_txq[queue]; 1083 1084 if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) 1085 return (AH_TRUE); 1086 1087 /* 1088 * Set registers by channel mode 1089 */ 1090 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; 1091 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; 1092 hal->ah_aifs = AR5K_TUNE_AIFS; 1093 if (IEEE80211_IS_CHAN_XR(channel)) { 1094 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; 1095 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; 1096 hal->ah_aifs = AR5K_TUNE_AIFS_XR; 1097 } else if (IEEE80211_IS_CHAN_B(channel)) { 1098 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; 1099 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; 1100 hal->ah_aifs = AR5K_TUNE_AIFS_11B; 1101 } 1102 1103 /* 1104 * Set retry limits 1105 */ 1106 if (hal->ah_software_retry == AH_TRUE) { 1107 /* XXX Need to test this */ 1108 retry_lg = hal->ah_limit_tx_retries; 1109 retry_sh = retry_lg = 1110 retry_lg > AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY ? 1111 AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY : retry_lg; 1112 } else { 1113 retry_lg = AR5K_INIT_LG_RETRY; 1114 retry_sh = AR5K_INIT_SH_RETRY; 1115 } 1116 1117 AR5K_REG_WRITE(AR5K_AR5212_DCU_RETRY_LMT(queue), 1118 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 1119 AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY) | 1120 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 1121 AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY) | 1122 AR5K_REG_SM(retry_lg, AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY) | 1123 AR5K_REG_SM(retry_sh, AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY)); 1124 1125 /* 1126 * Set initial content window (cw_min/cw_max) 1127 */ 1128 cw_min = 1; 1129 while (cw_min < hal->ah_cw_min) 1130 cw_min = (cw_min << 1) | 1; 1131 1132 cw_min = tq->tqi_cw_min < 0 ? 1133 (cw_min >> (-tq->tqi_cw_min)) : 1134 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 1135 cw_max = tq->tqi_cw_max < 0 ? 1136 (cw_max >> (-tq->tqi_cw_max)) : 1137 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 1138 1139 AR5K_REG_WRITE(AR5K_AR5212_DCU_LCL_IFS(queue), 1140 AR5K_REG_SM(cw_min, AR5K_AR5212_DCU_LCL_IFS_CW_MIN) | 1141 AR5K_REG_SM(cw_max, AR5K_AR5212_DCU_LCL_IFS_CW_MAX) | 1142 AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, 1143 AR5K_AR5212_DCU_LCL_IFS_AIFS)); 1144 1145 /* 1146 * Set misc registers 1147 */ 1148 AR5K_REG_WRITE(AR5K_AR5212_QCU_MISC(queue), 1149 AR5K_AR5212_QCU_MISC_DCU_EARLY); 1150 1151 if (tq->tqi_cbr_period) { 1152 AR5K_REG_WRITE(AR5K_AR5212_QCU_CBRCFG(queue), 1153 AR5K_REG_SM(tq->tqi_cbr_period, 1154 AR5K_AR5212_QCU_CBRCFG_INTVAL) | 1155 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 1156 AR5K_AR5212_QCU_CBRCFG_ORN_THRES)); 1157 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1158 AR5K_AR5212_QCU_MISC_FRSHED_CBR); 1159 if (tq->tqi_cbr_overflow_limit) 1160 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1161 AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE); 1162 } 1163 1164 if (tq->tqi_ready_time) { 1165 AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), 1166 AR5K_REG_SM(tq->tqi_ready_time, 1167 AR5K_AR5212_QCU_RDYTIMECFG_INTVAL) | 1168 AR5K_AR5212_QCU_RDYTIMECFG_ENABLE); 1169 } 1170 1171 if (tq->tqi_burst_time) { 1172 AR5K_REG_WRITE(AR5K_AR5212_DCU_CHAN_TIME(queue), 1173 AR5K_REG_SM(tq->tqi_burst_time, 1174 AR5K_AR5212_DCU_CHAN_TIME_DUR) | 1175 AR5K_AR5212_DCU_CHAN_TIME_ENABLE); 1176 1177 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { 1178 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1179 AR5K_AR5212_QCU_MISC_TXE); 1180 } 1181 } 1182 1183 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { 1184 AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), 1185 AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS); 1186 } 1187 1188 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 1189 AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), 1190 AR5K_AR5212_DCU_MISC_BACKOFF_FRAG); 1191 } 1192 1193 /* 1194 * Set registers by queue type 1195 */ 1196 switch (tq->tqi_type) { 1197 case HAL_TX_QUEUE_BEACON: 1198 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1199 AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | 1200 AR5K_AR5212_QCU_MISC_CBREXP_BCN | 1201 AR5K_AR5212_QCU_MISC_BCN_ENABLE); 1202 1203 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), 1204 (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1205 AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL) | 1206 AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS | 1207 AR5K_AR5212_DCU_MISC_BCN_ENABLE); 1208 1209 AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), 1210 ((AR5K_TUNE_BEACON_INTERVAL - 1211 (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - 1212 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | 1213 AR5K_AR5212_QCU_RDYTIMECFG_ENABLE); 1214 break; 1215 1216 case HAL_TX_QUEUE_CAB: 1217 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1218 AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | 1219 AR5K_AR5212_QCU_MISC_CBREXP | 1220 AR5K_AR5212_QCU_MISC_CBREXP_BCN); 1221 1222 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), 1223 (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1224 AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL)); 1225 break; 1226 1227 case HAL_TX_QUEUE_PSPOLL: 1228 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1229 AR5K_AR5212_QCU_MISC_CBREXP); 1230 break; 1231 1232 case HAL_TX_QUEUE_DATA: 1233 default: 1234 break; 1235 } 1236 1237 /* 1238 * Enable tx queue in the secondary interrupt mask registers 1239 */ 1240 AR5K_REG_WRITE(AR5K_AR5212_SIMR0, 1241 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) | 1242 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC)); 1243 AR5K_REG_WRITE(AR5K_AR5212_SIMR1, 1244 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR)); 1245 AR5K_REG_WRITE(AR5K_AR5212_SIMR2, 1246 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN)); 1247 1248 return (AH_TRUE); 1249 } 1250 1251 u_int32_t 1252 ar5k_ar5212_get_tx_buf(struct ath_hal *hal, u_int queue) 1253 { 1254 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1255 1256 /* 1257 * Get the transmit queue descriptor pointer from the selected queue 1258 */ 1259 return (AR5K_REG_READ(AR5K_AR5212_QCU_TXDP(queue))); 1260 } 1261 1262 HAL_BOOL 1263 ar5k_ar5212_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) 1264 { 1265 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1266 1267 /* 1268 * Set the transmit queue descriptor pointer for the selected queue 1269 * (this won't work if the queue is still active) 1270 */ 1271 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, queue)) 1272 return (AH_FALSE); 1273 1274 AR5K_REG_WRITE(AR5K_AR5212_QCU_TXDP(queue), phys_addr); 1275 1276 return (AH_TRUE); 1277 } 1278 1279 u_int32_t 1280 ar5k_ar5212_num_tx_pending(struct ath_hal *hal, u_int queue) 1281 { 1282 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1283 return (AR5K_AR5212_QCU_STS(queue) & AR5K_AR5212_QCU_STS_FRMPENDCNT); 1284 } 1285 1286 HAL_BOOL 1287 ar5k_ar5212_tx_start(struct ath_hal *hal, u_int queue) 1288 { 1289 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1290 1291 /* Return if queue is disabled */ 1292 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXD, queue)) 1293 return (AH_FALSE); 1294 1295 /* Start queue */ 1296 AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXE, queue); 1297 1298 return (AH_TRUE); 1299 } 1300 1301 HAL_BOOL 1302 ar5k_ar5212_stop_tx_dma(struct ath_hal *hal, u_int queue) 1303 { 1304 int i = 100, pending; 1305 1306 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1307 1308 /* 1309 * Schedule TX disable and wait until queue is empty 1310 */ 1311 AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXD, queue); 1312 1313 do { 1314 pending = AR5K_REG_READ(AR5K_AR5212_QCU_STS(queue)) & 1315 AR5K_AR5212_QCU_STS_FRMPENDCNT; 1316 delay(100); 1317 } while (--i && pending); 1318 1319 /* Clear register */ 1320 AR5K_REG_WRITE(AR5K_AR5212_QCU_TXD, 0); 1321 1322 return (AH_TRUE); 1323 } 1324 1325 HAL_BOOL 1326 ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1327 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, 1328 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, 1329 u_int flags, u_int rtscts_rate, u_int rtscts_duration) 1330 { 1331 struct ar5k_ar5212_tx_desc *tx_desc; 1332 1333 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1334 1335 /* 1336 * Validate input 1337 */ 1338 if (tx_tries0 == 0) 1339 return (AH_FALSE); 1340 1341 if ((tx_desc->tx_control_0 = (packet_length & 1342 AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length) 1343 return (AH_FALSE); 1344 1345 tx_desc->tx_control_0 |= 1346 AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) | 1347 AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT); 1348 tx_desc->tx_control_1 = 1349 AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE); 1350 tx_desc->tx_control_2 = 1351 AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, 1352 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0); 1353 tx_desc->tx_control_3 = 1354 tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; 1355 1356 #define _TX_FLAGS(_c, _flag) \ 1357 if (flags & HAL_TXDESC_##_flag) \ 1358 tx_desc->tx_control_##_c |= \ 1359 AR5K_AR5212_DESC_TX_CTL##_c##_##_flag 1360 1361 _TX_FLAGS(0, CLRDMASK); 1362 _TX_FLAGS(0, VEOL); 1363 _TX_FLAGS(0, INTREQ); 1364 _TX_FLAGS(0, RTSENA); 1365 _TX_FLAGS(0, CTSENA); 1366 _TX_FLAGS(1, NOACK); 1367 1368 #undef _TX_FLAGS 1369 1370 /* 1371 * WEP crap 1372 */ 1373 if (key_index != HAL_TXKEYIX_INVALID) { 1374 tx_desc->tx_control_0 |= 1375 AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID; 1376 tx_desc->tx_control_1 |= 1377 AR5K_REG_SM(key_index, 1378 AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); 1379 } 1380 1381 /* 1382 * RTS/CTS 1383 */ 1384 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 1385 if ((flags & HAL_TXDESC_RTSENA) && 1386 (flags & HAL_TXDESC_CTSENA)) 1387 return (AH_FALSE); 1388 tx_desc->tx_control_2 |= 1389 rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION; 1390 tx_desc->tx_control_3 |= 1391 AR5K_REG_SM(rtscts_rate, 1392 AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE); 1393 } 1394 1395 return (AH_TRUE); 1396 } 1397 1398 HAL_BOOL 1399 ar5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1400 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment) 1401 { 1402 struct ar5k_ar5212_tx_desc *tx_desc; 1403 struct ar5k_ar5212_tx_status *tx_status; 1404 1405 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1406 tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2]; 1407 1408 /* Clear status descriptor */ 1409 bzero(tx_status, sizeof(struct ar5k_ar5212_tx_status)); 1410 1411 /* Validate segment length and initialize the descriptor */ 1412 if (segment_length & ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN) 1413 return (AH_FALSE); 1414 tx_desc->tx_control_1 = 1415 #if 0 1416 (tx_desc->tx_control_1 & ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN) | 1417 #endif 1418 segment_length; 1419 1420 if (first_segment != AH_TRUE) 1421 tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN; 1422 1423 if (last_segment != AH_TRUE) 1424 tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE; 1425 1426 return (AH_TRUE); 1427 } 1428 1429 HAL_BOOL 1430 ar5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, 1431 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 1432 u_int tx_rate3, u_int tx_tries3) 1433 { 1434 struct ar5k_ar5212_tx_desc *tx_desc; 1435 1436 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1437 1438 #define _XTX_TRIES(_n) \ 1439 if (tx_tries##_n) { \ 1440 tx_desc->tx_control_2 |= \ 1441 AR5K_REG_SM(tx_tries##_n, \ 1442 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n); \ 1443 tx_desc->tx_control_3 |= \ 1444 AR5K_REG_SM(tx_rate##_n, \ 1445 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n); \ 1446 } 1447 1448 _XTX_TRIES(1); 1449 _XTX_TRIES(2); 1450 _XTX_TRIES(3); 1451 1452 #undef _XTX_TRIES 1453 1454 return (AH_TRUE); 1455 } 1456 1457 HAL_STATUS 1458 ar5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) 1459 { 1460 struct ar5k_ar5212_tx_status *tx_status; 1461 struct ar5k_ar5212_tx_desc *tx_desc; 1462 1463 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1464 tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2]; 1465 1466 /* No frame has been send or error */ 1467 if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE) == 0) 1468 return (HAL_EINPROGRESS); 1469 1470 /* 1471 * Get descriptor status 1472 */ 1473 desc->ds_us.tx.ts_tstamp = 1474 AR5K_REG_MS(tx_status->tx_status_0, 1475 AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP); 1476 desc->ds_us.tx.ts_shortretry = 1477 AR5K_REG_MS(tx_status->tx_status_0, 1478 AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT); 1479 desc->ds_us.tx.ts_longretry = 1480 AR5K_REG_MS(tx_status->tx_status_0, 1481 AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT); 1482 desc->ds_us.tx.ts_seqnum = 1483 AR5K_REG_MS(tx_status->tx_status_1, 1484 AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM); 1485 desc->ds_us.tx.ts_rssi = 1486 AR5K_REG_MS(tx_status->tx_status_1, 1487 AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 1488 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & 1489 AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; 1490 desc->ds_us.tx.ts_status = 0; 1491 1492 switch (AR5K_REG_MS(tx_status->tx_status_1, 1493 AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX)) { 1494 case 0: 1495 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & 1496 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; 1497 break; 1498 case 1: 1499 desc->ds_us.tx.ts_rate = 1500 AR5K_REG_MS(tx_desc->tx_control_3, 1501 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1); 1502 desc->ds_us.tx.ts_longretry += 1503 AR5K_REG_MS(tx_desc->tx_control_2, 1504 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1); 1505 break; 1506 case 2: 1507 desc->ds_us.tx.ts_rate = 1508 AR5K_REG_MS(tx_desc->tx_control_3, 1509 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2); 1510 desc->ds_us.tx.ts_longretry += 1511 AR5K_REG_MS(tx_desc->tx_control_2, 1512 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2); 1513 break; 1514 case 3: 1515 desc->ds_us.tx.ts_rate = 1516 AR5K_REG_MS(tx_desc->tx_control_3, 1517 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3); 1518 desc->ds_us.tx.ts_longretry += 1519 AR5K_REG_MS(tx_desc->tx_control_2, 1520 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3); 1521 break; 1522 } 1523 1524 if ((tx_status->tx_status_0 & 1525 AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { 1526 if (tx_status->tx_status_0 & 1527 AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 1528 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; 1529 1530 if (tx_status->tx_status_0 & 1531 AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN) 1532 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; 1533 1534 if (tx_status->tx_status_0 & 1535 AR5K_AR5212_DESC_TX_STATUS0_FILTERED) 1536 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; 1537 } 1538 1539 return (HAL_OK); 1540 } 1541 1542 HAL_BOOL 1543 ar5k_ar5212_has_veol(struct ath_hal *hal) 1544 { 1545 return (AH_TRUE); 1546 } 1547 1548 /* 1549 * Receive functions 1550 */ 1551 1552 u_int32_t 1553 ar5k_ar5212_get_rx_buf(struct ath_hal *hal) 1554 { 1555 return (AR5K_REG_READ(AR5K_AR5212_RXDP)); 1556 } 1557 1558 void 1559 ar5k_ar5212_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) 1560 { 1561 AR5K_REG_WRITE(AR5K_AR5212_RXDP, phys_addr); 1562 } 1563 1564 void 1565 ar5k_ar5212_start_rx(struct ath_hal *hal) 1566 { 1567 AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXE); 1568 } 1569 1570 HAL_BOOL 1571 ar5k_ar5212_stop_rx_dma(struct ath_hal *hal) 1572 { 1573 int i; 1574 1575 AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXD); 1576 1577 /* 1578 * It may take some time to disable the DMA receive unit 1579 */ 1580 for (i = 2000; 1581 i > 0 && (AR5K_REG_READ(AR5K_AR5212_CR) & AR5K_AR5212_CR_RXE) != 0; 1582 i--) 1583 AR5K_DELAY(10); 1584 1585 return (i > 0 ? AH_TRUE : AH_FALSE); 1586 } 1587 1588 void 1589 ar5k_ar5212_start_rx_pcu(struct ath_hal *hal) 1590 { 1591 AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX); 1592 } 1593 1594 void 1595 ar5k_ar5212_stop_pcu_recv(struct ath_hal *hal) 1596 { 1597 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX); 1598 } 1599 1600 void 1601 ar5k_ar5212_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, 1602 u_int32_t filter1) 1603 { 1604 /* Set the multicat filter */ 1605 AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL0, filter0); 1606 AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL1, filter1); 1607 } 1608 1609 HAL_BOOL 1610 ar5k_ar5212_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) 1611 { 1612 if (index >= 64) { 1613 return (AH_FALSE); 1614 } else if (index >= 32) { 1615 AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL1, 1616 (1 << (index - 32))); 1617 } else { 1618 AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL0, 1619 (1 << index)); 1620 } 1621 1622 return (AH_TRUE); 1623 } 1624 1625 HAL_BOOL 1626 ar5k_ar5212_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) 1627 { 1628 1629 if (index >= 64) { 1630 return (AH_FALSE); 1631 } else if (index >= 32) { 1632 AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL1, 1633 (1 << (index - 32))); 1634 } else { 1635 AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL0, 1636 (1 << index)); 1637 } 1638 1639 return (AH_TRUE); 1640 } 1641 1642 u_int32_t 1643 ar5k_ar5212_get_rx_filter(struct ath_hal *hal) 1644 { 1645 u_int32_t data, filter = 0; 1646 1647 filter = AR5K_REG_READ(AR5K_AR5212_RX_FILTER); 1648 data = AR5K_REG_READ(AR5K_AR5212_PHY_ERR_FIL); 1649 1650 if (data & AR5K_AR5212_PHY_ERR_FIL_RADAR) 1651 filter |= HAL_RX_FILTER_PHYRADAR; 1652 if (data & (AR5K_AR5212_PHY_ERR_FIL_OFDM | 1653 AR5K_AR5212_PHY_ERR_FIL_CCK)) 1654 filter |= HAL_RX_FILTER_PHYERR; 1655 1656 return (filter); 1657 } 1658 1659 void 1660 ar5k_ar5212_set_rx_filter(struct ath_hal *hal, u_int32_t filter) 1661 { 1662 u_int32_t data = 0; 1663 1664 if (filter & HAL_RX_FILTER_PHYRADAR) 1665 data |= AR5K_AR5212_PHY_ERR_FIL_RADAR; 1666 if (filter & HAL_RX_FILTER_PHYERR) 1667 data |= AR5K_AR5212_PHY_ERR_FIL_OFDM | 1668 AR5K_AR5212_PHY_ERR_FIL_CCK; 1669 1670 if (data) { 1671 AR5K_REG_ENABLE_BITS(AR5K_AR5212_RXCFG, 1672 AR5K_AR5212_RXCFG_ZLFDMA); 1673 } else { 1674 AR5K_REG_DISABLE_BITS(AR5K_AR5212_RXCFG, 1675 AR5K_AR5212_RXCFG_ZLFDMA); 1676 } 1677 1678 AR5K_REG_WRITE(AR5K_AR5212_RX_FILTER, filter & 0xff); 1679 AR5K_REG_WRITE(AR5K_AR5212_PHY_ERR_FIL, data); 1680 } 1681 1682 HAL_BOOL 1683 ar5k_ar5212_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1684 u_int32_t size, u_int flags) 1685 { 1686 struct ar5k_ar5212_rx_desc *rx_desc; 1687 1688 rx_desc = (struct ar5k_ar5212_rx_desc*)&desc->ds_ctl0; 1689 1690 if ((rx_desc->rx_control_1 = (size & 1691 AR5K_AR5212_DESC_RX_CTL1_BUF_LEN)) != size) 1692 return (AH_FALSE); 1693 1694 if (flags & HAL_RXDESC_INTREQ) 1695 rx_desc->rx_control_1 |= AR5K_AR5212_DESC_RX_CTL1_INTREQ; 1696 1697 return (AH_TRUE); 1698 } 1699 1700 HAL_STATUS 1701 ar5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1702 u_int32_t phys_addr, struct ath_desc *next) 1703 { 1704 struct ar5k_ar5212_rx_status *rx_status; 1705 struct ar5k_ar5212_rx_error *rx_err; 1706 1707 rx_status = (struct ar5k_ar5212_rx_status*)&desc->ds_hw[0]; 1708 1709 /* Overlay on error */ 1710 rx_err = (struct ar5k_ar5212_rx_error*)&desc->ds_hw[0]; 1711 1712 /* No frame received / not ready */ 1713 if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0) 1714 return (HAL_EINPROGRESS); 1715 1716 /* 1717 * Frame receive status 1718 */ 1719 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 1720 AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN; 1721 desc->ds_us.rx.rs_rssi = 1722 AR5K_REG_MS(rx_status->rx_status_0, 1723 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL); 1724 desc->ds_us.rx.rs_rate = 1725 AR5K_REG_MS(rx_status->rx_status_0, 1726 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE); 1727 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 1728 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA; 1729 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 1730 AR5K_AR5212_DESC_RX_STATUS0_MORE; 1731 desc->ds_us.rx.rs_tstamp = 1732 AR5K_REG_MS(rx_status->rx_status_1, 1733 AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); 1734 desc->ds_us.rx.rs_status = 0; 1735 1736 /* 1737 * Key table status 1738 */ 1739 if (rx_status->rx_status_1 & 1740 AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID) { 1741 desc->ds_us.rx.rs_keyix = 1742 AR5K_REG_MS(rx_status->rx_status_1, 1743 AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX); 1744 } else { 1745 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; 1746 } 1747 1748 /* 1749 * Receive/descriptor errors 1750 */ 1751 if ((rx_status->rx_status_1 & 1752 AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { 1753 if (rx_status->rx_status_1 & 1754 AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR) 1755 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; 1756 1757 if (rx_status->rx_status_1 & 1758 AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) { 1759 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; 1760 desc->ds_us.rx.rs_phyerr = 1761 AR5K_REG_MS(rx_err->rx_error_1, 1762 AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE); 1763 } 1764 1765 if (rx_status->rx_status_1 & 1766 AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) 1767 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; 1768 1769 if (rx_status->rx_status_1 & 1770 AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR) 1771 desc->ds_us.rx.rs_status |= HAL_RXERR_MIC; 1772 } 1773 1774 return (HAL_OK); 1775 } 1776 1777 void 1778 ar5k_ar5212_set_rx_signal(struct ath_hal *hal) 1779 { 1780 /* Signal state monitoring is not yet supported */ 1781 } 1782 1783 /* 1784 * Misc functions 1785 */ 1786 1787 void 1788 ar5k_ar5212_dump_state(struct ath_hal *hal) 1789 { 1790 #ifdef AR5K_DEBUG 1791 #define AR5K_PRINT_REGISTER(_x) \ 1792 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5212_##_x)); 1793 1794 printf("MAC registers:\n"); 1795 AR5K_PRINT_REGISTER(CR); 1796 AR5K_PRINT_REGISTER(CFG); 1797 AR5K_PRINT_REGISTER(IER); 1798 AR5K_PRINT_REGISTER(TXCFG); 1799 AR5K_PRINT_REGISTER(RXCFG); 1800 AR5K_PRINT_REGISTER(MIBC); 1801 AR5K_PRINT_REGISTER(TOPS); 1802 AR5K_PRINT_REGISTER(RXNOFRM); 1803 AR5K_PRINT_REGISTER(RPGTO); 1804 AR5K_PRINT_REGISTER(RFCNT); 1805 AR5K_PRINT_REGISTER(MISC); 1806 AR5K_PRINT_REGISTER(PISR); 1807 AR5K_PRINT_REGISTER(SISR0); 1808 AR5K_PRINT_REGISTER(SISR1); 1809 AR5K_PRINT_REGISTER(SISR3); 1810 AR5K_PRINT_REGISTER(SISR4); 1811 AR5K_PRINT_REGISTER(DCM_ADDR); 1812 AR5K_PRINT_REGISTER(DCM_DATA); 1813 AR5K_PRINT_REGISTER(DCCFG); 1814 AR5K_PRINT_REGISTER(CCFG); 1815 AR5K_PRINT_REGISTER(CCFG_CUP); 1816 AR5K_PRINT_REGISTER(CPC0); 1817 AR5K_PRINT_REGISTER(CPC1); 1818 AR5K_PRINT_REGISTER(CPC2); 1819 AR5K_PRINT_REGISTER(CPCORN); 1820 AR5K_PRINT_REGISTER(QCU_TXE); 1821 AR5K_PRINT_REGISTER(QCU_TXD); 1822 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); 1823 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); 1824 AR5K_PRINT_REGISTER(DCU_FP); 1825 AR5K_PRINT_REGISTER(DCU_TXP); 1826 AR5K_PRINT_REGISTER(DCU_TX_FILTER); 1827 AR5K_PRINT_REGISTER(RC); 1828 AR5K_PRINT_REGISTER(SCR); 1829 AR5K_PRINT_REGISTER(INTPEND); 1830 AR5K_PRINT_REGISTER(PCICFG); 1831 AR5K_PRINT_REGISTER(GPIOCR); 1832 AR5K_PRINT_REGISTER(GPIODO); 1833 AR5K_PRINT_REGISTER(SREV); 1834 AR5K_PRINT_REGISTER(EEPROM_BASE); 1835 AR5K_PRINT_REGISTER(EEPROM_DATA); 1836 AR5K_PRINT_REGISTER(EEPROM_CMD); 1837 AR5K_PRINT_REGISTER(EEPROM_CFG); 1838 AR5K_PRINT_REGISTER(PCU_MIN); 1839 AR5K_PRINT_REGISTER(STA_ID0); 1840 AR5K_PRINT_REGISTER(STA_ID1); 1841 AR5K_PRINT_REGISTER(BSS_ID0); 1842 AR5K_PRINT_REGISTER(SLOT_TIME); 1843 AR5K_PRINT_REGISTER(TIME_OUT); 1844 AR5K_PRINT_REGISTER(RSSI_THR); 1845 AR5K_PRINT_REGISTER(BEACON); 1846 AR5K_PRINT_REGISTER(CFP_PERIOD); 1847 AR5K_PRINT_REGISTER(TIMER0); 1848 AR5K_PRINT_REGISTER(TIMER2); 1849 AR5K_PRINT_REGISTER(TIMER3); 1850 AR5K_PRINT_REGISTER(CFP_DUR); 1851 AR5K_PRINT_REGISTER(MCAST_FIL0); 1852 AR5K_PRINT_REGISTER(MCAST_FIL1); 1853 AR5K_PRINT_REGISTER(DIAG_SW); 1854 AR5K_PRINT_REGISTER(TSF_U32); 1855 AR5K_PRINT_REGISTER(ADDAC_TEST); 1856 AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); 1857 AR5K_PRINT_REGISTER(LAST_TSTP); 1858 AR5K_PRINT_REGISTER(NAV); 1859 AR5K_PRINT_REGISTER(RTS_OK); 1860 AR5K_PRINT_REGISTER(ACK_FAIL); 1861 AR5K_PRINT_REGISTER(FCS_FAIL); 1862 AR5K_PRINT_REGISTER(BEACON_CNT); 1863 AR5K_PRINT_REGISTER(TSF_PARM); 1864 AR5K_PRINT_REGISTER(RATE_DUR_0); 1865 AR5K_PRINT_REGISTER(KEYTABLE_0); 1866 printf("\n"); 1867 1868 printf("PHY registers:\n"); 1869 AR5K_PRINT_REGISTER(PHY_TURBO); 1870 AR5K_PRINT_REGISTER(PHY_AGC); 1871 AR5K_PRINT_REGISTER(PHY_TIMING_3); 1872 AR5K_PRINT_REGISTER(PHY_CHIP_ID); 1873 AR5K_PRINT_REGISTER(PHY_AGCCTL); 1874 AR5K_PRINT_REGISTER(PHY_NF); 1875 AR5K_PRINT_REGISTER(PHY_SCR); 1876 AR5K_PRINT_REGISTER(PHY_SLMT); 1877 AR5K_PRINT_REGISTER(PHY_SCAL); 1878 AR5K_PRINT_REGISTER(PHY_RX_DELAY); 1879 AR5K_PRINT_REGISTER(PHY_IQ); 1880 AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); 1881 AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1); 1882 AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2); 1883 AR5K_PRINT_REGISTER(PHY_FC); 1884 AR5K_PRINT_REGISTER(PHY_RADAR); 1885 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); 1886 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); 1887 printf("\n"); 1888 #endif 1889 } 1890 1891 HAL_BOOL 1892 ar5k_ar5212_get_diag_state(struct ath_hal *hal, int id, void **device, 1893 u_int *size) 1894 { 1895 /* 1896 * We'll ignore this right now. This seems to be some kind of an obscure 1897 * debugging interface for the binary-only HAL. 1898 */ 1899 return (AH_FALSE); 1900 } 1901 1902 void 1903 ar5k_ar5212_get_lladdr(struct ath_hal *hal, u_int8_t *mac) 1904 { 1905 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); 1906 } 1907 1908 HAL_BOOL 1909 ar5k_ar5212_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) 1910 { 1911 u_int32_t low_id, high_id; 1912 1913 /* Set new station ID */ 1914 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); 1915 1916 low_id = AR5K_LOW_ID(mac); 1917 high_id = 0x0000ffff & AR5K_HIGH_ID(mac); 1918 1919 AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); 1920 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, high_id); 1921 1922 return (AH_TRUE); 1923 } 1924 1925 HAL_BOOL 1926 ar5k_ar5212_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, 1927 HAL_STATUS *status) 1928 { 1929 ieee80211_regdomain_t ieee_regdomain; 1930 1931 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); 1932 1933 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, 1934 &ieee_regdomain) == AH_TRUE) { 1935 *status = HAL_OK; 1936 return (AH_TRUE); 1937 } 1938 1939 *status = EIO; 1940 1941 return (AH_FALSE); 1942 } 1943 1944 void 1945 ar5k_ar5212_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) 1946 { 1947 u_int32_t led; 1948 1949 AR5K_REG_DISABLE_BITS(AR5K_AR5212_PCICFG, 1950 AR5K_AR5212_PCICFG_LEDMODE | AR5K_AR5212_PCICFG_LED); 1951 1952 /* 1953 * Some blinking values, define at your wish 1954 */ 1955 switch (state) { 1956 case IEEE80211_S_SCAN: 1957 case IEEE80211_S_AUTH: 1958 led = AR5K_AR5212_PCICFG_LEDMODE_PROP | 1959 AR5K_AR5212_PCICFG_LED_PEND; 1960 break; 1961 1962 case IEEE80211_S_INIT: 1963 led = AR5K_AR5212_PCICFG_LEDMODE_PROP | 1964 AR5K_AR5212_PCICFG_LED_NONE; 1965 break; 1966 1967 case IEEE80211_S_ASSOC: 1968 case IEEE80211_S_RUN: 1969 led = AR5K_AR5212_PCICFG_LEDMODE_PROP | 1970 AR5K_AR5212_PCICFG_LED_ASSOC; 1971 break; 1972 1973 default: 1974 led = AR5K_AR5212_PCICFG_LEDMODE_PROM | 1975 AR5K_AR5212_PCICFG_LED_NONE; 1976 break; 1977 } 1978 1979 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, led); 1980 } 1981 1982 void 1983 ar5k_ar5212_set_associd(struct ath_hal *hal, const u_int8_t *bssid, 1984 u_int16_t assoc_id, u_int16_t tim_offset) 1985 { 1986 u_int32_t low_id, high_id; 1987 1988 /* 1989 * Set simple BSSID mask 1990 */ 1991 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, 0xfffffff); 1992 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, 0xfffffff); 1993 1994 /* 1995 * Set BSSID which triggers the "SME Join" operation 1996 */ 1997 low_id = AR5K_LOW_ID(bssid); 1998 high_id = AR5K_HIGH_ID(bssid); 1999 AR5K_REG_WRITE(AR5K_AR5212_BSS_ID0, low_id); 2000 AR5K_REG_WRITE(AR5K_AR5212_BSS_ID1, high_id | 2001 ((assoc_id & 0x3fff) << AR5K_AR5212_BSS_ID1_AID_S)); 2002 bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN); 2003 2004 if (assoc_id == 0) { 2005 ar5k_ar5212_disable_pspoll(hal); 2006 return; 2007 } 2008 2009 AR5K_REG_WRITE(AR5K_AR5212_BEACON, 2010 (AR5K_REG_READ(AR5K_AR5212_BEACON) & 2011 ~AR5K_AR5212_BEACON_TIM) | 2012 (((tim_offset ? tim_offset + 4 : 0) << 2013 AR5K_AR5212_BEACON_TIM_S) & 2014 AR5K_AR5212_BEACON_TIM)); 2015 2016 ar5k_ar5212_enable_pspoll(hal, NULL, 0); 2017 } 2018 2019 HAL_BOOL 2020 ar5k_ar5212_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) 2021 { 2022 u_int32_t low_id, high_id; 2023 2024 low_id = AR5K_LOW_ID(mask); 2025 high_id = 0x0000ffff & AR5K_HIGH_ID(mask); 2026 2027 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, low_id); 2028 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, high_id); 2029 2030 return (AH_TRUE); 2031 } 2032 2033 HAL_BOOL 2034 ar5k_ar5212_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) 2035 { 2036 if (gpio > AR5K_AR5212_NUM_GPIO) 2037 return (AH_FALSE); 2038 2039 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, 2040 (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) 2041 | AR5K_AR5212_GPIOCR_ALL(gpio)); 2042 2043 return (AH_TRUE); 2044 } 2045 2046 HAL_BOOL 2047 ar5k_ar5212_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) 2048 { 2049 if (gpio > AR5K_AR5212_NUM_GPIO) 2050 return (AH_FALSE); 2051 2052 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, 2053 (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) 2054 | AR5K_AR5212_GPIOCR_NONE(gpio)); 2055 2056 return (AH_TRUE); 2057 } 2058 2059 u_int32_t 2060 ar5k_ar5212_get_gpio(struct ath_hal *hal, u_int32_t gpio) 2061 { 2062 if (gpio > AR5K_AR5212_NUM_GPIO) 2063 return (0xffffffff); 2064 2065 /* GPIO input magic */ 2066 return (((AR5K_REG_READ(AR5K_AR5212_GPIODI) & 2067 AR5K_AR5212_GPIODI_M) >> gpio) & 0x1); 2068 } 2069 2070 HAL_BOOL 2071 ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) 2072 { 2073 u_int32_t data; 2074 2075 if (gpio > AR5K_AR5212_NUM_GPIO) 2076 return (0xffffffff); 2077 2078 /* GPIO output magic */ 2079 data = AR5K_REG_READ(AR5K_AR5212_GPIODO); 2080 2081 data &= ~(1 << gpio); 2082 data |= (val&1) << gpio; 2083 2084 AR5K_REG_WRITE(AR5K_AR5212_GPIODO, data); 2085 2086 return (AH_TRUE); 2087 } 2088 2089 void 2090 ar5k_ar5212_set_gpio_intr(struct ath_hal *hal, u_int gpio, 2091 u_int32_t interrupt_level) 2092 { 2093 u_int32_t data; 2094 2095 if (gpio > AR5K_AR5212_NUM_GPIO) 2096 return; 2097 2098 /* 2099 * Set the GPIO interrupt 2100 */ 2101 data = (AR5K_REG_READ(AR5K_AR5212_GPIOCR) & 2102 ~(AR5K_AR5212_GPIOCR_INT_SEL(gpio) | AR5K_AR5212_GPIOCR_INT_SELH | 2103 AR5K_AR5212_GPIOCR_INT_ENA | AR5K_AR5212_GPIOCR_ALL(gpio))) | 2104 (AR5K_AR5212_GPIOCR_INT_SEL(gpio) | AR5K_AR5212_GPIOCR_INT_ENA); 2105 2106 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, 2107 interrupt_level ? data : (data | AR5K_AR5212_GPIOCR_INT_SELH)); 2108 2109 hal->ah_imr |= AR5K_AR5212_PIMR_GPIO; 2110 2111 /* Enable GPIO interrupts */ 2112 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, AR5K_AR5212_PIMR_GPIO); 2113 } 2114 2115 u_int32_t 2116 ar5k_ar5212_get_tsf32(struct ath_hal *hal) 2117 { 2118 return (AR5K_REG_READ(AR5K_AR5212_TSF_L32)); 2119 } 2120 2121 u_int64_t 2122 ar5k_ar5212_get_tsf64(struct ath_hal *hal) 2123 { 2124 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32); 2125 2126 return (AR5K_REG_READ(AR5K_AR5212_TSF_L32) | (tsf << 32)); 2127 } 2128 2129 void 2130 ar5k_ar5212_reset_tsf(struct ath_hal *hal) 2131 { 2132 AR5K_REG_ENABLE_BITS(AR5K_AR5212_BEACON, 2133 AR5K_AR5212_BEACON_RESET_TSF); 2134 } 2135 2136 u_int16_t 2137 ar5k_ar5212_get_regdomain(struct ath_hal *hal) 2138 { 2139 return (ar5k_get_regdomain(hal)); 2140 } 2141 2142 HAL_BOOL 2143 ar5k_ar5212_detect_card_present(struct ath_hal *hal) 2144 { 2145 u_int16_t magic; 2146 2147 /* 2148 * Checking the EEPROM's magic value could be an indication 2149 * if the card is still present. I didn't find another suitable 2150 * way to do this. 2151 */ 2152 if (ar5k_ar5212_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) 2153 return (AH_FALSE); 2154 2155 return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); 2156 } 2157 2158 void 2159 ar5k_ar5212_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) 2160 { 2161 /* Read-And-Clear */ 2162 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5212_ACK_FAIL); 2163 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5212_RTS_FAIL); 2164 statistics->rts_good += AR5K_REG_READ(AR5K_AR5212_RTS_OK); 2165 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5212_FCS_FAIL); 2166 statistics->beacons += AR5K_REG_READ(AR5K_AR5212_BEACON_CNT); 2167 2168 /* Reset profile count registers */ 2169 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_TX, 0); 2170 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RX, 0); 2171 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RXCLR, 0); 2172 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_CYCLE, 0); 2173 } 2174 2175 HAL_RFGAIN 2176 ar5k_ar5212_get_rf_gain(struct ath_hal *hal) 2177 { 2178 u_int32_t data, type; 2179 2180 if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active)) 2181 return (HAL_RFGAIN_INACTIVE); 2182 2183 if (hal->ah_rf_gain != HAL_RFGAIN_READ_REQUESTED) 2184 goto done; 2185 2186 data = AR5K_REG_READ(AR5K_AR5212_PHY_PAPD_PROBE); 2187 2188 if (!(data & AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT)) { 2189 hal->ah_gain.g_current = 2190 data >> AR5K_AR5212_PHY_PAPD_PROBE_GAINF_S; 2191 type = AR5K_REG_MS(data, AR5K_AR5212_PHY_PAPD_PROBE_TYPE); 2192 2193 if (type == AR5K_AR5212_PHY_PAPD_PROBE_TYPE_CCK) 2194 hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR; 2195 2196 if (hal->ah_radio >= AR5K_AR5112) { 2197 ar5k_rfregs_gainf_corr(hal); 2198 hal->ah_gain.g_current = 2199 hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? 2200 (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : 2201 0; 2202 } 2203 2204 if (ar5k_rfregs_gain_readback(hal) && 2205 AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && 2206 ar5k_rfregs_gain_adjust(hal)) 2207 hal->ah_rf_gain = HAL_RFGAIN_NEED_CHANGE; 2208 } 2209 2210 done: 2211 return (hal->ah_rf_gain); 2212 } 2213 2214 HAL_BOOL 2215 ar5k_ar5212_set_slot_time(struct ath_hal *hal, u_int slot_time) 2216 { 2217 if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) 2218 return (AH_FALSE); 2219 2220 AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT, slot_time); 2221 2222 return (AH_TRUE); 2223 } 2224 2225 u_int 2226 ar5k_ar5212_get_slot_time(struct ath_hal *hal) 2227 { 2228 return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff); 2229 } 2230 2231 HAL_BOOL 2232 ar5k_ar5212_set_ack_timeout(struct ath_hal *hal, u_int timeout) 2233 { 2234 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_ACK), 2235 hal->ah_turbo) <= timeout) 2236 return (AH_FALSE); 2237 2238 AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_ACK, 2239 ar5k_htoclock(timeout, hal->ah_turbo)); 2240 2241 return (AH_TRUE); 2242 } 2243 2244 u_int 2245 ar5k_ar5212_get_ack_timeout(struct ath_hal *hal) 2246 { 2247 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT), 2248 AR5K_AR5212_TIME_OUT_ACK), hal->ah_turbo)); 2249 } 2250 2251 HAL_BOOL 2252 ar5k_ar5212_set_cts_timeout(struct ath_hal *hal, u_int timeout) 2253 { 2254 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_CTS), 2255 hal->ah_turbo) <= timeout) 2256 return (AH_FALSE); 2257 2258 AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_CTS, 2259 ar5k_htoclock(timeout, hal->ah_turbo)); 2260 2261 return (AH_TRUE); 2262 } 2263 2264 u_int 2265 ar5k_ar5212_get_cts_timeout(struct ath_hal *hal) 2266 { 2267 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT), 2268 AR5K_AR5212_TIME_OUT_CTS), hal->ah_turbo)); 2269 } 2270 2271 /* 2272 * Key table (WEP) functions 2273 */ 2274 2275 HAL_BOOL 2276 ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) 2277 { 2278 /* 2279 * The AR5212 only supports WEP 2280 */ 2281 if (cipher == HAL_CIPHER_WEP) 2282 return (AH_TRUE); 2283 2284 return (AH_FALSE); 2285 } 2286 2287 u_int32_t 2288 ar5k_ar5212_get_keycache_size(struct ath_hal *hal) 2289 { 2290 return (AR5K_AR5212_KEYCACHE_SIZE); 2291 } 2292 2293 HAL_BOOL 2294 ar5k_ar5212_reset_key(struct ath_hal *hal, u_int16_t entry) 2295 { 2296 int i; 2297 2298 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2299 2300 for (i = 0; i < AR5K_AR5212_KEYCACHE_SIZE; i++) 2301 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), 0); 2302 2303 /* Set NULL encryption */ 2304 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_TYPE(entry), 2305 AR5K_AR5212_KEYTABLE_TYPE_NULL); 2306 2307 return (AH_FALSE); 2308 } 2309 2310 HAL_BOOL 2311 ar5k_ar5212_is_key_valid(struct ath_hal *hal, u_int16_t entry) 2312 { 2313 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2314 2315 /* 2316 * Check the validation flag at the end of the entry 2317 */ 2318 if (AR5K_REG_READ(AR5K_AR5212_KEYTABLE_MAC1(entry)) & 2319 AR5K_AR5212_KEYTABLE_VALID) 2320 return (AH_TRUE); 2321 2322 return (AH_FALSE); 2323 } 2324 2325 HAL_BOOL 2326 ar5k_ar5212_set_key(struct ath_hal *hal, u_int16_t entry, 2327 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) 2328 { 2329 int i; 2330 u_int32_t key_v[AR5K_AR5212_KEYCACHE_SIZE - 2]; 2331 2332 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2333 2334 bzero(&key_v, sizeof(key_v)); 2335 2336 switch (keyval->wk_len) { 2337 case AR5K_KEYVAL_LENGTH_40: 2338 bcopy(keyval->wk_key, &key_v[0], 4); 2339 bcopy(keyval->wk_key + 4, &key_v[1], 1); 2340 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_40; 2341 break; 2342 2343 case AR5K_KEYVAL_LENGTH_104: 2344 bcopy(keyval->wk_key, &key_v[0], 4); 2345 bcopy(keyval->wk_key + 4, &key_v[1], 2); 2346 bcopy(keyval->wk_key + 6, &key_v[2], 4); 2347 bcopy(keyval->wk_key + 10, &key_v[3], 2); 2348 bcopy(keyval->wk_key + 12, &key_v[4], 1); 2349 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_104; 2350 break; 2351 2352 case AR5K_KEYVAL_LENGTH_128: 2353 bcopy(keyval->wk_key, &key_v[0], 4); 2354 bcopy(keyval->wk_key + 4, &key_v[1], 2); 2355 bcopy(keyval->wk_key + 6, &key_v[2], 4); 2356 bcopy(keyval->wk_key + 10, &key_v[3], 2); 2357 bcopy(keyval->wk_key + 12, &key_v[4], 4); 2358 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_128; 2359 break; 2360 2361 default: 2362 /* Unsupported key length (not WEP40/104/128) */ 2363 return (AH_FALSE); 2364 } 2365 2366 for (i = 0; i < AR5K_ELEMENTS(key_v); i++) 2367 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), key_v[i]); 2368 2369 return (ar5k_ar5212_set_key_lladdr(hal, entry, mac)); 2370 } 2371 2372 HAL_BOOL 2373 ar5k_ar5212_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, 2374 const u_int8_t *mac) 2375 { 2376 u_int32_t low_id, high_id; 2377 const u_int8_t *mac_v; 2378 2379 /* 2380 * Invalid entry (key table overflow) 2381 */ 2382 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2383 2384 /* MAC may be NULL if it's a broadcast key */ 2385 mac_v = mac == NULL ? etherbroadcastaddr : mac; 2386 2387 low_id = AR5K_LOW_ID(mac_v); 2388 high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5212_KEYTABLE_VALID; 2389 2390 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC0(entry), low_id); 2391 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC1(entry), high_id); 2392 2393 return (AH_TRUE); 2394 } 2395 2396 HAL_BOOL 2397 ar5k_ar5212_softcrypto(struct ath_hal *hal, HAL_BOOL enable) 2398 { 2399 u_int32_t bits; 2400 int i; 2401 2402 bits = AR5K_AR5212_DIAG_SW_DIS_ENC | AR5K_AR5212_DIAG_SW_DIS_DEC; 2403 if (enable == AH_TRUE) { 2404 /* Disable the hardware crypto engine */ 2405 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, bits); 2406 } else { 2407 /* Enable the hardware crypto engine */ 2408 AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, bits); 2409 } 2410 2411 /* Reset the key cache */ 2412 for (i = 0; i < AR5K_AR5212_KEYTABLE_SIZE; i++) 2413 ar5k_ar5212_reset_key(hal, i); 2414 2415 return (AH_TRUE); 2416 } 2417 2418 /* 2419 * Power management functions 2420 */ 2421 2422 HAL_BOOL 2423 ar5k_ar5212_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, 2424 HAL_BOOL set_chip, u_int16_t sleep_duration) 2425 { 2426 u_int32_t staid; 2427 int i; 2428 2429 staid = AR5K_REG_READ(AR5K_AR5212_STA_ID1); 2430 2431 switch (mode) { 2432 case HAL_PM_AUTO: 2433 staid &= ~AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; 2434 /* FALLTHROUGH */ 2435 case HAL_PM_NETWORK_SLEEP: 2436 if (set_chip == AH_TRUE) { 2437 AR5K_REG_WRITE(AR5K_AR5212_SCR, 2438 AR5K_AR5212_SCR_SLE | sleep_duration); 2439 } 2440 staid |= AR5K_AR5212_STA_ID1_PWR_SV; 2441 break; 2442 2443 case HAL_PM_FULL_SLEEP: 2444 if (set_chip == AH_TRUE) { 2445 AR5K_REG_WRITE(AR5K_AR5212_SCR, 2446 AR5K_AR5212_SCR_SLE_SLP); 2447 } 2448 staid |= AR5K_AR5212_STA_ID1_PWR_SV; 2449 break; 2450 2451 case HAL_PM_AWAKE: 2452 if (set_chip == AH_FALSE) 2453 goto commit; 2454 2455 AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE_WAKE); 2456 2457 for (i = 5000; i > 0; i--) { 2458 /* Check if the AR5212 did wake up */ 2459 if ((AR5K_REG_READ(AR5K_AR5212_PCICFG) & 2460 AR5K_AR5212_PCICFG_SPWR_DN) == 0) 2461 break; 2462 2463 /* Wait a bit and retry */ 2464 AR5K_DELAY(200); 2465 AR5K_REG_WRITE(AR5K_AR5212_SCR, 2466 AR5K_AR5212_SCR_SLE_WAKE); 2467 } 2468 2469 /* Fail if the AR5212 didn't wake up */ 2470 if (i <= 0) 2471 return (AH_FALSE); 2472 2473 staid &= ~AR5K_AR5212_STA_ID1_PWR_SV; 2474 break; 2475 2476 default: 2477 return (AH_FALSE); 2478 } 2479 2480 commit: 2481 hal->ah_power_mode = mode; 2482 2483 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, staid); 2484 2485 return (AH_TRUE); 2486 } 2487 2488 HAL_POWER_MODE 2489 ar5k_ar5212_get_power_mode(struct ath_hal *hal) 2490 { 2491 return (hal->ah_power_mode); 2492 } 2493 2494 HAL_BOOL 2495 ar5k_ar5212_query_pspoll_support(struct ath_hal *hal) 2496 { 2497 /* nope */ 2498 return (AH_FALSE); 2499 } 2500 2501 HAL_BOOL 2502 ar5k_ar5212_init_pspoll(struct ath_hal *hal) 2503 { 2504 /* 2505 * Not used on the AR5212 2506 */ 2507 return (AH_FALSE); 2508 } 2509 2510 HAL_BOOL 2511 ar5k_ar5212_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, 2512 u_int16_t assoc_id) 2513 { 2514 return (AH_FALSE); 2515 } 2516 2517 HAL_BOOL 2518 ar5k_ar5212_disable_pspoll(struct ath_hal *hal) 2519 { 2520 return (AH_FALSE); 2521 } 2522 2523 /* 2524 * Beacon functions 2525 */ 2526 2527 void 2528 ar5k_ar5212_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, 2529 u_int32_t interval) 2530 { 2531 u_int32_t timer1, timer2, timer3; 2532 2533 /* 2534 * Set the additional timers by mode 2535 */ 2536 switch (hal->ah_op_mode) { 2537 case HAL_M_STA: 2538 timer1 = 0x0000ffff; 2539 timer2 = 0x0007ffff; 2540 break; 2541 2542 default: 2543 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 2544 0x00000003; 2545 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 2546 0x00000003; 2547 } 2548 2549 timer3 = next_beacon + 2550 (hal->ah_atim_window ? hal->ah_atim_window : 1); 2551 2552 /* 2553 * Enable all timers and set the beacon register 2554 * (next beacon, DMA beacon, software beacon, ATIM window time) 2555 */ 2556 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, next_beacon); 2557 AR5K_REG_WRITE(AR5K_AR5212_TIMER1, timer1); 2558 AR5K_REG_WRITE(AR5K_AR5212_TIMER2, timer2); 2559 AR5K_REG_WRITE(AR5K_AR5212_TIMER3, timer3); 2560 2561 AR5K_REG_WRITE(AR5K_AR5212_BEACON, interval & 2562 (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_RESET_TSF | 2563 AR5K_AR5212_BEACON_ENABLE)); 2564 } 2565 2566 void 2567 ar5k_ar5212_set_beacon_timers(struct ath_hal *hal, 2568 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, 2569 u_int32_t cfp_count) 2570 { 2571 u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; 2572 2573 /* Return on an invalid beacon state */ 2574 if (state->bs_interval < 1) 2575 return; 2576 2577 interval = state->bs_intval; 2578 dtim = state->bs_dtimperiod; 2579 2580 /* 2581 * PCF support? 2582 */ 2583 if (state->bs_cfp_period > 0) { 2584 /* Enable CFP mode and set the CFP and timer registers */ 2585 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 2586 state->bs_interval; 2587 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 2588 state->bs_interval; 2589 2590 AR5K_REG_ENABLE_BITS(AR5K_AR5212_STA_ID1, 2591 AR5K_AR5212_STA_ID1_PCF); 2592 AR5K_REG_WRITE(AR5K_AR5212_CFP_PERIOD, cfp_period); 2593 AR5K_REG_WRITE(AR5K_AR5212_CFP_DUR, state->bs_cfp_max_duration); 2594 AR5K_REG_WRITE(AR5K_AR5212_TIMER2, 2595 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); 2596 } else { 2597 /* Disable PCF mode */ 2598 AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1, 2599 AR5K_AR5212_STA_ID1_PCF); 2600 } 2601 2602 /* 2603 * Enable the beacon timer register 2604 */ 2605 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, state->bs_next_beacon); 2606 2607 /* 2608 * Start the beacon timers 2609 */ 2610 AR5K_REG_WRITE(AR5K_AR5212_BEACON, 2611 (AR5K_REG_READ(AR5K_AR5212_BEACON) &~ 2612 (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_TIM)) | 2613 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 2614 AR5K_AR5212_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 2615 AR5K_AR5212_BEACON_PERIOD)); 2616 2617 /* 2618 * Write new beacon miss threshold, if it appears to be valid 2619 */ 2620 if ((AR5K_AR5212_RSSI_THR_BMISS >> AR5K_AR5212_RSSI_THR_BMISS_S) < 2621 state->bs_bmiss_threshold) 2622 return; 2623 2624 AR5K_REG_WRITE_BITS(AR5K_AR5212_RSSI_THR_M, 2625 AR5K_AR5212_RSSI_THR_BMISS, state->bs_bmiss_threshold); 2626 2627 /* 2628 * Set sleep registers 2629 */ 2630 if ((state->bs_sleepduration > state->bs_interval) && 2631 (roundup(state->bs_sleepduration, interval) == 2632 state->bs_sleepduration)) 2633 interval = state->bs_sleepduration; 2634 2635 if (state->bs_sleepduration > dtim && 2636 (dtim == 0 || roundup(state->bs_sleepduration, dtim) == 2637 state->bs_sleepduration)) 2638 dtim = state->bs_sleepduration; 2639 2640 if (interval > dtim) 2641 return; 2642 2643 next_beacon = interval == dtim ? 2644 state->bs_nextdtim: state->bs_nexttbtt; 2645 2646 AR5K_REG_WRITE(AR5K_AR5212_SLEEP0, 2647 AR5K_REG_SM((state->bs_nextdtim - 3) << 3, 2648 AR5K_AR5212_SLEEP0_NEXT_DTIM) | 2649 AR5K_REG_SM(10, AR5K_AR5212_SLEEP0_CABTO) | 2650 AR5K_AR5212_SLEEP0_ENH_SLEEP_EN | 2651 AR5K_AR5212_SLEEP0_ASSUME_DTIM); 2652 AR5K_REG_WRITE(AR5K_AR5212_SLEEP1, 2653 AR5K_REG_SM((next_beacon - 3) << 3, 2654 AR5K_AR5212_SLEEP1_NEXT_TIM) | 2655 AR5K_REG_SM(10, AR5K_AR5212_SLEEP1_BEACON_TO)); 2656 AR5K_REG_WRITE(AR5K_AR5212_SLEEP2, 2657 AR5K_REG_SM(interval, AR5K_AR5212_SLEEP2_TIM_PER) | 2658 AR5K_REG_SM(dtim, AR5K_AR5212_SLEEP2_DTIM_PER)); 2659 } 2660 2661 void 2662 ar5k_ar5212_reset_beacon(struct ath_hal *hal) 2663 { 2664 /* 2665 * Disable beacon timer 2666 */ 2667 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, 0); 2668 2669 /* 2670 * Disable some beacon register values 2671 */ 2672 AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1, 2673 AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5212_STA_ID1_PCF); 2674 AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_AR5212_BEACON_PERIOD); 2675 } 2676 2677 HAL_BOOL 2678 ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr) 2679 { 2680 HAL_BOOL ret; 2681 2682 /* 2683 * Wait for beaconn queue to be done 2684 */ 2685 ret = ar5k_register_timeout(hal, 2686 AR5K_AR5212_QCU_STS(HAL_TX_QUEUE_ID_BEACON), 2687 AR5K_AR5212_QCU_STS_FRMPENDCNT, 0, AH_FALSE); 2688 2689 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) 2690 return (AH_FALSE); 2691 2692 return (ret); 2693 } 2694 2695 /* 2696 * Interrupt handling 2697 */ 2698 2699 HAL_BOOL 2700 ar5k_ar5212_is_intr_pending(struct ath_hal *hal) 2701 { 2702 return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? AH_FALSE : AH_TRUE); 2703 } 2704 2705 HAL_BOOL 2706 ar5k_ar5212_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) 2707 { 2708 u_int32_t data; 2709 2710 /* 2711 * Read interrupt status from the Read-And-Clear shadow register 2712 */ 2713 data = AR5K_REG_READ(AR5K_AR5212_RAC_PISR); 2714 2715 /* 2716 * Get abstract interrupt mask (HAL-compatible) 2717 */ 2718 *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; 2719 2720 if (data == HAL_INT_NOCARD) 2721 return (AH_FALSE); 2722 2723 if (data & (AR5K_AR5212_PISR_RXOK | AR5K_AR5212_PISR_RXERR)) 2724 *interrupt_mask |= HAL_INT_RX; 2725 2726 if (data & (AR5K_AR5212_PISR_TXOK | AR5K_AR5212_PISR_TXERR)) 2727 *interrupt_mask |= HAL_INT_TX; 2728 2729 if (data & (AR5K_AR5212_PISR_HIUERR)) 2730 *interrupt_mask |= HAL_INT_FATAL; 2731 2732 /* 2733 * Special interrupt handling (not caught by the driver) 2734 */ 2735 if (((*interrupt_mask) & AR5K_AR5212_PISR_RXPHY) && 2736 hal->ah_radar.r_enabled == AH_TRUE) 2737 ar5k_radar_alert(hal); 2738 2739 if (*interrupt_mask == 0) 2740 AR5K_PRINTF("0x%08x\n", data); 2741 2742 return (AH_TRUE); 2743 } 2744 2745 u_int32_t 2746 ar5k_ar5212_get_intr(struct ath_hal *hal) 2747 { 2748 /* Return the interrupt mask stored previously */ 2749 return (hal->ah_imr); 2750 } 2751 2752 HAL_INT 2753 ar5k_ar5212_set_intr(struct ath_hal *hal, HAL_INT new_mask) 2754 { 2755 HAL_INT old_mask, int_mask; 2756 2757 /* 2758 * Disable card interrupts to prevent any race conditions 2759 * (they will be re-enabled afterwards). 2760 */ 2761 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); 2762 2763 old_mask = hal->ah_imr; 2764 2765 /* 2766 * Add additional, chipset-dependent interrupt mask flags 2767 * and write them to the IMR (interrupt mask register). 2768 */ 2769 int_mask = new_mask & HAL_INT_COMMON; 2770 2771 if (new_mask & HAL_INT_RX) 2772 int_mask |= 2773 AR5K_AR5212_PIMR_RXOK | 2774 AR5K_AR5212_PIMR_RXERR | 2775 AR5K_AR5212_PIMR_RXORN | 2776 AR5K_AR5212_PIMR_RXDESC; 2777 2778 if (new_mask & HAL_INT_TX) 2779 int_mask |= 2780 AR5K_AR5212_PIMR_TXOK | 2781 AR5K_AR5212_PIMR_TXERR | 2782 AR5K_AR5212_PIMR_TXDESC | 2783 AR5K_AR5212_PIMR_TXURN; 2784 2785 if (new_mask & HAL_INT_FATAL) { 2786 int_mask |= AR5K_AR5212_PIMR_HIUERR; 2787 AR5K_REG_ENABLE_BITS(AR5K_AR5212_SIMR2, 2788 AR5K_AR5212_SIMR2_MCABT | 2789 AR5K_AR5212_SIMR2_SSERR | 2790 AR5K_AR5212_SIMR2_DPERR); 2791 } 2792 2793 AR5K_REG_WRITE(AR5K_AR5212_PIMR, int_mask); 2794 2795 /* Store new interrupt mask */ 2796 hal->ah_imr = new_mask; 2797 2798 /* ..re-enable interrupts */ 2799 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); 2800 2801 return (old_mask); 2802 } 2803 2804 /* 2805 * Misc internal functions 2806 */ 2807 2808 HAL_BOOL 2809 ar5k_ar5212_get_capabilities(struct ath_hal *hal) 2810 { 2811 u_int16_t ee_header; 2812 2813 /* Capabilities stored in the EEPROM */ 2814 ee_header = hal->ah_capabilities.cap_eeprom.ee_header; 2815 2816 /* 2817 * XXX The AR5212 tranceiver supports frequencies from 4920 to 6100GHz 2818 * XXX and from 2312 to 2732GHz. There are problems with the current 2819 * XXX ieee80211 implementation because the IEEE channel mapping 2820 * XXX does not support negative channel numbers (2312MHz is channel 2821 * XXX -19). Of course, this doesn't matter because these channels 2822 * XXX are out of range but some regulation domains like MKK (Japan) 2823 * XXX will support frequencies somewhere around 4.8GHz. 2824 */ 2825 2826 /* 2827 * Set radio capabilities 2828 */ 2829 2830 if (AR5K_EEPROM_HDR_11A(ee_header)) { 2831 hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ 2832 hal->ah_capabilities.cap_range.range_5ghz_max = 6100; 2833 2834 /* Set supported modes */ 2835 hal->ah_capabilities.cap_mode = 2836 HAL_MODE_11A | HAL_MODE_TURBO | HAL_MODE_XR; 2837 } 2838 2839 /* This chip will support 802.11b if the 2GHz radio is connected */ 2840 if (AR5K_EEPROM_HDR_11B(ee_header) || AR5K_EEPROM_HDR_11G(ee_header)) { 2841 hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ 2842 hal->ah_capabilities.cap_range.range_2ghz_max = 2732; 2843 2844 if (AR5K_EEPROM_HDR_11B(ee_header)) 2845 hal->ah_capabilities.cap_mode |= HAL_MODE_11B; 2846 #if 0 2847 if (AR5K_EEPROM_HDR_11G(ee_header)) 2848 hal->ah_capabilities.cap_mode |= HAL_MODE_11G; 2849 #endif 2850 } 2851 2852 /* GPIO */ 2853 hal->ah_gpio_npins = AR5K_AR5212_NUM_GPIO; 2854 2855 /* Set number of supported TX queues */ 2856 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5212_TX_NUM_QUEUES; 2857 2858 return (AH_TRUE); 2859 } 2860 2861 void 2862 ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable) 2863 { 2864 /* 2865 * Enable radar detection 2866 */ 2867 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); 2868 2869 if (enable == AH_TRUE) { 2870 AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, 2871 AR5K_AR5212_PHY_RADAR_ENABLE); 2872 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, 2873 AR5K_AR5212_PIMR_RXPHY); 2874 } else { 2875 AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, 2876 AR5K_AR5212_PHY_RADAR_DISABLE); 2877 AR5K_REG_DISABLE_BITS(AR5K_AR5212_PIMR, 2878 AR5K_AR5212_PIMR_RXPHY); 2879 } 2880 2881 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); 2882 } 2883 2884 /* 2885 * EEPROM access functions 2886 */ 2887 2888 HAL_BOOL 2889 ar5k_ar5212_eeprom_is_busy(struct ath_hal *hal) 2890 { 2891 return (AR5K_REG_READ(AR5K_AR5212_CFG) & AR5K_AR5212_CFG_EEBS ? 2892 AH_TRUE : AH_FALSE); 2893 } 2894 2895 int 2896 ar5k_ar5212_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) 2897 { 2898 u_int32_t status, i; 2899 2900 /* 2901 * Initialize EEPROM access 2902 */ 2903 AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset); 2904 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, 2905 AR5K_AR5212_EEPROM_CMD_READ); 2906 2907 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 2908 status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS); 2909 if (status & AR5K_AR5212_EEPROM_STAT_RDDONE) { 2910 if (status & AR5K_AR5212_EEPROM_STAT_RDERR) 2911 return (EIO); 2912 *data = (u_int16_t) 2913 (AR5K_REG_READ(AR5K_AR5212_EEPROM_DATA) & 0xffff); 2914 return (0); 2915 } 2916 AR5K_DELAY(15); 2917 } 2918 2919 return (ETIMEDOUT); 2920 } 2921 2922 int 2923 ar5k_ar5212_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) 2924 { 2925 u_int32_t status, timeout; 2926 2927 /* Enable eeprom access */ 2928 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, 2929 AR5K_AR5212_EEPROM_CMD_RESET); 2930 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, 2931 AR5K_AR5212_EEPROM_CMD_WRITE); 2932 2933 /* 2934 * Prime write pump 2935 */ 2936 AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset - 1); 2937 2938 for (timeout = 10000; timeout > 0; timeout--) { 2939 AR5K_DELAY(1); 2940 status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS); 2941 if (status & AR5K_AR5212_EEPROM_STAT_WRDONE) { 2942 if (status & AR5K_AR5212_EEPROM_STAT_WRERR) 2943 return (EIO); 2944 return (0); 2945 } 2946 } 2947 2948 return (ETIMEDOUT); 2949 } 2950 2951 /* 2952 * TX power setup 2953 */ 2954 2955 HAL_BOOL 2956 ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower) 2957 { 2958 HAL_BOOL tpc = hal->ah_txpower.txp_tpc; 2959 int i; 2960 2961 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 2962 AR5K_PRINTF("invalid tx power: %u\n", txpower); 2963 return (AH_FALSE); 2964 } 2965 2966 /* Reset TX power values */ 2967 bzero(&hal->ah_txpower, sizeof(hal->ah_txpower)); 2968 hal->ah_txpower.txp_tpc = tpc; 2969 2970 /* Initialize TX power table */ 2971 ar5k_txpower_table(hal, channel, txpower); 2972 2973 /* 2974 * Write TX power values 2975 */ 2976 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2977 AR5K_REG_WRITE(AR5K_AR5212_PHY_PCDAC_TXPOWER(i), 2978 ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 2979 0xffff) << 16) | (((hal->ah_txpower.txp_pcdac[i << 1] << 8) 2980 | 0xff) & 0xffff)); 2981 } 2982 2983 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE1, 2984 AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16) 2985 | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0)); 2986 2987 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE2, 2988 AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16) 2989 | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0)); 2990 2991 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE3, 2992 AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16) 2993 | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0)); 2994 2995 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE4, 2996 AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) 2997 | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); 2998 2999 if (hal->ah_txpower.txp_tpc == AH_TRUE) { 3000 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, 3001 AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3002 AR5K_TUNE_MAX_TXPOWER); 3003 } else { 3004 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, 3005 AR5K_AR5212_PHY_TXPOWER_RATE_MAX | 3006 AR5K_TUNE_MAX_TXPOWER); 3007 } 3008 3009 return (AH_TRUE); 3010 } 3011 3012 HAL_BOOL 3013 ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int power) 3014 { 3015 HAL_CHANNEL *channel = &hal->ah_current_channel; 3016 3017 AR5K_PRINTF("changing txpower to %d\n", power); 3018 return (ar5k_ar5212_txpower(hal, channel, power)); 3019 } 3020