1 /* $OpenBSD: ar5212.c,v 1.56 2016/01/12 09:28:09 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for the Atheros AR5001 Wireless LAN chipset 21 * (AR5212 + AR5111/AR5112). 22 */ 23 24 #include <dev/ic/ar5xxx.h> 25 #include <dev/ic/ar5212reg.h> 26 #include <dev/ic/ar5212var.h> 27 28 HAL_BOOL ar5k_ar5212_nic_reset(struct ath_hal *, u_int32_t); 29 HAL_BOOL ar5k_ar5212_nic_wakeup(struct ath_hal *, u_int16_t); 30 u_int16_t ar5k_ar5212_radio_revision(struct ath_hal *, HAL_CHIP); 31 void ar5k_ar5212_fill(struct ath_hal *); 32 HAL_BOOL ar5k_ar5212_txpower(struct ath_hal *, HAL_CHANNEL *, u_int); 33 HAL_BOOL ar5k_ar5212_warm_reset(struct ath_hal *); 34 35 /* 36 * Initial register setting for the AR5212 37 */ 38 static const struct ar5k_ini ar5212_ini[] = AR5K_AR5212_INI; 39 static const struct ar5k_mode ar5212_mode[] = AR5K_AR5212_MODE; 40 static const struct ar5k_mode ar5212_ar5111_mode[] = AR5K_AR5212_AR5111_MODE; 41 static const struct ar5k_mode ar5212_ar5112_mode[] = AR5K_AR5212_AR5112_MODE; 42 static const struct ar5k_mode ar5413_mode[] = AR5K_AR5413_MODE; 43 static const struct ar5k_mode ar2413_mode[] = AR5K_AR2413_MODE; 44 static const struct ar5k_mode ar2425_mode[] = AR5K_AR2425_MODE; 45 static const struct ar5k_ini ar5111_bbgain[] = AR5K_AR5111_INI_BBGAIN; 46 static const struct ar5k_ini ar5112_bbgain[] = AR5K_AR5112_INI_BBGAIN; 47 static const struct ar5k_ini ar5212_pcie[] = AR5K_AR5212_PCIE; 48 49 AR5K_HAL_FUNCTIONS(extern, ar5k_ar5212,); 50 51 void 52 ar5k_ar5212_fill(struct ath_hal *hal) 53 { 54 hal->ah_magic = AR5K_AR5212_MAGIC; 55 56 /* 57 * Init/Exit functions 58 */ 59 AR5K_HAL_FUNCTION(hal, ar5212, get_rate_table); 60 AR5K_HAL_FUNCTION(hal, ar5212, detach); 61 62 /* 63 * Reset functions 64 */ 65 AR5K_HAL_FUNCTION(hal, ar5212, reset); 66 AR5K_HAL_FUNCTION(hal, ar5212, set_opmode); 67 AR5K_HAL_FUNCTION(hal, ar5212, calibrate); 68 69 /* 70 * TX functions 71 */ 72 AR5K_HAL_FUNCTION(hal, ar5212, update_tx_triglevel); 73 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queue); 74 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_queueprops); 75 AR5K_HAL_FUNCTION(hal, ar5212, release_tx_queue); 76 AR5K_HAL_FUNCTION(hal, ar5212, reset_tx_queue); 77 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_buf); 78 AR5K_HAL_FUNCTION(hal, ar5212, put_tx_buf); 79 AR5K_HAL_FUNCTION(hal, ar5212, tx_start); 80 AR5K_HAL_FUNCTION(hal, ar5212, stop_tx_dma); 81 AR5K_HAL_FUNCTION(hal, ar5212, setup_tx_desc); 82 AR5K_HAL_FUNCTION(hal, ar5212, setup_xtx_desc); 83 AR5K_HAL_FUNCTION(hal, ar5212, fill_tx_desc); 84 AR5K_HAL_FUNCTION(hal, ar5212, proc_tx_desc); 85 AR5K_HAL_FUNCTION(hal, ar5212, has_veol); 86 87 /* 88 * RX functions 89 */ 90 AR5K_HAL_FUNCTION(hal, ar5212, get_rx_buf); 91 AR5K_HAL_FUNCTION(hal, ar5212, put_rx_buf); 92 AR5K_HAL_FUNCTION(hal, ar5212, start_rx); 93 AR5K_HAL_FUNCTION(hal, ar5212, stop_rx_dma); 94 AR5K_HAL_FUNCTION(hal, ar5212, start_rx_pcu); 95 AR5K_HAL_FUNCTION(hal, ar5212, stop_pcu_recv); 96 AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filter); 97 AR5K_HAL_FUNCTION(hal, ar5212, set_mcast_filterindex); 98 AR5K_HAL_FUNCTION(hal, ar5212, clear_mcast_filter_idx); 99 AR5K_HAL_FUNCTION(hal, ar5212, get_rx_filter); 100 AR5K_HAL_FUNCTION(hal, ar5212, set_rx_filter); 101 AR5K_HAL_FUNCTION(hal, ar5212, setup_rx_desc); 102 AR5K_HAL_FUNCTION(hal, ar5212, proc_rx_desc); 103 AR5K_HAL_FUNCTION(hal, ar5212, set_rx_signal); 104 105 /* 106 * Misc functions 107 */ 108 AR5K_HAL_FUNCTION(hal, ar5212, dump_state); 109 AR5K_HAL_FUNCTION(hal, ar5212, get_diag_state); 110 AR5K_HAL_FUNCTION(hal, ar5212, get_lladdr); 111 AR5K_HAL_FUNCTION(hal, ar5212, set_lladdr); 112 AR5K_HAL_FUNCTION(hal, ar5212, set_regdomain); 113 AR5K_HAL_FUNCTION(hal, ar5212, set_ledstate); 114 AR5K_HAL_FUNCTION(hal, ar5212, set_associd); 115 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_input); 116 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_output); 117 AR5K_HAL_FUNCTION(hal, ar5212, get_gpio); 118 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio); 119 AR5K_HAL_FUNCTION(hal, ar5212, set_gpio_intr); 120 AR5K_HAL_FUNCTION(hal, ar5212, get_tsf32); 121 AR5K_HAL_FUNCTION(hal, ar5212, get_tsf64); 122 AR5K_HAL_FUNCTION(hal, ar5212, reset_tsf); 123 AR5K_HAL_FUNCTION(hal, ar5212, get_regdomain); 124 AR5K_HAL_FUNCTION(hal, ar5212, detect_card_present); 125 AR5K_HAL_FUNCTION(hal, ar5212, update_mib_counters); 126 AR5K_HAL_FUNCTION(hal, ar5212, get_rf_gain); 127 AR5K_HAL_FUNCTION(hal, ar5212, set_slot_time); 128 AR5K_HAL_FUNCTION(hal, ar5212, get_slot_time); 129 AR5K_HAL_FUNCTION(hal, ar5212, set_ack_timeout); 130 AR5K_HAL_FUNCTION(hal, ar5212, get_ack_timeout); 131 AR5K_HAL_FUNCTION(hal, ar5212, set_cts_timeout); 132 AR5K_HAL_FUNCTION(hal, ar5212, get_cts_timeout); 133 134 /* 135 * Key table (WEP) functions 136 */ 137 AR5K_HAL_FUNCTION(hal, ar5212, is_cipher_supported); 138 AR5K_HAL_FUNCTION(hal, ar5212, get_keycache_size); 139 AR5K_HAL_FUNCTION(hal, ar5212, reset_key); 140 AR5K_HAL_FUNCTION(hal, ar5212, is_key_valid); 141 AR5K_HAL_FUNCTION(hal, ar5212, set_key); 142 AR5K_HAL_FUNCTION(hal, ar5212, set_key_lladdr); 143 AR5K_HAL_FUNCTION(hal, ar5212, softcrypto); 144 145 /* 146 * Power management functions 147 */ 148 AR5K_HAL_FUNCTION(hal, ar5212, set_power); 149 AR5K_HAL_FUNCTION(hal, ar5212, get_power_mode); 150 AR5K_HAL_FUNCTION(hal, ar5212, query_pspoll_support); 151 AR5K_HAL_FUNCTION(hal, ar5212, init_pspoll); 152 AR5K_HAL_FUNCTION(hal, ar5212, enable_pspoll); 153 AR5K_HAL_FUNCTION(hal, ar5212, disable_pspoll); 154 155 /* 156 * Beacon functions 157 */ 158 AR5K_HAL_FUNCTION(hal, ar5212, init_beacon); 159 AR5K_HAL_FUNCTION(hal, ar5212, set_beacon_timers); 160 AR5K_HAL_FUNCTION(hal, ar5212, reset_beacon); 161 AR5K_HAL_FUNCTION(hal, ar5212, wait_for_beacon); 162 163 /* 164 * Interrupt functions 165 */ 166 AR5K_HAL_FUNCTION(hal, ar5212, is_intr_pending); 167 AR5K_HAL_FUNCTION(hal, ar5212, get_isr); 168 AR5K_HAL_FUNCTION(hal, ar5212, get_intr); 169 AR5K_HAL_FUNCTION(hal, ar5212, set_intr); 170 171 /* 172 * Chipset functions (ar5k-specific, non-HAL) 173 */ 174 AR5K_HAL_FUNCTION(hal, ar5212, get_capabilities); 175 AR5K_HAL_FUNCTION(hal, ar5212, radar_alert); 176 177 /* 178 * EEPROM access 179 */ 180 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_is_busy); 181 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_read); 182 AR5K_HAL_FUNCTION(hal, ar5212, eeprom_write); 183 184 /* 185 * Unused functions or functions not implemented 186 */ 187 AR5K_HAL_FUNCTION(hal, ar5212, set_bssid_mask); 188 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_queueprops); 189 AR5K_HAL_FUNCTION(hal, ar5212, num_tx_pending); 190 AR5K_HAL_FUNCTION(hal, ar5212, phy_disable); 191 AR5K_HAL_FUNCTION(hal, ar5212, set_txpower_limit); 192 AR5K_HAL_FUNCTION(hal, ar5212, set_def_antenna); 193 AR5K_HAL_FUNCTION(hal, ar5212, get_def_antenna); 194 #ifdef notyet 195 AR5K_HAL_FUNCTION(hal, ar5212, set_capability); 196 AR5K_HAL_FUNCTION(hal, ar5212, proc_mib_event); 197 AR5K_HAL_FUNCTION(hal, ar5212, get_tx_inter_queue); 198 #endif 199 } 200 201 struct ath_hal * 202 ar5k_ar5212_attach(u_int16_t device, void *sc, bus_space_tag_t st, 203 bus_space_handle_t sh, int *status) 204 { 205 struct ath_hal *hal = (struct ath_hal*) sc; 206 u_int8_t mac[IEEE80211_ADDR_LEN]; 207 u_int32_t srev; 208 209 ar5k_ar5212_fill(hal); 210 211 /* Bring device out of sleep and reset its units */ 212 if (ar5k_ar5212_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) 213 return (NULL); 214 215 /* Get MAC, PHY and RADIO revisions */ 216 srev = AR5K_REG_READ(AR5K_AR5212_SREV); 217 hal->ah_mac_srev = srev; 218 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5212_SREV_VER); 219 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5212_SREV_REV); 220 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID) & 221 0x00ffffffff; 222 hal->ah_radio_5ghz_revision = 223 ar5k_ar5212_radio_revision(hal, HAL_CHIP_5GHZ); 224 hal->ah_radio_2ghz_revision = 225 ar5k_ar5212_radio_revision(hal, HAL_CHIP_2GHZ); 226 227 /* Single chip radio */ 228 if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision) 229 hal->ah_radio_2ghz_revision = 0; 230 231 /* Identify the chipset (this has to be done in an early step) */ 232 hal->ah_version = AR5K_AR5212; 233 if (device == AR5K_VERSION_DEV) { 234 hal->ah_radio = AR5K_AR5413; 235 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5424; 236 hal->ah_radio_5ghz_revision = hal->ah_radio_2ghz_revision = 237 AR5K_SREV_VER_AR5413; 238 } else if (srev == AR5K_SREV_VER_AR2425) { 239 hal->ah_radio = AR5K_AR2425; 240 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112; 241 hal->ah_radio_5ghz_revision = AR5K_SREV_RAD_SC2; 242 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) { 243 hal->ah_radio = AR5K_AR5111; 244 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5111; 245 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) { 246 hal->ah_radio = AR5K_AR5112; 247 if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) 248 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112; 249 else 250 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 251 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) { 252 hal->ah_radio = AR5K_AR2413; 253 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 254 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) { 255 hal->ah_radio = AR5K_AR5413; 256 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 257 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133 && 258 srev < AR5K_SREV_VER_AR5424) { 259 hal->ah_radio = AR5K_AR2413; 260 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112A; 261 } else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) { 262 hal->ah_radio = AR5K_AR5413; 263 hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5424; 264 } 265 hal->ah_phy = AR5K_AR5212_PHY(0); 266 267 if (hal->ah_pci_express == AH_TRUE) { 268 /* PCI-Express based devices need some extra initialization */ 269 ar5k_write_ini(hal, ar5212_pcie, nitems(ar5212_pcie), 0); 270 } 271 272 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 273 ar5k_ar5212_set_associd(hal, mac, 0, 0); 274 ar5k_ar5212_get_lladdr(hal, mac); 275 ar5k_ar5212_set_opmode(hal); 276 277 return (hal); 278 } 279 280 HAL_BOOL 281 ar5k_ar5212_nic_reset(struct ath_hal *hal, u_int32_t val) 282 { 283 HAL_BOOL ret = AH_FALSE; 284 u_int32_t mask = val ? val : ~0; 285 286 /* Read-and-clear */ 287 AR5K_REG_READ(AR5K_AR5212_RXDP); 288 289 /* 290 * Reset the device and wait until success 291 */ 292 AR5K_REG_WRITE(AR5K_AR5212_RC, val); 293 294 /* Wait at least 128 PCI clocks */ 295 AR5K_DELAY(15); 296 297 val &= 298 AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; 299 300 mask &= 301 AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; 302 303 ret = ar5k_register_timeout(hal, AR5K_AR5212_RC, mask, val, AH_FALSE); 304 305 /* 306 * Reset configuration register 307 */ 308 if ((val & AR5K_AR5212_RC_PCU) == 0) 309 AR5K_REG_WRITE(AR5K_AR5212_CFG, AR5K_AR5212_INIT_CFG); 310 311 return (ret); 312 } 313 314 HAL_BOOL 315 ar5k_ar5212_nic_wakeup(struct ath_hal *hal, u_int16_t flags) 316 { 317 u_int32_t turbo, mode, clock; 318 319 turbo = 0; 320 mode = 0; 321 clock = 0; 322 323 /* 324 * Get channel mode flags 325 */ 326 327 if (hal->ah_radio >= AR5K_AR5112) { 328 mode = AR5K_AR5212_PHY_MODE_RAD_AR5112; 329 clock = AR5K_AR5212_PHY_PLL_AR5112; 330 } else { 331 mode = AR5K_AR5212_PHY_MODE_RAD_AR5111; 332 clock = AR5K_AR5212_PHY_PLL_AR5111; 333 } 334 335 if (flags & IEEE80211_CHAN_2GHZ) { 336 mode |= AR5K_AR5212_PHY_MODE_FREQ_2GHZ; 337 clock |= AR5K_AR5212_PHY_PLL_44MHZ; 338 } else if (flags & IEEE80211_CHAN_5GHZ) { 339 mode |= AR5K_AR5212_PHY_MODE_FREQ_5GHZ; 340 clock |= AR5K_AR5212_PHY_PLL_40MHZ; 341 } else { 342 AR5K_PRINT("invalid radio frequency mode\n"); 343 return (AH_FALSE); 344 } 345 346 if (flags & IEEE80211_CHAN_CCK) { 347 mode |= AR5K_AR5212_PHY_MODE_MOD_CCK; 348 } else if (flags & IEEE80211_CHAN_OFDM) { 349 mode |= AR5K_AR5212_PHY_MODE_MOD_OFDM; 350 } else if (flags & IEEE80211_CHAN_DYN) { 351 mode |= AR5K_AR5212_PHY_MODE_MOD_DYN; 352 } else { 353 AR5K_PRINT("invalid radio frequency mode\n"); 354 return (AH_FALSE); 355 } 356 357 /* 358 * Reset and wakeup the device 359 */ 360 361 /* ...reset chipset and PCI device (if not PCI-E) */ 362 if (hal->ah_pci_express == AH_FALSE && 363 ar5k_ar5212_nic_reset(hal, AR5K_AR5212_RC_CHIP) == AH_FALSE) { 364 AR5K_PRINT("failed to reset the AR5212 + PCI chipset\n"); 365 return (AH_FALSE); 366 } 367 368 /* ...wakeup */ 369 if (ar5k_ar5212_set_power(hal, 370 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 371 AR5K_PRINT("failed to resume the AR5212 (again)\n"); 372 return (AH_FALSE); 373 } 374 375 /* ...final warm reset */ 376 if (ar5k_ar5212_nic_reset(hal, 0) == AH_FALSE) { 377 AR5K_PRINT("failed to warm reset the AR5212\n"); 378 return (AH_FALSE); 379 } 380 381 /* ...set the PHY operating mode */ 382 AR5K_REG_WRITE(AR5K_AR5212_PHY_PLL, clock); 383 AR5K_DELAY(300); 384 385 AR5K_REG_WRITE(AR5K_AR5212_PHY_MODE, mode); 386 AR5K_REG_WRITE(AR5K_AR5212_PHY_TURBO, turbo); 387 388 return (AH_TRUE); 389 } 390 391 u_int16_t 392 ar5k_ar5212_radio_revision(struct ath_hal *hal, HAL_CHIP chip) 393 { 394 int i; 395 u_int32_t srev; 396 u_int16_t ret; 397 398 /* 399 * Set the radio chip access register 400 */ 401 switch (chip) { 402 case HAL_CHIP_2GHZ: 403 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_2GHZ); 404 break; 405 case HAL_CHIP_5GHZ: 406 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); 407 break; 408 default: 409 return (0); 410 } 411 412 AR5K_DELAY(2000); 413 414 /* ...wait until PHY is ready and read the selected radio revision */ 415 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x34), 0x00001c16); 416 417 for (i = 0; i < 8; i++) 418 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x20), 0x00010000); 419 srev = (AR5K_REG_READ(AR5K_AR5212_PHY(0x100)) >> 24) & 0xff; 420 421 ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); 422 423 /* Reset to the 5GHz mode */ 424 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); 425 426 return (ret); 427 } 428 429 const HAL_RATE_TABLE * 430 ar5k_ar5212_get_rate_table(struct ath_hal *hal, u_int mode) 431 { 432 switch (mode) { 433 case HAL_MODE_11A: 434 return (&hal->ah_rt_11a); 435 case HAL_MODE_11B: 436 return (&hal->ah_rt_11b); 437 case HAL_MODE_11G: 438 case HAL_MODE_PUREG: 439 return (&hal->ah_rt_11g); 440 case HAL_MODE_XR: 441 return (&hal->ah_rt_xr); 442 default: 443 return (NULL); 444 } 445 446 return (NULL); 447 } 448 449 void 450 ar5k_ar5212_detach(struct ath_hal *hal) 451 { 452 if (hal->ah_rf_banks != NULL) 453 free(hal->ah_rf_banks, M_DEVBUF, 0); 454 455 /* 456 * Free HAL structure, assume interrupts are down 457 */ 458 free(hal, M_DEVBUF, 0); 459 } 460 461 HAL_BOOL 462 ar5k_ar5212_phy_disable(struct ath_hal *hal) 463 { 464 AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_DISABLE); 465 return (AH_TRUE); 466 } 467 468 HAL_BOOL 469 ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, 470 HAL_BOOL chanchange, HAL_STATUS *status) 471 { 472 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 473 u_int8_t mac[IEEE80211_ADDR_LEN]; 474 u_int32_t data, s_seq, s_ant, s_led[3], dmasize; 475 u_int i, mode, freq, ee_mode, ant[2]; 476 const HAL_RATE_TABLE *rt; 477 478 /* 479 * Save some registers before a reset 480 */ 481 if (chanchange == AH_TRUE) { 482 s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0)); 483 s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA); 484 } else { 485 s_seq = 0; 486 s_ant = 1; 487 } 488 489 s_led[0] = AR5K_REG_READ(AR5K_AR5212_PCICFG) & 490 AR5K_AR5212_PCICFG_LEDSTATE; 491 s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR); 492 s_led[2] = AR5K_REG_READ(AR5K_AR5212_GPIODO); 493 494 if (chanchange == AH_TRUE && hal->ah_rf_banks != NULL) 495 ar5k_ar5212_get_rf_gain(hal); 496 497 if (ar5k_ar5212_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) 498 return (AH_FALSE); 499 500 /* 501 * Initialize operating mode 502 */ 503 hal->ah_op_mode = op_mode; 504 505 switch (channel->c_channel_flags & CHANNEL_MODES) { 506 case CHANNEL_A: 507 mode = AR5K_INI_VAL_11A; 508 freq = AR5K_INI_RFGAIN_5GHZ; 509 ee_mode = AR5K_EEPROM_MODE_11A; 510 break; 511 case CHANNEL_B: 512 mode = AR5K_INI_VAL_11B; 513 freq = AR5K_INI_RFGAIN_2GHZ; 514 ee_mode = AR5K_EEPROM_MODE_11B; 515 break; 516 case CHANNEL_G: 517 case CHANNEL_PUREG: 518 mode = AR5K_INI_VAL_11G; 519 freq = AR5K_INI_RFGAIN_2GHZ; 520 ee_mode = AR5K_EEPROM_MODE_11G; 521 break; 522 case CHANNEL_XR: 523 mode = AR5K_INI_VAL_XR; 524 freq = AR5K_INI_RFGAIN_5GHZ; 525 ee_mode = AR5K_EEPROM_MODE_11A; 526 break; 527 default: 528 AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); 529 return (AH_FALSE); 530 } 531 532 /* PHY access enable */ 533 AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); 534 535 /* 536 * Write initial mode and register settings 537 */ 538 ar5k_write_mode(hal, ar5212_mode, nitems(ar5212_mode), mode); 539 ar5k_write_ini(hal, ar5212_ini, nitems(ar5212_ini), chanchange); 540 541 switch (hal->ah_radio) { 542 case AR5K_AR5111: 543 ar5k_write_mode(hal, ar5212_ar5111_mode, 544 nitems(ar5212_ar5111_mode), mode); 545 break; 546 case AR5K_AR5112: 547 ar5k_write_mode(hal, ar5212_ar5112_mode, 548 nitems(ar5212_ar5112_mode), mode); 549 break; 550 case AR5K_AR5413: 551 ar5k_write_mode(hal, ar5413_mode, 552 nitems(ar5413_mode), mode); 553 break; 554 case AR5K_AR2413: 555 AR5K_REG_WRITE(AR5K_AR5212_PHY(648), 0x018830c6); 556 ar5k_write_mode(hal, ar2413_mode, 557 nitems(ar2413_mode), mode); 558 break; 559 case AR5K_AR2425: 560 AR5K_REG_WRITE(AR5K_AR5212_PHY(648), 0x018830c6); 561 if (mode == AR5K_INI_VAL_11B) 562 mode = AR5K_INI_VAL_11G; 563 ar5k_write_mode(hal, ar2425_mode, 564 nitems(ar2425_mode), mode); 565 break; 566 default: 567 AR5K_PRINTF("invalid radio: %d\n", hal->ah_radio); 568 return (AH_FALSE); 569 } 570 571 if (hal->ah_radio == AR5K_AR5111) 572 ar5k_write_ini(hal, ar5111_bbgain, 573 nitems(ar5111_bbgain), chanchange); 574 else 575 ar5k_write_ini(hal, ar5112_bbgain, 576 nitems(ar5112_bbgain), chanchange); 577 578 /* 579 * Write initial RF gain settings 580 */ 581 if (ar5k_rfgain(hal, freq) == AH_FALSE) 582 return (AH_FALSE); 583 584 AR5K_DELAY(1000); 585 586 /* 587 * Set rate duration table 588 */ 589 rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_XR); 590 591 for (i = 0; i < rt->rt_rate_count; i++) { 592 AR5K_REG_WRITE(AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code), 593 ath_hal_computetxtime(hal, rt, 14, 594 rt->rt_info[i].r_control_rate, AH_FALSE)); 595 } 596 597 rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_11B); 598 for (i = 0; i < rt->rt_rate_count; i++) { 599 data = AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code); 600 AR5K_REG_WRITE(data, 601 ath_hal_computetxtime(hal, rt, 14, 602 rt->rt_info[i].r_control_rate, AH_FALSE)); 603 if (rt->rt_info[i].r_short_preamble) { 604 AR5K_REG_WRITE(data + 605 (rt->rt_info[i].r_short_preamble << 2), 606 ath_hal_computetxtime(hal, rt, 14, 607 rt->rt_info[i].r_control_rate, AH_FALSE)); 608 } 609 } 610 611 /* Fix for first revision of the AR5112 RF chipset */ 612 if (hal->ah_radio >= AR5K_AR5112 && 613 hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 614 AR5K_REG_WRITE(AR5K_AR5212_PHY_CCKTXCTL, 615 AR5K_AR5212_PHY_CCKTXCTL_WORLD); 616 if (channel->c_channel_flags & IEEE80211_CHAN_OFDM) 617 data = 0xffb81020; 618 else 619 data = 0xffb80d20; 620 AR5K_REG_WRITE(AR5K_AR5212_PHY_FC, data); 621 } 622 623 /* 624 * Set TX power (XXX use txpower from net80211) 625 */ 626 if (ar5k_ar5212_txpower(hal, channel, 627 AR5K_TUNE_DEFAULT_TXPOWER) == AH_FALSE) 628 return (AH_FALSE); 629 630 /* 631 * Write RF registers 632 */ 633 if (ar5k_rfregs(hal, channel, mode) == AH_FALSE) 634 return (AH_FALSE); 635 636 /* 637 * Configure additional registers 638 */ 639 640 /* OFDM timings */ 641 if (channel->c_channel_flags & IEEE80211_CHAN_OFDM) { 642 u_int32_t coef_scaled, coef_exp, coef_man, ds_coef_exp, 643 ds_coef_man, clock; 644 645 clock = 40; 646 coef_scaled = ((5 * (clock << 24)) / 2) / channel->c_channel; 647 648 for (coef_exp = 31; coef_exp > 0; coef_exp--) 649 if ((coef_scaled >> coef_exp) & 0x1) 650 break; 651 652 if (!coef_exp) 653 return (AH_FALSE); 654 655 coef_exp = 14 - (coef_exp - 24); 656 coef_man = coef_scaled + (1 << (24 - coef_exp - 1)); 657 ds_coef_man = coef_man >> (24 - coef_exp); 658 ds_coef_exp = coef_exp - 16; 659 660 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3, 661 AR5K_AR5212_PHY_TIMING_3_DSC_MAN, ds_coef_man); 662 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_TIMING_3, 663 AR5K_AR5212_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 664 } 665 666 if (hal->ah_radio == AR5K_AR5111) { 667 if (channel->c_channel_flags & IEEE80211_CHAN_B) 668 AR5K_REG_ENABLE_BITS(AR5K_AR5212_TXCFG, 669 AR5K_AR5212_TXCFG_B_MODE); 670 else 671 AR5K_REG_DISABLE_BITS(AR5K_AR5212_TXCFG, 672 AR5K_AR5212_TXCFG_B_MODE); 673 } 674 675 /* Set antenna mode */ 676 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x44), 677 hal->ah_antenna[ee_mode][0], 0xfffffc06); 678 679 if (freq == AR5K_INI_RFGAIN_2GHZ) 680 ant[0] = ant[1] = HAL_ANT_FIXED_B; 681 else 682 ant[0] = ant[1] = HAL_ANT_FIXED_A; 683 684 AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0, 685 hal->ah_antenna[ee_mode][ant[0]]); 686 AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1, 687 hal->ah_antenna[ee_mode][ant[1]]); 688 689 /* Commit values from EEPROM */ 690 if (hal->ah_radio == AR5K_AR5111) 691 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_FC, 692 AR5K_AR5212_PHY_FC_TX_CLIP, ee->ee_tx_clip); 693 694 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x5a), 695 AR5K_AR5212_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); 696 697 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x11), 698 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); 699 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x12), 700 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); 701 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x14), 702 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | 703 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); 704 705 AR5K_REG_WRITE(AR5K_AR5212_PHY(0x0d), 706 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 707 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 708 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 709 (ee->ee_tx_frm2xpa_enable[ee_mode])); 710 711 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x0a), 712 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); 713 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x19), 714 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); 715 AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49), 4, 0xffffff01); 716 717 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, 718 AR5K_AR5212_PHY_IQ_CORR_ENABLE | 719 (ee->ee_i_cal[ee_mode] << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S) | 720 ee->ee_q_cal[ee_mode]); 721 722 if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) { 723 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_GAIN_2GHZ, 724 AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX, 725 ee->ee_margin_tx_rx[ee_mode]); 726 } 727 728 /* 729 * Restore saved values 730 */ 731 AR5K_REG_WRITE(AR5K_AR5212_DCU_SEQNUM(0), s_seq); 732 AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, s_ant); 733 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, s_led[0]); 734 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, s_led[1]); 735 AR5K_REG_WRITE(AR5K_AR5212_GPIODO, s_led[2]); 736 737 /* 738 * Misc 739 */ 740 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 741 ar5k_ar5212_set_associd(hal, mac, 0, 0); 742 ar5k_ar5212_set_opmode(hal); 743 AR5K_REG_WRITE(AR5K_AR5212_PISR, 0xffffffff); 744 AR5K_REG_WRITE(AR5K_AR5212_RSSI_THR, AR5K_TUNE_RSSI_THRES); 745 746 /* 747 * Set Rx/Tx DMA Configuration 748 * 749 * XXX Limit DMA size on PCI-E chipsets to 128 bytes because 750 * XXX we saw RX overruns and TX errors with higher values. 751 */ 752 dmasize = hal->ah_pci_express == AH_TRUE ? 753 AR5K_AR5212_DMASIZE_128B : AR5K_AR5212_DMASIZE_512B; 754 AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, AR5K_AR5212_TXCFG_SDMAMR, 755 dmasize | AR5K_AR5212_TXCFG_DMASIZE); 756 AR5K_REG_WRITE_BITS(AR5K_AR5212_RXCFG, AR5K_AR5212_RXCFG_SDMAMW, 757 dmasize); 758 759 /* 760 * Set channel and calibrate the PHY 761 */ 762 if (ar5k_channel(hal, channel) == AH_FALSE) 763 return (AH_FALSE); 764 765 /* 766 * Enable the PHY and wait until completion 767 */ 768 AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_ENABLE); 769 770 data = AR5K_REG_READ(AR5K_AR5212_PHY_RX_DELAY) & 771 AR5K_AR5212_PHY_RX_DELAY_M; 772 data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? 773 ((data << 2) / 22) : (data / 10); 774 775 AR5K_DELAY(100 + data); 776 777 /* 778 * Start calibration 779 */ 780 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, 781 AR5K_AR5212_PHY_AGCCTL_NF | 782 AR5K_AR5212_PHY_AGCCTL_CAL); 783 784 hal->ah_calibration = AH_FALSE; 785 if ((channel->c_channel_flags & IEEE80211_CHAN_B) == 0) { 786 hal->ah_calibration = AH_TRUE; 787 AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_IQ, 788 AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX, 15); 789 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, 790 AR5K_AR5212_PHY_IQ_RUN); 791 } 792 793 /* 794 * Reset queues and start beacon timers at the end of the reset routine 795 */ 796 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { 797 AR5K_REG_WRITE_Q(AR5K_AR5212_DCU_QCUMASK(i), i); 798 if (ar5k_ar5212_reset_tx_queue(hal, i) == AH_FALSE) { 799 AR5K_PRINTF("failed to reset TX queue #%d\n", i); 800 return (AH_FALSE); 801 } 802 } 803 804 /* Pre-enable interrupts */ 805 ar5k_ar5212_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); 806 807 /* 808 * Set RF kill flags if supported by the device (read from the EEPROM) 809 */ 810 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { 811 ar5k_ar5212_set_gpio_input(hal, 0); 812 if ((hal->ah_gpio[0] = ar5k_ar5212_get_gpio(hal, 0)) == 0) 813 ar5k_ar5212_set_gpio_intr(hal, 0, 1); 814 else 815 ar5k_ar5212_set_gpio_intr(hal, 0, 0); 816 } 817 818 /* 819 * Set the 32MHz reference clock 820 */ 821 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCR, AR5K_AR5212_PHY_SCR_32MHZ); 822 AR5K_REG_WRITE(AR5K_AR5212_PHY_SLMT, AR5K_AR5212_PHY_SLMT_32MHZ); 823 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCAL, AR5K_AR5212_PHY_SCAL_32MHZ); 824 AR5K_REG_WRITE(AR5K_AR5212_PHY_SCLOCK, AR5K_AR5212_PHY_SCLOCK_32MHZ); 825 AR5K_REG_WRITE(AR5K_AR5212_PHY_SDELAY, AR5K_AR5212_PHY_SDELAY_32MHZ); 826 AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, hal->ah_phy_spending); 827 828 /* 829 * Disable beacons and reset the register 830 */ 831 AR5K_REG_DISABLE_BITS(AR5K_AR5212_BEACON, 832 AR5K_AR5212_BEACON_ENABLE | AR5K_AR5212_BEACON_RESET_TSF); 833 834 return (AH_TRUE); 835 } 836 837 void 838 ar5k_ar5212_set_def_antenna(struct ath_hal *hal, u_int ant) 839 { 840 AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, ant); 841 } 842 843 u_int 844 ar5k_ar5212_get_def_antenna(struct ath_hal *hal) 845 { 846 return AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA); 847 } 848 849 void 850 ar5k_ar5212_set_opmode(struct ath_hal *hal) 851 { 852 u_int32_t pcu_reg, low_id, high_id; 853 854 pcu_reg = 0; 855 856 switch (hal->ah_op_mode) { 857 #ifndef IEEE80211_STA_ONLY 858 case IEEE80211_M_IBSS: 859 pcu_reg |= AR5K_AR5212_STA_ID1_ADHOC | 860 AR5K_AR5212_STA_ID1_DESC_ANTENNA; 861 break; 862 863 case IEEE80211_M_HOSTAP: 864 pcu_reg |= AR5K_AR5212_STA_ID1_AP | 865 AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA; 866 break; 867 #endif 868 869 case IEEE80211_M_STA: 870 case IEEE80211_M_MONITOR: 871 pcu_reg |= AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; 872 break; 873 874 default: 875 return; 876 } 877 878 /* 879 * Set PCU registers 880 */ 881 low_id = AR5K_LOW_ID(hal->ah_sta_id); 882 high_id = AR5K_HIGH_ID(hal->ah_sta_id); 883 AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); 884 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, pcu_reg | high_id); 885 886 return; 887 } 888 889 HAL_BOOL 890 ar5k_ar5212_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 891 { 892 u_int32_t i_pwr, q_pwr; 893 int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; 894 895 if (hal->ah_calibration == AH_FALSE || 896 AR5K_REG_READ(AR5K_AR5212_PHY_IQ) & AR5K_AR5212_PHY_IQ_RUN) 897 goto done; 898 899 hal->ah_calibration = AH_FALSE; 900 901 iq_corr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_CORR); 902 i_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_I); 903 q_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_Q); 904 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 905 q_coffd = q_pwr >> 6; 906 907 if (i_coffd == 0 || q_coffd == 0) 908 goto done; 909 910 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 911 q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; 912 913 /* Commit new IQ value */ 914 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, 915 AR5K_AR5212_PHY_IQ_CORR_ENABLE | 916 ((u_int32_t)q_coff) | 917 ((u_int32_t)i_coff << AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S)); 918 919 done: 920 /* Start noise floor calibration */ 921 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, 922 AR5K_AR5212_PHY_AGCCTL_NF); 923 924 /* Request RF gain */ 925 if (channel->c_channel_flags & IEEE80211_CHAN_5GHZ) { 926 AR5K_REG_WRITE(AR5K_AR5212_PHY_PAPD_PROBE, 927 AR5K_REG_SM(hal->ah_txpower.txp_max, 928 AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER) | 929 AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT); 930 hal->ah_rf_gain = HAL_RFGAIN_READ_REQUESTED; 931 } 932 933 return (AH_TRUE); 934 } 935 936 /* 937 * Transmit functions 938 */ 939 940 HAL_BOOL 941 ar5k_ar5212_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) 942 { 943 u_int32_t trigger_level, imr; 944 HAL_BOOL status = AH_FALSE; 945 946 /* 947 * Disable interrupts by setting the mask 948 */ 949 imr = ar5k_ar5212_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); 950 951 trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TXCFG), 952 AR5K_AR5212_TXCFG_TXFULL); 953 954 if (increase == AH_FALSE) { 955 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 956 goto done; 957 } else 958 trigger_level += 959 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 960 961 /* 962 * Update trigger level on success 963 */ 964 AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, 965 AR5K_AR5212_TXCFG_TXFULL, trigger_level); 966 status = AH_TRUE; 967 968 done: 969 /* 970 * Restore interrupt mask 971 */ 972 ar5k_ar5212_set_intr(hal, imr); 973 974 return (status); 975 } 976 977 int 978 ar5k_ar5212_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, 979 const HAL_TXQ_INFO *queue_info) 980 { 981 u_int queue; 982 983 /* 984 * Get queue by type 985 */ 986 if (queue_type == HAL_TX_QUEUE_DATA) { 987 for (queue = HAL_TX_QUEUE_ID_DATA_MIN; 988 hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; 989 queue++) 990 if (queue > HAL_TX_QUEUE_ID_DATA_MAX) 991 return (-1); 992 } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { 993 queue = HAL_TX_QUEUE_ID_PSPOLL; 994 } else if (queue_type == HAL_TX_QUEUE_BEACON) { 995 queue = HAL_TX_QUEUE_ID_BEACON; 996 } else if (queue_type == HAL_TX_QUEUE_CAB) { 997 queue = HAL_TX_QUEUE_ID_CAB; 998 } else 999 return (-1); 1000 1001 /* 1002 * Setup internal queue structure 1003 */ 1004 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 1005 if (queue_info != NULL) { 1006 if (ar5k_ar5212_setup_tx_queueprops(hal, queue, queue_info) 1007 != AH_TRUE) 1008 return (-1); 1009 } 1010 hal->ah_txq[queue].tqi_type = queue_type; 1011 1012 AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); 1013 1014 return (queue); 1015 } 1016 1017 HAL_BOOL 1018 ar5k_ar5212_setup_tx_queueprops(struct ath_hal *hal, int queue, 1019 const HAL_TXQ_INFO *queue_info) 1020 { 1021 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1022 1023 if (hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE) 1024 return (AH_FALSE); 1025 1026 bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 1027 1028 if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && 1029 (queue_info->tqi_subtype >= HAL_WME_AC_VI) && 1030 (queue_info->tqi_subtype <= HAL_WME_UPSD)) 1031 hal->ah_txq[queue].tqi_flags |= 1032 AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 1033 1034 return (AH_TRUE); 1035 } 1036 1037 HAL_BOOL 1038 ar5k_ar5212_get_tx_queueprops(struct ath_hal *hal, int queue, 1039 HAL_TXQ_INFO *queue_info) 1040 { 1041 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1042 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO)); 1043 return (AH_TRUE); 1044 } 1045 1046 HAL_BOOL 1047 ar5k_ar5212_release_tx_queue(struct ath_hal *hal, u_int queue) 1048 { 1049 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1050 1051 /* This queue will be skipped in further operations */ 1052 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; 1053 AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); 1054 1055 return (AH_FALSE); 1056 } 1057 1058 HAL_BOOL 1059 ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue) 1060 { 1061 u_int32_t cw_min, cw_max, retry_lg, retry_sh; 1062 struct ieee80211_channel *channel = (struct ieee80211_channel*) 1063 &hal->ah_current_channel; 1064 HAL_TXQ_INFO *tq; 1065 1066 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1067 1068 tq = &hal->ah_txq[queue]; 1069 1070 if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) 1071 return (AH_TRUE); 1072 1073 /* 1074 * Set registers by channel mode 1075 */ 1076 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN; 1077 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; 1078 hal->ah_aifs = AR5K_TUNE_AIFS; 1079 if (IEEE80211_IS_CHAN_XR(channel)) { 1080 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR; 1081 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR; 1082 hal->ah_aifs = AR5K_TUNE_AIFS_XR; 1083 } else if (IEEE80211_IS_CHAN_B(channel)) { 1084 cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; 1085 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; 1086 hal->ah_aifs = AR5K_TUNE_AIFS_11B; 1087 } 1088 1089 /* 1090 * Set retry limits 1091 */ 1092 if (hal->ah_software_retry == AH_TRUE) { 1093 /* XXX Need to test this */ 1094 retry_lg = hal->ah_limit_tx_retries; 1095 retry_sh = retry_lg = 1096 retry_lg > AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY ? 1097 AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY : retry_lg; 1098 } else { 1099 retry_lg = AR5K_INIT_LG_RETRY; 1100 retry_sh = AR5K_INIT_SH_RETRY; 1101 } 1102 1103 AR5K_REG_WRITE(AR5K_AR5212_DCU_RETRY_LMT(queue), 1104 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 1105 AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY) | 1106 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 1107 AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY) | 1108 AR5K_REG_SM(retry_lg, AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY) | 1109 AR5K_REG_SM(retry_sh, AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY)); 1110 1111 /* 1112 * Set initial content window (cw_min/cw_max) 1113 */ 1114 cw_min = 1; 1115 while (cw_min < hal->ah_cw_min) 1116 cw_min = (cw_min << 1) | 1; 1117 1118 cw_min = tq->tqi_cw_min < 0 ? 1119 (cw_min >> (-tq->tqi_cw_min)) : 1120 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 1121 cw_max = tq->tqi_cw_max < 0 ? 1122 (cw_max >> (-tq->tqi_cw_max)) : 1123 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 1124 1125 AR5K_REG_WRITE(AR5K_AR5212_DCU_LCL_IFS(queue), 1126 AR5K_REG_SM(cw_min, AR5K_AR5212_DCU_LCL_IFS_CW_MIN) | 1127 AR5K_REG_SM(cw_max, AR5K_AR5212_DCU_LCL_IFS_CW_MAX) | 1128 AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, 1129 AR5K_AR5212_DCU_LCL_IFS_AIFS)); 1130 1131 /* 1132 * Set misc registers 1133 */ 1134 AR5K_REG_WRITE(AR5K_AR5212_QCU_MISC(queue), 1135 AR5K_AR5212_QCU_MISC_DCU_EARLY); 1136 1137 if (tq->tqi_cbr_period) { 1138 AR5K_REG_WRITE(AR5K_AR5212_QCU_CBRCFG(queue), 1139 AR5K_REG_SM(tq->tqi_cbr_period, 1140 AR5K_AR5212_QCU_CBRCFG_INTVAL) | 1141 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 1142 AR5K_AR5212_QCU_CBRCFG_ORN_THRES)); 1143 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1144 AR5K_AR5212_QCU_MISC_FRSHED_CBR); 1145 if (tq->tqi_cbr_overflow_limit) 1146 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1147 AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE); 1148 } 1149 1150 if (tq->tqi_ready_time) { 1151 AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), 1152 AR5K_REG_SM(tq->tqi_ready_time, 1153 AR5K_AR5212_QCU_RDYTIMECFG_INTVAL) | 1154 AR5K_AR5212_QCU_RDYTIMECFG_ENABLE); 1155 } 1156 1157 if (tq->tqi_burst_time) { 1158 AR5K_REG_WRITE(AR5K_AR5212_DCU_CHAN_TIME(queue), 1159 AR5K_REG_SM(tq->tqi_burst_time, 1160 AR5K_AR5212_DCU_CHAN_TIME_DUR) | 1161 AR5K_AR5212_DCU_CHAN_TIME_ENABLE); 1162 1163 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { 1164 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1165 AR5K_AR5212_QCU_MISC_TXE); 1166 } 1167 } 1168 1169 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { 1170 AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), 1171 AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS); 1172 } 1173 1174 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 1175 AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), 1176 AR5K_AR5212_DCU_MISC_BACKOFF_FRAG); 1177 } 1178 1179 /* 1180 * Set registers by queue type 1181 */ 1182 switch (tq->tqi_type) { 1183 case HAL_TX_QUEUE_BEACON: 1184 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1185 AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | 1186 AR5K_AR5212_QCU_MISC_CBREXP_BCN | 1187 AR5K_AR5212_QCU_MISC_BCN_ENABLE); 1188 1189 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), 1190 (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1191 AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL) | 1192 AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS | 1193 AR5K_AR5212_DCU_MISC_BCN_ENABLE); 1194 1195 AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), 1196 ((AR5K_TUNE_BEACON_INTERVAL - 1197 (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - 1198 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | 1199 AR5K_AR5212_QCU_RDYTIMECFG_ENABLE); 1200 break; 1201 1202 case HAL_TX_QUEUE_CAB: 1203 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1204 AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT | 1205 AR5K_AR5212_QCU_MISC_CBREXP | 1206 AR5K_AR5212_QCU_MISC_CBREXP_BCN); 1207 1208 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), 1209 (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1210 AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL)); 1211 break; 1212 1213 case HAL_TX_QUEUE_PSPOLL: 1214 AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), 1215 AR5K_AR5212_QCU_MISC_CBREXP); 1216 break; 1217 1218 case HAL_TX_QUEUE_DATA: 1219 default: 1220 break; 1221 } 1222 1223 /* 1224 * Enable tx queue in the secondary interrupt mask registers 1225 */ 1226 AR5K_REG_WRITE(AR5K_AR5212_SIMR0, 1227 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) | 1228 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC)); 1229 AR5K_REG_WRITE(AR5K_AR5212_SIMR1, 1230 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR)); 1231 AR5K_REG_WRITE(AR5K_AR5212_SIMR2, 1232 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN)); 1233 1234 return (AH_TRUE); 1235 } 1236 1237 u_int32_t 1238 ar5k_ar5212_get_tx_buf(struct ath_hal *hal, u_int queue) 1239 { 1240 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1241 1242 /* 1243 * Get the transmit queue descriptor pointer from the selected queue 1244 */ 1245 return (AR5K_REG_READ(AR5K_AR5212_QCU_TXDP(queue))); 1246 } 1247 1248 HAL_BOOL 1249 ar5k_ar5212_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) 1250 { 1251 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1252 1253 /* 1254 * Set the transmit queue descriptor pointer for the selected queue 1255 * (this won't work if the queue is still active) 1256 */ 1257 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, queue)) 1258 return (AH_FALSE); 1259 1260 AR5K_REG_WRITE(AR5K_AR5212_QCU_TXDP(queue), phys_addr); 1261 1262 return (AH_TRUE); 1263 } 1264 1265 u_int32_t 1266 ar5k_ar5212_num_tx_pending(struct ath_hal *hal, u_int queue) 1267 { 1268 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1269 return (AR5K_AR5212_QCU_STS(queue) & AR5K_AR5212_QCU_STS_FRMPENDCNT); 1270 } 1271 1272 HAL_BOOL 1273 ar5k_ar5212_tx_start(struct ath_hal *hal, u_int queue) 1274 { 1275 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1276 1277 /* Return if queue is disabled */ 1278 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXD, queue)) 1279 return (AH_FALSE); 1280 1281 /* Start queue */ 1282 AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXE, queue); 1283 1284 return (AH_TRUE); 1285 } 1286 1287 HAL_BOOL 1288 ar5k_ar5212_stop_tx_dma(struct ath_hal *hal, u_int queue) 1289 { 1290 int i = 100, pending; 1291 1292 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1293 1294 /* 1295 * Schedule TX disable and wait until queue is empty 1296 */ 1297 AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXD, queue); 1298 1299 do { 1300 pending = AR5K_REG_READ(AR5K_AR5212_QCU_STS(queue)) & 1301 AR5K_AR5212_QCU_STS_FRMPENDCNT; 1302 delay(100); 1303 } while (--i && pending); 1304 1305 /* Clear register */ 1306 AR5K_REG_WRITE(AR5K_AR5212_QCU_TXD, 0); 1307 1308 return (AH_TRUE); 1309 } 1310 1311 HAL_BOOL 1312 ar5k_ar5212_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1313 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, 1314 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, 1315 u_int flags, u_int rtscts_rate, u_int rtscts_duration) 1316 { 1317 struct ar5k_ar5212_tx_desc *tx_desc; 1318 1319 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1320 1321 /* 1322 * Validate input 1323 */ 1324 if (tx_tries0 == 0) 1325 return (AH_FALSE); 1326 1327 if ((tx_desc->tx_control_0 = (packet_length & 1328 AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN)) != packet_length) 1329 return (AH_FALSE); 1330 1331 tx_desc->tx_control_0 |= 1332 AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) | 1333 AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT); 1334 tx_desc->tx_control_1 = 1335 AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE); 1336 tx_desc->tx_control_2 = 1337 AR5K_REG_SM(tx_tries0, AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0); 1338 tx_desc->tx_control_3 = 1339 tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; 1340 1341 #define _TX_FLAGS(_c, _flag) \ 1342 if (flags & HAL_TXDESC_##_flag) \ 1343 tx_desc->tx_control_##_c |= \ 1344 AR5K_AR5212_DESC_TX_CTL##_c##_##_flag 1345 1346 _TX_FLAGS(0, CLRDMASK); 1347 _TX_FLAGS(0, VEOL); 1348 _TX_FLAGS(0, INTREQ); 1349 _TX_FLAGS(0, RTSENA); 1350 _TX_FLAGS(0, CTSENA); 1351 _TX_FLAGS(1, NOACK); 1352 1353 #undef _TX_FLAGS 1354 1355 /* 1356 * WEP crap 1357 */ 1358 if (key_index != HAL_TXKEYIX_INVALID) { 1359 tx_desc->tx_control_0 |= 1360 AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID; 1361 tx_desc->tx_control_1 |= 1362 AR5K_REG_SM(key_index, 1363 AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); 1364 } 1365 1366 /* 1367 * RTS/CTS 1368 */ 1369 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 1370 if ((flags & HAL_TXDESC_RTSENA) && 1371 (flags & HAL_TXDESC_CTSENA)) 1372 return (AH_FALSE); 1373 tx_desc->tx_control_2 |= 1374 rtscts_duration & AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION; 1375 tx_desc->tx_control_3 |= 1376 AR5K_REG_SM(rtscts_rate, 1377 AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE); 1378 } 1379 1380 return (AH_TRUE); 1381 } 1382 1383 HAL_BOOL 1384 ar5k_ar5212_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1385 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment) 1386 { 1387 struct ar5k_ar5212_tx_desc *tx_desc; 1388 struct ar5k_ar5212_tx_status *tx_status; 1389 1390 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1391 tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2]; 1392 1393 /* Clear status descriptor */ 1394 bzero(tx_status, sizeof(struct ar5k_ar5212_tx_status)); 1395 1396 /* Validate segment length and initialize the descriptor */ 1397 if (segment_length & ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN) 1398 return (AH_FALSE); 1399 tx_desc->tx_control_1 = 1400 #if 0 1401 (tx_desc->tx_control_1 & ~AR5K_AR5212_DESC_TX_CTL1_BUF_LEN) | 1402 #endif 1403 segment_length; 1404 1405 if (first_segment != AH_TRUE) 1406 tx_desc->tx_control_0 &= ~AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN; 1407 1408 if (last_segment != AH_TRUE) 1409 tx_desc->tx_control_1 |= AR5K_AR5212_DESC_TX_CTL1_MORE; 1410 1411 return (AH_TRUE); 1412 } 1413 1414 HAL_BOOL 1415 ar5k_ar5212_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, 1416 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 1417 u_int tx_rate3, u_int tx_tries3) 1418 { 1419 struct ar5k_ar5212_tx_desc *tx_desc; 1420 1421 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1422 1423 #define _XTX_TRIES(_n) \ 1424 if (tx_tries##_n) { \ 1425 tx_desc->tx_control_2 |= \ 1426 AR5K_REG_SM(tx_tries##_n, \ 1427 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES##_n); \ 1428 tx_desc->tx_control_3 |= \ 1429 AR5K_REG_SM(tx_rate##_n, \ 1430 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE##_n); \ 1431 } 1432 1433 _XTX_TRIES(1); 1434 _XTX_TRIES(2); 1435 _XTX_TRIES(3); 1436 1437 #undef _XTX_TRIES 1438 1439 return (AH_TRUE); 1440 } 1441 1442 HAL_STATUS 1443 ar5k_ar5212_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) 1444 { 1445 struct ar5k_ar5212_tx_status *tx_status; 1446 struct ar5k_ar5212_tx_desc *tx_desc; 1447 1448 tx_desc = (struct ar5k_ar5212_tx_desc*)&desc->ds_ctl0; 1449 tx_status = (struct ar5k_ar5212_tx_status*)&desc->ds_hw[2]; 1450 1451 /* No frame has been send or error */ 1452 if ((tx_status->tx_status_1 & AR5K_AR5212_DESC_TX_STATUS1_DONE) == 0) 1453 return (HAL_EINPROGRESS); 1454 1455 /* 1456 * Get descriptor status 1457 */ 1458 desc->ds_us.tx.ts_tstamp = 1459 AR5K_REG_MS(tx_status->tx_status_0, 1460 AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP); 1461 desc->ds_us.tx.ts_shortretry = 1462 AR5K_REG_MS(tx_status->tx_status_0, 1463 AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT); 1464 desc->ds_us.tx.ts_longretry = 1465 AR5K_REG_MS(tx_status->tx_status_0, 1466 AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT); 1467 desc->ds_us.tx.ts_seqnum = 1468 AR5K_REG_MS(tx_status->tx_status_1, 1469 AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM); 1470 desc->ds_us.tx.ts_rssi = 1471 AR5K_REG_MS(tx_status->tx_status_1, 1472 AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 1473 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 & 1474 AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1; 1475 desc->ds_us.tx.ts_status = 0; 1476 1477 switch (AR5K_REG_MS(tx_status->tx_status_1, 1478 AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX)) { 1479 case 0: 1480 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 & 1481 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0; 1482 break; 1483 case 1: 1484 desc->ds_us.tx.ts_rate = 1485 AR5K_REG_MS(tx_desc->tx_control_3, 1486 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1); 1487 desc->ds_us.tx.ts_longretry += 1488 AR5K_REG_MS(tx_desc->tx_control_2, 1489 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1); 1490 break; 1491 case 2: 1492 desc->ds_us.tx.ts_rate = 1493 AR5K_REG_MS(tx_desc->tx_control_3, 1494 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2); 1495 desc->ds_us.tx.ts_longretry += 1496 AR5K_REG_MS(tx_desc->tx_control_2, 1497 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2); 1498 break; 1499 case 3: 1500 desc->ds_us.tx.ts_rate = 1501 AR5K_REG_MS(tx_desc->tx_control_3, 1502 AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3); 1503 desc->ds_us.tx.ts_longretry += 1504 AR5K_REG_MS(tx_desc->tx_control_2, 1505 AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3); 1506 break; 1507 } 1508 1509 if ((tx_status->tx_status_0 & 1510 AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { 1511 if (tx_status->tx_status_0 & 1512 AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 1513 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; 1514 1515 if (tx_status->tx_status_0 & 1516 AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN) 1517 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; 1518 1519 if (tx_status->tx_status_0 & 1520 AR5K_AR5212_DESC_TX_STATUS0_FILTERED) 1521 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; 1522 } 1523 1524 return (HAL_OK); 1525 } 1526 1527 HAL_BOOL 1528 ar5k_ar5212_has_veol(struct ath_hal *hal) 1529 { 1530 return (AH_TRUE); 1531 } 1532 1533 /* 1534 * Receive functions 1535 */ 1536 1537 u_int32_t 1538 ar5k_ar5212_get_rx_buf(struct ath_hal *hal) 1539 { 1540 return (AR5K_REG_READ(AR5K_AR5212_RXDP)); 1541 } 1542 1543 void 1544 ar5k_ar5212_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) 1545 { 1546 AR5K_REG_WRITE(AR5K_AR5212_RXDP, phys_addr); 1547 } 1548 1549 void 1550 ar5k_ar5212_start_rx(struct ath_hal *hal) 1551 { 1552 AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXE); 1553 } 1554 1555 HAL_BOOL 1556 ar5k_ar5212_stop_rx_dma(struct ath_hal *hal) 1557 { 1558 int i; 1559 1560 AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXD); 1561 1562 /* 1563 * It may take some time to disable the DMA receive unit 1564 */ 1565 for (i = 2000; 1566 i > 0 && (AR5K_REG_READ(AR5K_AR5212_CR) & AR5K_AR5212_CR_RXE) != 0; 1567 i--) 1568 AR5K_DELAY(10); 1569 1570 return (i > 0 ? AH_TRUE : AH_FALSE); 1571 } 1572 1573 void 1574 ar5k_ar5212_start_rx_pcu(struct ath_hal *hal) 1575 { 1576 AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX); 1577 } 1578 1579 void 1580 ar5k_ar5212_stop_pcu_recv(struct ath_hal *hal) 1581 { 1582 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX); 1583 } 1584 1585 void 1586 ar5k_ar5212_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, 1587 u_int32_t filter1) 1588 { 1589 /* Set the multicat filter */ 1590 AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL0, filter0); 1591 AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL1, filter1); 1592 } 1593 1594 HAL_BOOL 1595 ar5k_ar5212_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) 1596 { 1597 if (index >= 64) { 1598 return (AH_FALSE); 1599 } else if (index >= 32) { 1600 AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL1, 1601 (1 << (index - 32))); 1602 } else { 1603 AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL0, 1604 (1 << index)); 1605 } 1606 1607 return (AH_TRUE); 1608 } 1609 1610 HAL_BOOL 1611 ar5k_ar5212_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) 1612 { 1613 1614 if (index >= 64) { 1615 return (AH_FALSE); 1616 } else if (index >= 32) { 1617 AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL1, 1618 (1 << (index - 32))); 1619 } else { 1620 AR5K_REG_DISABLE_BITS(AR5K_AR5212_MCAST_FIL0, 1621 (1 << index)); 1622 } 1623 1624 return (AH_TRUE); 1625 } 1626 1627 u_int32_t 1628 ar5k_ar5212_get_rx_filter(struct ath_hal *hal) 1629 { 1630 u_int32_t data, filter = 0; 1631 1632 filter = AR5K_REG_READ(AR5K_AR5212_RX_FILTER); 1633 data = AR5K_REG_READ(AR5K_AR5212_PHY_ERR_FIL); 1634 1635 if (data & AR5K_AR5212_PHY_ERR_FIL_RADAR) 1636 filter |= HAL_RX_FILTER_PHYRADAR; 1637 if (data & (AR5K_AR5212_PHY_ERR_FIL_OFDM | 1638 AR5K_AR5212_PHY_ERR_FIL_CCK)) 1639 filter |= HAL_RX_FILTER_PHYERR; 1640 1641 return (filter); 1642 } 1643 1644 void 1645 ar5k_ar5212_set_rx_filter(struct ath_hal *hal, u_int32_t filter) 1646 { 1647 u_int32_t data = 0; 1648 1649 if (filter & HAL_RX_FILTER_PHYRADAR) 1650 data |= AR5K_AR5212_PHY_ERR_FIL_RADAR; 1651 if (filter & HAL_RX_FILTER_PHYERR) 1652 data |= AR5K_AR5212_PHY_ERR_FIL_OFDM | 1653 AR5K_AR5212_PHY_ERR_FIL_CCK; 1654 1655 if (data) { 1656 AR5K_REG_ENABLE_BITS(AR5K_AR5212_RXCFG, 1657 AR5K_AR5212_RXCFG_ZLFDMA); 1658 } else { 1659 AR5K_REG_DISABLE_BITS(AR5K_AR5212_RXCFG, 1660 AR5K_AR5212_RXCFG_ZLFDMA); 1661 } 1662 1663 AR5K_REG_WRITE(AR5K_AR5212_RX_FILTER, filter & 0xff); 1664 AR5K_REG_WRITE(AR5K_AR5212_PHY_ERR_FIL, data); 1665 } 1666 1667 HAL_BOOL 1668 ar5k_ar5212_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1669 u_int32_t size, u_int flags) 1670 { 1671 struct ar5k_ar5212_rx_desc *rx_desc; 1672 1673 rx_desc = (struct ar5k_ar5212_rx_desc*)&desc->ds_ctl0; 1674 1675 if ((rx_desc->rx_control_1 = (size & 1676 AR5K_AR5212_DESC_RX_CTL1_BUF_LEN)) != size) 1677 return (AH_FALSE); 1678 1679 if (flags & HAL_RXDESC_INTREQ) 1680 rx_desc->rx_control_1 |= AR5K_AR5212_DESC_RX_CTL1_INTREQ; 1681 1682 return (AH_TRUE); 1683 } 1684 1685 HAL_STATUS 1686 ar5k_ar5212_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1687 u_int32_t phys_addr, struct ath_desc *next) 1688 { 1689 struct ar5k_ar5212_rx_status *rx_status; 1690 struct ar5k_ar5212_rx_error *rx_err; 1691 1692 rx_status = (struct ar5k_ar5212_rx_status*)&desc->ds_hw[0]; 1693 1694 /* Overlay on error */ 1695 rx_err = (struct ar5k_ar5212_rx_error*)&desc->ds_hw[0]; 1696 1697 /* No frame received / not ready */ 1698 if ((rx_status->rx_status_1 & AR5K_AR5212_DESC_RX_STATUS1_DONE) == 0) 1699 return (HAL_EINPROGRESS); 1700 1701 /* 1702 * Frame receive status 1703 */ 1704 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 1705 AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN; 1706 desc->ds_us.rx.rs_rssi = 1707 AR5K_REG_MS(rx_status->rx_status_0, 1708 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL); 1709 desc->ds_us.rx.rs_rate = 1710 AR5K_REG_MS(rx_status->rx_status_0, 1711 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE); 1712 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 1713 AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA; 1714 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 1715 AR5K_AR5212_DESC_RX_STATUS0_MORE; 1716 desc->ds_us.rx.rs_tstamp = 1717 AR5K_REG_MS(rx_status->rx_status_1, 1718 AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); 1719 desc->ds_us.rx.rs_status = 0; 1720 1721 /* 1722 * Key table status 1723 */ 1724 if (rx_status->rx_status_1 & 1725 AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID) { 1726 desc->ds_us.rx.rs_keyix = 1727 AR5K_REG_MS(rx_status->rx_status_1, 1728 AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX); 1729 } else { 1730 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; 1731 } 1732 1733 /* 1734 * Receive/descriptor errors 1735 */ 1736 if ((rx_status->rx_status_1 & 1737 AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { 1738 if (rx_status->rx_status_1 & 1739 AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR) 1740 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; 1741 1742 if (rx_status->rx_status_1 & 1743 AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR) { 1744 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; 1745 desc->ds_us.rx.rs_phyerr = 1746 AR5K_REG_MS(rx_err->rx_error_1, 1747 AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE); 1748 } 1749 1750 if (rx_status->rx_status_1 & 1751 AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) 1752 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; 1753 1754 if (rx_status->rx_status_1 & 1755 AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR) 1756 desc->ds_us.rx.rs_status |= HAL_RXERR_MIC; 1757 } 1758 1759 return (HAL_OK); 1760 } 1761 1762 void 1763 ar5k_ar5212_set_rx_signal(struct ath_hal *hal) 1764 { 1765 /* Signal state monitoring is not yet supported */ 1766 } 1767 1768 /* 1769 * Misc functions 1770 */ 1771 1772 void 1773 ar5k_ar5212_dump_state(struct ath_hal *hal) 1774 { 1775 #ifdef AR5K_DEBUG 1776 #define AR5K_PRINT_REGISTER(_x) \ 1777 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5212_##_x)); 1778 1779 printf("MAC registers:\n"); 1780 AR5K_PRINT_REGISTER(CR); 1781 AR5K_PRINT_REGISTER(CFG); 1782 AR5K_PRINT_REGISTER(IER); 1783 AR5K_PRINT_REGISTER(TXCFG); 1784 AR5K_PRINT_REGISTER(RXCFG); 1785 AR5K_PRINT_REGISTER(MIBC); 1786 AR5K_PRINT_REGISTER(TOPS); 1787 AR5K_PRINT_REGISTER(RXNOFRM); 1788 AR5K_PRINT_REGISTER(RPGTO); 1789 AR5K_PRINT_REGISTER(RFCNT); 1790 AR5K_PRINT_REGISTER(MISC); 1791 AR5K_PRINT_REGISTER(PISR); 1792 AR5K_PRINT_REGISTER(SISR0); 1793 AR5K_PRINT_REGISTER(SISR1); 1794 AR5K_PRINT_REGISTER(SISR3); 1795 AR5K_PRINT_REGISTER(SISR4); 1796 AR5K_PRINT_REGISTER(DCM_ADDR); 1797 AR5K_PRINT_REGISTER(DCM_DATA); 1798 AR5K_PRINT_REGISTER(DCCFG); 1799 AR5K_PRINT_REGISTER(CCFG); 1800 AR5K_PRINT_REGISTER(CCFG_CUP); 1801 AR5K_PRINT_REGISTER(CPC0); 1802 AR5K_PRINT_REGISTER(CPC1); 1803 AR5K_PRINT_REGISTER(CPC2); 1804 AR5K_PRINT_REGISTER(CPCORN); 1805 AR5K_PRINT_REGISTER(QCU_TXE); 1806 AR5K_PRINT_REGISTER(QCU_TXD); 1807 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); 1808 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); 1809 AR5K_PRINT_REGISTER(DCU_FP); 1810 AR5K_PRINT_REGISTER(DCU_TXP); 1811 AR5K_PRINT_REGISTER(DCU_TX_FILTER); 1812 AR5K_PRINT_REGISTER(RC); 1813 AR5K_PRINT_REGISTER(SCR); 1814 AR5K_PRINT_REGISTER(INTPEND); 1815 AR5K_PRINT_REGISTER(PCICFG); 1816 AR5K_PRINT_REGISTER(GPIOCR); 1817 AR5K_PRINT_REGISTER(GPIODO); 1818 AR5K_PRINT_REGISTER(SREV); 1819 AR5K_PRINT_REGISTER(EEPROM_BASE); 1820 AR5K_PRINT_REGISTER(EEPROM_DATA); 1821 AR5K_PRINT_REGISTER(EEPROM_CMD); 1822 AR5K_PRINT_REGISTER(EEPROM_CFG); 1823 AR5K_PRINT_REGISTER(PCU_MIN); 1824 AR5K_PRINT_REGISTER(STA_ID0); 1825 AR5K_PRINT_REGISTER(STA_ID1); 1826 AR5K_PRINT_REGISTER(BSS_ID0); 1827 AR5K_PRINT_REGISTER(SLOT_TIME); 1828 AR5K_PRINT_REGISTER(TIME_OUT); 1829 AR5K_PRINT_REGISTER(RSSI_THR); 1830 AR5K_PRINT_REGISTER(BEACON); 1831 AR5K_PRINT_REGISTER(CFP_PERIOD); 1832 AR5K_PRINT_REGISTER(TIMER0); 1833 AR5K_PRINT_REGISTER(TIMER2); 1834 AR5K_PRINT_REGISTER(TIMER3); 1835 AR5K_PRINT_REGISTER(CFP_DUR); 1836 AR5K_PRINT_REGISTER(MCAST_FIL0); 1837 AR5K_PRINT_REGISTER(MCAST_FIL1); 1838 AR5K_PRINT_REGISTER(DIAG_SW); 1839 AR5K_PRINT_REGISTER(TSF_U32); 1840 AR5K_PRINT_REGISTER(ADDAC_TEST); 1841 AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); 1842 AR5K_PRINT_REGISTER(LAST_TSTP); 1843 AR5K_PRINT_REGISTER(NAV); 1844 AR5K_PRINT_REGISTER(RTS_OK); 1845 AR5K_PRINT_REGISTER(ACK_FAIL); 1846 AR5K_PRINT_REGISTER(FCS_FAIL); 1847 AR5K_PRINT_REGISTER(BEACON_CNT); 1848 AR5K_PRINT_REGISTER(TSF_PARM); 1849 AR5K_PRINT_REGISTER(RATE_DUR_0); 1850 AR5K_PRINT_REGISTER(KEYTABLE_0); 1851 printf("\n"); 1852 1853 printf("PHY registers:\n"); 1854 AR5K_PRINT_REGISTER(PHY_TURBO); 1855 AR5K_PRINT_REGISTER(PHY_AGC); 1856 AR5K_PRINT_REGISTER(PHY_TIMING_3); 1857 AR5K_PRINT_REGISTER(PHY_CHIP_ID); 1858 AR5K_PRINT_REGISTER(PHY_AGCCTL); 1859 AR5K_PRINT_REGISTER(PHY_NF); 1860 AR5K_PRINT_REGISTER(PHY_SCR); 1861 AR5K_PRINT_REGISTER(PHY_SLMT); 1862 AR5K_PRINT_REGISTER(PHY_SCAL); 1863 AR5K_PRINT_REGISTER(PHY_RX_DELAY); 1864 AR5K_PRINT_REGISTER(PHY_IQ); 1865 AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); 1866 AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE1); 1867 AR5K_PRINT_REGISTER(PHY_TXPOWER_RATE2); 1868 AR5K_PRINT_REGISTER(PHY_FC); 1869 AR5K_PRINT_REGISTER(PHY_RADAR); 1870 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); 1871 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); 1872 printf("\n"); 1873 #endif 1874 } 1875 1876 HAL_BOOL 1877 ar5k_ar5212_get_diag_state(struct ath_hal *hal, int id, void **device, 1878 u_int *size) 1879 { 1880 /* 1881 * We'll ignore this right now. This seems to be some kind of an obscure 1882 * debugging interface for the binary-only HAL. 1883 */ 1884 return (AH_FALSE); 1885 } 1886 1887 void 1888 ar5k_ar5212_get_lladdr(struct ath_hal *hal, u_int8_t *mac) 1889 { 1890 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); 1891 } 1892 1893 HAL_BOOL 1894 ar5k_ar5212_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) 1895 { 1896 u_int32_t low_id, high_id; 1897 1898 /* Set new station ID */ 1899 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); 1900 1901 low_id = AR5K_LOW_ID(mac); 1902 high_id = 0x0000ffff & AR5K_HIGH_ID(mac); 1903 1904 AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); 1905 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, high_id); 1906 1907 return (AH_TRUE); 1908 } 1909 1910 HAL_BOOL 1911 ar5k_ar5212_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, 1912 HAL_STATUS *status) 1913 { 1914 ieee80211_regdomain_t ieee_regdomain; 1915 1916 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); 1917 1918 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, 1919 &ieee_regdomain) == AH_TRUE) { 1920 *status = HAL_OK; 1921 return (AH_TRUE); 1922 } 1923 1924 *status = EIO; 1925 1926 return (AH_FALSE); 1927 } 1928 1929 void 1930 ar5k_ar5212_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) 1931 { 1932 u_int32_t led; 1933 1934 AR5K_REG_DISABLE_BITS(AR5K_AR5212_PCICFG, 1935 AR5K_AR5212_PCICFG_LEDMODE | AR5K_AR5212_PCICFG_LED); 1936 1937 /* 1938 * Some blinking values, define at your wish 1939 */ 1940 switch (state) { 1941 case IEEE80211_S_SCAN: 1942 case IEEE80211_S_AUTH: 1943 led = AR5K_AR5212_PCICFG_LEDMODE_PROP | 1944 AR5K_AR5212_PCICFG_LED_PEND; 1945 break; 1946 1947 case IEEE80211_S_INIT: 1948 led = AR5K_AR5212_PCICFG_LEDMODE_PROP | 1949 AR5K_AR5212_PCICFG_LED_NONE; 1950 break; 1951 1952 case IEEE80211_S_ASSOC: 1953 case IEEE80211_S_RUN: 1954 led = AR5K_AR5212_PCICFG_LEDMODE_PROP | 1955 AR5K_AR5212_PCICFG_LED_ASSOC; 1956 break; 1957 1958 default: 1959 led = AR5K_AR5212_PCICFG_LEDMODE_PROM | 1960 AR5K_AR5212_PCICFG_LED_NONE; 1961 break; 1962 } 1963 1964 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, led); 1965 } 1966 1967 void 1968 ar5k_ar5212_set_associd(struct ath_hal *hal, const u_int8_t *bssid, 1969 u_int16_t assoc_id, u_int16_t tim_offset) 1970 { 1971 u_int32_t low_id, high_id; 1972 1973 /* 1974 * Set simple BSSID mask 1975 */ 1976 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, 0xfffffff); 1977 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, 0xfffffff); 1978 1979 /* 1980 * Set BSSID which triggers the "SME Join" operation 1981 */ 1982 low_id = AR5K_LOW_ID(bssid); 1983 high_id = AR5K_HIGH_ID(bssid); 1984 AR5K_REG_WRITE(AR5K_AR5212_BSS_ID0, low_id); 1985 AR5K_REG_WRITE(AR5K_AR5212_BSS_ID1, high_id | 1986 ((assoc_id & 0x3fff) << AR5K_AR5212_BSS_ID1_AID_S)); 1987 bcopy(bssid, &hal->ah_bssid, IEEE80211_ADDR_LEN); 1988 1989 if (assoc_id == 0) { 1990 ar5k_ar5212_disable_pspoll(hal); 1991 return; 1992 } 1993 1994 AR5K_REG_WRITE(AR5K_AR5212_BEACON, 1995 (AR5K_REG_READ(AR5K_AR5212_BEACON) & 1996 ~AR5K_AR5212_BEACON_TIM) | 1997 (((tim_offset ? tim_offset + 4 : 0) << 1998 AR5K_AR5212_BEACON_TIM_S) & 1999 AR5K_AR5212_BEACON_TIM)); 2000 2001 ar5k_ar5212_enable_pspoll(hal, NULL, 0); 2002 } 2003 2004 HAL_BOOL 2005 ar5k_ar5212_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) 2006 { 2007 u_int32_t low_id, high_id; 2008 2009 low_id = AR5K_LOW_ID(mask); 2010 high_id = 0x0000ffff & AR5K_HIGH_ID(mask); 2011 2012 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, low_id); 2013 AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, high_id); 2014 2015 return (AH_TRUE); 2016 } 2017 2018 HAL_BOOL 2019 ar5k_ar5212_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) 2020 { 2021 if (gpio > AR5K_AR5212_NUM_GPIO) 2022 return (AH_FALSE); 2023 2024 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, 2025 (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) 2026 | AR5K_AR5212_GPIOCR_ALL(gpio)); 2027 2028 return (AH_TRUE); 2029 } 2030 2031 HAL_BOOL 2032 ar5k_ar5212_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) 2033 { 2034 if (gpio > AR5K_AR5212_NUM_GPIO) 2035 return (AH_FALSE); 2036 2037 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, 2038 (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio)) 2039 | AR5K_AR5212_GPIOCR_NONE(gpio)); 2040 2041 return (AH_TRUE); 2042 } 2043 2044 u_int32_t 2045 ar5k_ar5212_get_gpio(struct ath_hal *hal, u_int32_t gpio) 2046 { 2047 if (gpio > AR5K_AR5212_NUM_GPIO) 2048 return (0xffffffff); 2049 2050 /* GPIO input magic */ 2051 return (((AR5K_REG_READ(AR5K_AR5212_GPIODI) & 2052 AR5K_AR5212_GPIODI_M) >> gpio) & 0x1); 2053 } 2054 2055 HAL_BOOL 2056 ar5k_ar5212_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) 2057 { 2058 u_int32_t data; 2059 2060 if (gpio > AR5K_AR5212_NUM_GPIO) 2061 return (0xffffffff); 2062 2063 /* GPIO output magic */ 2064 data = AR5K_REG_READ(AR5K_AR5212_GPIODO); 2065 2066 data &= ~(1 << gpio); 2067 data |= (val&1) << gpio; 2068 2069 AR5K_REG_WRITE(AR5K_AR5212_GPIODO, data); 2070 2071 return (AH_TRUE); 2072 } 2073 2074 void 2075 ar5k_ar5212_set_gpio_intr(struct ath_hal *hal, u_int gpio, 2076 u_int32_t interrupt_level) 2077 { 2078 u_int32_t data; 2079 2080 if (gpio > AR5K_AR5212_NUM_GPIO) 2081 return; 2082 2083 /* 2084 * Set the GPIO interrupt 2085 */ 2086 data = (AR5K_REG_READ(AR5K_AR5212_GPIOCR) & 2087 ~(AR5K_AR5212_GPIOCR_INT_SEL(gpio) | AR5K_AR5212_GPIOCR_INT_SELH | 2088 AR5K_AR5212_GPIOCR_INT_ENA | AR5K_AR5212_GPIOCR_ALL(gpio))) | 2089 (AR5K_AR5212_GPIOCR_INT_SEL(gpio) | AR5K_AR5212_GPIOCR_INT_ENA); 2090 2091 AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, 2092 interrupt_level ? data : (data | AR5K_AR5212_GPIOCR_INT_SELH)); 2093 2094 hal->ah_imr |= AR5K_AR5212_PIMR_GPIO; 2095 2096 /* Enable GPIO interrupts */ 2097 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, AR5K_AR5212_PIMR_GPIO); 2098 } 2099 2100 u_int32_t 2101 ar5k_ar5212_get_tsf32(struct ath_hal *hal) 2102 { 2103 return (AR5K_REG_READ(AR5K_AR5212_TSF_L32)); 2104 } 2105 2106 u_int64_t 2107 ar5k_ar5212_get_tsf64(struct ath_hal *hal) 2108 { 2109 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32); 2110 2111 return (AR5K_REG_READ(AR5K_AR5212_TSF_L32) | (tsf << 32)); 2112 } 2113 2114 void 2115 ar5k_ar5212_reset_tsf(struct ath_hal *hal) 2116 { 2117 AR5K_REG_ENABLE_BITS(AR5K_AR5212_BEACON, 2118 AR5K_AR5212_BEACON_RESET_TSF); 2119 } 2120 2121 u_int16_t 2122 ar5k_ar5212_get_regdomain(struct ath_hal *hal) 2123 { 2124 return (ar5k_get_regdomain(hal)); 2125 } 2126 2127 HAL_BOOL 2128 ar5k_ar5212_detect_card_present(struct ath_hal *hal) 2129 { 2130 u_int16_t magic; 2131 2132 /* 2133 * Checking the EEPROM's magic value could be an indication 2134 * if the card is still present. I didn't find another suitable 2135 * way to do this. 2136 */ 2137 if (ar5k_ar5212_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) 2138 return (AH_FALSE); 2139 2140 return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); 2141 } 2142 2143 void 2144 ar5k_ar5212_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) 2145 { 2146 /* Read-And-Clear */ 2147 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5212_ACK_FAIL); 2148 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5212_RTS_FAIL); 2149 statistics->rts_good += AR5K_REG_READ(AR5K_AR5212_RTS_OK); 2150 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5212_FCS_FAIL); 2151 statistics->beacons += AR5K_REG_READ(AR5K_AR5212_BEACON_CNT); 2152 2153 /* Reset profile count registers */ 2154 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_TX, 0); 2155 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RX, 0); 2156 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RXCLR, 0); 2157 AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_CYCLE, 0); 2158 } 2159 2160 HAL_RFGAIN 2161 ar5k_ar5212_get_rf_gain(struct ath_hal *hal) 2162 { 2163 u_int32_t data, type; 2164 2165 if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active)) 2166 return (HAL_RFGAIN_INACTIVE); 2167 2168 if (hal->ah_rf_gain != HAL_RFGAIN_READ_REQUESTED) 2169 goto done; 2170 2171 data = AR5K_REG_READ(AR5K_AR5212_PHY_PAPD_PROBE); 2172 2173 if (!(data & AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT)) { 2174 hal->ah_gain.g_current = 2175 data >> AR5K_AR5212_PHY_PAPD_PROBE_GAINF_S; 2176 type = AR5K_REG_MS(data, AR5K_AR5212_PHY_PAPD_PROBE_TYPE); 2177 2178 if (type == AR5K_AR5212_PHY_PAPD_PROBE_TYPE_CCK) 2179 hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR; 2180 2181 if (hal->ah_radio >= AR5K_AR5112) { 2182 ar5k_rfregs_gainf_corr(hal); 2183 hal->ah_gain.g_current = 2184 hal->ah_gain.g_current >= hal->ah_gain.g_f_corr ? 2185 (hal->ah_gain.g_current - hal->ah_gain.g_f_corr) : 2186 0; 2187 } 2188 2189 if (ar5k_rfregs_gain_readback(hal) && 2190 AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) && 2191 ar5k_rfregs_gain_adjust(hal)) 2192 hal->ah_rf_gain = HAL_RFGAIN_NEED_CHANGE; 2193 } 2194 2195 done: 2196 return (hal->ah_rf_gain); 2197 } 2198 2199 HAL_BOOL 2200 ar5k_ar5212_set_slot_time(struct ath_hal *hal, u_int slot_time) 2201 { 2202 if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) 2203 return (AH_FALSE); 2204 2205 AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT, slot_time); 2206 2207 return (AH_TRUE); 2208 } 2209 2210 u_int 2211 ar5k_ar5212_get_slot_time(struct ath_hal *hal) 2212 { 2213 return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff); 2214 } 2215 2216 HAL_BOOL 2217 ar5k_ar5212_set_ack_timeout(struct ath_hal *hal, u_int timeout) 2218 { 2219 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_ACK)) 2220 <= timeout) 2221 return (AH_FALSE); 2222 2223 AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_ACK, 2224 ar5k_htoclock(timeout)); 2225 2226 return (AH_TRUE); 2227 } 2228 2229 u_int 2230 ar5k_ar5212_get_ack_timeout(struct ath_hal *hal) 2231 { 2232 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT), 2233 AR5K_AR5212_TIME_OUT_ACK))); 2234 } 2235 2236 HAL_BOOL 2237 ar5k_ar5212_set_cts_timeout(struct ath_hal *hal, u_int timeout) 2238 { 2239 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5212_TIME_OUT_CTS)) 2240 <= timeout) 2241 return (AH_FALSE); 2242 2243 AR5K_REG_WRITE_BITS(AR5K_AR5212_TIME_OUT, AR5K_AR5212_TIME_OUT_CTS, 2244 ar5k_htoclock(timeout)); 2245 2246 return (AH_TRUE); 2247 } 2248 2249 u_int 2250 ar5k_ar5212_get_cts_timeout(struct ath_hal *hal) 2251 { 2252 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT), 2253 AR5K_AR5212_TIME_OUT_CTS))); 2254 } 2255 2256 /* 2257 * Key table (WEP) functions 2258 */ 2259 2260 HAL_BOOL 2261 ar5k_ar5212_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) 2262 { 2263 /* 2264 * The AR5212 only supports WEP 2265 */ 2266 if (cipher == HAL_CIPHER_WEP) 2267 return (AH_TRUE); 2268 2269 return (AH_FALSE); 2270 } 2271 2272 u_int32_t 2273 ar5k_ar5212_get_keycache_size(struct ath_hal *hal) 2274 { 2275 return (AR5K_AR5212_KEYCACHE_SIZE); 2276 } 2277 2278 HAL_BOOL 2279 ar5k_ar5212_reset_key(struct ath_hal *hal, u_int16_t entry) 2280 { 2281 int i; 2282 2283 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2284 2285 for (i = 0; i < AR5K_AR5212_KEYCACHE_SIZE; i++) 2286 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), 0); 2287 2288 /* Set NULL encryption */ 2289 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_TYPE(entry), 2290 AR5K_AR5212_KEYTABLE_TYPE_NULL); 2291 2292 return (AH_FALSE); 2293 } 2294 2295 HAL_BOOL 2296 ar5k_ar5212_is_key_valid(struct ath_hal *hal, u_int16_t entry) 2297 { 2298 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2299 2300 /* 2301 * Check the validation flag at the end of the entry 2302 */ 2303 if (AR5K_REG_READ(AR5K_AR5212_KEYTABLE_MAC1(entry)) & 2304 AR5K_AR5212_KEYTABLE_VALID) 2305 return (AH_TRUE); 2306 2307 return (AH_FALSE); 2308 } 2309 2310 HAL_BOOL 2311 ar5k_ar5212_set_key(struct ath_hal *hal, u_int16_t entry, 2312 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) 2313 { 2314 int i; 2315 u_int32_t key_v[AR5K_AR5212_KEYCACHE_SIZE - 2]; 2316 2317 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2318 2319 bzero(&key_v, sizeof(key_v)); 2320 2321 switch (keyval->wk_len) { 2322 case AR5K_KEYVAL_LENGTH_40: 2323 bcopy(keyval->wk_key, &key_v[0], 4); 2324 bcopy(keyval->wk_key + 4, &key_v[1], 1); 2325 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_40; 2326 break; 2327 2328 case AR5K_KEYVAL_LENGTH_104: 2329 bcopy(keyval->wk_key, &key_v[0], 4); 2330 bcopy(keyval->wk_key + 4, &key_v[1], 2); 2331 bcopy(keyval->wk_key + 6, &key_v[2], 4); 2332 bcopy(keyval->wk_key + 10, &key_v[3], 2); 2333 bcopy(keyval->wk_key + 12, &key_v[4], 1); 2334 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_104; 2335 break; 2336 2337 case AR5K_KEYVAL_LENGTH_128: 2338 bcopy(keyval->wk_key, &key_v[0], 4); 2339 bcopy(keyval->wk_key + 4, &key_v[1], 2); 2340 bcopy(keyval->wk_key + 6, &key_v[2], 4); 2341 bcopy(keyval->wk_key + 10, &key_v[3], 2); 2342 bcopy(keyval->wk_key + 12, &key_v[4], 4); 2343 key_v[5] = AR5K_AR5212_KEYTABLE_TYPE_128; 2344 break; 2345 2346 default: 2347 /* Unsupported key length (not WEP40/104/128) */ 2348 return (AH_FALSE); 2349 } 2350 2351 for (i = 0; i < nitems(key_v); i++) 2352 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), key_v[i]); 2353 2354 return (ar5k_ar5212_set_key_lladdr(hal, entry, mac)); 2355 } 2356 2357 HAL_BOOL 2358 ar5k_ar5212_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, 2359 const u_int8_t *mac) 2360 { 2361 u_int32_t low_id, high_id; 2362 const u_int8_t *mac_v; 2363 2364 /* 2365 * Invalid entry (key table overflow) 2366 */ 2367 AR5K_ASSERT_ENTRY(entry, AR5K_AR5212_KEYTABLE_SIZE); 2368 2369 /* MAC may be NULL if it's a broadcast key */ 2370 mac_v = mac == NULL ? etherbroadcastaddr : mac; 2371 2372 low_id = AR5K_LOW_ID(mac_v); 2373 high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5212_KEYTABLE_VALID; 2374 2375 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC0(entry), low_id); 2376 AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC1(entry), high_id); 2377 2378 return (AH_TRUE); 2379 } 2380 2381 HAL_BOOL 2382 ar5k_ar5212_softcrypto(struct ath_hal *hal, HAL_BOOL enable) 2383 { 2384 u_int32_t bits; 2385 int i; 2386 2387 bits = AR5K_AR5212_DIAG_SW_DIS_ENC | AR5K_AR5212_DIAG_SW_DIS_DEC; 2388 if (enable == AH_TRUE) { 2389 /* Disable the hardware crypto engine */ 2390 AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, bits); 2391 } else { 2392 /* Enable the hardware crypto engine */ 2393 AR5K_REG_DISABLE_BITS(AR5K_AR5212_DIAG_SW, bits); 2394 } 2395 2396 /* Reset the key cache */ 2397 for (i = 0; i < AR5K_AR5212_KEYTABLE_SIZE; i++) 2398 ar5k_ar5212_reset_key(hal, i); 2399 2400 return (AH_TRUE); 2401 } 2402 2403 /* 2404 * warm reset MAC and PHY 2405 */ 2406 2407 HAL_BOOL 2408 ar5k_ar5212_warm_reset(struct ath_hal *hal) 2409 { 2410 u_int32_t flags; 2411 2412 flags = AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB; 2413 if (hal->ah_pci_express == AH_FALSE) 2414 flags |= AR5K_AR5212_RC_PCI; 2415 2416 /* reset chipset and PCI device */ 2417 if (ar5k_ar5212_nic_reset(hal, flags) == AH_FALSE) 2418 return (AH_FALSE); 2419 2420 /* wakeup */ 2421 if (ar5k_ar5212_set_power(hal, 2422 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) 2423 return (AH_FALSE); 2424 2425 /* reset chipset */ 2426 if (ar5k_ar5212_nic_reset(hal, 0) == AH_FALSE) 2427 return (AH_FALSE); 2428 2429 return (AH_TRUE); 2430 } 2431 2432 /* 2433 * Power management functions 2434 */ 2435 2436 HAL_BOOL 2437 ar5k_ar5212_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, 2438 HAL_BOOL set_chip, u_int16_t sleep_duration) 2439 { 2440 u_int32_t staid; 2441 int i; 2442 2443 staid = AR5K_REG_READ(AR5K_AR5212_STA_ID1); 2444 2445 switch (mode) { 2446 case HAL_PM_AUTO: 2447 staid &= ~AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA; 2448 /* FALLTHROUGH */ 2449 case HAL_PM_NETWORK_SLEEP: 2450 if (set_chip == AH_TRUE) { 2451 AR5K_REG_WRITE(AR5K_AR5212_SCR, 2452 AR5K_AR5212_SCR_SLE | sleep_duration); 2453 } 2454 staid |= AR5K_AR5212_STA_ID1_PWR_SV; 2455 break; 2456 2457 case HAL_PM_FULL_SLEEP: 2458 if (set_chip == AH_TRUE) 2459 if (ar5k_ar5212_warm_reset(hal) == AH_FALSE) 2460 return (AH_FALSE); 2461 staid |= AR5K_AR5212_STA_ID1_PWR_SV; 2462 break; 2463 2464 case HAL_PM_AWAKE: 2465 if (set_chip == AH_FALSE) 2466 goto commit; 2467 2468 AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE_WAKE); 2469 2470 for (i = 5000; i > 0; i--) { 2471 /* Check if the AR5212 did wake up */ 2472 if ((AR5K_REG_READ(AR5K_AR5212_PCICFG) & 2473 AR5K_AR5212_PCICFG_SPWR_DN) == 0) 2474 break; 2475 2476 /* Wait a bit and retry */ 2477 AR5K_DELAY(200); 2478 AR5K_REG_WRITE(AR5K_AR5212_SCR, 2479 AR5K_AR5212_SCR_SLE_WAKE); 2480 } 2481 2482 /* Fail if the AR5212 didn't wake up */ 2483 if (i <= 0) 2484 return (AH_FALSE); 2485 2486 staid &= ~AR5K_AR5212_STA_ID1_PWR_SV; 2487 break; 2488 2489 default: 2490 return (AH_FALSE); 2491 } 2492 2493 commit: 2494 hal->ah_power_mode = mode; 2495 2496 AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, staid); 2497 2498 return (AH_TRUE); 2499 } 2500 2501 HAL_POWER_MODE 2502 ar5k_ar5212_get_power_mode(struct ath_hal *hal) 2503 { 2504 return (hal->ah_power_mode); 2505 } 2506 2507 HAL_BOOL 2508 ar5k_ar5212_query_pspoll_support(struct ath_hal *hal) 2509 { 2510 /* nope */ 2511 return (AH_FALSE); 2512 } 2513 2514 HAL_BOOL 2515 ar5k_ar5212_init_pspoll(struct ath_hal *hal) 2516 { 2517 /* 2518 * Not used on the AR5212 2519 */ 2520 return (AH_FALSE); 2521 } 2522 2523 HAL_BOOL 2524 ar5k_ar5212_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, 2525 u_int16_t assoc_id) 2526 { 2527 return (AH_FALSE); 2528 } 2529 2530 HAL_BOOL 2531 ar5k_ar5212_disable_pspoll(struct ath_hal *hal) 2532 { 2533 return (AH_FALSE); 2534 } 2535 2536 /* 2537 * Beacon functions 2538 */ 2539 2540 void 2541 ar5k_ar5212_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, 2542 u_int32_t interval) 2543 { 2544 u_int32_t timer1, timer2, timer3; 2545 2546 /* 2547 * Set the additional timers by mode 2548 */ 2549 switch (hal->ah_op_mode) { 2550 case HAL_M_STA: 2551 timer1 = 0x0000ffff; 2552 timer2 = 0x0007ffff; 2553 break; 2554 2555 default: 2556 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 2557 0x00000003; 2558 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 2559 0x00000003; 2560 } 2561 2562 timer3 = next_beacon + 2563 (hal->ah_atim_window ? hal->ah_atim_window : 1); 2564 2565 /* 2566 * Enable all timers and set the beacon register 2567 * (next beacon, DMA beacon, software beacon, ATIM window time) 2568 */ 2569 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, next_beacon); 2570 AR5K_REG_WRITE(AR5K_AR5212_TIMER1, timer1); 2571 AR5K_REG_WRITE(AR5K_AR5212_TIMER2, timer2); 2572 AR5K_REG_WRITE(AR5K_AR5212_TIMER3, timer3); 2573 2574 AR5K_REG_WRITE(AR5K_AR5212_BEACON, interval & 2575 (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_RESET_TSF | 2576 AR5K_AR5212_BEACON_ENABLE)); 2577 } 2578 2579 void 2580 ar5k_ar5212_set_beacon_timers(struct ath_hal *hal, 2581 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, 2582 u_int32_t cfp_count) 2583 { 2584 u_int32_t cfp_period, next_cfp, dtim, interval, next_beacon; 2585 2586 /* Return on an invalid beacon state */ 2587 if (state->bs_interval < 1) 2588 return; 2589 2590 interval = state->bs_intval; 2591 dtim = state->bs_dtimperiod; 2592 2593 /* 2594 * PCF support? 2595 */ 2596 if (state->bs_cfp_period > 0) { 2597 /* Enable CFP mode and set the CFP and timer registers */ 2598 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 2599 state->bs_interval; 2600 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 2601 state->bs_interval; 2602 2603 AR5K_REG_ENABLE_BITS(AR5K_AR5212_STA_ID1, 2604 AR5K_AR5212_STA_ID1_PCF); 2605 AR5K_REG_WRITE(AR5K_AR5212_CFP_PERIOD, cfp_period); 2606 AR5K_REG_WRITE(AR5K_AR5212_CFP_DUR, state->bs_cfp_max_duration); 2607 AR5K_REG_WRITE(AR5K_AR5212_TIMER2, 2608 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); 2609 } else { 2610 /* Disable PCF mode */ 2611 AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1, 2612 AR5K_AR5212_STA_ID1_PCF); 2613 } 2614 2615 /* 2616 * Enable the beacon timer register 2617 */ 2618 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, state->bs_next_beacon); 2619 2620 /* 2621 * Start the beacon timers 2622 */ 2623 AR5K_REG_WRITE(AR5K_AR5212_BEACON, 2624 (AR5K_REG_READ(AR5K_AR5212_BEACON) &~ 2625 (AR5K_AR5212_BEACON_PERIOD | AR5K_AR5212_BEACON_TIM)) | 2626 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 2627 AR5K_AR5212_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 2628 AR5K_AR5212_BEACON_PERIOD)); 2629 2630 /* 2631 * Write new beacon miss threshold, if it appears to be valid 2632 */ 2633 if ((AR5K_AR5212_RSSI_THR_BMISS >> AR5K_AR5212_RSSI_THR_BMISS_S) < 2634 state->bs_bmiss_threshold) 2635 return; 2636 2637 AR5K_REG_WRITE_BITS(AR5K_AR5212_RSSI_THR_M, 2638 AR5K_AR5212_RSSI_THR_BMISS, state->bs_bmiss_threshold); 2639 2640 /* 2641 * Set sleep registers 2642 */ 2643 if ((state->bs_sleepduration > state->bs_interval) && 2644 (roundup(state->bs_sleepduration, interval) == 2645 state->bs_sleepduration)) 2646 interval = state->bs_sleepduration; 2647 2648 if (state->bs_sleepduration > dtim && 2649 (dtim == 0 || roundup(state->bs_sleepduration, dtim) == 2650 state->bs_sleepduration)) 2651 dtim = state->bs_sleepduration; 2652 2653 if (interval > dtim) 2654 return; 2655 2656 next_beacon = interval == dtim ? 2657 state->bs_nextdtim: state->bs_nexttbtt; 2658 2659 AR5K_REG_WRITE(AR5K_AR5212_SLEEP0, 2660 AR5K_REG_SM((state->bs_nextdtim - 3) << 3, 2661 AR5K_AR5212_SLEEP0_NEXT_DTIM) | 2662 AR5K_REG_SM(10, AR5K_AR5212_SLEEP0_CABTO) | 2663 AR5K_AR5212_SLEEP0_ENH_SLEEP_EN | 2664 AR5K_AR5212_SLEEP0_ASSUME_DTIM); 2665 AR5K_REG_WRITE(AR5K_AR5212_SLEEP1, 2666 AR5K_REG_SM((next_beacon - 3) << 3, 2667 AR5K_AR5212_SLEEP1_NEXT_TIM) | 2668 AR5K_REG_SM(10, AR5K_AR5212_SLEEP1_BEACON_TO)); 2669 AR5K_REG_WRITE(AR5K_AR5212_SLEEP2, 2670 AR5K_REG_SM(interval, AR5K_AR5212_SLEEP2_TIM_PER) | 2671 AR5K_REG_SM(dtim, AR5K_AR5212_SLEEP2_DTIM_PER)); 2672 } 2673 2674 void 2675 ar5k_ar5212_reset_beacon(struct ath_hal *hal) 2676 { 2677 /* 2678 * Disable beacon timer 2679 */ 2680 AR5K_REG_WRITE(AR5K_AR5212_TIMER0, 0); 2681 2682 /* 2683 * Disable some beacon register values 2684 */ 2685 AR5K_REG_DISABLE_BITS(AR5K_AR5212_STA_ID1, 2686 AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5212_STA_ID1_PCF); 2687 AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_AR5212_BEACON_PERIOD); 2688 } 2689 2690 HAL_BOOL 2691 ar5k_ar5212_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr) 2692 { 2693 HAL_BOOL ret; 2694 2695 /* 2696 * Wait for beaconn queue to be done 2697 */ 2698 ret = ar5k_register_timeout(hal, 2699 AR5K_AR5212_QCU_STS(HAL_TX_QUEUE_ID_BEACON), 2700 AR5K_AR5212_QCU_STS_FRMPENDCNT, 0, AH_FALSE); 2701 2702 if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) 2703 return (AH_FALSE); 2704 2705 return (ret); 2706 } 2707 2708 /* 2709 * Interrupt handling 2710 */ 2711 2712 HAL_BOOL 2713 ar5k_ar5212_is_intr_pending(struct ath_hal *hal) 2714 { 2715 return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? AH_FALSE : AH_TRUE); 2716 } 2717 2718 HAL_BOOL 2719 ar5k_ar5212_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) 2720 { 2721 u_int32_t data; 2722 2723 /* 2724 * Read interrupt status from the Read-And-Clear shadow register 2725 */ 2726 data = AR5K_REG_READ(AR5K_AR5212_RAC_PISR); 2727 2728 /* 2729 * Get abstract interrupt mask (HAL-compatible) 2730 */ 2731 *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; 2732 2733 if (data == HAL_INT_NOCARD) 2734 return (AH_FALSE); 2735 2736 if (data & (AR5K_AR5212_PISR_RXOK | AR5K_AR5212_PISR_RXERR)) 2737 *interrupt_mask |= HAL_INT_RX; 2738 2739 if (data & (AR5K_AR5212_PISR_TXOK | AR5K_AR5212_PISR_TXERR)) 2740 *interrupt_mask |= HAL_INT_TX; 2741 2742 if (data & (AR5K_AR5212_PISR_HIUERR)) 2743 *interrupt_mask |= HAL_INT_FATAL; 2744 2745 /* 2746 * Special interrupt handling (not caught by the driver) 2747 */ 2748 if (((*interrupt_mask) & AR5K_AR5212_PISR_RXPHY) && 2749 hal->ah_radar.r_enabled == AH_TRUE) 2750 ar5k_radar_alert(hal); 2751 2752 if (*interrupt_mask == 0) 2753 AR5K_PRINTF("0x%08x\n", data); 2754 2755 return (AH_TRUE); 2756 } 2757 2758 u_int32_t 2759 ar5k_ar5212_get_intr(struct ath_hal *hal) 2760 { 2761 /* Return the interrupt mask stored previously */ 2762 return (hal->ah_imr); 2763 } 2764 2765 HAL_INT 2766 ar5k_ar5212_set_intr(struct ath_hal *hal, HAL_INT new_mask) 2767 { 2768 HAL_INT old_mask, int_mask; 2769 2770 /* 2771 * Disable card interrupts to prevent any race conditions 2772 * (they will be re-enabled afterwards). 2773 */ 2774 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); 2775 2776 old_mask = hal->ah_imr; 2777 2778 /* 2779 * Add additional, chipset-dependent interrupt mask flags 2780 * and write them to the IMR (interrupt mask register). 2781 */ 2782 int_mask = new_mask & HAL_INT_COMMON; 2783 2784 if (new_mask & HAL_INT_RX) 2785 int_mask |= 2786 AR5K_AR5212_PIMR_RXOK | 2787 AR5K_AR5212_PIMR_RXERR | 2788 AR5K_AR5212_PIMR_RXORN | 2789 AR5K_AR5212_PIMR_RXDESC; 2790 2791 if (new_mask & HAL_INT_TX) 2792 int_mask |= 2793 AR5K_AR5212_PIMR_TXOK | 2794 AR5K_AR5212_PIMR_TXERR | 2795 AR5K_AR5212_PIMR_TXDESC | 2796 AR5K_AR5212_PIMR_TXURN; 2797 2798 if (new_mask & HAL_INT_FATAL) { 2799 int_mask |= AR5K_AR5212_PIMR_HIUERR; 2800 AR5K_REG_ENABLE_BITS(AR5K_AR5212_SIMR2, 2801 AR5K_AR5212_SIMR2_MCABT | 2802 AR5K_AR5212_SIMR2_SSERR | 2803 AR5K_AR5212_SIMR2_DPERR); 2804 } 2805 2806 AR5K_REG_WRITE(AR5K_AR5212_PIMR, int_mask); 2807 2808 /* Store new interrupt mask */ 2809 hal->ah_imr = new_mask; 2810 2811 /* ..re-enable interrupts */ 2812 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); 2813 2814 return (old_mask); 2815 } 2816 2817 /* 2818 * Misc internal functions 2819 */ 2820 2821 HAL_BOOL 2822 ar5k_ar5212_get_capabilities(struct ath_hal *hal) 2823 { 2824 u_int16_t ee_header; 2825 u_int a, b, g; 2826 2827 /* Capabilities stored in the EEPROM */ 2828 ee_header = hal->ah_capabilities.cap_eeprom.ee_header; 2829 2830 a = AR5K_EEPROM_HDR_11A(ee_header); 2831 b = AR5K_EEPROM_HDR_11B(ee_header); 2832 g = AR5K_EEPROM_HDR_11G(ee_header); 2833 2834 /* 2835 * If the EEPROM is not reporting any mode, we try 11b. 2836 * This might fix a few broken devices with invalid EEPROM. 2837 */ 2838 if (!a && !b && !g) 2839 b = 1; 2840 2841 /* 2842 * XXX The AR5212 tranceiver supports frequencies from 4920 to 6100GHz 2843 * XXX and from 2312 to 2732GHz. There are problems with the current 2844 * XXX ieee80211 implementation because the IEEE channel mapping 2845 * XXX does not support negative channel numbers (2312MHz is channel 2846 * XXX -19). Of course, this doesn't matter because these channels 2847 * XXX are out of range but some regulation domains like MKK (Japan) 2848 * XXX will support frequencies somewhere around 4.8GHz. 2849 */ 2850 2851 /* 2852 * Set radio capabilities 2853 */ 2854 2855 if (a) { 2856 hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ 2857 hal->ah_capabilities.cap_range.range_5ghz_max = 6100; 2858 2859 /* Set supported modes */ 2860 hal->ah_capabilities.cap_mode = 2861 HAL_MODE_11A | HAL_MODE_TURBO | HAL_MODE_XR; 2862 } 2863 2864 /* This chip will support 802.11b if the 2GHz radio is connected */ 2865 if (b || g) { 2866 hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ 2867 hal->ah_capabilities.cap_range.range_2ghz_max = 2732; 2868 2869 if (b) 2870 hal->ah_capabilities.cap_mode |= HAL_MODE_11B; 2871 #if 0 2872 if (g) 2873 hal->ah_capabilities.cap_mode |= HAL_MODE_11G; 2874 #endif 2875 } 2876 2877 /* GPIO */ 2878 hal->ah_gpio_npins = AR5K_AR5212_NUM_GPIO; 2879 2880 /* Set number of supported TX queues */ 2881 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5212_TX_NUM_QUEUES; 2882 2883 return (AH_TRUE); 2884 } 2885 2886 void 2887 ar5k_ar5212_radar_alert(struct ath_hal *hal, HAL_BOOL enable) 2888 { 2889 /* 2890 * Enable radar detection 2891 */ 2892 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); 2893 2894 if (enable == AH_TRUE) { 2895 AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, 2896 AR5K_AR5212_PHY_RADAR_ENABLE); 2897 AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, 2898 AR5K_AR5212_PIMR_RXPHY); 2899 } else { 2900 AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, 2901 AR5K_AR5212_PHY_RADAR_DISABLE); 2902 AR5K_REG_DISABLE_BITS(AR5K_AR5212_PIMR, 2903 AR5K_AR5212_PIMR_RXPHY); 2904 } 2905 2906 AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); 2907 } 2908 2909 /* 2910 * EEPROM access functions 2911 */ 2912 2913 HAL_BOOL 2914 ar5k_ar5212_eeprom_is_busy(struct ath_hal *hal) 2915 { 2916 return (AR5K_REG_READ(AR5K_AR5212_CFG) & AR5K_AR5212_CFG_EEBS ? 2917 AH_TRUE : AH_FALSE); 2918 } 2919 2920 int 2921 ar5k_ar5212_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) 2922 { 2923 u_int32_t status, i; 2924 2925 /* 2926 * Initialize EEPROM access 2927 */ 2928 AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset); 2929 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, 2930 AR5K_AR5212_EEPROM_CMD_READ); 2931 2932 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 2933 status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS); 2934 if (status & AR5K_AR5212_EEPROM_STAT_RDDONE) { 2935 if (status & AR5K_AR5212_EEPROM_STAT_RDERR) 2936 return (EIO); 2937 *data = (u_int16_t) 2938 (AR5K_REG_READ(AR5K_AR5212_EEPROM_DATA) & 0xffff); 2939 return (0); 2940 } 2941 AR5K_DELAY(15); 2942 } 2943 2944 return (ETIMEDOUT); 2945 } 2946 2947 int 2948 ar5k_ar5212_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) 2949 { 2950 u_int32_t status, timeout; 2951 2952 /* Enable eeprom access */ 2953 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, 2954 AR5K_AR5212_EEPROM_CMD_RESET); 2955 AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, 2956 AR5K_AR5212_EEPROM_CMD_WRITE); 2957 2958 /* 2959 * Prime write pump 2960 */ 2961 AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset - 1); 2962 2963 for (timeout = 10000; timeout > 0; timeout--) { 2964 AR5K_DELAY(1); 2965 status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS); 2966 if (status & AR5K_AR5212_EEPROM_STAT_WRDONE) { 2967 if (status & AR5K_AR5212_EEPROM_STAT_WRERR) 2968 return (EIO); 2969 return (0); 2970 } 2971 } 2972 2973 return (ETIMEDOUT); 2974 } 2975 2976 /* 2977 * TX power setup 2978 */ 2979 2980 HAL_BOOL 2981 ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower) 2982 { 2983 HAL_BOOL tpc = hal->ah_txpower.txp_tpc; 2984 int i; 2985 2986 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 2987 AR5K_PRINTF("invalid tx power: %u\n", txpower); 2988 return (AH_FALSE); 2989 } 2990 2991 /* Reset TX power values */ 2992 bzero(&hal->ah_txpower, sizeof(hal->ah_txpower)); 2993 hal->ah_txpower.txp_tpc = tpc; 2994 2995 /* Initialize TX power table */ 2996 ar5k_txpower_table(hal, channel, txpower); 2997 2998 /* 2999 * Write TX power values 3000 */ 3001 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 3002 AR5K_REG_WRITE(AR5K_AR5212_PHY_PCDAC_TXPOWER(i), 3003 ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 3004 0xffff) << 16) | (((hal->ah_txpower.txp_pcdac[i << 1] << 8) 3005 | 0xff) & 0xffff)); 3006 } 3007 3008 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE1, 3009 AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16) 3010 | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0)); 3011 3012 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE2, 3013 AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16) 3014 | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0)); 3015 3016 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE3, 3017 AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16) 3018 | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0)); 3019 3020 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE4, 3021 AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16) 3022 | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0)); 3023 3024 if (hal->ah_txpower.txp_tpc == AH_TRUE) { 3025 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, 3026 AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3027 AR5K_TUNE_MAX_TXPOWER); 3028 } else { 3029 AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, 3030 AR5K_AR5212_PHY_TXPOWER_RATE_MAX | 3031 AR5K_TUNE_MAX_TXPOWER); 3032 } 3033 3034 return (AH_TRUE); 3035 } 3036 3037 HAL_BOOL 3038 ar5k_ar5212_set_txpower_limit(struct ath_hal *hal, u_int power) 3039 { 3040 HAL_CHANNEL *channel = &hal->ah_current_channel; 3041 3042 AR5K_PRINTF("changing txpower to %d\n", power); 3043 return (ar5k_ar5212_txpower(hal, channel, power)); 3044 } 3045