1 /* $OpenBSD: ar5416.c,v 1.19 2016/01/05 18:41:15 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 * Routines for AR5416, AR5418 and AR9160 chipsets. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/endian.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 #include <net/if.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/ic/athnreg.h> 57 #include <dev/ic/athnvar.h> 58 59 #include <dev/ic/ar5008reg.h> 60 #include <dev/ic/ar5416reg.h> 61 62 int ar5416_attach(struct athn_softc *); 63 void ar5416_setup(struct athn_softc *); 64 void ar5416_swap_rom(struct athn_softc *); 65 const struct ar_spur_chan * 66 ar5416_get_spur_chans(struct athn_softc *, int); 67 int ar5416_set_synth(struct athn_softc *, struct ieee80211_channel *, 68 struct ieee80211_channel *); 69 uint8_t ar5416_reverse_bits(uint8_t, int); 70 uint8_t ar5416_get_rf_rev(struct athn_softc *); 71 void ar5416_init_from_rom(struct athn_softc *, struct ieee80211_channel *, 72 struct ieee80211_channel *); 73 int ar5416_init_calib(struct athn_softc *, struct ieee80211_channel *, 74 struct ieee80211_channel *); 75 void ar5416_set_power_calib(struct athn_softc *, 76 struct ieee80211_channel *); 77 void ar5416_set_txpower(struct athn_softc *, struct ieee80211_channel *, 78 struct ieee80211_channel *); 79 void ar5416_spur_mitigate(struct athn_softc *, struct ieee80211_channel *, 80 struct ieee80211_channel *); 81 void ar5416_rw_rfbits(uint32_t *, int, int, uint32_t, int); 82 void ar5416_rw_bank6tpc(struct athn_softc *, struct ieee80211_channel *, 83 uint32_t *); 84 void ar5416_rf_reset(struct athn_softc *, struct ieee80211_channel *); 85 void ar5416_reset_bb_gain(struct athn_softc *, struct ieee80211_channel *); 86 void ar5416_force_bias(struct athn_softc *, struct ieee80211_channel *); 87 void ar9160_rw_addac(struct athn_softc *, struct ieee80211_channel *, 88 uint32_t *); 89 void ar5416_reset_addac(struct athn_softc *, struct ieee80211_channel *); 90 void ar5416_get_pdadcs(struct athn_softc *, struct ieee80211_channel *, 91 int, int, uint8_t, uint8_t *, uint8_t *); 92 93 /* Extern functions. */ 94 uint8_t athn_chan2fbin(struct ieee80211_channel *); 95 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *); 96 int ar5008_attach(struct athn_softc *); 97 void ar5008_write_txpower(struct athn_softc *, int16_t power[]); 98 void ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *, 99 struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *); 100 void ar5008_set_viterbi_mask(struct athn_softc *, int); 101 void ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *, 102 uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]); 103 void ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *, 104 uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]); 105 void ar9280_olpc_get_pdadcs(struct athn_softc *, struct ieee80211_channel *, 106 int, uint8_t *, uint8_t *, uint8_t *); 107 108 109 int 110 ar5416_attach(struct athn_softc *sc) 111 { 112 sc->eep_base = AR5416_EEP_START_LOC; 113 sc->eep_size = sizeof(struct ar5416_eeprom); 114 sc->def_nf = AR5416_PHY_CCA_MAX_GOOD_VALUE; 115 sc->ngpiopins = 14; 116 sc->led_pin = 1; 117 sc->workaround = AR5416_WA_DEFAULT; 118 sc->ops.setup = ar5416_setup; 119 sc->ops.swap_rom = ar5416_swap_rom; 120 sc->ops.init_from_rom = ar5416_init_from_rom; 121 sc->ops.set_txpower = ar5416_set_txpower; 122 sc->ops.set_synth = ar5416_set_synth; 123 sc->ops.spur_mitigate = ar5416_spur_mitigate; 124 sc->ops.get_spur_chans = ar5416_get_spur_chans; 125 if (AR_SREV_9160_10_OR_LATER(sc)) 126 sc->ini = &ar9160_ini; 127 else 128 sc->ini = &ar5416_ini; 129 sc->serdes = &ar5416_serdes; 130 131 return (ar5008_attach(sc)); 132 } 133 134 void 135 ar5416_setup(struct athn_softc *sc) 136 { 137 /* Select ADDAC programming. */ 138 if (AR_SREV_9160_11(sc)) 139 sc->addac = &ar9160_1_1_addac; 140 else if (AR_SREV_9160_10_OR_LATER(sc)) 141 sc->addac = &ar9160_1_0_addac; 142 else if (AR_SREV_5416_22_OR_LATER(sc)) 143 sc->addac = &ar5416_2_2_addac; 144 else 145 sc->addac = &ar5416_2_1_addac; 146 } 147 148 void 149 ar5416_swap_rom(struct athn_softc *sc) 150 { 151 struct ar5416_eeprom *eep = sc->eep; 152 struct ar5416_modal_eep_header *modal; 153 int i, j; 154 155 for (i = 0; i < 2; i++) { /* Dual-band. */ 156 modal = &eep->modalHeader[i]; 157 158 modal->antCtrlCommon = swap32(modal->antCtrlCommon); 159 for (j = 0; j < AR5416_MAX_CHAINS; j++) { 160 modal->antCtrlChain[j] = 161 swap32(modal->antCtrlChain[j]); 162 } 163 for (j = 0; j < AR_EEPROM_MODAL_SPURS; j++) { 164 modal->spurChans[j].spurChan = 165 swap16(modal->spurChans[j].spurChan); 166 } 167 } 168 } 169 170 const struct ar_spur_chan * 171 ar5416_get_spur_chans(struct athn_softc *sc, int is2ghz) 172 { 173 const struct ar5416_eeprom *eep = sc->eep; 174 175 return (eep->modalHeader[is2ghz].spurChans); 176 } 177 178 int 179 ar5416_set_synth(struct athn_softc *sc, struct ieee80211_channel *c, 180 struct ieee80211_channel *extc) 181 { 182 uint32_t phy, reg; 183 uint32_t freq = c->ic_freq; 184 uint8_t chansel; 185 186 phy = 0; 187 if (IEEE80211_IS_CHAN_2GHZ(c)) { 188 if (((freq - 2192) % 5) == 0) { 189 chansel = ((freq - 672) * 2 - 3040) / 10; 190 } else if (((freq - 2224) % 5) == 0) { 191 chansel = ((freq - 704) * 2 - 3040) / 10; 192 phy |= AR5416_BMODE_SYNTH; 193 } else 194 return (EINVAL); 195 chansel <<= 2; 196 197 reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL); 198 if (freq == 2484) /* Channel 14. */ 199 reg |= AR_PHY_CCK_TX_CTRL_JAPAN; 200 else 201 reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN; 202 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg); 203 204 /* Fix for orientation sensitivity issue. */ 205 if (AR_SREV_5416(sc)) 206 ar5416_force_bias(sc, c); 207 } else { 208 if (freq >= 5120 && (freq % 20) == 0) { 209 chansel = (freq - 4800) / 20; 210 chansel <<= 2; 211 phy |= SM(AR5416_AMODE_REFSEL, 2); 212 } else if ((freq % 10) == 0) { 213 chansel = (freq - 4800) / 10; 214 chansel <<= 1; 215 if (AR_SREV_9160_10_OR_LATER(sc)) 216 phy |= SM(AR5416_AMODE_REFSEL, 1); 217 else 218 phy |= SM(AR5416_AMODE_REFSEL, 2); 219 } else if ((freq % 5) == 0) { 220 chansel = (freq - 4800) / 5; 221 phy |= SM(AR5416_AMODE_REFSEL, 2); 222 } else 223 return (EINVAL); 224 } 225 chansel = ar5416_reverse_bits(chansel, 8); 226 phy |= chansel << 8 | 1 << 5 | 1; 227 DPRINTFN(4, ("AR_PHY(0x37)=0x%08x\n", phy)); 228 AR_WRITE(sc, AR_PHY(0x37), phy); 229 return (0); 230 } 231 232 void 233 ar5416_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 234 struct ieee80211_channel *extc) 235 { 236 static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 }; 237 const struct ar5416_eeprom *eep = sc->eep; 238 const struct ar5416_modal_eep_header *modal; 239 uint32_t reg, offset; 240 uint8_t txRxAtten; 241 int i; 242 243 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)]; 244 245 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 246 247 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 248 if (AR_SREV_5416_20_OR_LATER(sc) && 249 (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5)) 250 offset = chainoffset[i]; 251 else 252 offset = i * 0x1000; 253 254 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, 255 modal->antCtrlChain[i]); 256 257 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); 258 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 259 modal->iqCalICh[i]); 260 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 261 modal->iqCalQCh[i]); 262 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); 263 264 if (i > 0 && !AR_SREV_5416_20_OR_LATER(sc)) 265 continue; 266 267 if (sc->eep_rev >= AR_EEP_MINOR_VER_3) { 268 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 269 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN, 270 modal->bswMargin[i]); 271 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN, 272 modal->bswAtten[i]); 273 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 274 } 275 if (sc->eep_rev >= AR_EEP_MINOR_VER_3) 276 txRxAtten = modal->txRxAttenCh[i]; 277 else /* Workaround for ROM versions < 14.3. */ 278 txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44; 279 reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 280 reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); 281 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 282 283 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 284 reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN, 285 modal->rxTxMarginCh[i]); 286 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 287 } 288 reg = AR_READ(sc, AR_PHY_SETTLING); 289 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 290 AR_WRITE(sc, AR_PHY_SETTLING, reg); 291 292 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 293 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 294 reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize); 295 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 296 297 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 298 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 299 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 300 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 301 AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 302 303 reg = AR_READ(sc, AR_PHY_RF_CTL3); 304 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 305 AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 306 307 reg = AR_READ(sc, AR_PHY_CCA(0)); 308 reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62); 309 AR_WRITE(sc, AR_PHY_CCA(0), reg); 310 311 reg = AR_READ(sc, AR_PHY_EXT_CCA(0)); 312 reg = RW(reg, AR_PHY_EXT_CCA_THRESH62, modal->thresh62); 313 AR_WRITE(sc, AR_PHY_EXT_CCA(0), reg); 314 315 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) { 316 reg = AR_READ(sc, AR_PHY_RF_CTL2); 317 reg = RW(reg, AR_PHY_TX_END_DATA_START, 318 modal->txFrameToDataStart); 319 reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); 320 AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 321 } 322 if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) { 323 /* Overwrite switch settling with HT-40 value. */ 324 reg = AR_READ(sc, AR_PHY_SETTLING); 325 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 326 AR_WRITE(sc, AR_PHY_SETTLING, reg); 327 } 328 } 329 330 int 331 ar5416_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, 332 struct ieee80211_channel *extc) 333 { 334 int ntries; 335 336 if (AR_SREV_9280_10_OR_LATER(sc)) { 337 /* XXX Linux tests AR9287?! */ 338 AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); 339 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, 340 AR_PHY_AGC_CONTROL_FLTR_CAL); 341 } 342 /* Calibrate the AGC. */ 343 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 344 /* Poll for offset calibration completion. */ 345 for (ntries = 0; ntries < 10000; ntries++) { 346 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & 347 AR_PHY_AGC_CONTROL_CAL)) 348 break; 349 DELAY(10); 350 } 351 if (ntries == 10000) 352 return (ETIMEDOUT); 353 if (AR_SREV_9280_10_OR_LATER(sc)) { 354 AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); 355 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, 356 AR_PHY_AGC_CONTROL_FLTR_CAL); 357 } 358 return (0); 359 } 360 361 void 362 ar5416_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 363 int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries, 364 uint8_t *pdadcs) 365 { 366 const struct ar5416_eeprom *eep = sc->eep; 367 const struct ar5416_cal_data_per_freq *pierdata; 368 const uint8_t *pierfreq; 369 struct athn_pier lopier, hipier; 370 int16_t delta; 371 uint8_t fbin, pwroff; 372 int i, lo, hi, npiers; 373 374 if (IEEE80211_IS_CHAN_2GHZ(c)) { 375 pierfreq = eep->calFreqPier2G; 376 pierdata = eep->calPierData2G[chain]; 377 npiers = AR5416_NUM_2G_CAL_PIERS; 378 } else { 379 pierfreq = eep->calFreqPier5G; 380 pierdata = eep->calPierData5G[chain]; 381 npiers = AR5416_NUM_5G_CAL_PIERS; 382 } 383 /* Find channel in ROM pier table. */ 384 fbin = athn_chan2fbin(c); 385 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 386 387 lopier.fbin = pierfreq[lo]; 388 hipier.fbin = pierfreq[hi]; 389 for (i = 0; i < nxpdgains; i++) { 390 lopier.pwr[i] = pierdata[lo].pwrPdg[i]; 391 lopier.vpd[i] = pierdata[lo].vpdPdg[i]; 392 hipier.pwr[i] = pierdata[lo].pwrPdg[i]; 393 hipier.vpd[i] = pierdata[lo].vpdPdg[i]; 394 } 395 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains, 396 AR5416_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs); 397 398 if (!AR_SREV_9280_20_OR_LATER(sc)) 399 return; 400 401 if (sc->eep_rev >= AR_EEP_MINOR_VER_21) 402 pwroff = eep->baseEepHeader.pwrTableOffset; 403 else 404 pwroff = AR_PWR_TABLE_OFFSET_DB; 405 delta = (pwroff - AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */ 406 407 /* Change the original gain boundaries setting. */ 408 for (i = 0; i < nxpdgains; i++) { 409 /* XXX Possible overflows? */ 410 boundaries[i] -= delta; 411 if (boundaries[i] > AR_MAX_RATE_POWER - overlap) 412 boundaries[i] = AR_MAX_RATE_POWER - overlap; 413 } 414 if (delta != 0) { 415 /* Shift the PDADC table to start at the new offset. */ 416 for (i = 0; i < AR_NUM_PDADC_VALUES; i++) 417 pdadcs[i] = pdadcs[MIN(i + delta, 418 AR_NUM_PDADC_VALUES - 1)]; 419 } 420 } 421 422 void 423 ar5416_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c) 424 { 425 static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 }; 426 const struct ar5416_eeprom *eep = sc->eep; 427 const struct ar5416_modal_eep_header *modal; 428 uint8_t boundaries[AR_PD_GAINS_IN_MASK]; 429 uint8_t pdadcs[AR_NUM_PDADC_VALUES]; 430 uint8_t xpdgains[AR5416_NUM_PD_GAINS]; 431 uint8_t overlap, txgain; 432 uint32_t reg, offset; 433 int i, j, nxpdgains; 434 435 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)]; 436 437 if (sc->eep_rev < AR_EEP_MINOR_VER_2) { 438 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5), 439 AR_PHY_TPCRG5_PD_GAIN_OVERLAP); 440 } else 441 overlap = modal->pdGainOverlap; 442 443 if ((sc->flags & ATHN_FLAG_OLPC) && IEEE80211_IS_CHAN_2GHZ(c)) { 444 /* XXX not here. */ 445 sc->pdadc = 446 ((const struct ar_cal_data_per_freq_olpc *) 447 eep->calPierData2G[0])->vpdPdg[0][0]; 448 } 449 450 nxpdgains = 0; 451 memset(xpdgains, 0, sizeof(xpdgains)); 452 for (i = AR5416_PD_GAINS_IN_MASK - 1; i >= 0; i--) { 453 if (nxpdgains >= AR5416_NUM_PD_GAINS) 454 break; /* Can't happen. */ 455 if (modal->xpdGain & (1 << i)) 456 xpdgains[nxpdgains++] = i; 457 } 458 reg = AR_READ(sc, AR_PHY_TPCRG1); 459 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1); 460 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); 461 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]); 462 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_3, xpdgains[2]); 463 AR_WRITE(sc, AR_PHY_TPCRG1, reg); 464 465 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 466 if (!(sc->txchainmask & (1 << i))) 467 continue; 468 469 if (AR_SREV_5416_20_OR_LATER(sc) && 470 (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5)) 471 offset = chainoffset[i]; 472 else 473 offset = i * 0x1000; 474 475 if (sc->flags & ATHN_FLAG_OLPC) { 476 ar9280_olpc_get_pdadcs(sc, c, i, boundaries, 477 pdadcs, &txgain); 478 479 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0); 480 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 481 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg); 482 483 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1); 484 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 485 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg); 486 487 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7); 488 reg = RW(reg, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, txgain); 489 AR_WRITE(sc, AR_PHY_TX_PWRCTRL7, reg); 490 491 overlap = 6; 492 } else { 493 ar5416_get_pdadcs(sc, c, i, nxpdgains, overlap, 494 boundaries, pdadcs); 495 } 496 /* Write boundaries. */ 497 if (i == 0 || AR_SREV_5416_20_OR_LATER(sc)) { 498 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, 499 overlap); 500 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, 501 boundaries[0]); 502 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, 503 boundaries[1]); 504 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, 505 boundaries[2]); 506 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, 507 boundaries[3]); 508 AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg); 509 } 510 /* Write PDADC values. */ 511 for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) { 512 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j, 513 pdadcs[j + 0] << 0 | 514 pdadcs[j + 1] << 8 | 515 pdadcs[j + 2] << 16 | 516 pdadcs[j + 3] << 24); 517 } 518 } 519 } 520 521 void 522 ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 523 struct ieee80211_channel *extc) 524 { 525 const struct ar5416_eeprom *eep = sc->eep; 526 const struct ar5416_modal_eep_header *modal; 527 uint8_t tpow_cck[4], tpow_ofdm[4]; 528 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4]; 529 uint8_t tpow_ht20[8], tpow_ht40[8]; 530 uint8_t ht40inc; 531 int16_t pwr = 0, pwroff, max_ant_gain, power[ATHN_POWER_COUNT]; 532 uint8_t cckinc; 533 int i; 534 535 ar5416_set_power_calib(sc, c); 536 537 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)]; 538 539 /* Compute transmit power reduction due to antenna gain. */ 540 max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]); 541 max_ant_gain = MAX(modal->antennaGainCh[2], max_ant_gain); 542 /* XXX */ 543 544 /* 545 * Reduce scaled power by number of active chains to get per-chain 546 * transmit power level. 547 */ 548 if (sc->ntxchains == 2) 549 pwr -= AR_PWR_DECREASE_FOR_2_CHAIN; 550 else if (sc->ntxchains == 3) 551 pwr -= AR_PWR_DECREASE_FOR_3_CHAIN; 552 if (pwr < 0) 553 pwr = 0; 554 555 if (IEEE80211_IS_CHAN_2GHZ(c)) { 556 /* Get CCK target powers. */ 557 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck, 558 AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 559 560 /* Get OFDM target powers. */ 561 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G, 562 AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 563 564 /* Get HT-20 target powers. */ 565 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, 566 eep->calTargetPower2GHT20, AR5416_NUM_2G_20_TARGET_POWERS, 567 tpow_ht20); 568 569 if (extc != NULL) { 570 /* Get HT-40 target powers. */ 571 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40, 572 eep->calTargetPower2GHT40, 573 AR5416_NUM_2G_40_TARGET_POWERS, tpow_ht40); 574 575 /* Get secondary channel CCK target powers. */ 576 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B, 577 eep->calTargetPowerCck, 578 AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck_ext); 579 580 /* Get secondary channel OFDM target powers. */ 581 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G, 582 eep->calTargetPower2G, 583 AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm_ext); 584 } 585 } else { 586 /* Get OFDM target powers. */ 587 ar5008_get_lg_tpow(sc, c, AR_CTL_11A, eep->calTargetPower5G, 588 AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm); 589 590 /* Get HT-20 target powers. */ 591 ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT20, 592 eep->calTargetPower5GHT20, AR5416_NUM_5G_20_TARGET_POWERS, 593 tpow_ht20); 594 595 if (extc != NULL) { 596 /* Get HT-40 target powers. */ 597 ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT40, 598 eep->calTargetPower5GHT40, 599 AR5416_NUM_5G_40_TARGET_POWERS, tpow_ht40); 600 601 /* Get secondary channel OFDM target powers. */ 602 ar5008_get_lg_tpow(sc, extc, AR_CTL_11A, 603 eep->calTargetPower5G, 604 AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm_ext); 605 } 606 } 607 608 /* Compute CCK/OFDM delta. */ 609 cckinc = (sc->flags & ATHN_FLAG_OLPC) ? -2 : 0; 610 611 memset(power, 0, sizeof(power)); 612 /* Shuffle target powers accross transmit rates. */ 613 power[ATHN_POWER_OFDM6 ] = 614 power[ATHN_POWER_OFDM9 ] = 615 power[ATHN_POWER_OFDM12] = 616 power[ATHN_POWER_OFDM18] = 617 power[ATHN_POWER_OFDM24] = tpow_ofdm[0]; 618 power[ATHN_POWER_OFDM36] = tpow_ofdm[1]; 619 power[ATHN_POWER_OFDM48] = tpow_ofdm[2]; 620 power[ATHN_POWER_OFDM54] = tpow_ofdm[3]; 621 power[ATHN_POWER_XR ] = tpow_ofdm[0]; 622 if (IEEE80211_IS_CHAN_2GHZ(c)) { 623 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0] + cckinc; 624 power[ATHN_POWER_CCK2_LP ] = 625 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1] + cckinc; 626 power[ATHN_POWER_CCK55_LP] = 627 power[ATHN_POWER_CCK55_SP] = tpow_cck[2] + cckinc; 628 power[ATHN_POWER_CCK11_LP] = 629 power[ATHN_POWER_CCK11_SP] = tpow_cck[3] + cckinc; 630 } 631 for (i = 0; i < nitems(tpow_ht20); i++) 632 power[ATHN_POWER_HT20(i)] = tpow_ht20[i]; 633 if (extc != NULL) { 634 /* Correct PAR difference between HT40 and HT20/Legacy. */ 635 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) 636 ht40inc = modal->ht40PowerIncForPdadc; 637 else 638 ht40inc = AR_HT40_POWER_INC_FOR_PDADC; 639 for (i = 0; i < nitems(tpow_ht40); i++) 640 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc; 641 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0]; 642 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0] + cckinc; 643 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0]; 644 if (IEEE80211_IS_CHAN_2GHZ(c)) 645 power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0] + cckinc; 646 } 647 648 if (AR_SREV_9280_10_OR_LATER(sc)) { 649 if (sc->eep_rev >= AR_EEP_MINOR_VER_21) 650 pwroff = eep->baseEepHeader.pwrTableOffset; 651 else 652 pwroff = AR_PWR_TABLE_OFFSET_DB; 653 for (i = 0; i < ATHN_POWER_COUNT; i++) 654 power[i] -= pwroff * 2; /* In half dB. */ 655 } 656 for (i = 0; i < ATHN_POWER_COUNT; i++) { 657 if (power[i] > AR_MAX_RATE_POWER) 658 power[i] = AR_MAX_RATE_POWER; 659 } 660 661 /* Write transmit power values to hardware. */ 662 ar5008_write_txpower(sc, power); 663 664 /* 665 * Write transmit power substraction for dynamic chain changing 666 * and per-packet transmit power. 667 */ 668 AR_WRITE(sc, AR_PHY_POWER_TX_SUB, 669 (modal->pwrDecreaseFor3Chain & 0x3f) << 6 | 670 (modal->pwrDecreaseFor2Chain & 0x3f)); 671 } 672 673 void 674 ar5416_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c, 675 struct ieee80211_channel *extc) 676 { 677 const struct ar_spur_chan *spurchans; 678 int i, spur, bin, spur_delta_phase, spur_freq_sd; 679 680 spurchans = sc->ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c)); 681 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 682 spur = spurchans[i].spurChan; 683 if (spur == AR_NO_SPUR) 684 return; /* XXX disable if it was enabled! */ 685 spur -= c->ic_freq * 10; 686 /* Verify range +/-9.5MHz */ 687 if (abs(spur) < 95) 688 break; 689 } 690 if (i == AR_EEPROM_MODAL_SPURS) 691 return; /* XXX disable if it was enabled! */ 692 DPRINTFN(2, ("enabling spur mitigation\n")); 693 694 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, 695 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 696 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 697 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 698 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 699 700 AR_WRITE(sc, AR_PHY_SPUR_REG, 701 AR_PHY_SPUR_REG_MASK_RATE_CNTL | 702 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 703 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 704 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 705 SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH)); 706 707 spur_delta_phase = (spur * 524288) / 100; 708 if (IEEE80211_IS_CHAN_2GHZ(c)) 709 spur_freq_sd = (spur * 2048) / 440; 710 else 711 spur_freq_sd = (spur * 2048) / 400; 712 713 AR_WRITE(sc, AR_PHY_TIMING11, 714 AR_PHY_TIMING11_USE_SPUR_IN_AGC | 715 SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) | 716 SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase)); 717 718 bin = spur * 32; 719 ar5008_set_viterbi_mask(sc, bin); 720 } 721 722 uint8_t 723 ar5416_reverse_bits(uint8_t v, int nbits) 724 { 725 KASSERT(nbits <= 8); 726 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 727 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 728 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 729 return (v >> (8 - nbits)); 730 } 731 732 uint8_t 733 ar5416_get_rf_rev(struct athn_softc *sc) 734 { 735 uint8_t rev, reg; 736 int i; 737 738 /* Allow access to analog chips. */ 739 AR_WRITE(sc, AR_PHY(0), 0x00000007); 740 741 AR_WRITE(sc, AR_PHY(0x36), 0x00007058); 742 for (i = 0; i < 8; i++) 743 AR_WRITE(sc, AR_PHY(0x20), 0x00010000); 744 reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff; 745 reg = (reg & 0xf0) >> 4 | (reg & 0x0f) << 4; 746 747 rev = ar5416_reverse_bits(reg, 8); 748 if ((rev & AR_RADIO_SREV_MAJOR) == 0) 749 rev = AR_RAD5133_SREV_MAJOR; 750 return (rev); 751 } 752 753 /* 754 * Replace bits "off" to "off+nbits-1" in column "col" with the specified 755 * value. 756 */ 757 void 758 ar5416_rw_rfbits(uint32_t *buf, int col, int off, uint32_t val, int nbits) 759 { 760 int idx, bit; 761 762 KASSERT(off >= 1 && col < 4 && nbits <= 32); 763 764 off--; /* Starts at 1. */ 765 while (nbits-- > 0) { 766 idx = off / 8; 767 bit = off % 8; 768 buf[idx] &= ~(1 << (bit + col * 8)); 769 buf[idx] |= ((val >> nbits) & 1) << (bit + col * 8); 770 off++; 771 } 772 } 773 774 /* 775 * Overwrite db and ob based on ROM settings. 776 */ 777 void 778 ar5416_rw_bank6tpc(struct athn_softc *sc, struct ieee80211_channel *c, 779 uint32_t *rwbank6tpc) 780 { 781 const struct ar5416_eeprom *eep = sc->eep; 782 const struct ar5416_modal_eep_header *modal; 783 784 if (IEEE80211_IS_CHAN_5GHZ(c)) { 785 modal = &eep->modalHeader[0]; 786 /* 5GHz db in column 0, bits [200-202]. */ 787 ar5416_rw_rfbits(rwbank6tpc, 0, 200, modal->db, 3); 788 /* 5GHz ob in column 0, bits [203-205]. */ 789 ar5416_rw_rfbits(rwbank6tpc, 0, 203, modal->ob, 3); 790 } else { 791 modal = &eep->modalHeader[1]; 792 /* 2GHz db in column 0, bits [194-196]. */ 793 ar5416_rw_rfbits(rwbank6tpc, 0, 194, modal->db, 3); 794 /* 2GHz ob in column 0, bits [197-199]. */ 795 ar5416_rw_rfbits(rwbank6tpc, 0, 197, modal->ob, 3); 796 } 797 } 798 799 /* 800 * Program analog RF. 801 */ 802 void 803 ar5416_rf_reset(struct athn_softc *sc, struct ieee80211_channel *c) 804 { 805 const uint32_t *bank6tpc; 806 int i; 807 808 /* Bank 0. */ 809 AR_WRITE(sc, 0x98b0, 0x1e5795e5); 810 AR_WRITE(sc, 0x98e0, 0x02008020); 811 812 /* Bank 1. */ 813 AR_WRITE(sc, 0x98b0, 0x02108421); 814 AR_WRITE(sc, 0x98ec, 0x00000008); 815 816 /* Bank 2. */ 817 AR_WRITE(sc, 0x98b0, 0x0e73ff17); 818 AR_WRITE(sc, 0x98e0, 0x00000420); 819 820 /* Bank 3. */ 821 if (IEEE80211_IS_CHAN_5GHZ(c)) 822 AR_WRITE(sc, 0x98f0, 0x01400018); 823 else 824 AR_WRITE(sc, 0x98f0, 0x01c00018); 825 826 /* Select the Bank 6 TPC values to use. */ 827 if (AR_SREV_9160_10_OR_LATER(sc)) 828 bank6tpc = ar9160_bank6tpc_vals; 829 else 830 bank6tpc = ar5416_bank6tpc_vals; 831 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) { 832 uint32_t *rwbank6tpc = sc->rwbuf; 833 834 /* Copy values from .rodata to writable buffer. */ 835 memcpy(rwbank6tpc, bank6tpc, 32 * sizeof(uint32_t)); 836 ar5416_rw_bank6tpc(sc, c, rwbank6tpc); 837 bank6tpc = rwbank6tpc; 838 } 839 /* Bank 6 TPC. */ 840 for (i = 0; i < 32; i++) 841 AR_WRITE(sc, 0x989c, bank6tpc[i]); 842 if (IEEE80211_IS_CHAN_5GHZ(c)) 843 AR_WRITE(sc, 0x98d0, 0x0000000f); 844 else 845 AR_WRITE(sc, 0x98d0, 0x0010000f); 846 847 /* Bank 7. */ 848 AR_WRITE(sc, 0x989c, 0x00000500); 849 AR_WRITE(sc, 0x989c, 0x00000800); 850 AR_WRITE(sc, 0x98cc, 0x0000000e); 851 } 852 853 void 854 ar5416_reset_bb_gain(struct athn_softc *sc, struct ieee80211_channel *c) 855 { 856 const uint32_t *pvals; 857 int i; 858 859 if (IEEE80211_IS_CHAN_2GHZ(c)) 860 pvals = ar5416_bb_rfgain_vals_2g; 861 else 862 pvals = ar5416_bb_rfgain_vals_5g; 863 for (i = 0; i < 64; i++) 864 AR_WRITE(sc, AR_PHY_BB_RFGAIN(i), pvals[i]); 865 } 866 867 /* 868 * Fix orientation sensitivity issue on AR5416/2GHz by increasing 869 * rf_pwd_icsyndiv. 870 */ 871 void 872 ar5416_force_bias(struct athn_softc *sc, struct ieee80211_channel *c) 873 { 874 uint32_t *rwbank6 = sc->rwbuf; 875 uint8_t bias; 876 int i; 877 878 KASSERT(IEEE80211_IS_CHAN_2GHZ(c)); 879 880 /* Copy values from .rodata to writable buffer. */ 881 memcpy(rwbank6, ar5416_bank6_vals, sizeof(ar5416_bank6_vals)); 882 883 if (c->ic_freq < 2412) 884 bias = 0; 885 else if (c->ic_freq < 2422) 886 bias = 1; 887 else 888 bias = 2; 889 ar5416_reverse_bits(bias, 3); 890 891 /* Overwrite "rf_pwd_icsyndiv" (column 3, bits [181-183].) */ 892 ar5416_rw_rfbits(rwbank6, 3, 181, bias, 3); 893 894 /* Write Bank 6. */ 895 for (i = 0; i < 32; i++) 896 AR_WRITE(sc, 0x989c, rwbank6[i]); 897 AR_WRITE(sc, 0x98d0, 0x0010000f); 898 } 899 900 /* 901 * Overwrite XPA bias level based on ROM setting. 902 */ 903 void 904 ar9160_rw_addac(struct athn_softc *sc, struct ieee80211_channel *c, 905 uint32_t *addac) 906 { 907 struct ar5416_eeprom *eep = sc->eep; 908 struct ar5416_modal_eep_header *modal; 909 uint8_t fbin, bias; 910 int i; 911 912 /* XXX xpaBiasLvlFreq values have not been endian-swapped? */ 913 914 /* Get the XPA bias level to use for the specified channel. */ 915 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)]; 916 if (modal->xpaBiasLvl == 0xff) { 917 bias = modal->xpaBiasLvlFreq[0] >> 14; 918 fbin = athn_chan2fbin(c); 919 for (i = 1; i < 3; i++) { 920 if (modal->xpaBiasLvlFreq[i] == 0) 921 break; 922 if ((modal->xpaBiasLvlFreq[i] & 0xff) < fbin) 923 break; 924 bias = modal->xpaBiasLvlFreq[i] >> 14; 925 } 926 } else 927 bias = modal->xpaBiasLvl & 0x3; 928 929 bias = ar5416_reverse_bits(bias, 2); /* Put in host bit-order. */ 930 DPRINTFN(4, ("bias level=%d\n", bias)); 931 if (IEEE80211_IS_CHAN_2GHZ(c)) 932 ar5416_rw_rfbits(addac, 0, 60, bias, 2); 933 else 934 ar5416_rw_rfbits(addac, 0, 55, bias, 2); 935 } 936 937 void 938 ar5416_reset_addac(struct athn_softc *sc, struct ieee80211_channel *c) 939 { 940 const struct athn_addac *addac = sc->addac; 941 const uint32_t *pvals; 942 int i; 943 944 if (AR_SREV_9160(sc) && sc->eep_rev >= AR_EEP_MINOR_VER_7) { 945 uint32_t *rwaddac = sc->rwbuf; 946 947 /* Copy values from .rodata to writable buffer. */ 948 memcpy(rwaddac, addac->vals, addac->nvals * sizeof(uint32_t)); 949 ar9160_rw_addac(sc, c, rwaddac); 950 pvals = rwaddac; 951 } else 952 pvals = addac->vals; 953 for (i = 0; i < addac->nvals; i++) 954 AR_WRITE(sc, 0x989c, pvals[i]); 955 AR_WRITE(sc, 0x98cc, 0); /* Finalize. */ 956 } 957