1 /* $OpenBSD: ar5xxx.h,v 1.53 2014/12/26 05:46:32 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * HAL interface for Atheros Wireless LAN devices. 21 * 22 * ar5k is a free replacement of the binary-only HAL used by some drivers 23 * for Atheros chipsets. While using a different ABI, it tries to be 24 * source-compatible with the original (non-free) HAL interface. 25 * 26 * Many thanks to various contributors who supported the development of 27 * ar5k with hard work and useful information. And, of course, for all the 28 * people who encouraged me to continue this work which has been based 29 * on my initial approach found on http://team.vantronix.net/ar5k/. 30 */ 31 32 #ifndef _AR5K_H 33 #define _AR5K_H 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/errno.h> 43 #include <sys/endian.h> 44 45 #include <machine/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_arp.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_radiotap.h> 57 #include <net80211/ieee80211_regdomain.h> 58 59 /* 60 * Possible chipsets (could appear in different combinations) 61 */ 62 63 enum ar5k_version { 64 AR5K_AR5210 = 0, 65 AR5K_AR5211 = 1, 66 AR5K_AR5212 = 2, 67 }; 68 69 enum ar5k_radio { 70 AR5K_AR5110 = 0, 71 AR5K_AR5111 = 1, 72 AR5K_AR5112 = 2, 73 AR5K_AR2413 = 3, 74 AR5K_AR5413 = 4, 75 AR5K_AR2425 = 5 76 }; 77 78 /* 79 * Generic definitions 80 */ 81 82 typedef enum { 83 AH_FALSE = 0, 84 AH_TRUE, 85 } HAL_BOOL; 86 87 typedef enum { 88 HAL_MODE_11A = 0x001, 89 HAL_MODE_TURBO = 0x002, 90 HAL_MODE_11B = 0x004, 91 HAL_MODE_PUREG = 0x008, 92 HAL_MODE_11G = 0x010, 93 HAL_MODE_108G = 0x020, 94 HAL_MODE_XR = 0x040, 95 HAL_MODE_ALL = 0xfff 96 } HAL_MODE; 97 98 typedef enum { 99 HAL_ANT_VARIABLE = 0, 100 HAL_ANT_FIXED_A = 1, 101 HAL_ANT_FIXED_B = 2, 102 HAL_ANT_MAX = 3, 103 } HAL_ANT_SETTING; 104 105 typedef enum { 106 HAL_M_STA = 1, 107 HAL_M_IBSS = 0, 108 HAL_M_HOSTAP = 6, 109 HAL_M_MONITOR = 8, 110 } HAL_OPMODE; 111 112 typedef int HAL_STATUS; 113 114 #define HAL_OK 0 115 #define HAL_EINPROGRESS EINPROGRESS 116 117 #define AR5K_MAX_RSSI 64 118 119 /* 120 * TX queues 121 */ 122 123 typedef enum { 124 HAL_TX_QUEUE_INACTIVE = 0, 125 HAL_TX_QUEUE_DATA, 126 HAL_TX_QUEUE_BEACON, 127 HAL_TX_QUEUE_CAB, 128 HAL_TX_QUEUE_PSPOLL, 129 } HAL_TX_QUEUE; 130 131 #define HAL_NUM_TX_QUEUES 10 132 133 typedef enum { 134 HAL_TX_QUEUE_ID_DATA_MIN = 0, 135 HAL_TX_QUEUE_ID_DATA_MAX = 6, 136 HAL_TX_QUEUE_ID_PSPOLL = 7, 137 HAL_TX_QUEUE_ID_BEACON = 8, 138 HAL_TX_QUEUE_ID_CAB = 9, 139 } HAL_TX_QUEUE_ID; 140 141 typedef enum { 142 HAL_WME_AC_BK = 0, 143 HAL_WME_AC_BE = 1, 144 HAL_WME_AC_VI = 2, 145 HAL_WME_AC_VO = 3, 146 HAL_WME_UPSD = 4, 147 } HAL_TX_QUEUE_SUBTYPE; 148 149 #define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 150 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 151 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004 152 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008 153 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010 154 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020 155 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040 156 157 typedef struct { 158 u_int32_t tqi_ver; 159 HAL_TX_QUEUE tqi_type; 160 HAL_TX_QUEUE_SUBTYPE tqi_subtype; 161 u_int16_t tqi_flags; 162 u_int32_t tqi_priority; 163 u_int32_t tqi_aifs; 164 int32_t tqi_cw_min; 165 int32_t tqi_cw_max; 166 u_int32_t tqi_cbr_period; 167 u_int32_t tqi_cbr_overflow_limit; 168 u_int32_t tqi_burst_time; 169 u_int32_t tqi_ready_time; 170 } HAL_TXQ_INFO; 171 172 typedef enum { 173 HAL_PKT_TYPE_NORMAL = 0, 174 HAL_PKT_TYPE_ATIM = 1, 175 HAL_PKT_TYPE_PSPOLL = 2, 176 HAL_PKT_TYPE_BEACON = 3, 177 HAL_PKT_TYPE_PROBE_RESP = 4, 178 HAL_PKT_TYPE_PIFS = 5, 179 } HAL_PKT_TYPE; 180 181 /* 182 * Used to compute TX times 183 */ 184 185 #define AR5K_CCK_SIFS_TIME 10 186 #define AR5K_CCK_PREAMBLE_BITS 144 187 #define AR5K_CCK_PLCP_BITS 48 188 #define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3) 189 #define AR5K_CCK_PHY_TIME(_sp) (_sp ? \ 190 ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \ 191 (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS)) 192 #define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \ 193 AR5K_CCK_PHY_TIME(_sp) + \ 194 ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \ 195 AR5K_CCK_SIFS_TIME 196 197 #define AR5K_OFDM_SIFS_TIME 16 198 #define AR5K_OFDM_PREAMBLE_TIME 20 199 #define AR5K_OFDM_PLCP_BITS 22 200 #define AR5K_OFDM_SYMBOL_TIME 4 201 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) 202 #define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ 203 AR5K_OFDM_SYMBOL_TIME) / 1000) 204 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3)) 205 #define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \ 206 howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps)) 207 #define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \ 208 AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \ 209 (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME) 210 211 #define AR5K_TURBO_SIFS_TIME 8 212 #define AR5K_TURBO_PREAMBLE_TIME 14 213 #define AR5K_TURBO_PLCP_BITS 22 214 #define AR5K_TURBO_SYMBOL_TIME 4 215 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) 216 #define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \ 217 AR5K_TURBO_SYMBOL_TIME) / 1000) 218 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3)) 219 #define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \ 220 howmany(AR5K_TURBO_NUM_BITS(_frmlen), \ 221 AR5K_TURBO_NUM_BITS_PER_SYM(_kbps)) 222 #define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \ 223 AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \ 224 (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME) 225 226 #define AR5K_XR_SIFS_TIME 16 227 #define AR5K_XR_PLCP_BITS 22 228 #define AR5K_XR_SYMBOL_TIME 4 229 #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76) 230 #define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \ 231 AR5K_XR_SYMBOL_TIME) / 1000) 232 #define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3)) 233 #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \ 234 howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps)) 235 #define AR5K_XR_TX_TIME(_kbps, _frmlen) \ 236 AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \ 237 (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME) 238 239 /* 240 * RX definitions 241 */ 242 243 #define HAL_RX_FILTER_UCAST 0x00000001 244 #define HAL_RX_FILTER_MCAST 0x00000002 245 #define HAL_RX_FILTER_BCAST 0x00000004 246 #define HAL_RX_FILTER_CONTROL 0x00000008 247 #define HAL_RX_FILTER_BEACON 0x00000010 248 #define HAL_RX_FILTER_PROM 0x00000020 249 #define HAL_RX_FILTER_PROBEREQ 0x00000080 250 #define HAL_RX_FILTER_PHYERR 0x00000100 251 #define HAL_RX_FILTER_PHYRADAR 0x00000200 252 253 typedef struct { 254 u_int32_t ackrcv_bad; 255 u_int32_t rts_bad; 256 u_int32_t rts_good; 257 u_int32_t fcs_bad; 258 u_int32_t beacons; 259 } HAL_MIB_STATS; 260 261 /* 262 * Beacon/AP definitions 263 */ 264 265 #define HAL_BEACON_PERIOD 0x0000ffff 266 #define HAL_BEACON_ENA 0x00800000 267 #define HAL_BEACON_RESET_TSF 0x01000000 268 269 typedef struct { 270 u_int32_t bs_next_beacon; 271 u_int32_t bs_next_dtim; 272 u_int32_t bs_interval; 273 u_int8_t bs_dtim_period; 274 u_int8_t bs_cfp_period; 275 u_int16_t bs_cfp_max_duration; 276 u_int16_t bs_cfp_du_remain; 277 u_int16_t bs_tim_offset; 278 u_int16_t bs_sleep_duration; 279 u_int16_t bs_bmiss_threshold; 280 281 #define bs_nexttbtt bs_next_beacon 282 #define bs_intval bs_interval 283 #define bs_nextdtim bs_next_dtim 284 #define bs_bmissthreshold bs_bmiss_threshold 285 #define bs_sleepduration bs_sleep_duration 286 #define bs_dtimperiod bs_dtim_period 287 288 } HAL_BEACON_STATE; 289 290 /* 291 * Power management 292 */ 293 294 typedef enum { 295 HAL_PM_UNDEFINED = 0, 296 HAL_PM_AUTO, 297 HAL_PM_AWAKE, 298 HAL_PM_FULL_SLEEP, 299 HAL_PM_NETWORK_SLEEP, 300 } HAL_POWER_MODE; 301 302 /* 303 * Weak wireless crypto definitions (use IPsec/WLSec/...) 304 */ 305 306 typedef enum { 307 HAL_CIPHER_WEP = 0, 308 HAL_CIPHER_AES_CCM, 309 HAL_CIPHER_CKIP, 310 } HAL_CIPHER; 311 312 #define AR5K_KEYVAL_LENGTH_40 5 313 #define AR5K_KEYVAL_LENGTH_104 13 314 #define AR5K_KEYVAL_LENGTH_128 16 315 #define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128 316 317 typedef struct { 318 int wk_len; 319 u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX]; 320 } HAL_KEYVAL; 321 322 #define AR5K_ASSERT_ENTRY(_e, _s) do { \ 323 if (_e >= _s) \ 324 return (AH_FALSE); \ 325 } while (0) 326 327 /* 328 * PHY 329 */ 330 331 #define AR5K_MAX_RATES 32 332 333 typedef struct { 334 u_int8_t valid; 335 u_int8_t phy; 336 u_int16_t rateKbps; 337 u_int8_t rateCode; 338 u_int8_t shortPreamble; 339 u_int8_t dot11Rate; 340 u_int8_t controlRate; 341 342 #define r_valid valid 343 #define r_phy phy 344 #define r_rate_kbps rateKbps 345 #define r_rate_code rateCode 346 #define r_short_preamble shortPreamble 347 #define r_dot11_rate dot11Rate 348 #define r_control_rate controlRate 349 350 } HAL_RATE; 351 352 typedef struct { 353 u_int16_t rateCount; 354 u_int8_t rateCodeToIndex[AR5K_MAX_RATES]; 355 HAL_RATE info[AR5K_MAX_RATES]; 356 357 #define rt_rate_count rateCount 358 #define rt_rate_code_index rateCodeToIndex 359 #define rt_info info 360 361 } HAL_RATE_TABLE; 362 363 #define AR5K_RATES_11A { 8, { \ 364 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ 365 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ 366 255, 255, 255, 255, 255, 255, 255, 255 }, { \ 367 { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 0 }, \ 368 { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 0 }, \ 369 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 2 }, \ 370 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 2 }, \ 371 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 4 }, \ 372 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 4 }, \ 373 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 4 }, \ 374 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 4 } } \ 375 } 376 377 #define AR5K_RATES_11B { 4, { \ 378 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ 379 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ 380 3, 2, 1, 0, 255, 255, 255, 255 }, { \ 381 { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 }, \ 382 { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 132, 1 }, \ 383 { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 139, 1 }, \ 384 { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 150, 1 } } \ 385 } 386 387 #define AR5K_RATES_11G { 12, { \ 388 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ 389 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ 390 3, 2, 1, 0, 255, 255, 255, 255 }, { \ 391 { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 }, \ 392 { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 132, 1 }, \ 393 { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 139, 2 }, \ 394 { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 150, 3 }, \ 395 { 0, IEEE80211_T_OFDM, 6000, 11, 0, 12, 4 }, \ 396 { 0, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \ 397 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 24, 6 }, \ 398 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \ 399 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 48, 8 }, \ 400 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \ 401 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \ 402 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \ 403 } 404 405 #define AR5K_RATES_TURBO { 8, { \ 406 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ 407 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ 408 255, 255, 255, 255, 255, 255, 255, 255 }, { \ 409 { 1, IEEE80211_T_TURBO, 6000, 11, 0, 140, 0 }, \ 410 { 1, IEEE80211_T_TURBO, 9000, 15, 0, 18, 0 }, \ 411 { 1, IEEE80211_T_TURBO, 12000, 10, 0, 152, 2 }, \ 412 { 1, IEEE80211_T_TURBO, 18000, 14, 0, 36, 2 }, \ 413 { 1, IEEE80211_T_TURBO, 24000, 9, 0, 176, 4 }, \ 414 { 1, IEEE80211_T_TURBO, 36000, 13, 0, 72, 4 }, \ 415 { 1, IEEE80211_T_TURBO, 48000, 8, 0, 96, 4 }, \ 416 { 1, IEEE80211_T_TURBO, 54000, 12, 0, 108, 4 } } \ 417 } 418 419 #define AR5K_RATES_XR { 12, { \ 420 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \ 421 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ 422 255, 255, 255, 255, 255, 255, 255, 255 }, { \ 423 { 1, IEEE80211_T_XR, 500, 7, 0, 129, 0 }, \ 424 { 1, IEEE80211_T_XR, 1000, 2, 0, 139, 1 }, \ 425 { 1, IEEE80211_T_XR, 2000, 6, 0, 150, 2 }, \ 426 { 1, IEEE80211_T_XR, 3000, 1, 0, 150, 3 }, \ 427 { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 4 }, \ 428 { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \ 429 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 6 }, \ 430 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \ 431 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 8 }, \ 432 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \ 433 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \ 434 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \ 435 } 436 437 typedef enum { 438 HAL_RFGAIN_INACTIVE = 0, 439 HAL_RFGAIN_READ_REQUESTED, 440 HAL_RFGAIN_NEED_CHANGE, 441 } HAL_RFGAIN; 442 443 typedef struct { 444 u_int16_t channel; /* MHz */ 445 u_int16_t channelFlags; 446 447 #define c_channel channel 448 #define c_channel_flags channelFlags 449 450 } HAL_CHANNEL; 451 452 #define HAL_SLOT_TIME_9 396 453 #define HAL_SLOT_TIME_20 880 454 #define HAL_SLOT_TIME_MAX 0xffff 455 456 #define CHANNEL_A (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM) 457 #define CHANNEL_B (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK) 458 #define CHANNEL_G (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN) 459 #define CHANNEL_PUREG (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM) 460 #define CHANNEL_T (CHANNEL_A | IEEE80211_CHAN_TURBO) 461 #define CHANNEL_TG (CHANNEL_PUREG | IEEE80211_CHAN_TURBO) 462 #define CHANNEL_XR (CHANNEL_A | IEEE80211_CHAN_XR) 463 #define CHANNEL_MODES \ 464 (CHANNEL_A | CHANNEL_B | CHANNEL_G | CHANNEL_PUREG | \ 465 CHANNEL_T | CHANNEL_TG | CHANNEL_XR) 466 467 typedef enum { 468 HAL_CHIP_5GHZ = IEEE80211_CHAN_5GHZ, 469 HAL_CHIP_2GHZ = IEEE80211_CHAN_2GHZ 470 } HAL_CHIP; 471 472 /* 473 * The following structure will be used to map 2GHz channels to 474 * 5GHz Atheros channels. 475 */ 476 477 struct ar5k_athchan_2ghz { 478 u_int32_t a2_flags; 479 u_int16_t a2_athchan; 480 }; 481 482 /* 483 * Regulation stuff 484 */ 485 486 typedef enum ieee80211_countrycode HAL_CTRY_CODE; 487 488 /* 489 * HAL interrupt abstraction 490 */ 491 492 #define HAL_INT_RX 0x00000001 493 #define HAL_INT_RXDESC 0x00000002 494 #define HAL_INT_RXNOFRM 0x00000008 495 #define HAL_INT_RXEOL 0x00000010 496 #define HAL_INT_RXORN 0x00000020 497 #define HAL_INT_TX 0x00000040 498 #define HAL_INT_TXDESC 0x00000080 499 #define HAL_INT_TXURN 0x00000800 500 #define HAL_INT_MIB 0x00001000 501 #define HAL_INT_RXPHY 0x00004000 502 #define HAL_INT_RXKCM 0x00008000 503 #define HAL_INT_SWBA 0x00010000 504 #define HAL_INT_BMISS 0x00040000 505 #define HAL_INT_BNR 0x00100000 506 #define HAL_INT_GPIO 0x01000000 507 #define HAL_INT_FATAL 0x40000000 508 #define HAL_INT_GLOBAL 0x80000000 509 #define HAL_INT_NOCARD 0xffffffff 510 #define HAL_INT_COMMON ( \ 511 HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | \ 512 HAL_INT_RXORN | HAL_INT_TXURN | HAL_INT_TXDESC | \ 513 HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | \ 514 HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO \ 515 ) 516 517 typedef u_int32_t HAL_INT; 518 519 /* 520 * LED states 521 */ 522 523 typedef enum ieee80211_state HAL_LED_STATE; 524 525 #define HAL_LED_INIT IEEE80211_S_INIT 526 #define HAL_LED_SCAN IEEE80211_S_SCAN 527 #define HAL_LED_AUTH IEEE80211_S_AUTH 528 #define HAL_LED_ASSOC IEEE80211_S_ASSOC 529 #define HAL_LED_RUN IEEE80211_S_RUN 530 531 /* GPIO-controlled software LED */ 532 #define AR5K_SOFTLED_PIN 0 533 #define AR5K_SOFTLED_ON 0 534 #define AR5K_SOFTLED_OFF 1 535 536 /* 537 * Gain settings 538 */ 539 540 #define AR5K_GAIN_CRN_FIX_BITS_5111 4 541 #define AR5K_GAIN_CRN_FIX_BITS_5112 7 542 #define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 543 #define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 544 #define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 545 #define AR5K_GAIN_CCK_PROBE_CORR 5 546 #define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 547 #define AR5K_GAIN_STEP_COUNT 10 548 #define AR5K_GAIN_PARAM_TX_CLIP 0 549 #define AR5K_GAIN_PARAM_PD_90 1 550 #define AR5K_GAIN_PARAM_PD_84 2 551 #define AR5K_GAIN_PARAM_GAIN_SEL 3 552 #define AR5K_GAIN_PARAM_MIX_ORN 0 553 #define AR5K_GAIN_PARAM_PD_138 1 554 #define AR5K_GAIN_PARAM_PD_137 2 555 #define AR5K_GAIN_PARAM_PD_136 3 556 #define AR5K_GAIN_PARAM_PD_132 4 557 #define AR5K_GAIN_PARAM_PD_131 5 558 #define AR5K_GAIN_PARAM_PD_130 6 559 #define AR5K_GAIN_CHECK_ADJUST(_g) \ 560 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) 561 562 struct ar5k_gain_opt_step { 563 int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]; 564 int32_t gos_gain; 565 }; 566 567 struct ar5k_gain_opt { 568 u_int32_t go_default; 569 u_int32_t go_steps_count; 570 const struct ar5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]; 571 }; 572 573 struct ar5k_gain { 574 u_int32_t g_step_idx; 575 u_int32_t g_current; 576 u_int32_t g_target; 577 u_int32_t g_low; 578 u_int32_t g_high; 579 u_int32_t g_f_corr; 580 u_int32_t g_active; 581 const struct ar5k_gain_opt_step *g_step; 582 }; 583 584 #define AR5K_AR5111_GAIN_OPT { \ 585 4, \ 586 9, \ 587 { \ 588 { { 4, 1, 1, 1 }, 6 }, \ 589 { { 4, 0, 1, 1 }, 4 }, \ 590 { { 3, 1, 1, 1 }, 3 }, \ 591 { { 4, 0, 0, 1 }, 1 }, \ 592 { { 4, 1, 1, 0 }, 0 }, \ 593 { { 4, 0, 1, 0 }, -2 }, \ 594 { { 3, 1, 1, 0 }, -3 }, \ 595 { { 4, 0, 0, 0 }, -4 }, \ 596 { { 2, 1, 1, 0 }, -6 } \ 597 } \ 598 } 599 600 #define AR5K_AR5112_GAIN_OPT { \ 601 1, \ 602 8, \ 603 { \ 604 { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \ 605 { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \ 606 { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \ 607 { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \ 608 { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \ 609 { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \ 610 { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \ 611 { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \ 612 } \ 613 } 614 615 /* 616 * Common ar5xxx EEPROM data registers 617 */ 618 619 #define AR5K_EEPROM_MAGIC 0x003d 620 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 621 #define AR5K_EEPROM_PROTECT 0x003f 622 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 623 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 624 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 625 #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 626 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 627 #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 628 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 629 #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 630 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 631 #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 632 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 633 #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 634 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 635 #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 636 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 637 #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 638 #define AR5K_EEPROM_REG_DOMAIN 0x00bf 639 #define AR5K_EEPROM_INFO_BASE 0x00c0 640 #define AR5K_EEPROM_INFO_MAX \ 641 (0x400 - AR5K_EEPROM_INFO_BASE) 642 #define AR5K_EEPROM_INFO_CKSUM 0xffff 643 #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) 644 645 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) 646 #define AR5K_EEPROM_VERSION_3_0 0x3000 647 #define AR5K_EEPROM_VERSION_3_1 0x3001 648 #define AR5K_EEPROM_VERSION_3_2 0x3002 649 #define AR5K_EEPROM_VERSION_3_3 0x3003 650 #define AR5K_EEPROM_VERSION_3_4 0x3004 651 #define AR5K_EEPROM_VERSION_4_0 0x4000 652 #define AR5K_EEPROM_VERSION_4_1 0x4001 653 #define AR5K_EEPROM_VERSION_4_2 0x4002 654 #define AR5K_EEPROM_VERSION_4_3 0x4003 655 #define AR5K_EEPROM_VERSION_4_6 0x4006 656 #define AR5K_EEPROM_VERSION_4_7 0x3007 657 658 #define AR5K_EEPROM_MODE_11A 0 659 #define AR5K_EEPROM_MODE_11B 1 660 #define AR5K_EEPROM_MODE_11G 2 661 662 #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) 663 #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) 664 #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) 665 #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) 666 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) 667 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) 668 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) 669 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) 670 #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) 671 672 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c 673 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 674 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 675 #define AR5K_EEPROM_RFKILL_POLARITY_S 1 676 677 /* Newer EEPROMs are using a different offset */ 678 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ 679 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) 680 681 #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) 682 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) 683 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) 684 685 #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) 686 #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) 687 #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) 688 #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) 689 690 /* Since 3.1 */ 691 #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec 692 #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed 693 694 /* Misc values available since EEPROM 4.0 */ 695 #define AR5K_EEPROM_MISC0 0x00c4 696 #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) 697 #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) 698 #define AR5K_EEPROM_MISC1 0x00c5 699 #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) 700 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) 701 702 /* Some EEPROM defines */ 703 #define AR5K_EEPROM_EEP_SCALE 100 704 #define AR5K_EEPROM_EEP_DELTA 10 705 #define AR5K_EEPROM_N_MODES 3 706 #define AR5K_EEPROM_N_5GHZ_CHAN 10 707 #define AR5K_EEPROM_N_2GHZ_CHAN 3 708 #define AR5K_EEPROM_MAX_CHAN 10 709 #define AR5K_EEPROM_N_PCDAC 11 710 #define AR5K_EEPROM_N_TEST_FREQ 8 711 #define AR5K_EEPROM_N_EDGES 8 712 #define AR5K_EEPROM_N_INTERCEPTS 11 713 #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff) 714 #define AR5K_EEPROM_PCDAC_M 0x3f 715 #define AR5K_EEPROM_PCDAC_START 1 716 #define AR5K_EEPROM_PCDAC_STOP 63 717 #define AR5K_EEPROM_PCDAC_STEP 1 718 #define AR5K_EEPROM_NON_EDGE_M 0x40 719 #define AR5K_EEPROM_CHANNEL_POWER 8 720 #define AR5K_EEPROM_N_OBDB 4 721 #define AR5K_EEPROM_OBDB_DIS 0xffff 722 #define AR5K_EEPROM_CHANNEL_DIS 0xff 723 #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10) 724 #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32) 725 #define AR5K_EEPROM_MAX_CTLS 32 726 #define AR5K_EEPROM_N_XPD_PER_CHANNEL 4 727 #define AR5K_EEPROM_N_XPD0_POINTS 4 728 #define AR5K_EEPROM_N_XPD3_POINTS 3 729 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 730 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 731 #define AR5K_EEPROM_POWER_M 0x3f 732 #define AR5K_EEPROM_POWER_MIN 0 733 #define AR5K_EEPROM_POWER_MAX 3150 734 #define AR5K_EEPROM_POWER_STEP 50 735 #define AR5K_EEPROM_POWER_TABLE_SIZE 64 736 #define AR5K_EEPROM_N_POWER_LOC_11B 4 737 #define AR5K_EEPROM_N_POWER_LOC_11G 6 738 #define AR5K_EEPROM_I_GAIN 10 739 #define AR5K_EEPROM_CCK_OFDM_DELTA 15 740 #define AR5K_EEPROM_N_IQ_CAL 2 741 742 struct ar5k_eeprom_info { 743 u_int16_t ee_magic; 744 u_int16_t ee_protect; 745 u_int16_t ee_regdomain; 746 u_int16_t ee_version; 747 u_int16_t ee_header; 748 u_int16_t ee_ant_gain; 749 u_int16_t ee_misc0; 750 u_int16_t ee_misc1; 751 u_int16_t ee_cck_ofdm_gain_delta; 752 u_int16_t ee_cck_ofdm_power_delta; 753 u_int16_t ee_scaled_cck_delta; 754 u_int16_t ee_tx_clip; 755 u_int16_t ee_pwd_84; 756 u_int16_t ee_pwd_90; 757 u_int16_t ee_gain_select; 758 759 u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES]; 760 u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES]; 761 u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES]; 762 u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES]; 763 u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES]; 764 u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES]; 765 u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES]; 766 u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]; 767 u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; 768 u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]; 769 u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]; 770 u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]; 771 u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]; 772 u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES]; 773 u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES]; 774 u_int16_t ee_xpd[AR5K_EEPROM_N_MODES]; 775 u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES]; 776 u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES]; 777 u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES]; 778 u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES]; 779 u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN]; 780 u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; 781 782 u_int16_t ee_ctls; 783 u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS]; 784 785 int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES]; 786 int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES]; 787 int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES]; 788 }; 789 790 /* 791 * Chipset capabilities 792 */ 793 794 typedef struct { 795 /* 796 * Supported PHY modes 797 * (ie. IEEE80211_CHAN_A, IEEE80211_CHAN_B, ...) 798 */ 799 u_int16_t cap_mode; 800 801 /* 802 * Frequency range (without regulation restrictions) 803 */ 804 struct { 805 u_int16_t range_2ghz_min; 806 u_int16_t range_2ghz_max; 807 u_int16_t range_5ghz_min; 808 u_int16_t range_5ghz_max; 809 } cap_range; 810 811 /* 812 * Active regulation domain settings 813 */ 814 struct { 815 ieee80211_regdomain_t reg_current; 816 ieee80211_regdomain_t reg_hw; 817 } cap_regdomain; 818 819 /* 820 * Values stored in the EEPROM (some of them...) 821 */ 822 struct ar5k_eeprom_info cap_eeprom; 823 824 /* 825 * Queue information 826 */ 827 struct { 828 u_int8_t q_tx_num; 829 } cap_queues; 830 } ar5k_capabilities_t; 831 832 /* 833 * TX power and TPC settings 834 */ 835 836 #define AR5K_TXPOWER_OFDM(_r, _v) ( \ 837 ((0 & 1) << ((_v) + 6)) | \ 838 (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \ 839 ) 840 841 #define AR5K_TXPOWER_CCK(_r, _v) ( \ 842 (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \ 843 ) 844 845 /* 846 * Atheros descriptor definitions 847 */ 848 849 struct ath_tx_status { 850 u_int16_t ts_seqnum; 851 u_int16_t ts_tstamp; 852 u_int8_t ts_status; 853 u_int8_t ts_rate; 854 int8_t ts_rssi; 855 u_int8_t ts_shortretry; 856 u_int8_t ts_longretry; 857 u_int8_t ts_virtcol; 858 u_int8_t ts_antenna; 859 }; 860 861 #define HAL_TXSTAT_ALTRATE 0x80 862 #define HAL_TXERR_XRETRY 0x01 863 #define HAL_TXERR_FILT 0x02 864 #define HAL_TXERR_FIFO 0x04 865 866 struct ath_rx_status { 867 u_int16_t rs_datalen; 868 u_int16_t rs_tstamp; 869 u_int8_t rs_status; 870 u_int8_t rs_phyerr; 871 int8_t rs_rssi; 872 u_int8_t rs_keyix; 873 u_int8_t rs_rate; 874 u_int8_t rs_antenna; 875 u_int8_t rs_more; 876 }; 877 878 #define HAL_RXERR_CRC 0x01 879 #define HAL_RXERR_PHY 0x02 880 #define HAL_RXERR_FIFO 0x04 881 #define HAL_RXERR_DECRYPT 0x08 882 #define HAL_RXERR_MIC 0x10 883 #define HAL_RXKEYIX_INVALID ((u_int8_t) - 1) 884 #define HAL_TXKEYIX_INVALID ((u_int32_t) - 1) 885 886 #define HAL_PHYERR_UNDERRUN 0x00 887 #define HAL_PHYERR_TIMING 0x01 888 #define HAL_PHYERR_PARITY 0x02 889 #define HAL_PHYERR_RATE 0x03 890 #define HAL_PHYERR_LENGTH 0x04 891 #define HAL_PHYERR_RADAR 0x05 892 #define HAL_PHYERR_SERVICE 0x06 893 #define HAL_PHYERR_TOR 0x07 894 #define HAL_PHYERR_OFDM_TIMING 0x11 895 #define HAL_PHYERR_OFDM_SIGNAL_PARITY 0x12 896 #define HAL_PHYERR_OFDM_RATE_ILLEGAL 0x13 897 #define HAL_PHYERR_OFDM_LENGTH_ILLEGAL 0x14 898 #define HAL_PHYERR_OFDM_POWER_DROP 0x15 899 #define HAL_PHYERR_OFDM_SERVICE 0x16 900 #define HAL_PHYERR_OFDM_RESTART 0x17 901 #define HAL_PHYERR_CCK_TIMING 0x19 902 #define HAL_PHYERR_CCK_HEADER_CRC 0x1a 903 #define HAL_PHYERR_CCK_RATE_ILLEGAL 0x1b 904 #define HAL_PHYERR_CCK_SERVICE 0x1e 905 #define HAL_PHYERR_CCK_RESTART 0x1f 906 907 struct ath_desc { 908 u_int32_t ds_link; 909 u_int32_t ds_data; 910 u_int32_t ds_ctl0; 911 u_int32_t ds_ctl1; 912 u_int32_t ds_hw[4]; 913 914 union { 915 struct ath_rx_status rx; 916 struct ath_tx_status tx; 917 } ds_us; 918 919 #define ds_rxstat ds_us.rx 920 #define ds_txstat ds_us.tx 921 922 } __packed; 923 924 #define HAL_RXDESC_INTREQ 0x0020 925 926 #define HAL_TXDESC_CLRDMASK 0x0001 927 #define HAL_TXDESC_NOACK 0x0002 928 #define HAL_TXDESC_RTSENA 0x0004 929 #define HAL_TXDESC_CTSENA 0x0008 930 #define HAL_TXDESC_INTREQ 0x0010 931 #define HAL_TXDESC_VEOL 0x0020 932 933 /* 934 * Hardware abstraction layer structure 935 */ 936 937 #define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ar5k_##_n##_##_f 938 #define AR5K_HAL_FUNCTIONS(_t, _n, _a) \ 939 _t const HAL_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, \ 940 u_int mode); \ 941 _t void (_a _n##_detach)(struct ath_hal *); \ 942 /* Reset functions */ \ 943 _t HAL_BOOL (_a _n##_reset)(struct ath_hal *, HAL_OPMODE, \ 944 HAL_CHANNEL *, HAL_BOOL change_channel, HAL_STATUS *status); \ 945 _t void (_a _n##_set_opmode)(struct ath_hal *); \ 946 _t HAL_BOOL (_a _n##_calibrate)(struct ath_hal*, \ 947 HAL_CHANNEL *); \ 948 /* Transmit functions */ \ 949 _t HAL_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, \ 950 HAL_BOOL level); \ 951 _t int (_a _n##_setup_tx_queue)(struct ath_hal *, HAL_TX_QUEUE, \ 952 const HAL_TXQ_INFO *); \ 953 _t HAL_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \ 954 const HAL_TXQ_INFO *); \ 955 _t HAL_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \ 956 _t HAL_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \ 957 _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \ 958 _t HAL_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, \ 959 u_int32_t phys_addr); \ 960 _t HAL_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \ 961 _t HAL_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \ 962 _t HAL_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, \ 963 struct ath_desc *, \ 964 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, \ 965 u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \ 966 u_int antenna_mode, u_int flags, u_int rtscts_rate, \ 967 u_int rtscts_duration); \ 968 _t HAL_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, \ 969 struct ath_desc *, \ 970 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, \ 971 u_int tx_rate3, u_int tx_tries3); \ 972 _t HAL_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, \ 973 struct ath_desc *, \ 974 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg); \ 975 _t HAL_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, \ 976 struct ath_desc *); \ 977 _t HAL_BOOL (_a _n##_has_veol)(struct ath_hal *); \ 978 /* Receive Functions */ \ 979 _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \ 980 _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \ 981 _t void (_a _n##_start_rx)(struct ath_hal*); \ 982 _t HAL_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \ 983 _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \ 984 _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \ 985 _t void (_a _n##_set_mcast_filter)(struct ath_hal*, \ 986 u_int32_t filter0, u_int32_t filter1); \ 987 _t HAL_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, \ 988 u_int32_t index); \ 989 _t HAL_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*, \ 990 u_int32_t index); \ 991 _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \ 992 _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \ 993 _t HAL_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, \ 994 struct ath_desc *, u_int32_t size, u_int flags); \ 995 _t HAL_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, \ 996 struct ath_desc *, u_int32_t phyAddr, struct ath_desc *next); \ 997 _t void (_a _n##_set_rx_signal)(struct ath_hal *); \ 998 /* Misc Functions */ \ 999 _t void (_a _n##_dump_state)(struct ath_hal *); \ 1000 _t HAL_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int, void **, \ 1001 u_int *); \ 1002 _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \ 1003 _t HAL_BOOL (_a _n##_set_lladdr)(struct ath_hal *, \ 1004 const u_int8_t*); \ 1005 _t HAL_BOOL (_a _n##_set_regdomain)(struct ath_hal*, \ 1006 u_int16_t, HAL_STATUS *); \ 1007 _t void (_a _n##_set_ledstate)(struct ath_hal*, HAL_LED_STATE); \ 1008 _t void (_a _n##_set_associd)(struct ath_hal*, \ 1009 const u_int8_t *bssid, u_int16_t assocId, u_int16_t timOffset); \ 1010 _t HAL_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, \ 1011 u_int32_t gpio); \ 1012 _t HAL_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, \ 1013 u_int32_t gpio); \ 1014 _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \ 1015 _t HAL_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, \ 1016 u_int32_t val); \ 1017 _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \ 1018 _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \ 1019 _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \ 1020 _t void (_a _n##_reset_tsf)(struct ath_hal*); \ 1021 _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \ 1022 _t HAL_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \ 1023 _t void (_a _n##_update_mib_counters)(struct ath_hal*, \ 1024 HAL_MIB_STATS*); \ 1025 _t HAL_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, \ 1026 HAL_CIPHER); \ 1027 _t HAL_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \ 1028 _t HAL_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \ 1029 _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \ 1030 _t HAL_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \ 1031 _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \ 1032 _t HAL_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \ 1033 _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \ 1034 /* Key Cache Functions */ \ 1035 _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \ 1036 _t HAL_BOOL (_a _n##_reset_key)(struct ath_hal*, \ 1037 u_int16_t); \ 1038 _t HAL_BOOL (_a _n##_is_key_valid)(struct ath_hal *, \ 1039 u_int16_t); \ 1040 _t HAL_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, \ 1041 const HAL_KEYVAL *, const u_int8_t *, int); \ 1042 _t HAL_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, \ 1043 u_int16_t, const u_int8_t *); \ 1044 _t HAL_BOOL (_a _n##_softcrypto)(struct ath_hal *, HAL_BOOL); \ 1045 /* Power Management Functions */ \ 1046 _t HAL_BOOL (_a _n##_set_power)(struct ath_hal*, \ 1047 HAL_POWER_MODE mode, \ 1048 HAL_BOOL set_chip, u_int16_t sleep_duration); \ 1049 _t HAL_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \ 1050 _t HAL_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \ 1051 _t HAL_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \ 1052 _t HAL_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, \ 1053 u_int16_t); \ 1054 _t HAL_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \ 1055 /* Beacon Management Functions */ \ 1056 _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, \ 1057 u_int32_t intval); \ 1058 _t void (_a _n##_set_beacon_timers)(struct ath_hal *, \ 1059 const HAL_BEACON_STATE *, u_int32_t tsf, u_int32_t dtimCount, \ 1060 u_int32_t cfpCcount); \ 1061 _t void (_a _n##_reset_beacon)(struct ath_hal *); \ 1062 _t HAL_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, \ 1063 bus_addr_t); \ 1064 /* Interrupt functions */ \ 1065 _t HAL_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \ 1066 _t HAL_BOOL (_a _n##_get_isr)(struct ath_hal *, \ 1067 u_int32_t *); \ 1068 _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \ 1069 _t HAL_INT (_a _n##_set_intr)(struct ath_hal *, HAL_INT); \ 1070 /* Chipset functions (ar5k-specific, non-HAL) */ \ 1071 _t HAL_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \ 1072 _t void (_a _n##_radar_alert)(struct ath_hal *, HAL_BOOL enable); \ 1073 _t HAL_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \ 1074 _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, \ 1075 u_int16_t *data); \ 1076 _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, \ 1077 u_int16_t data); \ 1078 /* Unused functions */ \ 1079 _t HAL_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, \ 1080 HAL_TXQ_INFO *); \ 1081 _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \ 1082 _t HAL_BOOL (_a _n##_phy_disable)(struct ath_hal *); \ 1083 _t HAL_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \ 1084 _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \ 1085 _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \ 1086 _t HAL_BOOL (_a _n##_set_bssid_mask)(struct ath_hal *, \ 1087 const u_int8_t*); 1088 1089 #define AR5K_MAX_GPIO 10 1090 #define AR5K_MAX_RF_BANKS 8 1091 1092 struct ath_hal { 1093 u_int32_t ah_magic; 1094 u_int32_t ah_abi; 1095 u_int16_t ah_device; 1096 u_int16_t ah_sub_vendor; 1097 1098 void *ah_sc; 1099 bus_space_tag_t ah_st; 1100 bus_space_handle_t ah_sh; 1101 1102 HAL_INT ah_imr; 1103 1104 HAL_OPMODE ah_op_mode; 1105 HAL_POWER_MODE ah_power_mode; 1106 HAL_CHANNEL ah_current_channel; 1107 HAL_BOOL ah_turbo; 1108 HAL_BOOL ah_calibration; 1109 HAL_BOOL ah_running; 1110 HAL_BOOL ah_single_chip; 1111 HAL_BOOL ah_pci_express; 1112 HAL_RFGAIN ah_rf_gain; 1113 1114 int ah_chanoff; 1115 1116 HAL_RATE_TABLE ah_rt_11a; 1117 HAL_RATE_TABLE ah_rt_11b; 1118 HAL_RATE_TABLE ah_rt_11g; 1119 HAL_RATE_TABLE ah_rt_turbo; 1120 HAL_RATE_TABLE ah_rt_xr; 1121 1122 u_int32_t ah_mac_srev; 1123 u_int16_t ah_mac_version; 1124 u_int16_t ah_mac_revision; 1125 u_int16_t ah_phy_revision; 1126 u_int16_t ah_radio_5ghz_revision; 1127 u_int16_t ah_radio_2ghz_revision; 1128 1129 enum ar5k_version ah_version; 1130 enum ar5k_radio ah_radio; 1131 1132 u_int32_t ah_phy; 1133 u_int32_t ah_phy_spending; 1134 1135 HAL_BOOL ah_5ghz; 1136 HAL_BOOL ah_2ghz; 1137 1138 #define ah_regdomain ah_capabilities.cap_regdomain.reg_current 1139 #define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw 1140 #define ah_modes ah_capabilities.cap_mode 1141 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1142 1143 u_int32_t ah_atim_window; 1144 u_int32_t ah_aifs; 1145 u_int32_t ah_cw_min; 1146 u_int32_t ah_cw_max; 1147 HAL_BOOL ah_software_retry; 1148 u_int32_t ah_limit_tx_retries; 1149 1150 u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][HAL_ANT_MAX]; 1151 HAL_BOOL ah_ant_diversity; 1152 1153 u_int8_t ah_sta_id[IEEE80211_ADDR_LEN]; 1154 u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; 1155 1156 u_int32_t ah_gpio[AR5K_MAX_GPIO]; 1157 int ah_gpio_npins; 1158 1159 ar5k_capabilities_t ah_capabilities; 1160 1161 HAL_TXQ_INFO ah_txq[HAL_NUM_TX_QUEUES]; 1162 u_int32_t ah_txq_interrupts; 1163 1164 u_int32_t *ah_rf_banks; 1165 size_t ah_rf_banks_size; 1166 struct ar5k_gain ah_gain; 1167 u_int32_t ah_offset[AR5K_MAX_RF_BANKS]; 1168 1169 struct { 1170 u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE]; 1171 u_int16_t txp_rates[AR5K_MAX_RATES]; 1172 int16_t txp_min, txp_max; 1173 HAL_BOOL txp_tpc; 1174 int16_t txp_ofdm; 1175 } ah_txpower; 1176 1177 struct { 1178 HAL_BOOL r_enabled; 1179 int r_last_alert; 1180 HAL_CHANNEL r_last_channel; 1181 } ah_radar; 1182 1183 /* 1184 * Function pointers 1185 */ 1186 AR5K_HAL_FUNCTIONS(, ah, *); 1187 }; 1188 1189 /* 1190 * Common silicon revision/version values 1191 */ 1192 enum ar5k_srev_type { 1193 AR5K_VERSION_VER, 1194 AR5K_VERSION_REV, 1195 AR5K_VERSION_RAD, 1196 AR5K_VERSION_DEV, 1197 }; 1198 1199 struct ar5k_srev_name { 1200 const char *sr_name; 1201 enum ar5k_srev_type sr_type; 1202 u_int sr_val; 1203 }; 1204 1205 #define AR5K_SREV_NAME { \ 1206 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \ 1207 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \ 1208 { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\ 1209 { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\ 1210 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \ 1211 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \ 1212 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \ 1213 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },\ 1214 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },\ 1215 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },\ 1216 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },\ 1217 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },\ 1218 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },\ 1219 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },\ 1220 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },\ 1221 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },\ 1222 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },\ 1223 { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \ 1224 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \ 1225 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \ 1226 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \ 1227 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \ 1228 { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \ 1229 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \ 1230 { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \ 1231 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 }, \ 1232 { "2414", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 }, \ 1233 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 }, \ 1234 { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \ 1235 { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \ 1236 { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \ 1237 { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \ 1238 { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \ 1239 } 1240 1241 #define AR5K_SREV_UNKNOWN 0xffff 1242 1243 #define AR5K_SREV_VER_AR5210 0x00 1244 #define AR5K_SREV_VER_AR5311 0x10 1245 #define AR5K_SREV_VER_AR5311A 0x20 1246 #define AR5K_SREV_VER_AR5311B 0x30 1247 #define AR5K_SREV_VER_AR5211 0x40 1248 #define AR5K_SREV_VER_AR5212 0x50 1249 #define AR5K_SREV_VER_AR5213 0x55 1250 #define AR5K_SREV_VER_AR5213A 0x59 1251 #define AR5K_SREV_VER_AR2413 0x78 1252 #define AR5K_SREV_VER_AR2414 0x79 1253 #define AR5K_SREV_VER_AR2424 0xa0 /* PCI-Express */ 1254 #define AR5K_SREV_VER_AR5424 0xa3 /* PCI-Express */ 1255 #define AR5K_SREV_VER_AR5413 0xa4 1256 #define AR5K_SREV_VER_AR5414 0xa5 1257 #define AR5K_SREV_VER_AR5416 0xc0 /* PCI-Express */ 1258 #define AR5K_SREV_VER_AR5418 0xca /* PCI-Express */ 1259 #define AR5K_SREV_VER_AR2425 0xe2 /* PCI-Express */ 1260 #define AR5K_SREV_VER_UNSUPP 0xff 1261 1262 #define AR5K_SREV_RAD_5110 0x00 1263 #define AR5K_SREV_RAD_5111 0x10 1264 #define AR5K_SREV_RAD_5111A 0x15 1265 #define AR5K_SREV_RAD_2111 0x20 1266 #define AR5K_SREV_RAD_5112 0x30 1267 #define AR5K_SREV_RAD_5112A 0x35 1268 #define AR5K_SREV_RAD_2112 0x40 1269 #define AR5K_SREV_RAD_2112A 0x45 1270 #define AR5K_SREV_RAD_SC0 0x56 1271 #define AR5K_SREV_RAD_SC1 0x63 1272 #define AR5K_SREV_RAD_SC2 0xa2 1273 #define AR5K_SREV_RAD_5133 0xc0 1274 #define AR5K_SREV_RAD_UNSUPP 0xff 1275 1276 #define AR5K_DEVID_AR2413 0x001a 1277 #define AR5K_DEVID_AR5413 0x001b 1278 #define AR5K_DEVID_AR5424 0x001c 1279 1280 /* 1281 * Misc defines 1282 */ 1283 1284 #define HAL_ABI_VERSION 0x04090901 /* YYMMDDnn */ 1285 1286 #define AR5K_PRINTF(fmt, ...) printf("%s: " fmt, __func__, ##__VA_ARGS__) 1287 #define AR5K_PRINT(fmt) printf("%s: " fmt, __func__) 1288 #ifdef AR5K_DEBUG 1289 #define AR5K_TRACE printf("%s:%d\n", __func__, __LINE__) 1290 #else 1291 #define AR5K_TRACE 1292 #endif 1293 #define AR5K_DELAY(_n) delay(_n) 1294 1295 typedef struct ath_hal * (ar5k_attach_t) 1296 (u_int16_t, void *, bus_space_tag_t, bus_space_handle_t, HAL_STATUS *); 1297 typedef HAL_BOOL (ar5k_rfgain_t) 1298 (struct ath_hal *, HAL_CHANNEL *, u_int); 1299 1300 /* 1301 * Some tuneable values (these should be changeable by the user) 1302 */ 1303 1304 #define AR5K_TUNE_DMA_BEACON_RESP 2 1305 #define AR5K_TUNE_SW_BEACON_RESP 10 1306 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 1307 #define AR5K_TUNE_RADAR_ALERT AH_FALSE 1308 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 1309 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) 1310 #define AR5K_TUNE_RSSI_THRES 1792 1311 #define AR5K_TUNE_REGISTER_TIMEOUT 20000 1312 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000 1313 #define AR5K_TUNE_BEACON_INTERVAL 100 1314 #define AR5K_TUNE_AIFS 2 1315 #define AR5K_TUNE_AIFS_11B 2 1316 #define AR5K_TUNE_AIFS_XR 0 1317 #define AR5K_TUNE_CWMIN 15 1318 #define AR5K_TUNE_CWMIN_11B 31 1319 #define AR5K_TUNE_CWMIN_XR 3 1320 #define AR5K_TUNE_CWMAX 1023 1321 #define AR5K_TUNE_CWMAX_11B 1023 1322 #define AR5K_TUNE_CWMAX_XR 7 1323 #define AR5K_TUNE_NOISE_FLOOR -72 1324 #define AR5K_TUNE_MAX_TXPOWER 60 1325 #define AR5K_TUNE_DEFAULT_TXPOWER 30 1326 #define AR5K_TUNE_TPC_TXPOWER AH_TRUE 1327 #define AR5K_TUNE_ANT_DIVERSITY AH_TRUE 1328 1329 /* Default regulation domain if stored value EEPROM value is invalid */ 1330 #define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */ 1331 1332 /* 1333 * Common initial register values 1334 */ 1335 1336 #define AR5K_INIT_MODE ( \ 1337 IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN \ 1338 ) 1339 #define AR5K_INIT_TX_LATENCY 502 1340 #define AR5K_INIT_USEC 39 1341 #define AR5K_INIT_USEC_TURBO 79 1342 #define AR5K_INIT_USEC_32 31 1343 #define AR5K_INIT_CARR_SENSE_EN 1 1344 #define AR5K_INIT_PROG_IFS 920 1345 #define AR5K_INIT_PROG_IFS_TURBO 960 1346 #define AR5K_INIT_EIFS 3440 1347 #define AR5K_INIT_EIFS_TURBO 6880 1348 #define AR5K_INIT_SLOT_TIME 396 1349 #define AR5K_INIT_SLOT_TIME_TURBO 480 1350 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024 1351 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 1352 #define AR5K_INIT_SIFS 560 1353 #define AR5K_INIT_SIFS_TURBO 480 1354 #define AR5K_INIT_SH_RETRY 10 1355 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 1356 #define AR5K_INIT_SSH_RETRY 32 1357 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 1358 #define AR5K_INIT_TX_RETRY 10 1359 #define AR5K_INIT_TOPS 8 1360 #define AR5K_INIT_RXNOFRM 8 1361 #define AR5K_INIT_RPGTO 0 1362 #define AR5K_INIT_TXNOFRM 0 1363 #define AR5K_INIT_BEACON_PERIOD 65535 1364 #define AR5K_INIT_TIM_OFFSET 0 1365 #define AR5K_INIT_BEACON_EN 0 1366 #define AR5K_INIT_RESET_TSF 0 1367 #define AR5K_INIT_TRANSMIT_LATENCY ( \ 1368 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 1369 (AR5K_INIT_USEC) \ 1370 ) 1371 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \ 1372 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ 1373 (AR5K_INIT_USEC_TURBO) \ 1374 ) 1375 #define AR5K_INIT_PROTO_TIME_CNTRL ( \ 1376 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ 1377 (AR5K_INIT_PROG_IFS) \ 1378 ) 1379 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \ 1380 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\ 1381 (AR5K_INIT_PROG_IFS_TURBO) \ 1382 ) 1383 #define AR5K_INIT_BEACON_CONTROL ( \ 1384 (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \ 1385 (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \ 1386 ) 1387 1388 /* 1389 * AR5k register access 1390 */ 1391 1392 #define AR5K_REG_WRITE(_reg, _val) \ 1393 bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val)) 1394 #define AR5K_REG_READ(_reg) \ 1395 bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg)) 1396 1397 #define AR5K_REG_SM(_val, _flags) \ 1398 (((_val) << _flags##_S) & (_flags)) 1399 #define AR5K_REG_MS(_val, _flags) \ 1400 (((_val) & (_flags)) >> _flags##_S) 1401 #define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \ 1402 AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ 1403 (((_val) << _flags##_S) & (_flags))) 1404 #define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \ 1405 AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags)) 1406 #define AR5K_REG_ENABLE_BITS(_reg, _flags) \ 1407 AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) 1408 #define AR5K_REG_DISABLE_BITS(_reg, _flags) \ 1409 AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) 1410 1411 #define AR5K_PHY_WRITE(_reg, _val) \ 1412 AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val) 1413 #define AR5K_PHY_READ(_reg) \ 1414 AR5K_REG_READ(hal->ah_phy + ((_reg) << 2)) 1415 1416 #define AR5K_REG_WAIT(_i) \ 1417 if (_i % 64) \ 1418 AR5K_DELAY(1); 1419 1420 #define AR5K_EEPROM_READ(_o, _v) { \ 1421 if ((ret = hal->ah_eeprom_read(hal, (_o), \ 1422 &(_v))) != 0) \ 1423 return (ret); \ 1424 } 1425 #define AR5K_EEPROM_READ_HDR(_o, _v) \ 1426 AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \ 1427 1428 /* Read status of selected queue */ 1429 #define AR5K_REG_READ_Q(_reg, _queue) \ 1430 (AR5K_REG_READ(_reg) & (1 << _queue)) \ 1431 1432 #define AR5K_REG_WRITE_Q(_reg, _queue) \ 1433 AR5K_REG_WRITE(_reg, (1 << _queue)) 1434 1435 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 1436 _reg |= 1 << _queue; \ 1437 } while (0) 1438 1439 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 1440 _reg &= ~(1 << _queue); \ 1441 } while (0) 1442 1443 #define AR5K_LOW_ID(_a) ( \ 1444 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ 1445 ) 1446 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) 1447 1448 /* 1449 * Unaligned little endian access 1450 */ 1451 1452 #define AR5K_LE_READ_2(_p) \ 1453 (((const u_int8_t *)(_p))[0] | (((const u_int8_t *)(_p))[1] << 8)) 1454 #define AR5K_LE_READ_4(_p) \ 1455 (((const u_int8_t *)(_p))[0] | \ 1456 (((const u_int8_t *)(_p))[1] << 8) | \ 1457 (((const u_int8_t *)(_p))[2] << 16) | \ 1458 (((const u_int8_t *)(_p))[3] << 24)) 1459 #define AR5K_LE_WRITE_2(_p, _val) \ 1460 ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ 1461 (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff))) 1462 #define AR5K_LE_WRITE_4(_p, _val) \ 1463 ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \ 1464 (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \ 1465 (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \ 1466 (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff))) 1467 1468 /* 1469 * Initial register values 1470 */ 1471 1472 struct ar5k_ini { 1473 u_int16_t ini_register; 1474 u_int32_t ini_value; 1475 1476 enum { 1477 AR5K_INI_WRITE = 0, 1478 AR5K_INI_READ = 1, 1479 } ini_mode; 1480 }; 1481 1482 #define AR5K_PCU_MIN 0x8000 1483 #define AR5K_PCU_MAX 0x8fff 1484 1485 #define AR5K_INI_VAL_11A 0 1486 #define AR5K_INI_VAL_11A_TURBO 1 1487 #define AR5K_INI_VAL_11B 2 1488 #define AR5K_INI_VAL_11G 3 1489 #define AR5K_INI_VAL_11G_TURBO 4 1490 #define AR5K_INI_VAL_XR 0 1491 #define AR5K_INI_VAL_MAX 5 1492 1493 struct ar5k_mode { 1494 u_int16_t mode_register; 1495 u_int32_t mode_value[AR5K_INI_VAL_MAX]; 1496 }; 1497 1498 #define AR5K_INI_PHY_5111 0 1499 #define AR5K_INI_PHY_5112 1 1500 #define AR5K_INI_PHY_511X 1 1501 1502 #define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS 1503 #define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS 1504 1505 struct ar5k_ini_rf { 1506 u_int8_t rf_bank; 1507 u_int16_t rf_register; 1508 u_int32_t rf_value[5]; 1509 }; 1510 1511 #define AR5K_AR5111_INI_RF { \ 1512 { 0, 0x989c, \ 1513 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1514 { 0, 0x989c, \ 1515 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1516 { 0, 0x989c, \ 1517 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1518 { 0, 0x989c, \ 1519 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1520 { 0, 0x989c, \ 1521 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1522 { 0, 0x989c, \ 1523 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1524 { 0, 0x989c, \ 1525 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1526 { 0, 0x989c, \ 1527 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1528 { 0, 0x989c, \ 1529 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1530 { 0, 0x989c, \ 1531 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1532 { 0, 0x989c, \ 1533 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1534 { 0, 0x989c, \ 1535 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \ 1536 { 0, 0x989c, \ 1537 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1538 { 0, 0x989c, \ 1539 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1540 { 0, 0x989c, \ 1541 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \ 1542 { 0, 0x989c, \ 1543 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \ 1544 { 0, 0x98d4, \ 1545 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \ 1546 { 1, 0x98d4, \ 1547 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ 1548 { 2, 0x98d4, \ 1549 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \ 1550 { 3, 0x98d8, \ 1551 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \ 1552 { 6, 0x989c, \ 1553 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1554 { 6, 0x989c, \ 1555 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1556 { 6, 0x989c, \ 1557 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1558 { 6, 0x989c, \ 1559 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1560 { 6, 0x989c, \ 1561 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1562 { 6, 0x989c, \ 1563 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \ 1564 { 6, 0x989c, \ 1565 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \ 1566 { 6, 0x989c, \ 1567 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1568 { 6, 0x989c, \ 1569 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1570 { 6, 0x989c, \ 1571 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1572 { 6, 0x989c, \ 1573 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \ 1574 { 6, 0x989c, \ 1575 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \ 1576 { 6, 0x989c, \ 1577 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \ 1578 { 6, 0x989c, \ 1579 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \ 1580 { 6, 0x989c, \ 1581 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \ 1582 { 6, 0x989c, \ 1583 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \ 1584 { 6, 0x98d4, \ 1585 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \ 1586 { 7, 0x989c, \ 1587 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \ 1588 { 7, 0x989c, \ 1589 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \ 1590 { 7, 0x989c, \ 1591 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ 1592 { 7, 0x989c, \ 1593 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \ 1594 { 7, 0x989c, \ 1595 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \ 1596 { 7, 0x989c, \ 1597 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \ 1598 { 7, 0x989c, \ 1599 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \ 1600 { 7, 0x98cc, \ 1601 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \ 1602 } 1603 1604 #define AR5K_AR5112_INI_RF { \ 1605 { 1, 0x98d4, \ 1606 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ 1607 { 2, 0x98d0, \ 1608 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ 1609 { 3, 0x98dc, \ 1610 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ 1611 { 6, 0x989c, \ 1612 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \ 1613 { 6, 0x989c, \ 1614 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ 1615 { 6, 0x989c, \ 1616 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1617 { 6, 0x989c, \ 1618 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1619 { 6, 0x989c, \ 1620 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \ 1621 { 6, 0x989c, \ 1622 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \ 1623 { 6, 0x989c, \ 1624 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \ 1625 { 6, 0x989c, \ 1626 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ 1627 { 6, 0x989c, \ 1628 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ 1629 { 6, 0x989c, \ 1630 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \ 1631 { 6, 0x989c, \ 1632 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1633 { 6, 0x989c, \ 1634 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ 1635 { 6, 0x989c, \ 1636 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ 1637 { 6, 0x989c, \ 1638 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ 1639 { 6, 0x989c, \ 1640 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \ 1641 { 6, 0x989c, \ 1642 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \ 1643 { 6, 0x989c, \ 1644 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ 1645 { 6, 0x989c, \ 1646 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ 1647 { 6, 0x989c, \ 1648 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \ 1649 { 6, 0x989c, \ 1650 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \ 1651 { 6, 0x989c, \ 1652 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ 1653 { 6, 0x989c, \ 1654 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \ 1655 { 6, 0x989c, \ 1656 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ 1657 { 6, 0x989c, \ 1658 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ 1659 { 6, 0x989c, \ 1660 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \ 1661 { 6, 0x989c, \ 1662 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \ 1663 { 6, 0x989c, \ 1664 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \ 1665 { 6, 0x989c, \ 1666 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \ 1667 { 6, 0x989c, \ 1668 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \ 1669 { 6, 0x989c, \ 1670 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \ 1671 { 6, 0x989c, \ 1672 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \ 1673 { 6, 0x989c, \ 1674 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \ 1675 { 6, 0x989c, \ 1676 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \ 1677 { 6, 0x989c, \ 1678 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \ 1679 { 6, 0x989c, \ 1680 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \ 1681 { 6, 0x989c, \ 1682 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \ 1683 { 6, 0x989c, \ 1684 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \ 1685 { 6, 0x98d0, \ 1686 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \ 1687 { 7, 0x989c, \ 1688 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ 1689 { 7, 0x989c, \ 1690 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ 1691 { 7, 0x989c, \ 1692 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \ 1693 { 7, 0x989c, \ 1694 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ 1695 { 7, 0x989c, \ 1696 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \ 1697 { 7, 0x989c, \ 1698 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ 1699 { 7, 0x989c, \ 1700 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ 1701 { 7, 0x989c, \ 1702 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \ 1703 { 7, 0x989c, \ 1704 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \ 1705 { 7, 0x989c, \ 1706 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ 1707 { 7, 0x989c, \ 1708 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ 1709 { 7, 0x989c, \ 1710 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ 1711 { 7, 0x98c4, \ 1712 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ 1713 } 1714 1715 #define AR5K_AR5112A_INI_RF { \ 1716 { 1, 0x98d4, \ 1717 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ 1718 { 2, 0x98d0, \ 1719 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \ 1720 { 3, 0x98dc, \ 1721 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \ 1722 { 6, 0x989c, \ 1723 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \ 1724 { 6, 0x989c, \ 1725 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1726 { 6, 0x989c, \ 1727 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \ 1728 { 6, 0x989c, \ 1729 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ 1730 { 6, 0x989c, \ 1731 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \ 1732 { 6, 0x989c, \ 1733 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1734 { 6, 0x989c, \ 1735 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \ 1736 { 6, 0x989c, \ 1737 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \ 1738 { 6, 0x989c, \ 1739 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \ 1740 { 6, 0x989c, \ 1741 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \ 1742 { 6, 0x989c, \ 1743 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \ 1744 { 6, 0x989c, \ 1745 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \ 1746 { 6, 0x989c, \ 1747 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \ 1748 { 6, 0x989c, \ 1749 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1750 { 6, 0x989c, \ 1751 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \ 1752 { 6, 0x989c, \ 1753 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ 1754 { 6, 0x989c, \ 1755 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \ 1756 { 6, 0x989c, \ 1757 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \ 1758 { 6, 0x989c, \ 1759 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \ 1760 { 6, 0x989c, \ 1761 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \ 1762 { 6, 0x989c, \ 1763 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \ 1764 { 6, 0x989c, \ 1765 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \ 1766 { 6, 0x989c, \ 1767 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \ 1768 { 6, 0x989c, \ 1769 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \ 1770 { 6, 0x989c, \ 1771 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \ 1772 { 6, 0x989c, \ 1773 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \ 1774 { 6, 0x989c, \ 1775 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \ 1776 { 6, 0x989c, \ 1777 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \ 1778 { 6, 0x989c, \ 1779 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \ 1780 { 6, 0x989c, \ 1781 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \ 1782 { 6, 0x989c, \ 1783 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \ 1784 { 6, 0x989c, \ 1785 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \ 1786 { 6, 0x989c, \ 1787 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ 1788 { 6, 0x989c, \ 1789 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1790 { 6, 0x989c, \ 1791 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \ 1792 { 6, 0x989c, \ 1793 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \ 1794 { 6, 0x989c, \ 1795 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \ 1796 { 6, 0x989c, \ 1797 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \ 1798 { 6, 0x989c, \ 1799 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \ 1800 { 6, 0x98d8, \ 1801 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \ 1802 { 7, 0x989c, \ 1803 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \ 1804 { 7, 0x989c, \ 1805 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \ 1806 { 7, 0x989c, \ 1807 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \ 1808 { 7, 0x989c, \ 1809 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \ 1810 { 7, 0x989c, \ 1811 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \ 1812 { 7, 0x989c, \ 1813 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \ 1814 { 7, 0x989c, \ 1815 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \ 1816 { 7, 0x989c, \ 1817 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \ 1818 { 7, 0x989c, \ 1819 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \ 1820 { 7, 0x989c, \ 1821 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \ 1822 { 7, 0x989c, \ 1823 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \ 1824 { 7, 0x989c, \ 1825 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \ 1826 { 7, 0x98c4, \ 1827 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \ 1828 } 1829 1830 #define AR5K_AR5413_INI_RF { \ 1831 { 1, 0x98d4, \ 1832 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \ 1833 { 2, 0x98d0, \ 1834 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \ 1835 { 3, 0x98dc, \ 1836 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } }, \ 1837 { 6, 0x989c, \ 1838 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } }, \ 1839 { 6, 0x989c, \ 1840 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } }, \ 1841 { 6, 0x989c, \ 1842 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1843 { 6, 0x989c, \ 1844 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1845 { 6, 0x989c, \ 1846 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1847 { 6, 0x989c, \ 1848 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } }, \ 1849 { 6, 0x989c, \ 1850 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1851 { 6, 0x989c, \ 1852 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } }, \ 1853 { 6, 0x989c, \ 1854 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } }, \ 1855 { 6, 0x989c, \ 1856 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \ 1857 { 6, 0x989c, \ 1858 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } }, \ 1859 { 6, 0x989c, \ 1860 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } }, \ 1861 { 6, 0x989c, \ 1862 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ 1863 { 6, 0x989c, \ 1864 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ 1865 { 6, 0x989c, \ 1866 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ 1867 { 6, 0x989c, \ 1868 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \ 1869 { 6, 0x989c, \ 1870 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } }, \ 1871 { 6, 0x989c, \ 1872 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } }, \ 1873 { 6, 0x989c, \ 1874 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } }, \ 1875 { 6, 0x989c, \ 1876 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } }, \ 1877 { 6, 0x989c, \ 1878 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } }, \ 1879 { 6, 0x989c, \ 1880 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } }, \ 1881 { 6, 0x989c, \ 1882 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } }, \ 1883 { 6, 0x989c, \ 1884 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } }, \ 1885 { 6, 0x989c, \ 1886 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } }, \ 1887 { 6, 0x989c, \ 1888 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } }, \ 1889 { 6, 0x989c, \ 1890 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } }, \ 1891 { 6, 0x989c, \ 1892 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } }, \ 1893 { 6, 0x989c, \ 1894 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } }, \ 1895 { 6, 0x989c, \ 1896 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } }, \ 1897 { 6, 0x989c, \ 1898 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } }, \ 1899 { 6, 0x989c, \ 1900 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } }, \ 1901 { 6, 0x989c, \ 1902 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } }, \ 1903 { 6, 0x989c, \ 1904 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \ 1905 { 6, 0x989c, \ 1906 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } }, \ 1907 { 6, 0x989c, \ 1908 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } }, \ 1909 { 6, 0x98c8, \ 1910 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } }, \ 1911 { 7, 0x989c, \ 1912 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, \ 1913 { 7, 0x989c, \ 1914 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, \ 1915 { 7, 0x98cc, \ 1916 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, \ 1917 } 1918 1919 #define AR5K_AR2413_INI_RF { \ 1920 { 1, 0x98d4, { 0, 0, 0x00000020, 0x00000020, 0x00000020 } }, \ 1921 { 2, 0x98d0, { 0, 0, 0x02001408, 0x02001408, 0x02001408 } }, \ 1922 { 3, 0x98dc, { 0, 0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, \ 1923 { 6, 0x989c, { 0, 0, 0xf0000000, 0xf0000000, 0xf0000000 } }, \ 1924 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1925 { 6, 0x989c, { 0, 0, 0x03000000, 0x03000000, 0x03000000 } }, \ 1926 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1927 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1928 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1929 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1930 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1931 { 6, 0x989c, { 0, 0, 0x40400000, 0x40400000, 0x40400000 } }, \ 1932 { 6, 0x989c, { 0, 0, 0x65050000, 0x65050000, 0x65050000 } }, \ 1933 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1934 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1935 { 6, 0x989c, { 0, 0, 0x00420000, 0x00420000, 0x00420000 } }, \ 1936 { 6, 0x989c, { 0, 0, 0x00b50000, 0x00b50000, 0x00b50000 } }, \ 1937 { 6, 0x989c, { 0, 0, 0x00030000, 0x00030000, 0x00030000 } }, \ 1938 { 6, 0x989c, { 0, 0, 0x00f70000, 0x00f70000, 0x00f70000 } }, \ 1939 { 6, 0x989c, { 0, 0, 0x009d0000, 0x009d0000, 0x009d0000 } }, \ 1940 { 6, 0x989c, { 0, 0, 0x00220000, 0x00220000, 0x00220000 } }, \ 1941 { 6, 0x989c, { 0, 0, 0x04220000, 0x04220000, 0x04220000 } }, \ 1942 { 6, 0x989c, { 0, 0, 0x00230018, 0x00230018, 0x00230018 } }, \ 1943 { 6, 0x989c, { 0, 0, 0x00280050, 0x00280050, 0x00280050 } }, \ 1944 { 6, 0x989c, { 0, 0, 0x005000c3, 0x005000c3, 0x005000c3 } }, \ 1945 { 6, 0x989c, { 0, 0, 0x0004007f, 0x0004007f, 0x0004007f } }, \ 1946 { 6, 0x989c, { 0, 0, 0x00000458, 0x00000458, 0x00000458 } }, \ 1947 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \ 1948 { 6, 0x989c, { 0, 0, 0x0000c000, 0x0000c000, 0x0000c000 } }, \ 1949 { 6, 0x98d8, { 0, 0, 0x00400230, 0x00400230, 0x00400230 } }, \ 1950 { 7, 0x989c, { 0, 0, 0x00006400, 0x00006400, 0x00006400 } }, \ 1951 { 7, 0x989c, { 0, 0, 0x00000800, 0x00000800, 0x00000800 } }, \ 1952 { 7, 0x98cc, { 0, 0, 0x0000000e, 0x0000000e, 0x0000000e } }, \ 1953 } 1954 1955 #define AR5K_AR2425_INI_RF { \ 1956 { 1, 0x98d4, { 0, 0, 0, 0x00000020, 0x00000020 } }, \ 1957 { 2, 0x98d0, { 0, 0, 0, 0x02001408, 0x02001408 } }, \ 1958 { 3, 0x98dc, { 0, 0, 0, 0x00e020c0, 0x00e020c0 } }, \ 1959 { 6, 0x989c, { 0, 0, 0, 0x10000000, 0x10000000 } }, \ 1960 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1961 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1962 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1963 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1964 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1965 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1966 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1967 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1968 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1969 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1970 { 6, 0x989c, { 0, 0, 0, 0x002a0000, 0x002a0000 } }, \ 1971 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1972 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1973 { 6, 0x989c, { 0, 0, 0, 0x00100000, 0x00100000 } }, \ 1974 { 6, 0x989c, { 0, 0, 0, 0x00020000, 0x00020000 } }, \ 1975 { 6, 0x989c, { 0, 0, 0, 0x00730000, 0x00730000 } }, \ 1976 { 6, 0x989c, { 0, 0, 0, 0x00f80000, 0x00f80000 } }, \ 1977 { 6, 0x989c, { 0, 0, 0, 0x00e70000, 0x00e70000 } }, \ 1978 { 6, 0x989c, { 0, 0, 0, 0x00140000, 0x00140000 } }, \ 1979 { 6, 0x989c, { 0, 0, 0, 0x00910040, 0x00910040 } }, \ 1980 { 6, 0x989c, { 0, 0, 0, 0x0007001a, 0x0007001a } }, \ 1981 { 6, 0x989c, { 0, 0, 0, 0x00410000, 0x00410000 } }, \ 1982 { 6, 0x989c, { 0, 0, 0, 0x00810060, 0x00810060 } }, \ 1983 { 6, 0x989c, { 0, 0, 0, 0x00020803, 0x00020803 } }, \ 1984 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1985 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \ 1986 { 6, 0x989c, { 0, 0, 0, 0x00001660, 0x00001660 } }, \ 1987 { 6, 0x989c, { 0, 0, 0, 0x00001688, 0x00001688 } }, \ 1988 { 6, 0x98c4, { 0, 0, 0, 0x00000001, 0x00000001 } }, \ 1989 { 7, 0x989c, { 0, 0, 0, 0x00006400, 0x00006400 } }, \ 1990 { 7, 0x989c, { 0, 0, 0, 0x00000800, 0x00000800 } }, \ 1991 { 7, 0x98cc, { 0, 0, 0, 0x0000000e, 0x0000000e } } \ 1992 } 1993 1994 struct ar5k_ini_rfgain { 1995 u_int16_t rfg_register; 1996 u_int32_t rfg_value[2]; 1997 1998 #define AR5K_INI_RFGAIN_5GHZ 0 1999 #define AR5K_INI_RFGAIN_2GHZ 1 2000 #define AR5K_INI_RFGAIN(_n) (0x9a00 + ((_n) << 2)) 2001 }; 2002 2003 #define AR5K_AR5111_INI_RFGAIN { \ 2004 { AR5K_INI_RFGAIN(0), { 0x000001a9, 0x00000000 } }, \ 2005 { AR5K_INI_RFGAIN(1), { 0x000001e9, 0x00000040 } }, \ 2006 { AR5K_INI_RFGAIN(2), { 0x00000029, 0x00000080 } }, \ 2007 { AR5K_INI_RFGAIN(3), { 0x00000069, 0x00000150 } }, \ 2008 { AR5K_INI_RFGAIN(4), { 0x00000199, 0x00000190 } }, \ 2009 { AR5K_INI_RFGAIN(5), { 0x000001d9, 0x000001d0 } }, \ 2010 { AR5K_INI_RFGAIN(6), { 0x00000019, 0x00000010 } }, \ 2011 { AR5K_INI_RFGAIN(7), { 0x00000059, 0x00000044 } }, \ 2012 { AR5K_INI_RFGAIN(8), { 0x00000099, 0x00000084 } }, \ 2013 { AR5K_INI_RFGAIN(9), { 0x000001a5, 0x00000148 } }, \ 2014 { AR5K_INI_RFGAIN(10), { 0x000001e5, 0x00000188 } }, \ 2015 { AR5K_INI_RFGAIN(11), { 0x00000025, 0x000001c8 } }, \ 2016 { AR5K_INI_RFGAIN(12), { 0x000001c8, 0x00000014 } }, \ 2017 { AR5K_INI_RFGAIN(13), { 0x00000008, 0x00000042 } }, \ 2018 { AR5K_INI_RFGAIN(14), { 0x00000048, 0x00000082 } }, \ 2019 { AR5K_INI_RFGAIN(15), { 0x00000088, 0x00000178 } }, \ 2020 { AR5K_INI_RFGAIN(16), { 0x00000198, 0x000001b8 } }, \ 2021 { AR5K_INI_RFGAIN(17), { 0x000001d8, 0x000001f8 } }, \ 2022 { AR5K_INI_RFGAIN(18), { 0x00000018, 0x00000012 } }, \ 2023 { AR5K_INI_RFGAIN(19), { 0x00000058, 0x00000052 } }, \ 2024 { AR5K_INI_RFGAIN(20), { 0x00000098, 0x00000092 } }, \ 2025 { AR5K_INI_RFGAIN(21), { 0x000001a4, 0x0000017c } }, \ 2026 { AR5K_INI_RFGAIN(22), { 0x000001e4, 0x000001bc } }, \ 2027 { AR5K_INI_RFGAIN(23), { 0x00000024, 0x000001fc } }, \ 2028 { AR5K_INI_RFGAIN(24), { 0x00000064, 0x0000000a } }, \ 2029 { AR5K_INI_RFGAIN(25), { 0x000000a4, 0x0000004a } }, \ 2030 { AR5K_INI_RFGAIN(26), { 0x000000e4, 0x0000008a } }, \ 2031 { AR5K_INI_RFGAIN(27), { 0x0000010a, 0x0000015a } }, \ 2032 { AR5K_INI_RFGAIN(28), { 0x0000014a, 0x0000019a } }, \ 2033 { AR5K_INI_RFGAIN(29), { 0x0000018a, 0x000001da } }, \ 2034 { AR5K_INI_RFGAIN(30), { 0x000001ca, 0x0000000e } }, \ 2035 { AR5K_INI_RFGAIN(31), { 0x0000000a, 0x0000004e } }, \ 2036 { AR5K_INI_RFGAIN(32), { 0x0000004a, 0x0000008e } }, \ 2037 { AR5K_INI_RFGAIN(33), { 0x0000008a, 0x0000015e } }, \ 2038 { AR5K_INI_RFGAIN(34), { 0x000001ba, 0x0000019e } }, \ 2039 { AR5K_INI_RFGAIN(35), { 0x000001fa, 0x000001de } }, \ 2040 { AR5K_INI_RFGAIN(36), { 0x0000003a, 0x00000009 } }, \ 2041 { AR5K_INI_RFGAIN(37), { 0x0000007a, 0x00000049 } }, \ 2042 { AR5K_INI_RFGAIN(38), { 0x00000186, 0x00000089 } }, \ 2043 { AR5K_INI_RFGAIN(39), { 0x000001c6, 0x00000179 } }, \ 2044 { AR5K_INI_RFGAIN(40), { 0x00000006, 0x000001b9 } }, \ 2045 { AR5K_INI_RFGAIN(41), { 0x00000046, 0x000001f9 } }, \ 2046 { AR5K_INI_RFGAIN(42), { 0x00000086, 0x00000039 } }, \ 2047 { AR5K_INI_RFGAIN(43), { 0x000000c6, 0x00000079 } }, \ 2048 { AR5K_INI_RFGAIN(44), { 0x000000c6, 0x000000b9 } }, \ 2049 { AR5K_INI_RFGAIN(45), { 0x000000c6, 0x000001bd } }, \ 2050 { AR5K_INI_RFGAIN(46), { 0x000000c6, 0x000001fd } }, \ 2051 { AR5K_INI_RFGAIN(47), { 0x000000c6, 0x0000003d } }, \ 2052 { AR5K_INI_RFGAIN(48), { 0x000000c6, 0x0000007d } }, \ 2053 { AR5K_INI_RFGAIN(49), { 0x000000c6, 0x000000bd } }, \ 2054 { AR5K_INI_RFGAIN(50), { 0x000000c6, 0x000000fd } }, \ 2055 { AR5K_INI_RFGAIN(51), { 0x000000c6, 0x000000fd } }, \ 2056 { AR5K_INI_RFGAIN(52), { 0x000000c6, 0x000000fd } }, \ 2057 { AR5K_INI_RFGAIN(53), { 0x000000c6, 0x000000fd } }, \ 2058 { AR5K_INI_RFGAIN(54), { 0x000000c6, 0x000000fd } }, \ 2059 { AR5K_INI_RFGAIN(55), { 0x000000c6, 0x000000fd } }, \ 2060 { AR5K_INI_RFGAIN(56), { 0x000000c6, 0x000000fd } }, \ 2061 { AR5K_INI_RFGAIN(57), { 0x000000c6, 0x000000fd } }, \ 2062 { AR5K_INI_RFGAIN(58), { 0x000000c6, 0x000000fd } }, \ 2063 { AR5K_INI_RFGAIN(59), { 0x000000c6, 0x000000fd } }, \ 2064 { AR5K_INI_RFGAIN(60), { 0x000000c6, 0x000000fd } }, \ 2065 { AR5K_INI_RFGAIN(61), { 0x000000c6, 0x000000fd } }, \ 2066 { AR5K_INI_RFGAIN(62), { 0x000000c6, 0x000000fd } }, \ 2067 { AR5K_INI_RFGAIN(63), { 0x000000c6, 0x000000fd } } \ 2068 } 2069 2070 #define AR5K_AR5112_INI_RFGAIN { \ 2071 { AR5K_INI_RFGAIN(0), { 0x00000007, 0x00000007 } }, \ 2072 { AR5K_INI_RFGAIN(1), { 0x00000047, 0x00000047 } }, \ 2073 { AR5K_INI_RFGAIN(2), { 0x00000087, 0x00000087 } }, \ 2074 { AR5K_INI_RFGAIN(3), { 0x000001a0, 0x000001a0 } }, \ 2075 { AR5K_INI_RFGAIN(4), { 0x000001e0, 0x000001e0 } }, \ 2076 { AR5K_INI_RFGAIN(5), { 0x00000020, 0x00000020 } }, \ 2077 { AR5K_INI_RFGAIN(6), { 0x00000060, 0x00000060 } }, \ 2078 { AR5K_INI_RFGAIN(7), { 0x000001a1, 0x000001a1 } }, \ 2079 { AR5K_INI_RFGAIN(8), { 0x000001e1, 0x000001e1 } }, \ 2080 { AR5K_INI_RFGAIN(9), { 0x00000021, 0x00000021 } }, \ 2081 { AR5K_INI_RFGAIN(10), { 0x00000061, 0x00000061 } }, \ 2082 { AR5K_INI_RFGAIN(11), { 0x00000162, 0x00000162 } }, \ 2083 { AR5K_INI_RFGAIN(12), { 0x000001a2, 0x000001a2 } }, \ 2084 { AR5K_INI_RFGAIN(13), { 0x000001e2, 0x000001e2 } }, \ 2085 { AR5K_INI_RFGAIN(14), { 0x00000022, 0x00000022 } }, \ 2086 { AR5K_INI_RFGAIN(15), { 0x00000062, 0x00000062 } }, \ 2087 { AR5K_INI_RFGAIN(16), { 0x00000163, 0x00000163 } }, \ 2088 { AR5K_INI_RFGAIN(17), { 0x000001a3, 0x000001a3 } }, \ 2089 { AR5K_INI_RFGAIN(18), { 0x000001e3, 0x000001e3 } }, \ 2090 { AR5K_INI_RFGAIN(19), { 0x00000023, 0x00000023 } }, \ 2091 { AR5K_INI_RFGAIN(20), { 0x00000063, 0x00000063 } }, \ 2092 { AR5K_INI_RFGAIN(21), { 0x00000184, 0x00000184 } }, \ 2093 { AR5K_INI_RFGAIN(22), { 0x000001c4, 0x000001c4 } }, \ 2094 { AR5K_INI_RFGAIN(23), { 0x00000004, 0x00000004 } }, \ 2095 { AR5K_INI_RFGAIN(24), { 0x000001ea, 0x0000000b } }, \ 2096 { AR5K_INI_RFGAIN(25), { 0x0000002a, 0x0000004b } }, \ 2097 { AR5K_INI_RFGAIN(26), { 0x0000006a, 0x0000008b } }, \ 2098 { AR5K_INI_RFGAIN(27), { 0x000000aa, 0x000001ac } }, \ 2099 { AR5K_INI_RFGAIN(28), { 0x000001ab, 0x000001ec } }, \ 2100 { AR5K_INI_RFGAIN(29), { 0x000001eb, 0x0000002c } }, \ 2101 { AR5K_INI_RFGAIN(30), { 0x0000002b, 0x00000012 } }, \ 2102 { AR5K_INI_RFGAIN(31), { 0x0000006b, 0x00000052 } }, \ 2103 { AR5K_INI_RFGAIN(32), { 0x000000ab, 0x00000092 } }, \ 2104 { AR5K_INI_RFGAIN(33), { 0x000001ac, 0x00000193 } }, \ 2105 { AR5K_INI_RFGAIN(34), { 0x000001ec, 0x000001d3 } }, \ 2106 { AR5K_INI_RFGAIN(35), { 0x0000002c, 0x00000013 } }, \ 2107 { AR5K_INI_RFGAIN(36), { 0x0000003a, 0x00000053 } }, \ 2108 { AR5K_INI_RFGAIN(37), { 0x0000007a, 0x00000093 } }, \ 2109 { AR5K_INI_RFGAIN(38), { 0x000000ba, 0x00000194 } }, \ 2110 { AR5K_INI_RFGAIN(39), { 0x000001bb, 0x000001d4 } }, \ 2111 { AR5K_INI_RFGAIN(40), { 0x000001fb, 0x00000014 } }, \ 2112 { AR5K_INI_RFGAIN(41), { 0x0000003b, 0x0000003a } }, \ 2113 { AR5K_INI_RFGAIN(42), { 0x0000007b, 0x0000007a } }, \ 2114 { AR5K_INI_RFGAIN(43), { 0x000000bb, 0x000000ba } }, \ 2115 { AR5K_INI_RFGAIN(44), { 0x000001bc, 0x000001bb } }, \ 2116 { AR5K_INI_RFGAIN(45), { 0x000001fc, 0x000001fb } }, \ 2117 { AR5K_INI_RFGAIN(46), { 0x0000003c, 0x0000003b } }, \ 2118 { AR5K_INI_RFGAIN(47), { 0x0000007c, 0x0000007b } }, \ 2119 { AR5K_INI_RFGAIN(48), { 0x000000bc, 0x000000bb } }, \ 2120 { AR5K_INI_RFGAIN(49), { 0x000000fc, 0x000001bc } }, \ 2121 { AR5K_INI_RFGAIN(50), { 0x000000fc, 0x000001fc } }, \ 2122 { AR5K_INI_RFGAIN(51), { 0x000000fc, 0x0000003c } }, \ 2123 { AR5K_INI_RFGAIN(52), { 0x000000fc, 0x0000007c } }, \ 2124 { AR5K_INI_RFGAIN(53), { 0x000000fc, 0x000000bc } }, \ 2125 { AR5K_INI_RFGAIN(54), { 0x000000fc, 0x000000fc } }, \ 2126 { AR5K_INI_RFGAIN(55), { 0x000000fc, 0x000000fc } }, \ 2127 { AR5K_INI_RFGAIN(56), { 0x000000fc, 0x000000fc } }, \ 2128 { AR5K_INI_RFGAIN(57), { 0x000000fc, 0x000000fc } }, \ 2129 { AR5K_INI_RFGAIN(58), { 0x000000fc, 0x000000fc } }, \ 2130 { AR5K_INI_RFGAIN(59), { 0x000000fc, 0x000000fc } }, \ 2131 { AR5K_INI_RFGAIN(60), { 0x000000fc, 0x000000fc } }, \ 2132 { AR5K_INI_RFGAIN(61), { 0x000000fc, 0x000000fc } }, \ 2133 { AR5K_INI_RFGAIN(62), { 0x000000fc, 0x000000fc } }, \ 2134 { AR5K_INI_RFGAIN(63), { 0x000000fc, 0x000000fc } }, \ 2135 } 2136 2137 #define AR5K_AR5413_INI_RFGAIN { \ 2138 { AR5K_INI_RFGAIN(0), { 0x00000000, 0x00000000 } }, \ 2139 { AR5K_INI_RFGAIN(1), { 0x00000040, 0x00000040 } }, \ 2140 { AR5K_INI_RFGAIN(2), { 0x00000080, 0x00000080 } }, \ 2141 { AR5K_INI_RFGAIN(3), { 0x000001a1, 0x00000161 } }, \ 2142 { AR5K_INI_RFGAIN(4), { 0x000001e1, 0x000001a1 } }, \ 2143 { AR5K_INI_RFGAIN(5), { 0x00000021, 0x000001e1 } }, \ 2144 { AR5K_INI_RFGAIN(6), { 0x00000061, 0x00000021 } }, \ 2145 { AR5K_INI_RFGAIN(7), { 0x00000188, 0x00000061 } }, \ 2146 { AR5K_INI_RFGAIN(8), { 0x000001c8, 0x00000188 } }, \ 2147 { AR5K_INI_RFGAIN(9), { 0x00000008, 0x000001c8 } }, \ 2148 { AR5K_INI_RFGAIN(10), { 0x00000048, 0x00000008 } }, \ 2149 { AR5K_INI_RFGAIN(11), { 0x00000088, 0x00000048 } }, \ 2150 { AR5K_INI_RFGAIN(12), { 0x000001a9, 0x00000088 } }, \ 2151 { AR5K_INI_RFGAIN(13), { 0x000001e9, 0x00000169 } }, \ 2152 { AR5K_INI_RFGAIN(14), { 0x00000029, 0x000001a9 } }, \ 2153 { AR5K_INI_RFGAIN(15), { 0x00000069, 0x000001e9 } }, \ 2154 { AR5K_INI_RFGAIN(16), { 0x000001d0, 0x00000029 } }, \ 2155 { AR5K_INI_RFGAIN(17), { 0x00000010, 0x00000069 } }, \ 2156 { AR5K_INI_RFGAIN(18), { 0x00000050, 0x00000190 } }, \ 2157 { AR5K_INI_RFGAIN(19), { 0x00000090, 0x000001d0 } }, \ 2158 { AR5K_INI_RFGAIN(20), { 0x000001b1, 0x00000010 } }, \ 2159 { AR5K_INI_RFGAIN(21), { 0x000001f1, 0x00000050 } }, \ 2160 { AR5K_INI_RFGAIN(22), { 0x00000031, 0x00000090 } }, \ 2161 { AR5K_INI_RFGAIN(23), { 0x00000071, 0x00000171 } }, \ 2162 { AR5K_INI_RFGAIN(24), { 0x000001b8, 0x000001b1 } }, \ 2163 { AR5K_INI_RFGAIN(25), { 0x000001f8, 0x000001f1 } }, \ 2164 { AR5K_INI_RFGAIN(26), { 0x00000038, 0x00000031 } }, \ 2165 { AR5K_INI_RFGAIN(27), { 0x00000078, 0x00000071 } }, \ 2166 { AR5K_INI_RFGAIN(28), { 0x00000199, 0x00000198 } }, \ 2167 { AR5K_INI_RFGAIN(29), { 0x000001d9, 0x000001d8 } }, \ 2168 { AR5K_INI_RFGAIN(30), { 0x00000019, 0x00000018 } }, \ 2169 { AR5K_INI_RFGAIN(31), { 0x00000059, 0x00000058 } }, \ 2170 { AR5K_INI_RFGAIN(32), { 0x00000099, 0x00000098 } }, \ 2171 { AR5K_INI_RFGAIN(33), { 0x000000d9, 0x00000179 } }, \ 2172 { AR5K_INI_RFGAIN(34), { 0x000000f9, 0x000001b9 } }, \ 2173 { AR5K_INI_RFGAIN(35), { 0x000000f9, 0x000001f9 } }, \ 2174 { AR5K_INI_RFGAIN(36), { 0x000000f9, 0x00000039 } }, \ 2175 { AR5K_INI_RFGAIN(37), { 0x000000f9, 0x00000079 } }, \ 2176 { AR5K_INI_RFGAIN(38), { 0x000000f9, 0x000000b9 } }, \ 2177 { AR5K_INI_RFGAIN(39), { 0x000000f9, 0x000000f9 } }, \ 2178 { AR5K_INI_RFGAIN(40), { 0x000000f9, 0x000000f9 } }, \ 2179 { AR5K_INI_RFGAIN(41), { 0x000000f9, 0x000000f9 } }, \ 2180 { AR5K_INI_RFGAIN(42), { 0x000000f9, 0x000000f9 } }, \ 2181 { AR5K_INI_RFGAIN(43), { 0x000000f9, 0x000000f9 } }, \ 2182 { AR5K_INI_RFGAIN(44), { 0x000000f9, 0x000000f9 } }, \ 2183 { AR5K_INI_RFGAIN(45), { 0x000000f9, 0x000000f9 } }, \ 2184 { AR5K_INI_RFGAIN(46), { 0x000000f9, 0x000000f9 } }, \ 2185 { AR5K_INI_RFGAIN(47), { 0x000000f9, 0x000000f9 } }, \ 2186 { AR5K_INI_RFGAIN(48), { 0x000000f9, 0x000000f9 } }, \ 2187 { AR5K_INI_RFGAIN(49), { 0x000000f9, 0x000000f9 } }, \ 2188 { AR5K_INI_RFGAIN(50), { 0x000000f9, 0x000000f9 } }, \ 2189 { AR5K_INI_RFGAIN(51), { 0x000000f9, 0x000000f9 } }, \ 2190 { AR5K_INI_RFGAIN(52), { 0x000000f9, 0x000000f9 } }, \ 2191 { AR5K_INI_RFGAIN(53), { 0x000000f9, 0x000000f9 } }, \ 2192 { AR5K_INI_RFGAIN(54), { 0x000000f9, 0x000000f9 } }, \ 2193 { AR5K_INI_RFGAIN(55), { 0x000000f9, 0x000000f9 } }, \ 2194 { AR5K_INI_RFGAIN(56), { 0x000000f9, 0x000000f9 } }, \ 2195 { AR5K_INI_RFGAIN(57), { 0x000000f9, 0x000000f9 } }, \ 2196 { AR5K_INI_RFGAIN(58), { 0x000000f9, 0x000000f9 } }, \ 2197 { AR5K_INI_RFGAIN(59), { 0x000000f9, 0x000000f9 } }, \ 2198 { AR5K_INI_RFGAIN(60), { 0x000000f9, 0x000000f9 } }, \ 2199 { AR5K_INI_RFGAIN(61), { 0x000000f9, 0x000000f9 } }, \ 2200 { AR5K_INI_RFGAIN(62), { 0x000000f9, 0x000000f9 } }, \ 2201 { AR5K_INI_RFGAIN(63), { 0x000000f9, 0x000000f9 } } \ 2202 } 2203 2204 #define AR5K_AR2413_INI_RFGAIN { \ 2205 { AR5K_INI_RFGAIN(0), { 0, 0x00000000 } }, \ 2206 { AR5K_INI_RFGAIN(1), { 0, 0x00000040 } }, \ 2207 { AR5K_INI_RFGAIN(2), { 0, 0x00000080 } }, \ 2208 { AR5K_INI_RFGAIN(3), { 0, 0x00000181 } }, \ 2209 { AR5K_INI_RFGAIN(4), { 0, 0x000001c1 } }, \ 2210 { AR5K_INI_RFGAIN(5), { 0, 0x00000001 } }, \ 2211 { AR5K_INI_RFGAIN(6), { 0, 0x00000041 } }, \ 2212 { AR5K_INI_RFGAIN(7), { 0, 0x00000081 } }, \ 2213 { AR5K_INI_RFGAIN(8), { 0, 0x00000168 } }, \ 2214 { AR5K_INI_RFGAIN(9), { 0, 0x000001a8 } }, \ 2215 { AR5K_INI_RFGAIN(10), { 0, 0x000001e8 } }, \ 2216 { AR5K_INI_RFGAIN(11), { 0, 0x00000028 } }, \ 2217 { AR5K_INI_RFGAIN(12), { 0, 0x00000068 } }, \ 2218 { AR5K_INI_RFGAIN(13), { 0, 0x00000189 } }, \ 2219 { AR5K_INI_RFGAIN(14), { 0, 0x000001c9 } }, \ 2220 { AR5K_INI_RFGAIN(15), { 0, 0x00000009 } }, \ 2221 { AR5K_INI_RFGAIN(16), { 0, 0x00000049 } }, \ 2222 { AR5K_INI_RFGAIN(17), { 0, 0x00000089 } }, \ 2223 { AR5K_INI_RFGAIN(18), { 0, 0x00000190 } }, \ 2224 { AR5K_INI_RFGAIN(19), { 0, 0x000001d0 } }, \ 2225 { AR5K_INI_RFGAIN(20), { 0, 0x00000010 } }, \ 2226 { AR5K_INI_RFGAIN(21), { 0, 0x00000050 } }, \ 2227 { AR5K_INI_RFGAIN(22), { 0, 0x00000090 } }, \ 2228 { AR5K_INI_RFGAIN(23), { 0, 0x00000191 } }, \ 2229 { AR5K_INI_RFGAIN(24), { 0, 0x000001d1 } }, \ 2230 { AR5K_INI_RFGAIN(25), { 0, 0x00000011 } }, \ 2231 { AR5K_INI_RFGAIN(26), { 0, 0x00000051 } }, \ 2232 { AR5K_INI_RFGAIN(27), { 0, 0x00000091 } }, \ 2233 { AR5K_INI_RFGAIN(28), { 0, 0x00000178 } }, \ 2234 { AR5K_INI_RFGAIN(29), { 0, 0x000001b8 } }, \ 2235 { AR5K_INI_RFGAIN(30), { 0, 0x000001f8 } }, \ 2236 { AR5K_INI_RFGAIN(31), { 0, 0x00000038 } }, \ 2237 { AR5K_INI_RFGAIN(32), { 0, 0x00000078 } }, \ 2238 { AR5K_INI_RFGAIN(33), { 0, 0x00000199 } }, \ 2239 { AR5K_INI_RFGAIN(34), { 0, 0x000001d9 } }, \ 2240 { AR5K_INI_RFGAIN(35), { 0, 0x00000019 } }, \ 2241 { AR5K_INI_RFGAIN(36), { 0, 0x00000059 } }, \ 2242 { AR5K_INI_RFGAIN(37), { 0, 0x00000099 } }, \ 2243 { AR5K_INI_RFGAIN(38), { 0, 0x000000d9 } }, \ 2244 { AR5K_INI_RFGAIN(39), { 0, 0x000000f9 } }, \ 2245 { AR5K_INI_RFGAIN(40), { 0, 0x000000f9 } }, \ 2246 { AR5K_INI_RFGAIN(41), { 0, 0x000000f9 } }, \ 2247 { AR5K_INI_RFGAIN(42), { 0, 0x000000f9 } }, \ 2248 { AR5K_INI_RFGAIN(43), { 0, 0x000000f9 } }, \ 2249 { AR5K_INI_RFGAIN(44), { 0, 0x000000f9 } }, \ 2250 { AR5K_INI_RFGAIN(45), { 0, 0x000000f9 } }, \ 2251 { AR5K_INI_RFGAIN(46), { 0, 0x000000f9 } }, \ 2252 { AR5K_INI_RFGAIN(47), { 0, 0x000000f9 } }, \ 2253 { AR5K_INI_RFGAIN(48), { 0, 0x000000f9 } }, \ 2254 { AR5K_INI_RFGAIN(49), { 0, 0x000000f9 } }, \ 2255 { AR5K_INI_RFGAIN(50), { 0, 0x000000f9 } }, \ 2256 { AR5K_INI_RFGAIN(51), { 0, 0x000000f9 } }, \ 2257 { AR5K_INI_RFGAIN(52), { 0, 0x000000f9 } }, \ 2258 { AR5K_INI_RFGAIN(53), { 0, 0x000000f9 } }, \ 2259 { AR5K_INI_RFGAIN(54), { 0, 0x000000f9 } }, \ 2260 { AR5K_INI_RFGAIN(55), { 0, 0x000000f9 } }, \ 2261 { AR5K_INI_RFGAIN(56), { 0, 0x000000f9 } }, \ 2262 { AR5K_INI_RFGAIN(57), { 0, 0x000000f9 } }, \ 2263 { AR5K_INI_RFGAIN(58), { 0, 0x000000f9 } }, \ 2264 { AR5K_INI_RFGAIN(59), { 0, 0x000000f9 } }, \ 2265 { AR5K_INI_RFGAIN(60), { 0, 0x000000f9 } }, \ 2266 { AR5K_INI_RFGAIN(61), { 0, 0x000000f9 } }, \ 2267 { AR5K_INI_RFGAIN(62), { 0, 0x000000f9 } }, \ 2268 { AR5K_INI_RFGAIN(63), { 0, 0x000000f9 } }, \ 2269 } 2270 2271 /* 2272 * Prototypes 2273 */ 2274 2275 __BEGIN_DECLS 2276 2277 const char *ath_hal_probe(u_int16_t, u_int16_t); 2278 2279 struct ath_hal *ath_hal_attach(u_int16_t, void *, bus_space_tag_t, 2280 bus_space_handle_t, u_int, HAL_STATUS *); 2281 2282 u_int16_t ath_hal_computetxtime(struct ath_hal *, 2283 const HAL_RATE_TABLE *, u_int32_t, u_int16_t, HAL_BOOL); 2284 2285 HAL_BOOL ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *, 2286 u_int, u_int *, u_int16_t, HAL_BOOL, HAL_BOOL); 2287 2288 const char *ar5k_printver(enum ar5k_srev_type, u_int32_t); 2289 void ar5k_radar_alert(struct ath_hal *); 2290 ieee80211_regdomain_t ar5k_regdomain_to_ieee(u_int16_t); 2291 u_int16_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t); 2292 u_int16_t ar5k_get_regdomain(struct ath_hal *); 2293 2294 u_int32_t ar5k_bitswap(u_int32_t, u_int); 2295 u_int ar5k_clocktoh(u_int, HAL_BOOL); 2296 u_int ar5k_htoclock(u_int, HAL_BOOL); 2297 void ar5k_rt_copy(HAL_RATE_TABLE *, const HAL_RATE_TABLE *); 2298 2299 HAL_BOOL ar5k_register_timeout(struct ath_hal *, u_int32_t, 2300 u_int32_t, u_int32_t, HAL_BOOL); 2301 2302 int ar5k_eeprom_init(struct ath_hal *); 2303 int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *); 2304 HAL_BOOL ar5k_eeprom_regulation_domain(struct ath_hal *, 2305 HAL_BOOL, ieee80211_regdomain_t *); 2306 2307 HAL_BOOL ar5k_channel(struct ath_hal *, HAL_CHANNEL *); 2308 HAL_BOOL ar5k_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int); 2309 u_int32_t ar5k_rfregs_gainf_corr(struct ath_hal *); 2310 HAL_BOOL ar5k_rfregs_gain_readback(struct ath_hal *); 2311 int32_t ar5k_rfregs_gain_adjust(struct ath_hal *); 2312 HAL_BOOL ar5k_rfgain(struct ath_hal *, u_int); 2313 2314 void ar5k_txpower_table(struct ath_hal *, HAL_CHANNEL *, 2315 int16_t); 2316 2317 void ar5k_write_ini(struct ath_hal *, 2318 const struct ar5k_ini *, size_t, HAL_BOOL); 2319 void ar5k_write_mode(struct ath_hal *, 2320 const struct ar5k_mode *, size_t, u_int); 2321 2322 __END_DECLS 2323 2324 #endif /* _AR5K_H */ 2325