1 /* $OpenBSD: ar9003reg.h,v 1.7 2011/01/01 13:44:42 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * MAC registers. 22 */ 23 #define AR_ISR_S2_S 0x00d0 24 #define AR_ISR_S3_S 0x00d4 25 #define AR_ISR_S4_S 0x00d8 26 #define AR_ISR_S5_S 0x00dc 27 #define AR_GPIO_IN_OUT 0x4048 28 #define AR_GPIO_OE_OUT 0x4050 29 #define AR_GPIO_INTR_POL 0x4058 30 #define AR_GPIO_INPUT_EN_VAL 0x405c 31 #define AR_GPIO_INPUT_MUX1 0x4060 32 #define AR_GPIO_INPUT_MUX2 0x4064 33 #define AR_GPIO_OUTPUT_MUX(i) (0x4068 + (i) * 4) 34 #define AR_INPUT_STATE 0x4074 35 #define AR_EEPROM_STATUS_DATA 0x4084 36 #define AR_OBS 0x4088 37 #define AR_GPIO_PDPU 0x4090 38 #define AR_PCIE_MSI 0x40a4 39 #define AR_ENT_OTP 0x40d8 40 41 /* Bits for AR_ENT_OTP. */ 42 #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 43 #define AR_ENT_OTP_MPSD 0x00800000 44 45 /* 46 * PHY registers. 47 */ 48 #define AR_PHY_TIMING1 0x09800 49 #define AR_PHY_TIMING2 0x09804 50 #define AR_PHY_TIMING3 0x09808 51 #define AR_PHY_TIMING4 0x0980c 52 #define AR_PHY_TIMING5 0x09810 53 #define AR_PHY_TIMING6 0x09814 54 #define AR_PHY_TIMING11 0x09818 55 #define AR_PHY_SPUR_REG 0x0981c 56 #define AR_PHY_FIND_SIG_LOW 0x09820 57 #define AR_PHY_SFCORR 0x09824 58 #define AR_PHY_SFCORR_LOW 0x09828 59 #define AR_PHY_SFCORR_EXT 0x0982c 60 #define AR_PHY_EXT_CCA(i) (0x09830 + (i) * 0x1000) 61 #define AR_PHY_RADAR_0 0x09834 62 #define AR_PHY_RADAR_1 0x09838 63 #define AR_PHY_RADAR_EXT 0x0983c 64 #define AR_PHY_MULTICHAIN_CTRL 0x09880 65 #define AR_PHY_PERCHAIN_CSD 0x09884 66 #define AR_PHY_TX_CRC 0x098a0 67 #define AR_PHY_TST_DAC_CONST 0x098a4 68 #define AR_PHY_SPUR_REPORT_0 0x098a8 69 #define AR_PHY_TX_IQCAL_CONTROL_3 0x098b0 70 #define AR_PHY_IQ_ADC_MEAS_0_B(i) (0x098c0 + (i) * 0x1000) 71 #define AR_PHY_IQ_ADC_MEAS_1_B(i) (0x098c4 + (i) * 0x1000) 72 #define AR_PHY_IQ_ADC_MEAS_2_B(i) (0x098c8 + (i) * 0x1000) 73 #define AR_PHY_IQ_ADC_MEAS_3_B(i) (0x098cc + (i) * 0x1000) 74 #define AR_PHY_TX_PHASE_RAMP_0 0x098d0 75 #define AR_PHY_ADC_DC_GAIN_CORR(i) (0x098d4 + (i) * 0x1000) 76 #define AR_PHY_RX_IQCAL_CORR_B(i) (0x098dc + (i) * 0x1000) 77 #define AR_PHY_PAPRD_AM2AM 0x098e4 78 #define AR_PHY_PAPRD_AM2PM 0x098e8 79 #define AR_PHY_PAPRD_HT40 0x098ec 80 #define AR_PHY_PAPRD_CTRL0_B(i) (0x098f0 + (i) * 0x1000) 81 #define AR_PHY_PAPRD_CTRL1_B(i) (0x098f4 + (i) * 0x1000) 82 #define AR_PHY_PA_GAIN123_B(i) (0x098f8 + (i) * 0x1000) 83 #define AR_PHY_PAPRD_PRE_POST_SCALE_B0(i) \ 84 (0x09900 + (i) * 4) 85 #define AR_PHY_PAPRD_MEM_TAB_B(i, j) (0x09920 + (i) * 0x1000 + (j) * 4) 86 #define AR_PHY_CHAN_INFO_TAB(i, j) (0x09b00 + (i) * 0x1000 + (j) * 4) 87 #define AR_PHY_TIMING_3A 0x09c00 88 #define AR_PHY_LDPC_CNTL1 0x09c04 89 #define AR_PHY_LDPC_CNTL2 0x09c08 90 #define AR_PHY_PILOT_SPUR_MASK 0x09c0c 91 #define AR_PHY_CHAN_SPUR_MASK 0x09c10 92 #define AR_PHY_SGI_DELTA 0x09c14 93 #define AR_PHY_ML_CNTL_1 0x09c18 94 #define AR_PHY_ML_CNTL_2 0x09c1c 95 #define AR_PHY_TST_ADC 0x09c20 96 #define AR_PHY_SETTLING 0x09e00 97 #define AR_PHY_RXGAIN(i) (0x09e04 + (i) * 0x1000) 98 #define AR_PHY_GAINS_MINOFF0 0x09e08 99 #define AR_PHY_DESIRED_SZ 0x09e0c 100 #define AR_PHY_FIND_SIG 0x09e10 101 #define AR_PHY_AGC 0x09e14 102 #define AR_PHY_EXT_ATTEN_CTL(i) (0x09e18 + (i) * 0x1000) 103 #define AR_PHY_CCA(i) (0x09e1c + (i) * 0x1000) 104 #define AR_PHY_CCA_CTRL(i) (0x09e20 + (i) * 0x1000) 105 #define AR_PHY_RESTART 0x09e24 106 #define AR_PHY_MC_GAIN_CTRL 0x09e28 107 #define AR_PHY_EXTCHN_PWRTHR1 0x09e2c 108 #define AR_PHY_EXT_CHN_WIN 0x09e30 109 #define AR_PHY_20_40_DET_THR 0x09e34 110 #define AR_PHY_RIFS_SRCH 0x09e38 111 #define AR_PHY_PEAK_DET_CTRL_1 0x09e3c 112 #define AR_PHY_PEAK_DET_CTRL_2 0x09e40 113 #define AR_PHY_RX_GAIN_BOUNDS_1 0x09e44 114 #define AR_PHY_RX_GAIN_BOUNDS_2 0x09e48 115 #define AR_PHY_RSSI(i) (0x09f80 + (i) * 0x1000) 116 #define AR_PHY_SPUR_CCK_REP0 0x09f84 117 #define AR_PHY_CCK_DETECT 0x09fc0 118 #define AR_PHY_DAG_CTRLCCK 0x09fc4 119 #define AR_PHY_IQCORR_CTRL_CCK 0x09fc8 120 #define AR_PHY_CCK_SPUR_MIT 0x09fcc 121 #define AR_PHY_RX_OCGAIN 0x0a000 122 #define AR_PHY_D2_CHIP_ID 0x0a200 123 #define AR_PHY_GEN_CTRL 0x0a204 124 #define AR_PHY_MODE 0x0a208 125 #define AR_PHY_ACTIVE 0x0a20c 126 #define AR_PHY_SPUR_MASK_A 0x0a220 127 #define AR_PHY_SPUR_MASK_B 0x0a224 128 #define AR_PHY_SPECTRAL_SCAN 0x0a228 129 #define AR_PHY_RADAR_BW_FILTER 0x0a22c 130 #define AR_PHY_SEARCH_START_DELAY 0x0a230 131 #define AR_PHY_MAX_RX_LEN 0x0a234 132 #define AR_PHY_FRAME_CTL 0x0a238 133 #define AR_PHY_RFBUS_REQ 0x0a23c 134 #define AR_PHY_RFBUS_GRANT 0x0a240 135 #define AR_PHY_RIFS 0x0a244 136 #define AR_PHY_RX_CLR_DELAY 0x0a250 137 #define AR_PHY_RX_DELAY 0x0a254 138 #define AR_PHY_XPA_TIMING_CTL 0x0a264 139 #define AR_PHY_MISC_PA_CTL 0x0a280 140 #define AR_PHY_SWITCH_CHAIN(i) (0x0a284 + (i) * 0x1000) 141 #define AR_PHY_SWITCH_COM 0x0a288 142 #define AR_PHY_SWITCH_COM_2 0x0a28c 143 #define AR_PHY_RX_CHAINMASK 0x0a2a0 144 #define AR_PHY_CAL_CHAINMASK 0x0a2c0 145 #define AR_PHY_AGC_CONTROL 0x0a2c4 146 #define AR_PHY_CALMODE 0x0a2c8 147 #define AR_PHY_FCAL_1 0x0a2cc 148 #define AR_PHY_FCAL_2_0 0x0a2d0 149 #define AR_PHY_DFT_TONE_CTL_0 0x0a2d4 150 #define AR_PHY_CL_CAL_CTL 0x0a2d8 151 #define AR_PHY_CL_TAB_0 0x0a300 152 #define AR_PHY_SYNTH_CONTROL 0x0a340 153 #define AR_PHY_ADDAC_CLK_SEL 0x0a344 154 #define AR_PHY_PLL_CTL 0x0a348 155 #define AR_PHY_ANALOG_SWAP 0x0a34c 156 #define AR_PHY_ADDAC_PARA_CTL 0x0a350 157 #define AR_PHY_XPA_CFG 0x0a358 158 #define AR_PHY_TEST 0x0a360 159 #define AR_PHY_TEST_CTL_STATUS 0x0a364 160 #define AR_PHY_TSTDAC 0x0a368 161 #define AR_PHY_CHAN_STATUS 0x0a36c 162 #define AR_PHY_CHAN_INFO_MEMORY 0x0a370 163 #define AR_PHY_CHNINFO_NOISEPWR 0x0a374 164 #define AR_PHY_CHNINFO_GAINDIFF 0x0a378 165 #define AR_PHY_CHNINFO_FINETIM 0x0a37c 166 #define AR_PHY_CHAN_INFO_GAIN_0 0x0a380 167 #define AR_PHY_SCRAMBLER_SEED 0x0a390 168 #define AR_PHY_CCK_TX_CTRL 0x0a394 169 #define AR_PHY_HEAVYCLIP_CTL 0x0a3a4 170 #define AR_PHY_HEAVYCLIP_20 0x0a3a8 171 #define AR_PHY_HEAVYCLIP_40 0x0a3ac 172 #define AR_PHY_ILLEGAL_TXRATE 0x0a3b0 173 #define AR_PHY_PWRTX_RATE1 0x0a3c0 174 #define AR_PHY_PWRTX_RATE2 0x0a3c4 175 #define AR_PHY_PWRTX_RATE3 0x0a3c8 176 #define AR_PHY_PWRTX_RATE4 0x0a3cc 177 #define AR_PHY_PWRTX_RATE5 0x0a3d0 178 #define AR_PHY_PWRTX_RATE6 0x0a3d4 179 #define AR_PHY_PWRTX_RATE7 0x0a3d8 180 #define AR_PHY_PWRTX_RATE8 0x0a3dc 181 #define AR_PHY_PWRTX_RATE10 0x0a3e4 182 #define AR_PHY_PWRTX_RATE11 0x0a3e8 183 #define AR_PHY_PWRTX_RATE12 0x0a3ec 184 #define AR_PHY_PWRTX_MAX 0x0a3f0 185 #define AR_PHY_POWER_TX_SUB 0x0a3f4 186 #define AR_PHY_TPC_1 0x0a3f8 187 #define AR_PHY_TPC_4_B(i) (0x0a404 + (i) * 0x1000) 188 #define AR_PHY_TPC_5_B(i) (0x0a408 + (i) * 0x1000) 189 #define AR_PHY_TPC_6_B(i) (0x0a40c + (i) * 0x1000) 190 #define AR_PHY_TPC_11_B(i) (0x0a420 + (i) * 0x1000) 191 #define AR_PHY_TPC_12 0x0a424 192 #define AR_PHY_TPC_18 0x0a43c 193 #define AR_PHY_TPC_19 0x0a440 194 #define AR_PHY_BB_THERM_ADC_1 0x0a448 195 #define AR_PHY_BB_THERM_ADC_4 0x0a454 196 #define AR_PHY_TX_FORCED_GAIN 0x0a458 197 #define AR_PHY_PDADC_TAB(i) (0x0a480 + (i) * 0x1000) 198 #define AR_PHY_TXGAIN_TABLE(i) (0x0a500 + (i) * 4) 199 #define AR_PHY_TX_IQCAL_CONTROL_1 0x0a648 200 #define AR_PHY_TX_IQCAL_START 0x0a640 201 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i) \ 202 (0x0a650 + (i) * 0x1000) 203 #define AR_PHY_TX_IQCAL_STATUS_B(i) (0x0a68c + (i) * 0x1000) 204 #define AR_PHY_PAPRD_TRAINER_CNTL1 0x0a690 205 #define AR_PHY_PAPRD_TRAINER_CNTL2 0x0a694 206 #define AR_PHY_PAPRD_TRAINER_CNTL3 0x0a698 207 #define AR_PHY_PAPRD_TRAINER_CNTL4 0x0a69c 208 #define AR_PHY_PAPRD_TRAINER_STAT1 0x0a6a0 209 #define AR_PHY_PAPRD_TRAINER_STAT2 0x0a6a4 210 #define AR_PHY_PAPRD_TRAINER_STAT3 0x0a6a8 211 #define AR_PHY_PANIC_WD_STATUS 0x0a7c0 212 #define AR_PHY_PANIC_WD_CTL_1 0x0a7c4 213 #define AR_PHY_PANIC_WD_CTL_2 0x0a7c8 214 #define AR_PHY_BT_CTL 0x0a7cc 215 #define AR_PHY_ONLY_WARMRESET 0x0a7d0 216 #define AR_PHY_ONLY_CTL 0x0a7d4 217 #define AR_PHY_ECO_CTRL 0x0a7dc 218 219 /* 220 * Analog registers. 221 */ 222 #define AR_IS_ANALOG_REG(reg) ((reg) >= 0x16000 && (reg) <= 0x17000) 223 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c 224 #define AR_PHY_65NM_CH0_SYNTH7 0x16098 225 #define AR_PHY_65NM_CH0_BIAS1 0x160c0 226 #define AR_PHY_65NM_CH0_BIAS2 0x160c4 227 #define AR_PHY_65NM_CH0_BIAS4 0x160cc 228 #define AR_PHY_65NM_CH0_RXTX1 0x16100 229 #define AR_PHY_65NM_CH0_RXTX2 0x16104 230 #define AR_PHY_65NM_CH0_RXTX4 0x1610c 231 #define AR9485_PHY_65NM_CH0_TOP2 0x16284 232 #define AR_PHY_65NM_CH0_TOP 0x16288 233 #define AR_PHY_65NM_CH0_THERM 0x16290 234 #define AR9485_PHY_CH0_XTAL 0x16290 235 #define AR_PHY_65NM_CH1_RXTX1 0x16500 236 #define AR_PHY_65NM_CH1_RXTX2 0x16504 237 #define AR_PHY_65NM_CH2_RXTX1 0x16900 238 #define AR_PHY_65NM_CH2_RXTX2 0x16904 239 #define AR_PHY_PMU1 0x16c40 240 #define AR_PHY_PMU2 0x16c44 241 242 243 /* Bits for AR_PHY_TIMING2. */ 244 #define AR_PHY_TIMING2_FORCE_PPM_VAL_M 0x00000fff 245 #define AR_PHY_TIMING2_FORCE_PPM_VAL_S 0 246 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 247 248 /* Bits for AR_PHY_TIMING3. */ 249 #define AR_PHY_TIMING3_DSC_EXP_M 0x0001e000 250 #define AR_PHY_TIMING3_DSC_EXP_S 13 251 #define AR_PHY_TIMING3_DSC_MAN_M 0xfffe0000 252 #define AR_PHY_TIMING3_DSC_MAN_S 17 253 254 /* Bits for AR_PHY_TIMING4. */ 255 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_M 0x0000f000 256 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 257 #define AR_PHY_TIMING4_DO_CAL 0x00010000 258 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000 259 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000 260 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000 261 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000 262 263 /* Bits for AR_PHY_TIMING5. */ 264 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 265 #define AR_PHY_TIMING5_CYCPWR_THR1_M 0x000000fe 266 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 267 #define AR_PHY_TIMING5_RSSI_THR1A_ENA 0x00008000 268 #define AR_PHY_TIMING5_CYCPWR_THR1A_M 0x007f0000 269 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 270 #define AR_PHY_TIMING5_RSSI_THR1A_M 0x007f0000 271 #define AR_PHY_TIMING5_RSSI_THR1A_S 16 272 273 /* Bits for AR_PHY_TIMING11. */ 274 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M 0x000fffff 275 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 276 #define AR_PHY_TIMING11_SPUR_FREQ_SD_M 0x3ff00000 277 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 278 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000 279 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000 280 281 /* Bits for AR_PHY_SPUR_REG. */ 282 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M 0x000000ff 283 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 284 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100 285 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x00020000 286 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_M 0x03fc0000 287 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 288 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x04000000 289 290 /* Bits for AR_PHY_FIND_SIG_LOW. */ 291 #define AR_PHY_FIND_SIG_LOW_RELSTEP_M 0x0000001f 292 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 293 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_M 0x00000fc0 294 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 295 #define AR_PHY_FIND_SIG_LOW_FIRPWR_M 0x0007f000 296 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 297 298 /* Bits for AR_PHY_SFCORR. */ 299 #define AR_PHY_SFCORR_M2COUNT_THR_M 0x0000001f 300 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 301 #define AR_PHY_SFCORR_M1_THRESH_M 0x00fe0000 302 #define AR_PHY_SFCORR_M1_THRESH_S 17 303 #define AR_PHY_SFCORR_M2_THRESH_M 0x7f000000 304 #define AR_PHY_SFCORR_M2_THRESH_S 24 305 306 /* Bits for AR_PHY_SFCORR_LOW. */ 307 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 308 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M 0x00003f00 309 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 310 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M 0x001fc000 311 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 312 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M 0x0fe00000 313 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 314 315 /* Bits for AR_PHY_SFCORR_EXT. */ 316 #define AR_PHY_SFCORR_EXT_M1_THRESH_M 0x0000007f 317 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 318 #define AR_PHY_SFCORR_EXT_M2_THRESH_M 0x00003f80 319 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 320 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M 0x001fc000 321 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 322 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M 0x0fe00000 323 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 324 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000 325 326 /* Bits for AR_PHY_RADAR_0. */ 327 #define AR_PHY_RADAR_0_ENA 0x00000001 328 #define AR_PHY_RADAR_0_INBAND_M 0x0000003e 329 #define AR_PHY_RADAR_0_INBAND_S 1 330 #define AR_PHY_RADAR_0_PRSSI_M 0x00000fc0 331 #define AR_PHY_RADAR_0_PRSSI_S 6 332 #define AR_PHY_RADAR_0_HEIGHT_M 0x0003f000 333 #define AR_PHY_RADAR_0_HEIGHT_S 12 334 #define AR_PHY_RADAR_0_RRSSI_M 0x00fc0000 335 #define AR_PHY_RADAR_0_RRSSI_S 18 336 #define AR_PHY_RADAR_0_FIRPWR_M 0x7f000000 337 #define AR_PHY_RADAR_0_FIRPWR_S 24 338 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 339 340 /* Bits for AR_PHY_RADAR_1. */ 341 #define AR_PHY_RADAR_1_MAXLEN_M 0x000000ff 342 #define AR_PHY_RADAR_1_MAXLEN_S 0 343 #define AR_PHY_RADAR_1_RELSTEP_THRESH_M 0x00001f00 344 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 345 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 346 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 347 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 348 #define AR_PHY_RADAR_1_RELPWR_THRESH_M 0x003f0000 349 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 350 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 351 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 352 353 /* Bits for AR_PHY_RADAR_EXT. */ 354 #define AR_PHY_RADAR_EXT_ENA 0x00004000 355 #define AR_PHY_RADAR_DC_PWR_THRESH_M 0x007f8000 356 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15 357 #define AR_PHY_RADAR_LB_DC_CAP_M 0x7f800000 358 #define AR_PHY_RADAR_LB_DC_CAP_S 23 359 360 /* Bits for AR_PHY_TX_IQCAL_CONTROL_3. */ 361 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 362 363 /* Bits for AR_PHY_RX_IQCAL_CORR_B(0). */ 364 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_M 0x0000007f 365 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 366 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_M 0x00003f80 367 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 368 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 369 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_M 0x003f8000 370 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 371 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_M 0x1fc00000 372 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 373 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 374 375 /* Bits for AR_PHY_PAPRD_AM2AM. */ 376 #define AR_PHY_PAPRD_AM2AM_MASK_M 0x01ffffff 377 #define AR_PHY_PAPRD_AM2AM_MASK_S 0 378 379 /* Bits for AR_PHY_PAPRD_AM2PM. */ 380 #define AR_PHY_PAPRD_AM2PM_MASK_M 0x01ffffff 381 #define AR_PHY_PAPRD_AM2PM_MASK_S 0 382 383 /* Bits for AR_PHY_PAPRD_HT40. */ 384 #define AR_PHY_PAPRD_HT40_MASK_M 0x01ffffff 385 #define AR_PHY_PAPRD_HT40_MASK_S 0 386 387 /* Bits for AR_PHY_PAPRD_CTRL0_B(i). */ 388 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001 389 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE 0x00000002 390 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_M 0xf8000000 391 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27 392 393 /* Bits for AR_PHY_PAPRD_CTRL1_B(i). */ 394 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001 395 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA 0x00000002 396 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA 0x00000004 397 #define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_M 0x000001f8 398 #define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_S 3 399 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_M 0x0001fe00 400 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_S 9 401 #define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_M 0x0ffe0000 402 #define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_S 17 403 404 /* Bits for AR_PHY_PA_GAIN123_B(i). */ 405 #define AR_PHY_PA_GAIN123_PA_GAIN1_M 0x000003ff 406 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0 407 408 /* Bits for AR_PHY_PAPRD_PRE_POST_SCALE_B0(i). */ 409 #define AR_PHY_PAPRD_PRE_POST_SCALING_M 0x0003ffff 410 #define AR_PHY_PAPRD_PRE_POST_SCALING_S 0 411 412 /* Bits for AR_PHY_PAPRD_MEM_TAB_B(i). */ 413 #define AR_PHY_PAPRD_ANGLE_M 0x000007ff 414 #define AR_PHY_PAPRD_ANGLE_S 0 415 #define AR_PHY_PAPRD_PA_IN_M 0x003ff800 416 #define AR_PHY_PAPRD_PA_IN_S 11 417 418 /* Bits for AR_PHY_PILOT_SPUR_MASK. */ 419 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_M 0x0000001f 420 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 421 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_M 0x00000fe0 422 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 423 424 /* Bits for AR_PHY_CHAN_SPUR_MASK. */ 425 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_M 0x0000001f 426 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 427 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_M 0x00000fe0 428 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 429 430 /* Bits for AR_PHY_SGI_DELTA. */ 431 #define AR_PHY_SGI_DSC_EXP_M 0x0000000f 432 #define AR_PHY_SGI_DSC_EXP_S 0 433 #define AR_PHY_SGI_DSC_MAN_M 0x0007fff0 434 #define AR_PHY_SGI_DSC_MAN_S 4 435 436 /* Bits for AR_PHY_SETTLING. */ 437 #define AR_PHY_SETTLING_SWITCH_M 0x00003f80 438 #define AR_PHY_SETTLING_SWITCH_S 7 439 440 /* Bits for AR_PHY_RXGAIN(i). */ 441 #define AR_PHY_RXGAIN_TXRX_ATTEN_M 0x0003f000 442 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 443 #define AR_PHY_RXGAIN_TXRX_RF_MAX_M 0x007c0000 444 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 445 446 /* Bits for AR_PHY_DESIRED_SZ. */ 447 #define AR_PHY_DESIRED_SZ_ADC_M 0x000000ff 448 #define AR_PHY_DESIRED_SZ_ADC_S 0 449 #define AR_PHY_DESIRED_SZ_PGA_M 0x0000ff00 450 #define AR_PHY_DESIRED_SZ_PGA_S 8 451 #define AR_PHY_DESIRED_SZ_TOT_DES_M 0x0ff00000 452 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 453 454 /* Bits for AR_PHY_FIND_SIG. */ 455 #define AR_PHY_FIND_SIG_RELSTEP_M 0x0000001f 456 #define AR_PHY_FIND_SIG_RELSTEP_S 0 457 #define AR_PHY_FIND_SIG_RELPWR_M 0x000007c0 458 #define AR_PHY_FIND_SIG_RELPWR_S 6 459 #define AR_PHY_FIND_SIG_FIRSTEP_M 0x0003f000 460 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 461 #define AR_PHY_FIND_SIG_FIRPWR_M 0x03fc0000 462 #define AR_PHY_FIND_SIG_FIRPWR_S 18 463 464 /* Bits for AR_PHY_AGC. */ 465 #define AR_PHY_AGC_COARSE_PWR_CONST_M 0x0000007f 466 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0 467 #define AR_PHY_AGC_COARSE_LOW_M 0x00007f80 468 #define AR_PHY_AGC_COARSE_LOW_S 7 469 #define AR_PHY_AGC_COARSE_HIGH_M 0x003f8000 470 #define AR_PHY_AGC_COARSE_HIGH_S 15 471 472 /* Bits for AR_PHY_EXT_ATTEN_CTL(i). */ 473 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_M 0x0000001f 474 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 475 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_M 0x0000003f 476 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 477 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_M 0x00000fc0 478 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 479 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_M 0x00003c00 480 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 481 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_M 0x0001f000 482 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 483 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_M 0x003e0000 484 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 485 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_M 0x00fc0000 486 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 487 488 /* Bits for AR_PHY_CCA(i). */ 489 #define AR_PHY_MAXCCA_PWR_M 0x000001ff 490 #define AR_PHY_MAXCCA_PWR_S 0 491 #define AR_PHY_MINCCA_PWR_M 0x1ff00000 492 #define AR_PHY_MINCCA_PWR_S 20 493 494 /* Bits for AR_PHY_EXT_CCA(i). */ 495 #define AR_PHY_EXT_MAXCCA_PWR_M 0x000001ff 496 #define AR_PHY_EXT_MAXCCA_PWR_S 0 497 #define AR_PHY_EXT_MINCCA_PWR_M 0x01ff0000 498 #define AR_PHY_EXT_MINCCA_PWR_S 16 499 500 /* Bits for AR_PHY_RESTART. */ 501 #define AR_PHY_RESTART_ENA 0x00000001 502 #define AR_PHY_RESTART_DIV_GC_M 0x001c0000 503 #define AR_PHY_RESTART_DIV_GC_S 18 504 505 /* Bits for AR_PHY_MC_GAIN_CTRL. */ 506 #define AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV 0x01000000 507 #define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_M 0x7e000000 508 #define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_S 25 509 510 /* Bits for AR_PHY_CCK_DETECT. */ 511 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M 0x0000003f 512 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 513 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M 0x00001fc0 514 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 515 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x00002000 516 517 /* Bits for AR_PHY_DAG_CTRLCCK. */ 518 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 519 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_M 0x0001fc00 520 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 521 522 /* Bits for AR_PHY_CCK_SPUR_MIT. */ 523 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 524 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_M 0x000001fe 525 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 526 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_M 0x1ffffe00 527 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 528 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_M 0x60000000 529 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 530 531 /* Bits for AR_PHY_GEN_CTRL. */ 532 #define AR_PHY_GC_TURBO_MODE 0x00000001 533 #define AR_PHY_GC_TURBO_SHORT 0x00000002 534 #define AR_PHY_GC_DYN2040_EN 0x00000004 535 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 536 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 537 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 538 #define AR_PHY_GC_HT_EN 0x00000040 539 #define AR_PHY_GC_SHORT_GI_40 0x00000080 540 #define AR_PHY_GC_WALSH 0x00000100 541 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 542 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 543 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 544 545 /* Bits for AR_PHY_MODE. */ 546 #define AR_PHY_MODE_OFDM 0x00000000 547 #define AR_PHY_MODE_CCK 0x00000001 548 #define AR_PHY_MODE_DYNAMIC 0x00000004 549 #define AR_PHY_MODE_HALF 0x00000020 550 #define AR_PHY_MODE_QUARTER 0x00000040 551 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 552 #define AR_PHY_MODE_SVD_HALF 0x00000200 553 554 /* Bits for AR_PHY_ACTIVE. */ 555 #define AR_PHY_ACTIVE_DIS 0x00000000 556 #define AR_PHY_ACTIVE_EN 0x00000001 557 558 /* Bits for AR_PHY_SPUR_MASK_A. */ 559 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_M 0x000003ff 560 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 561 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_M 0x0001fc00 562 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 563 564 /* Bits for AR_PHY_SPECTRAL_SCAN. */ 565 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 566 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 567 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_M 0x000000f0 568 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 569 #define AR_PHY_SPECTRAL_SCAN_PERIOD_M 0x0000ff00 570 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 571 #define AR_PHY_SPECTRAL_SCAN_COUNT_M 0x00ff0000 572 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 573 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 574 575 /* Bits for AR_PHY_RFBUS_REQ. */ 576 #define AR_PHY_RFBUS_REQ_EN 0x00000001 577 578 /* Bits for AR_PHY_RFBUS_GRANT. */ 579 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 580 581 /* Bits for AR_PHY_RIFS. */ 582 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 583 584 /* Bits for AR_PHY_RX_DELAY. */ 585 #define AR_PHY_RX_DELAY_DELAY_M 0x00003fff 586 #define AR_PHY_RX_DELAY_DELAY_S 0 587 588 /* Bits for AR_PHY_XPA_TIMING_CTL. */ 589 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_M 0x000000ff 590 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 591 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_M 0x0000ff00 592 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 593 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_M 0x00ff0000 594 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 595 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_M 0xff000000 596 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 597 598 /* Bits for AR_PHY_SWITCH_CHAIN. */ 599 #define AR_SWITCH_TABLE_ALL_M 0x00000fff 600 #define AR_SWITCH_TABLE_ALL_S 0 601 602 /* Bits for AR_PHY_SWITCH_COM. */ 603 #define AR_SWITCH_TABLE_COM_ALL_M 0x0000ffff 604 #define AR_SWITCH_TABLE_COM_ALL_S 0 605 606 /* Bits for AR_SWITCH_TABLE_COM_2. */ 607 #define AR_SWITCH_TABLE_COM_2_ALL_M 0x00ffffff 608 #define AR_SWITCH_TABLE_COM_2_ALL_S 0 609 610 /* Bits for AR_PHY_AGC_CONTROL. */ 611 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 612 #define AR_PHY_AGC_CONTROL_NF 0x00000002 613 #define AR_PHY_AGC_CONTROL_YCOK_MAX_M 0x000003c0 614 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 615 #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 616 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 617 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 618 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 619 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 620 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 621 622 /* Bits for AR_PHY_CALMODE. */ 623 #define AR_PHY_CALMODE_IQ 0x00000000 624 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 625 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 626 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 627 628 /* Bits for AR_PHY_FCAL_2_0. */ 629 #define AR_PHY_FCAL20_CAP_STATUS_0_M 0x01f00000 630 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20 631 632 /* Bits for AR_PHY_SYNTH_CONTROL. */ 633 #define AR9380_BMODE 0x20000000 634 635 /* Bits for AR_PHY_ANALOG_SWAP. */ 636 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 637 638 /* Bits for AR_PHY_ADDAC_PARA_CTL. */ 639 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 640 641 /* Bits for AR_PHY_TEST. */ 642 #define AR_PHY_TEST_RFSILENT_BB 0x00002000 643 #define AR_PHY_TEST_BBB_OBS_SEL_M 0x00780000 644 #define AR_PHY_TEST_BBB_OBS_SEL_S 19 645 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 0x00800000 646 #define AR_PHY_TEST_CHAIN_SEL_M 0xc0000000 647 #define AR_PHY_TEST_CHAIN_SEL_S 30 648 649 /* Bits for AR_PHY_TEST_CTL_STATUS. */ 650 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x00000001 651 #define AR_PHY_TEST_CTL_TX_OBS_SEL_M 0x0000001c 652 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 653 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_M 0x00000060 654 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 655 #define AR_PHY_TEST_CTL_TSTADC_EN 0x00000100 656 #define AR_PHY_TEST_CTL_RX_OBS_SEL_M 0x00003c00 657 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 658 659 /* Bits for AR_PHY_CHAN_INFO_MEMORY. */ 660 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x00000001 661 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 662 663 /* Bits for AR_PHY_CHAN_INFO_GAIN_0. */ 664 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0x00000fff 665 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 666 667 /* Bits for AR_PHY_CCK_TX_CTRL. */ 668 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 669 670 /* Bits for AR_PHY_PWRTX_RATE5. */ 671 #define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_M 0x0000003f 672 #define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_S 0 673 674 /* Bits for AR_PHY_PWRTX_MAX. */ 675 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 676 677 /* Bits for AR_PHY_TPC_1. */ 678 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001 679 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_M 0x0000003e 680 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1 681 682 /* Bits for AR_PHY_TPC_5_B(i). */ 683 #define AR_PHY_TPC_5_PD_GAIN_OVERLAP_M 0x0000000f 684 #define AR_PHY_TPC_5_PD_GAIN_OVERLAP_S 0 685 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_M 0x000003f0 686 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_S 4 687 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_M 0x0000fc00 688 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_S 10 689 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_M 0x003f0000 690 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_S 16 691 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_M 0x0fc00000 692 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_S 22 693 694 /* Bits for AR_PHY_TPC_6_B(i). */ 695 #define AR_PHY_TPC_6_ERROR_EST_MODE_M 0x03000000 696 #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 697 698 /* Bits for AR_PHY_TPC_11_B(i). */ 699 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_M 0x00ff0000 700 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16 701 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_M 0xff000000 702 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_S 24 703 704 /* Bits for AR_PHY_TPC_12. */ 705 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_M 0x3e000000 706 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25 707 708 /* Bits for AR_PHY_TPC_18. */ 709 #define AR_PHY_TPC_18_THERM_CAL_M 0x000000ff 710 #define AR_PHY_TPC_18_THERM_CAL_S 0 711 #define AR_PHY_TPC_18_VOLT_CAL_M 0x0000ff00 712 #define AR_PHY_TPC_18_VOLT_CAL_S 8 713 714 /* Bits for AR_PHY_TPC_19. */ 715 #define AR_PHY_TPC_19_ALPHA_THERM_M 0x000000ff 716 #define AR_PHY_TPC_19_ALPHA_THERM_S 0 717 #define AR_PHY_TPC_19_ALPHA_VOLT_M 0x001f0000 718 #define AR_PHY_TPC_19_ALPHA_VOLT_S 16 719 720 /* Bits for AR_PHY_BB_THERM_ADC_1. */ 721 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_M 0x000000ff 722 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0 723 724 /* Bits for AR_PHY_BB_THERM_ADC_4. */ 725 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_M 0x000000ff 726 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S 0 727 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_M 0x0000ff00 728 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_S 8 729 730 /* Bits for AR_PHY_TX_FORCED_GAIN. */ 731 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001 732 #define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_M 0x0000000e 733 #define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_S 1 734 #define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_M 0x00000030 735 #define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_S 4 736 #define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_M 0x000003c0 737 #define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_S 6 738 #define AR_PHY_TX_FORCED_GAIN_PADRVGNA_M 0x00003c00 739 #define AR_PHY_TX_FORCED_GAIN_PADRVGNA_S 10 740 #define AR_PHY_TX_FORCED_GAIN_PADRVGNB_M 0x0003c000 741 #define AR_PHY_TX_FORCED_GAIN_PADRVGNB_S 14 742 #define AR_PHY_TX_FORCED_GAIN_PADRVGNC_M 0x003c0000 743 #define AR_PHY_TX_FORCED_GAIN_PADRVGNC_S 18 744 #define AR_PHY_TX_FORCED_GAIN_PADRVGND_M 0x00c00000 745 #define AR_PHY_TX_FORCED_GAIN_PADRVGND_S 22 746 #define AR_PHY_TX_FORCED_GAIN_ENABLE_PAL 0x01000000 747 748 /* Bits for AR_PHY_TXGAIN_TABLE(i). */ 749 #define AR_PHY_TXGAIN_TXBB1DBGAIN_M 0x00000007 750 #define AR_PHY_TXGAIN_TXBB1DBGAIN_S 0 751 #define AR_PHY_TXGAIN_TXBB6DBGAIN_M 0x00000018 752 #define AR_PHY_TXGAIN_TXBB6DBGAIN_S 3 753 #define AR_PHY_TXGAIN_TXMXRGAIN_M 0x000001e0 754 #define AR_PHY_TXGAIN_TXMXRGAIN_S 5 755 #define AR_PHY_TXGAIN_PADRVGNA_M 0x00001e00 756 #define AR_PHY_TXGAIN_PADRVGNA_S 9 757 #define AR_PHY_TXGAIN_PADRVGNB_M 0x0001e000 758 #define AR_PHY_TXGAIN_PADRVGNB_S 13 759 #define AR_PHY_TXGAIN_PADRVGNC_M 0x001e0000 760 #define AR_PHY_TXGAIN_PADRVGNC_S 17 761 #define AR_PHY_TXGAIN_PADRVGND_M 0x00600000 762 #define AR_PHY_TXGAIN_PADRVGND_S 21 763 #define AR_PHY_TXGAIN_INDEX_M 0xff000000 764 #define AR_PHY_TXGAIN_INDEX_S 24 765 766 /* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */ 767 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M 0x01fc0000 768 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 769 770 /* Bits for AR_PHY_TX_IQCAL_START. */ 771 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 772 773 /* Bits for AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i). */ 774 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_M 0x00003fff 775 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0 776 777 /* Bits for AR_PHY_TX_IQCAL_STATUS_B(i). */ 778 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 779 780 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL1. */ 781 #define AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE 0x00000001 782 #define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_M 0x0000007e 783 #define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_S 1 784 #define AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE 0x00000100 785 #define AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE 0x00000200 786 #define AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE 0x00000400 787 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE 0x00000800 788 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_M 0x0003f000 789 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_S 12 790 791 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL3. */ 792 #define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_M 0x0000003f 793 #define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_S 0 794 #define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_M 0x00000fc0 795 #define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_S 6 796 #define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_M 0x0001f000 797 #define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_S 12 798 #define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_M 0x000e0000 799 #define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_S 17 800 #define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_M 0x00f00000 801 #define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_S 20 802 #define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_M 0x0f000000 803 #define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_S 24 804 #define AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE 0x20000000 805 806 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL4. */ 807 #define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_M 0x00000fff 808 #define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_S 0 809 #define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_M 0x0000f000 810 #define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_S 12 811 #define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_M 0x03ff0000 812 #define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_S 16 813 814 /* Bits for AR_PHY_PAPRD_TRAINER_STAT1. */ 815 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE 0x00000001 816 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_INCOMPLETE 0x00000002 817 #define AR_PHY_PAPRD_TRAINER_STAT1_CORR_ERR 0x00000004 818 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_ACTIVE 0x00000008 819 #define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_M 0x000001f0 820 #define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_S 4 821 #define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_M 0x0001fe00 822 #define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_S 9 823 824 /* Bits for AR_PHY_PAPRD_TRAINER_STAT2. */ 825 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_M 0x0000ffff 826 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_S 0 827 #define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_M 0x001f0000 828 #define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_S 16 829 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_M 0x00600000 830 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_S 21 831 832 /* Bits for AR_PHY_PAPRD_TRAINER_STAT3. */ 833 #define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_M 0x000fffff 834 #define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_S 0 835 836 /* Bits for AR_PHY_65NM_CH0_SYNTH4. */ 837 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 838 839 /* Bits for AR_PHY_65NM_CH0_SYNTH7. */ 840 #define AR9380_FRACMODE 0x40000000 841 #define AR9380_LOAD_SYNTH 0x80000000 842 843 /* Bits for AR_PHY_65NM_CH0_BIAS1. */ 844 #define AR_PHY_65NM_CH0_BIAS1_0_M 0x000001c0 845 #define AR_PHY_65NM_CH0_BIAS1_0_S 6 846 #define AR_PHY_65NM_CH0_BIAS1_1_M 0x00000e00 847 #define AR_PHY_65NM_CH0_BIAS1_1_S 9 848 #define AR_PHY_65NM_CH0_BIAS1_2_M 0x00007000 849 #define AR_PHY_65NM_CH0_BIAS1_2_S 12 850 #define AR_PHY_65NM_CH0_BIAS1_3_M 0x00038000 851 #define AR_PHY_65NM_CH0_BIAS1_3_S 15 852 #define AR_PHY_65NM_CH0_BIAS1_4_M 0x001c0000 853 #define AR_PHY_65NM_CH0_BIAS1_4_S 18 854 #define AR_PHY_65NM_CH0_BIAS1_5_M 0x00e00000 855 #define AR_PHY_65NM_CH0_BIAS1_5_S 21 856 857 /* Bits for AR_PHY_65NM_CH0_BIAS2. */ 858 #define AR_PHY_65NM_CH0_BIAS2_0_M 0x000000e0 859 #define AR_PHY_65NM_CH0_BIAS2_0_S 5 860 #define AR_PHY_65NM_CH0_BIAS2_1_M 0x00000700 861 #define AR_PHY_65NM_CH0_BIAS2_1_S 8 862 #define AR_PHY_65NM_CH0_BIAS2_2_M 0x00003800 863 #define AR_PHY_65NM_CH0_BIAS2_2_S 11 864 #define AR_PHY_65NM_CH0_BIAS2_3_M 0x0001c000 865 #define AR_PHY_65NM_CH0_BIAS2_3_S 14 866 #define AR_PHY_65NM_CH0_BIAS2_4_M 0x000e0000 867 #define AR_PHY_65NM_CH0_BIAS2_4_S 17 868 #define AR_PHY_65NM_CH0_BIAS2_5_M 0x00700000 869 #define AR_PHY_65NM_CH0_BIAS2_5_S 20 870 #define AR_PHY_65NM_CH0_BIAS2_6_M 0x03800000 871 #define AR_PHY_65NM_CH0_BIAS2_6_S 23 872 #define AR_PHY_65NM_CH0_BIAS2_7_M 0x1c000000 873 #define AR_PHY_65NM_CH0_BIAS2_7_S 26 874 #define AR_PHY_65NM_CH0_BIAS2_8_M 0xe0000000 875 #define AR_PHY_65NM_CH0_BIAS2_8_S 29 876 877 /* Bits for AR_PHY_65NM_CH0_BIAS4. */ 878 #define AR_PHY_65NM_CH0_BIAS4_0_M 0x03800000 879 #define AR_PHY_65NM_CH0_BIAS4_0_S 23 880 #define AR_PHY_65NM_CH0_BIAS4_1_M 0x1c000000 881 #define AR_PHY_65NM_CH0_BIAS4_1_S 26 882 #define AR_PHY_65NM_CH0_BIAS4_2_M 0xe0000000 883 #define AR_PHY_65NM_CH0_BIAS4_2_S 29 884 885 /* Bits for AR_PHY_65NM_CH0_RXTX4. */ 886 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 887 888 /* Bits for AR9485_PHY_65NM_CH0_TOP2. */ 889 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M 0x0000f000 890 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_S 12 891 892 /* Bits for AR_PHY_65NM_CH0_TOP. */ 893 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_M 0x00000300 894 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S 8 895 896 /* Bits for AR_PHY_65NM_CH0_THERM. */ 897 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_M 0x00000003 898 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0 899 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004 900 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_M 0x0000ff00 901 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 902 #define AR_PHY_65NM_CH0_THERM_START 0x20000000 903 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 904 905 /* Bits for AR9485_PHY_CH0_XTAL. */ 906 #define AR9485_PHY_CH0_XTAL_CAPINDAC_M 0x7f000000 907 #define AR9485_PHY_CH0_XTAL_CAPINDAC_S 24 908 #define AR9485_PHY_CH0_XTAL_CAPOUTDAC_M 0x00fe0000 909 #define AR9485_PHY_CH0_XTAL_CAPOUTDAC_S 17 910 911 /* Bits for AR_PHY_PMU1. */ 912 #define AR_PHY_PMU1_PWD 0x00000001 913 914 /* Bits for AR_PHY_PMU2. */ 915 #define AR_PHY_PMU2_PGM 0x00200000 916 917 /* 918 * OTP registers. 919 */ 920 #define AR_OTP_BASE(i) (0x14000 + (i) * 4) 921 #define AR_OTP_STATUS 0x15f18 922 #define AR_OTP_READ_DATA 0x15f1c 923 924 /* Bits for AR_OTP_STATUS. */ 925 #define AR_OTP_STATUS_TYPE_M 0x00000007 926 #define AR_OTP_STATUS_TYPE_S 0 927 #define AR_OTP_STATUS_SM_BUSY 0x1 928 #define AR_OTP_STATUS_ACCESS_BUSY 0x2 929 #define AR_OTP_STATUS_VALID 0x4 930 931 932 #define AR9003_MAX_CHAINS 3 933 934 #define AR9003_TX_QDEPTH 8 935 #define AR9003_RX_LP_QDEPTH 128 936 #define AR9003_RX_HP_QDEPTH 16 937 938 #define AR9003_NTXSTATUS 64 939 940 /* Maximum number of DMA segments per Tx descriptor. */ 941 #define AR9003_MAX_SCATTER 4 942 943 /* 944 * Tx DMA descriptor. 945 */ 946 struct ar_tx_desc { 947 uint32_t ds_info; 948 uint32_t ds_link; 949 struct { 950 uint32_t ds_data; 951 uint32_t ds_ctl; 952 } __packed ds_segs[AR9003_MAX_SCATTER]; 953 uint32_t ds_ctl10; 954 uint32_t ds_ctl11; 955 uint32_t ds_ctl12; 956 uint32_t ds_ctl13; 957 uint32_t ds_ctl14; 958 uint32_t ds_ctl15; 959 uint32_t ds_ctl16; 960 uint32_t ds_ctl17; 961 uint32_t ds_ctl18; 962 uint32_t ds_ctl19; 963 uint32_t ds_ctl20; 964 uint32_t ds_ctl21; 965 uint32_t ds_ctl22; 966 /* 967 * Padding to make Tx descriptors 128 bytes such that they will 968 * not cross a 4KB boundary. 969 */ 970 uint32_t pad[9]; 971 } __packed __attribute__((aligned(4))); 972 973 /* Bits for ds_info. */ 974 #define AR_TXI_DESC_NDWORDS_M 0x000000ff 975 #define AR_TXI_DESC_NDWORDS_S 0 976 #define AR_TXI_QCU_NUM_M 0x00000f00 977 #define AR_TXI_QCU_NUM_S 8 978 #define AR_TXI_CTRL_STAT 0x00004000 979 #define AR_TXI_DESC_TX 0x00008000 980 #define AR_TXI_DESC_ID_M 0xffff0000 981 #define AR_TXI_DESC_ID_S 16 982 #define AR_VENDOR_ATHEROS 0x168c /* NB: PCI_VENDOR_ATHEROS */ 983 984 /* Bits for ds_ctl. */ 985 #define AR_TXC_BUF_LEN_M 0x0fff0000 986 #define AR_TXC_BUF_LEN_S 16 987 988 /* Bits for ds_ctl10. */ 989 #define AR_TXC10_PTR_CHK_SUM_M 0x0000ffff 990 #define AR_TXC10_PTR_CHK_SUM_S 0 991 992 /* Bits for ds_ctl11. */ 993 #define AR_TXC11_FRAME_LEN_M 0x00000fff 994 #define AR_TXC11_FRAME_LEN_S 0 995 #define AR_TXC11_XMIT_POWER_M 0x003f0000 996 #define AR_TXC11_XMIT_POWER_S 16 997 #define AR_TXC11_RTS_ENABLE 0x00400000 998 #define AR_TXC11_CLR_DEST_MASK 0x01000000 999 #define AR_TXC11_DEST_IDX_VALID 0x40000000 1000 #define AR_TXC11_CTS_ENABLE 0x80000000 1001 1002 /* Bits for ds_ctl12. */ 1003 #define AR_TXC12_PAPRD_CHAIN_MASK_M 0x00000e00 1004 #define AR_TXC12_PAPRD_CHAIN_MASK_S 9 1005 #define AR_TXC12_DEST_IDX_M 0x000fe000 1006 #define AR_TXC12_DEST_IDX_S 13 1007 #define AR_TXC12_FRAME_TYPE_M 0x00f00000 1008 #define AR_TXC12_FRAME_TYPE_S 20 1009 #define AR_FRAME_TYPE_NORMAL 0 1010 #define AR_FRAME_TYPE_ATIM 1 1011 #define AR_FRAME_TYPE_PSPOLL 2 1012 #define AR_FRAME_TYPE_BEACON 3 1013 #define AR_FRAME_TYPE_PROBE_RESP 4 1014 #define AR_TXC12_NO_ACK 0x01000000 1015 1016 /* Bits for ds_ctl13. */ 1017 #define AR_TXC13_BURST_DUR_M 0x00007fff 1018 #define AR_TXC13_BURST_DUR_S 0 1019 #define AR_TXC13_DUR_UPDATE_ENA 0x00008000 1020 #define AR_TXC13_XMIT_DATA_TRIES0_M 0x000f0000 1021 #define AR_TXC13_XMIT_DATA_TRIES0_S 16 1022 #define AR_TXC13_XMIT_DATA_TRIES1_M 0x00f00000 1023 #define AR_TXC13_XMIT_DATA_TRIES1_S 20 1024 #define AR_TXC13_XMIT_DATA_TRIES2_M 0x0f000000 1025 #define AR_TXC13_XMIT_DATA_TRIES2_S 24 1026 #define AR_TXC13_XMIT_DATA_TRIES3_M 0xf0000000 1027 #define AR_TXC13_XMIT_DATA_TRIES3_S 28 1028 1029 /* Bits for ds_ctl14. */ 1030 #define AR_TXC14_XMIT_RATE0_M 0x000000ff 1031 #define AR_TXC14_XMIT_RATE0_S 0 1032 #define AR_TXC14_XMIT_RATE1_M 0x0000ff00 1033 #define AR_TXC14_XMIT_RATE1_S 8 1034 #define AR_TXC14_XMIT_RATE2_M 0x00ff0000 1035 #define AR_TXC14_XMIT_RATE2_S 16 1036 #define AR_TXC14_XMIT_RATE3_M 0xff000000 1037 #define AR_TXC14_XMIT_RATE3_S 24 1038 1039 /* Bits for ds_ctl15. */ 1040 #define AR_TXC15_PACKET_DUR0_M 0x00007fff 1041 #define AR_TXC15_PACKET_DUR0_S 0 1042 #define AR_TXC15_RTSCTS_QUAL0 0x00008000 1043 #define AR_TXC15_PACKET_DUR1_M 0x7fff0000 1044 #define AR_TXC15_PACKET_DUR1_S 16 1045 #define AR_TXC15_RTSCTS_QUAL1 0x80000000 1046 /* Shortcut. */ 1047 #define AR_TXC15_RTSCTS_QUAL01 \ 1048 (AR_TXC15_RTSCTS_QUAL0 | AR_TXC15_RTSCTS_QUAL1) 1049 1050 /* Bits for ds_ctl16. */ 1051 #define AR_TXC16_PACKET_DUR2_M 0x00007fff 1052 #define AR_TXC16_PACKET_DUR2_S 0 1053 #define AR_TXC16_RTSCTS_QUAL2 0x00008000 1054 #define AR_TXC16_PACKET_DUR3_M 0x7fff0000 1055 #define AR_TXC16_PACKET_DUR3_S 16 1056 #define AR_TXC16_RTSCTS_QUAL3 0x80000000 1057 /* Shortcut. */ 1058 #define AR_TXC16_RTSCTS_QUAL23 \ 1059 (AR_TXC16_RTSCTS_QUAL2 | AR_TXC16_RTSCTS_QUAL3) 1060 1061 /* Bits for ds_ctl17. */ 1062 #define AR_TXC17_ENCR_TYPE_M 0x0c000000 1063 #define AR_TXC17_ENCR_TYPE_S 26 1064 #define AR_ENCR_TYPE_CLEAR 0 1065 #define AR_ENCR_TYPE_WEP 1 1066 #define AR_ENCR_TYPE_AES 2 1067 #define AR_ENCR_TYPE_TKIP 3 1068 1069 /* Bits for ds_ctl18. */ 1070 #define AR_TXC18_2040_0 0x00000001 1071 #define AR_TXC18_GI0 0x00000002 1072 #define AR_TXC18_CHAIN_SEL0_M 0x0000001c 1073 #define AR_TXC18_CHAIN_SEL0_S 2 1074 #define AR_TXC18_2040_1 0x00000020 1075 #define AR_TXC18_GI1 0x00000040 1076 #define AR_TXC18_CHAIN_SEL1_M 0x00000380 1077 #define AR_TXC18_CHAIN_SEL1_S 7 1078 #define AR_TXC18_2040_2 0x00000400 1079 #define AR_TXC18_GI2 0x00000800 1080 #define AR_TXC18_CHAIN_SEL2_M 0x00007000 1081 #define AR_TXC18_CHAIN_SEL2_S 12 1082 #define AR_TXC18_2040_3 0x00008000 1083 #define AR_TXC18_GI3 0x00010000 1084 #define AR_TXC18_CHAIN_SEL3_M 0x000e0000 1085 #define AR_TXC18_CHAIN_SEL3_S 17 1086 #define AR_TXC18_RTSCTS_RATE_M 0x0ff00000 1087 #define AR_TXC18_RTSCTS_RATE_S 20 1088 /* Shortcuts. */ 1089 #define AR_TXC18_2040_0123 \ 1090 (AR_TXC18_2040_0 | AR_TXC18_2040_1 | AR_TXC18_2040_2 | AR_TXC18_2040_3) 1091 #define AR_TXC18_GI0123 \ 1092 (AR_TXC18_GI0 | AR_TXC18_GI1 | AR_TXC18_GI2 | AR_TXC18_GI3) 1093 1094 /* Bits for ds_ctl19. */ 1095 #define AR_TXC19_NOT_SOUNDING 0x20000000 1096 1097 1098 /* 1099 * Tx status DMA descriptor. 1100 */ 1101 struct ar_tx_status { 1102 uint32_t ds_info; 1103 uint32_t ds_status1; 1104 uint32_t ds_status2; 1105 uint32_t ds_status3; 1106 uint32_t ds_status4; 1107 uint32_t ds_status5; 1108 uint32_t ds_status6; 1109 uint32_t ds_status7; 1110 uint32_t ds_status8; 1111 } __packed __attribute__((aligned(4))); 1112 1113 /* Bits for ds_status3. */ 1114 #define AR_TXS3_EXCESSIVE_RETRIES 0x00000002 1115 #define AR_TXS3_FIFO_UNDERRUN 0x00000004 1116 #define AR_TXS3_RTS_FAIL_CNT_M 0x000000f0 1117 #define AR_TXS3_RTS_FAIL_CNT_S 4 1118 #define AR_TXS3_DATA_FAIL_CNT_M 0x00000f00 1119 #define AR_TXS3_DATA_FAIL_CNT_S 8 1120 #define AR_TXS3_TX_DELIM_UNDERRUN 0x00010000 1121 #define AR_TXS3_TX_DATA_UNDERRUN 0x00020000 1122 /* Shortcut. */ 1123 #define AR_TXS3_UNDERRUN \ 1124 (AR_TXS3_FIFO_UNDERRUN | \ 1125 AR_TXS3_TX_DELIM_UNDERRUN | \ 1126 AR_TXS3_TX_DATA_UNDERRUN) 1127 1128 /* Bits for ds_status8. */ 1129 #define AR_TXS8_DONE 0x00000001 1130 #define AR_TXS8_FINAL_IDX_M 0x00600000 1131 #define AR_TXS8_FINAL_IDX_S 21 1132 1133 /* 1134 * Rx status DMA descriptor. 1135 */ 1136 struct ar_rx_status { 1137 uint32_t ds_info; 1138 uint32_t ds_status1; 1139 uint32_t ds_status2; 1140 uint32_t ds_status3; 1141 uint32_t ds_status4; 1142 uint32_t ds_status5; 1143 uint32_t ds_status6; 1144 uint32_t ds_status7; 1145 uint32_t ds_status8; 1146 uint32_t ds_status9; 1147 uint32_t ds_status10; 1148 uint32_t ds_status11; 1149 } __packed __attribute__((aligned(4))); 1150 1151 /* Bits for ds_info. */ 1152 #define AR_RXI_CTRL_STAT 0x00004000 1153 #define AR_RXI_DESC_TX 0x00008000 1154 #define AR_RXI_DESC_ID_M 0xffff0000 1155 #define AR_RXI_DESC_ID_S 16 1156 1157 /* Bits for ds_status1. */ 1158 #define AR_RXS1_DONE 0x00000001 1159 #define AR_RXS1_RATE_M 0x000003fc 1160 #define AR_RXS1_RATE_S 2 1161 1162 /* Bits for ds_status2. */ 1163 #define AR_RXS2_DATA_LEN_M 0x00000fff 1164 #define AR_RXS2_DATA_LEN_S 0 1165 1166 /* Bits for ds_status4. */ 1167 #define AR_RXS4_GI 0x00000001 1168 #define AR_RXS4_ANTENNA_M 0xffffff00 1169 #define AR_RXS4_ANTENNA_S 8 1170 1171 /* Bits for ds_status5. */ 1172 #define AR_RXS5_RSSI_COMBINED_M 0xff000000 1173 #define AR_RXS5_RSSI_COMBINED_S 24 1174 1175 /* Bits for ds_status11. */ 1176 #define AR_RXS11_FRAME_OK 0x00000002 1177 #define AR_RXS11_CRC_ERR 0x00000004 1178 #define AR_RXS11_DECRYPT_CRC_ERR 0x00000008 1179 #define AR_RXS11_PHY_ERR 0x00000010 1180 #define AR_RXS11_PHY_ERR_CODE_M 0x0000ff00 1181 #define AR_RXS11_PHY_ERR_CODE_S 8 1182 #define AR_RXS11_MICHAEL_ERR 0x00000020 1183 1184 /* 1185 * AR9003 family common ROM structures. 1186 */ 1187 #define AR_EEP_COMPRESS_NONE 0 1188 #define AR_EEP_COMPRESS_LZMA 1 1189 #define AR_EEP_COMPRESS_PAIRS 2 1190 #define AR_EEP_COMPRESS_BLOCK 3 1191 1192 struct ar_cal_target_power_leg { 1193 uint8_t tPow2x[4]; 1194 } __packed; 1195 1196 struct ar_cal_target_power_ht { 1197 uint8_t tPow2x[14]; 1198 } __packed; 1199