1 /* $OpenBSD: ar9285.c,v 1.22 2014/12/19 22:44:58 guenther Exp $ */ 2 3 /*- 4 * Copyright (c) 2009-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 * Routines for AR9285 and AR9271 chipsets. 23 */ 24 25 #include "athn_usb.h" 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/queue.h> 36 #include <sys/timeout.h> 37 #include <sys/conf.h> 38 #include <sys/device.h> 39 #include <sys/endian.h> 40 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/if_ether.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_amrr.h> 58 #include <net80211/ieee80211_radiotap.h> 59 60 #include <dev/ic/athnreg.h> 61 #include <dev/ic/athnvar.h> 62 63 #include <dev/ic/ar5008reg.h> 64 #include <dev/ic/ar9280reg.h> 65 #include <dev/ic/ar9285reg.h> 66 67 int ar9285_attach(struct athn_softc *); 68 void ar9285_setup(struct athn_softc *); 69 void ar9285_swap_rom(struct athn_softc *); 70 const struct ar_spur_chan *ar9285_get_spur_chans(struct athn_softc *, int); 71 void ar9285_init_from_rom(struct athn_softc *, struct ieee80211_channel *, 72 struct ieee80211_channel *); 73 void ar9285_pa_calib(struct athn_softc *); 74 void ar9271_pa_calib(struct athn_softc *); 75 int ar9285_cl_cal(struct athn_softc *, struct ieee80211_channel *, 76 struct ieee80211_channel *); 77 void ar9271_load_ani(struct athn_softc *); 78 int ar9285_init_calib(struct athn_softc *, struct ieee80211_channel *, 79 struct ieee80211_channel *); 80 void ar9285_get_pdadcs(struct athn_softc *, struct ieee80211_channel *, 81 int, uint8_t, uint8_t *, uint8_t *); 82 void ar9285_set_power_calib(struct athn_softc *, 83 struct ieee80211_channel *); 84 void ar9285_set_txpower(struct athn_softc *, struct ieee80211_channel *, 85 struct ieee80211_channel *); 86 87 /* Extern functions. */ 88 uint8_t athn_chan2fbin(struct ieee80211_channel *); 89 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *); 90 int ar5008_attach(struct athn_softc *); 91 void ar5008_write_txpower(struct athn_softc *, int16_t power[]); 92 void ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *, 93 struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *); 94 void ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *, 95 uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]); 96 void ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *, 97 uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]); 98 int ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *, 99 struct ieee80211_channel *); 100 void ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *, 101 struct ieee80211_channel *); 102 103 104 int 105 ar9285_attach(struct athn_softc *sc) 106 { 107 sc->eep_base = AR9285_EEP_START_LOC; 108 sc->eep_size = sizeof(struct ar9285_eeprom); 109 sc->def_nf = AR9285_PHY_CCA_MAX_GOOD_VALUE; 110 sc->ngpiopins = (sc->flags & ATHN_FLAG_USB) ? 16 : 12; 111 sc->led_pin = (sc->flags & ATHN_FLAG_USB) ? 15 : 1; 112 sc->workaround = AR9285_WA_DEFAULT; 113 sc->ops.setup = ar9285_setup; 114 sc->ops.swap_rom = ar9285_swap_rom; 115 sc->ops.init_from_rom = ar9285_init_from_rom; 116 sc->ops.set_txpower = ar9285_set_txpower; 117 sc->ops.set_synth = ar9280_set_synth; 118 sc->ops.spur_mitigate = ar9280_spur_mitigate; 119 sc->ops.get_spur_chans = ar9285_get_spur_chans; 120 #if NATHN_USB > 0 121 if (AR_SREV_9271(sc)) 122 sc->ini = &ar9271_ini; 123 else 124 #endif 125 sc->ini = &ar9285_1_2_ini; 126 sc->serdes = &ar9280_2_0_serdes; 127 128 return (ar5008_attach(sc)); 129 } 130 131 void 132 ar9285_setup(struct athn_softc *sc) 133 { 134 const struct ar9285_eeprom *eep = sc->eep; 135 uint8_t type; 136 137 /* Select initialization values based on ROM. */ 138 type = eep->baseEepHeader.txGainType; 139 DPRINTF(("Tx gain type=0x%x\n", type)); 140 #if NATHN_USB > 0 141 if (AR_SREV_9271(sc)) { 142 if (type == AR_EEP_TXGAIN_HIGH_POWER) 143 sc->tx_gain = &ar9271_tx_gain_high_power; 144 else 145 sc->tx_gain = &ar9271_tx_gain; 146 } else 147 #endif /* NATHN_USB */ 148 if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) { /* XE rev. */ 149 if (type == AR_EEP_TXGAIN_HIGH_POWER) 150 sc->tx_gain = &ar9285_2_0_tx_gain_high_power; 151 else 152 sc->tx_gain = &ar9285_2_0_tx_gain; 153 } else { 154 if (type == AR_EEP_TXGAIN_HIGH_POWER) 155 sc->tx_gain = &ar9285_1_2_tx_gain_high_power; 156 else 157 sc->tx_gain = &ar9285_1_2_tx_gain; 158 } 159 } 160 161 void 162 ar9285_swap_rom(struct athn_softc *sc) 163 { 164 struct ar9285_eeprom *eep = sc->eep; 165 int i; 166 167 eep->modalHeader.antCtrlCommon = 168 swap32(eep->modalHeader.antCtrlCommon); 169 eep->modalHeader.antCtrlChain = 170 swap32(eep->modalHeader.antCtrlChain); 171 172 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 173 eep->modalHeader.spurChans[i].spurChan = 174 swap16(eep->modalHeader.spurChans[i].spurChan); 175 } 176 } 177 178 const struct ar_spur_chan * 179 ar9285_get_spur_chans(struct athn_softc *sc, int is2ghz) 180 { 181 const struct ar9285_eeprom *eep = sc->eep; 182 183 KASSERT(is2ghz); 184 return (eep->modalHeader.spurChans); 185 } 186 187 void 188 ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 189 struct ieee80211_channel *extc) 190 { 191 const struct ar9285_eeprom *eep = sc->eep; 192 const struct ar9285_modal_eep_header *modal = &eep->modalHeader; 193 uint32_t reg, offset = 0x1000; 194 uint8_t ob[5], db1[5], db2[5]; 195 uint8_t txRxAtten; 196 197 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 198 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain); 199 200 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0); 201 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI); 202 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ); 203 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg); 204 205 if (sc->eep_rev >= AR_EEP_MINOR_VER_3) { 206 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ); 207 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 208 modal->bswMargin); 209 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 210 modal->bswAtten); 211 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 212 modal->xatten2Margin); 213 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 214 modal->xatten2Db); 215 AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg); 216 217 /* Duplicate values of chain 0 for chain 1. */ 218 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 219 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 220 modal->bswMargin); 221 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 222 modal->bswAtten); 223 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 224 modal->xatten2Margin); 225 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 226 modal->xatten2Db); 227 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 228 } 229 if (sc->eep_rev >= AR_EEP_MINOR_VER_3) 230 txRxAtten = modal->txRxAtten; 231 else /* Workaround for ROM versions < 14.3. */ 232 txRxAtten = 23; 233 reg = AR_READ(sc, AR_PHY_RXGAIN); 234 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); 235 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin); 236 AR_WRITE(sc, AR_PHY_RXGAIN, reg); 237 238 /* Duplicate values of chain 0 for chain 1. */ 239 reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 240 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); 241 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin); 242 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 243 244 if (modal->version >= 3) { 245 /* Setup antenna diversity from ROM. */ 246 reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); 247 reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0); 248 reg = RW(reg, AR9285_PHY_ANT_DIV_CTL, 249 (modal->ob_234 >> 12) & 0x1); 250 reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF, 251 (modal->db1_234 >> 12) & 0x3); 252 reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF, 253 (modal->db1_234 >> 14) & 0x3); 254 reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB, 255 (modal->ob_234 >> 13) & 0x1); 256 reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB, 257 (modal->ob_234 >> 14) & 0x1); 258 AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg); 259 reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */ 260 261 reg = AR_READ(sc, AR_PHY_CCK_DETECT); 262 if (modal->ob_234 & (1 << 15)) 263 reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 264 else 265 reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 266 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); 267 reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */ 268 } 269 if (modal->version >= 2) { 270 ob [0] = (modal->ob_01 >> 0) & 0xf; 271 ob [1] = (modal->ob_01 >> 4) & 0xf; 272 ob [2] = (modal->ob_234 >> 0) & 0xf; 273 ob [3] = (modal->ob_234 >> 4) & 0xf; 274 ob [4] = (modal->ob_234 >> 8) & 0xf; 275 276 db1[0] = (modal->db1_01 >> 0) & 0xf; 277 db1[1] = (modal->db1_01 >> 4) & 0xf; 278 db1[2] = (modal->db1_234 >> 0) & 0xf; 279 db1[3] = (modal->db1_234 >> 4) & 0xf; 280 db1[4] = (modal->db1_234 >> 8) & 0xf; 281 282 db2[0] = (modal->db2_01 >> 0) & 0xf; 283 db2[1] = (modal->db2_01 >> 4) & 0xf; 284 db2[2] = (modal->db2_234 >> 0) & 0xf; 285 db2[3] = (modal->db2_234 >> 4) & 0xf; 286 db2[4] = (modal->db2_234 >> 8) & 0xf; 287 288 } else if (modal->version == 1) { 289 ob [0] = (modal->ob_01 >> 0) & 0xf; 290 ob [1] = (modal->ob_01 >> 4) & 0xf; 291 /* Field ob_234 does not exist, use ob_01. */ 292 ob [2] = ob [3] = ob [4] = ob [1]; 293 294 db1[0] = (modal->db1_01 >> 0) & 0xf; 295 db1[1] = (modal->db1_01 >> 4) & 0xf; 296 /* Field db1_234 does not exist, use db1_01. */ 297 db1[2] = db1[3] = db1[4] = db1[1]; 298 299 db2[0] = (modal->db2_01 >> 0) & 0xf; 300 db2[1] = (modal->db2_01 >> 4) & 0xf; 301 /* Field db2_234 does not exist, use db2_01. */ 302 db2[2] = db2[3] = db2[4] = db2[1]; 303 304 } else { 305 ob [0] = modal->ob_01; 306 ob [1] = ob [2] = ob [3] = ob [4] = ob [0]; 307 308 db1[0] = modal->db1_01; 309 db1[1] = db1[2] = db1[3] = db1[4] = db1[0]; 310 311 /* Field db2_01 does not exist, use db1_01. */ 312 db2[0] = modal->db1_01; 313 db2[1] = db2[2] = db2[3] = db2[4] = db2[0]; 314 } 315 #if NATHN_USB > 0 316 if (AR_SREV_9271(sc)) { 317 reg = AR_READ(sc, AR9285_AN_RF2G3); 318 reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]); 319 reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]); 320 reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]); 321 reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]); 322 AR_WRITE(sc, AR9285_AN_RF2G3, reg); 323 AR_WRITE_BARRIER(sc); 324 DELAY(100); 325 reg = AR_READ(sc, AR9285_AN_RF2G4); 326 reg = RW(reg, AR9271_AN_RF2G4_DB2, db2[0]); 327 AR_WRITE(sc, AR9285_AN_RF2G4, reg); 328 AR_WRITE_BARRIER(sc); 329 DELAY(100); 330 } else 331 #endif /* ATHN_USB */ 332 { 333 reg = AR_READ(sc, AR9285_AN_RF2G3); 334 reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]); 335 reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]); 336 reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]); 337 reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]); 338 reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]); 339 reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]); 340 reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]); 341 reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]); 342 AR_WRITE(sc, AR9285_AN_RF2G3, reg); 343 AR_WRITE_BARRIER(sc); 344 DELAY(100); 345 reg = AR_READ(sc, AR9285_AN_RF2G4); 346 reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]); 347 reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]); 348 reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]); 349 reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]); 350 reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]); 351 reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]); 352 reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]); 353 AR_WRITE(sc, AR9285_AN_RF2G4, reg); 354 AR_WRITE_BARRIER(sc); 355 DELAY(100); 356 } 357 358 reg = AR_READ(sc, AR_PHY_SETTLING); 359 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 360 AR_WRITE(sc, AR_PHY_SETTLING, reg); 361 362 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 363 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 364 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 365 366 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 367 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 368 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 369 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 370 AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 371 372 reg = AR_READ(sc, AR_PHY_RF_CTL3); 373 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 374 AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 375 376 reg = AR_READ(sc, AR_PHY_CCA(0)); 377 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); 378 AR_WRITE(sc, AR_PHY_CCA(0), reg); 379 380 reg = AR_READ(sc, AR_PHY_EXT_CCA0); 381 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); 382 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); 383 384 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) { 385 reg = AR_READ(sc, AR_PHY_RF_CTL2); 386 reg = RW(reg, AR_PHY_TX_END_PA_ON, 387 modal->txFrameToPaOn); 388 reg = RW(reg, AR_PHY_TX_END_DATA_START, 389 modal->txFrameToDataStart); 390 AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 391 } 392 #ifndef IEEE80211_NO_HT 393 if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) { 394 reg = AR_READ(sc, AR_PHY_SETTLING); 395 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 396 AR_WRITE(sc, AR_PHY_SETTLING, reg); 397 } 398 #endif 399 AR_WRITE_BARRIER(sc); 400 } 401 402 void 403 ar9285_pa_calib(struct athn_softc *sc) 404 { 405 /* List of registers that need to be saved/restored. */ 406 static const uint16_t regs[] = { 407 AR9285_AN_TOP3, 408 AR9285_AN_RXTXBB1, 409 AR9285_AN_RF2G1, 410 AR9285_AN_RF2G2, 411 AR9285_AN_TOP2, 412 AR9285_AN_RF2G8, 413 AR9285_AN_RF2G7 414 }; 415 uint32_t svg[7], reg, ccomp_svg; 416 int i; 417 418 /* No PA calibration needed for high power solutions. */ 419 if (AR_SREV_9285(sc) && 420 ((struct ar9285_base_eep_header *)sc->eep)->txGainType == 421 AR_EEP_TXGAIN_HIGH_POWER) /* XXX AR9287? */ 422 return; 423 424 /* Save registers. */ 425 for (i = 0; i < nitems(regs); i++) 426 svg[i] = AR_READ(sc, regs[i]); 427 428 AR_CLRBITS(sc, AR9285_AN_RF2G6, 1); 429 AR_SETBITS(sc, AR_PHY(2), 1 << 27); 430 431 AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); 432 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); 433 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); 434 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); 435 AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); 436 AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); 437 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); 438 /* Power down PA drivers. */ 439 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); 440 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); 441 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); 442 443 reg = AR_READ(sc, AR9285_AN_RF2G8); 444 reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); 445 AR_WRITE(sc, AR9285_AN_RF2G8, reg); 446 447 reg = AR_READ(sc, AR9285_AN_RF2G7); 448 reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); 449 AR_WRITE(sc, AR9285_AN_RF2G7, reg); 450 451 reg = AR_READ(sc, AR9285_AN_RF2G6); 452 /* Save compensation capacitor value. */ 453 ccomp_svg = MS(reg, AR9285_AN_RF2G6_CCOMP); 454 /* Program compensation capacitor for dynamic PA. */ 455 reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf); 456 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 457 458 AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT); 459 AR_WRITE_BARRIER(sc); 460 DELAY(30); 461 462 /* Clear offsets 6-1. */ 463 AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS_6_1); 464 /* Clear offset 0. */ 465 AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 466 /* Set offsets 6-1. */ 467 for (i = 6; i >= 1; i--) { 468 AR_SETBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS(i)); 469 AR_WRITE_BARRIER(sc); 470 DELAY(1); 471 if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) { 472 AR_SETBITS(sc, AR9285_AN_RF2G6, 473 AR9285_AN_RF2G6_OFFS(i)); 474 } else { 475 AR_CLRBITS(sc, AR9285_AN_RF2G6, 476 AR9285_AN_RF2G6_OFFS(i)); 477 } 478 } 479 /* Set offset 0. */ 480 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 481 AR_WRITE_BARRIER(sc); 482 DELAY(1); 483 if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) 484 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 485 else 486 AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP); 487 488 AR_WRITE_BARRIER(sc); 489 490 AR_SETBITS(sc, AR9285_AN_RF2G6, 1); 491 AR_CLRBITS(sc, AR_PHY(2), 1 << 27); 492 493 /* Restore registers. */ 494 for (i = 0; i < nitems(regs); i++) 495 AR_WRITE(sc, regs[i], svg[i]); 496 497 /* Restore compensation capacitor value. */ 498 reg = AR_READ(sc, AR9285_AN_RF2G6); 499 reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg); 500 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 501 AR_WRITE_BARRIER(sc); 502 } 503 504 void 505 ar9271_pa_calib(struct athn_softc *sc) 506 { 507 #if NATHN_USB > 0 508 /* List of registers that need to be saved/restored. */ 509 static const uint16_t regs[] = { 510 AR9285_AN_TOP3, 511 AR9285_AN_RXTXBB1, 512 AR9285_AN_RF2G1, 513 AR9285_AN_RF2G2, 514 AR9285_AN_TOP2, 515 AR9285_AN_RF2G8, 516 AR9285_AN_RF2G7 517 }; 518 uint32_t svg[7], reg, rf2g3_svg; 519 int i; 520 521 /* Save registers. */ 522 for (i = 0; i < nitems(regs); i++) 523 svg[i] = AR_READ(sc, regs[i]); 524 525 AR_CLRBITS(sc, AR9285_AN_RF2G6, 1); 526 AR_SETBITS(sc, AR_PHY(2), 1 << 27); 527 528 AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); 529 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); 530 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); 531 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); 532 AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); 533 AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); 534 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); 535 /* Power down PA drivers. */ 536 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); 537 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); 538 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); 539 540 reg = AR_READ(sc, AR9285_AN_RF2G8); 541 reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); 542 AR_WRITE(sc, AR9285_AN_RF2G8, reg); 543 544 reg = AR_READ(sc, AR9285_AN_RF2G7); 545 reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); 546 AR_WRITE(sc, AR9285_AN_RF2G7, reg); 547 548 /* Save compensation capacitor value. */ 549 reg = rf2g3_svg = AR_READ(sc, AR9285_AN_RF2G3); 550 /* Program compensation capacitor for dynamic PA. */ 551 reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff); 552 AR_WRITE(sc, AR9285_AN_RF2G3, reg); 553 554 AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT); 555 AR_WRITE_BARRIER(sc); 556 DELAY(30); 557 558 /* Clear offsets 6-0. */ 559 AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS_6_0); 560 /* Set offsets 6-1. */ 561 for (i = 6; i >= 1; i--) { 562 reg = AR_READ(sc, AR9285_AN_RF2G6); 563 reg |= AR9271_AN_RF2G6_OFFS(i); 564 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 565 AR_WRITE_BARRIER(sc); 566 DELAY(1); 567 if (!(AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9)) 568 reg &= ~AR9271_AN_RF2G6_OFFS(i); 569 AR_WRITE(sc, AR9285_AN_RF2G6, reg); 570 } 571 AR_WRITE_BARRIER(sc); 572 573 AR_SETBITS(sc, AR9285_AN_RF2G6, 1); 574 AR_CLRBITS(sc, AR_PHY(2), 1 << 27); 575 576 /* Restore registers. */ 577 for (i = 0; i < nitems(regs); i++) 578 AR_WRITE(sc, regs[i], svg[i]); 579 580 /* Restore compensation capacitor value. */ 581 AR_WRITE(sc, AR9285_AN_RF2G3, rf2g3_svg); 582 AR_WRITE_BARRIER(sc); 583 #endif /* NATHN_USB */ 584 } 585 586 /* 587 * Carrier Leakage Calibration. 588 */ 589 int 590 ar9285_cl_cal(struct athn_softc *sc, struct ieee80211_channel *c, 591 struct ieee80211_channel *extc) 592 { 593 int ntries; 594 595 AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 596 #ifndef IEEE80211_NO_HT 597 if (0 && extc == NULL) { /* XXX IS_CHAN_HT20!! */ 598 AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); 599 AR_SETBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 600 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, 601 AR_PHY_AGC_CONTROL_FLTR_CAL); 602 AR_CLRBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); 603 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 604 for (ntries = 0; ntries < 10000; ntries++) { 605 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & 606 AR_PHY_AGC_CONTROL_CAL)) 607 break; 608 DELAY(10); 609 } 610 if (ntries == 10000) 611 return (ETIMEDOUT); 612 AR_CLRBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 613 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); 614 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 615 } 616 #endif 617 AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); 618 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); 619 AR_SETBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); 620 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 621 for (ntries = 0; ntries < 10000; ntries++) { 622 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & 623 AR_PHY_AGC_CONTROL_CAL)) 624 break; 625 DELAY(10); 626 } 627 if (ntries == 10000) 628 return (ETIMEDOUT); 629 AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); 630 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 631 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); 632 AR_WRITE_BARRIER(sc); 633 return (0); 634 } 635 636 void 637 ar9271_load_ani(struct athn_softc *sc) 638 { 639 #if NATHN_USB > 0 640 /* Write ANI registers. */ 641 AR_WRITE(sc, AR_PHY_DESIRED_SZ, 0x6d4000e2); 642 AR_WRITE(sc, AR_PHY_AGC_CTL1, 0x3139605e); 643 AR_WRITE(sc, AR_PHY_FIND_SIG, 0x7ec84d2e); 644 AR_WRITE(sc, AR_PHY_SFCORR_LOW, 0x06903881); 645 AR_WRITE(sc, AR_PHY_SFCORR, 0x5ac640d0); 646 AR_WRITE(sc, AR_PHY_CCK_DETECT, 0x803e68c8); 647 AR_WRITE(sc, AR_PHY_TIMING5, 0xd00a8007); 648 AR_WRITE(sc, AR_PHY_SFCORR_EXT, 0x05eea6d4); 649 AR_WRITE_BARRIER(sc); 650 #endif /* NATHN_USB */ 651 } 652 653 int 654 ar9285_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, 655 struct ieee80211_channel *extc) 656 { 657 uint32_t reg, mask, clcgain, rf2g5_svg; 658 int i, maxgain, nclcs, thresh, error; 659 660 /* Do carrier leakage calibration. */ 661 if ((error = ar9285_cl_cal(sc, c, extc)) != 0) 662 return (error); 663 664 /* Workaround for high temperature is not applicable on AR9271. */ 665 if (AR_SREV_9271(sc)) 666 return (0); 667 668 mask = 0; 669 nclcs = 0; 670 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7); 671 maxgain = MS(reg, AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX); 672 for (i = 0; i <= maxgain; i++) { 673 reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i)); 674 clcgain = MS(reg, AR_PHY_TX_GAIN_CLC); 675 /* NB: clcgain <= 0xf. */ 676 if (!(mask & (1 << clcgain))) { 677 mask |= 1 << clcgain; 678 nclcs++; 679 } 680 } 681 thresh = 0; 682 for (i = 0; i < nclcs; i++) { 683 reg = AR_READ(sc, AR_PHY_CLC_TBL(i)); 684 if (MS(reg, AR_PHY_CLC_I0) == 0) 685 thresh++; 686 if (MS(reg, AR_PHY_CLC_Q0) == 0) 687 thresh++; 688 } 689 if (thresh <= AR9285_CL_CAL_REDO_THRESH) 690 return (0); /* No need to redo. */ 691 692 /* Threshold reached, redo carrier leakage calibration. */ 693 DPRINTFN(2, ("CLC threshold=%d\n", thresh)); 694 rf2g5_svg = reg = AR_READ(sc, AR9285_AN_RF2G5); 695 if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) /* XE rev. */ 696 reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5); 697 else 698 reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4); 699 AR_WRITE(sc, AR9285_AN_RF2G5, reg); 700 AR_WRITE_BARRIER(sc); 701 error = ar9285_cl_cal(sc, c, extc); 702 AR_WRITE(sc, AR9285_AN_RF2G5, rf2g5_svg); 703 AR_WRITE_BARRIER(sc); 704 return (error); 705 } 706 707 void 708 ar9285_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 709 int nxpdgains, uint8_t overlap, uint8_t *boundaries, uint8_t *pdadcs) 710 { 711 const struct ar9285_eeprom *eep = sc->eep; 712 const struct ar9285_cal_data_per_freq *pierdata; 713 const uint8_t *pierfreq; 714 struct athn_pier lopier, hipier; 715 uint8_t fbin; 716 int i, lo, hi, npiers; 717 718 pierfreq = eep->calFreqPier2G; 719 pierdata = eep->calPierData2G; 720 npiers = AR9285_NUM_2G_CAL_PIERS; 721 722 /* Find channel in ROM pier table. */ 723 fbin = athn_chan2fbin(c); 724 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 725 726 lopier.fbin = pierfreq[lo]; 727 hipier.fbin = pierfreq[hi]; 728 for (i = 0; i < nxpdgains; i++) { 729 lopier.pwr[i] = pierdata[lo].pwrPdg[i]; 730 lopier.vpd[i] = pierdata[lo].vpdPdg[i]; 731 hipier.pwr[i] = pierdata[lo].pwrPdg[i]; 732 hipier.vpd[i] = pierdata[lo].vpdPdg[i]; 733 } 734 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains, 735 AR9285_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs); 736 } 737 738 void 739 ar9285_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c) 740 { 741 const struct ar9285_eeprom *eep = sc->eep; 742 uint8_t boundaries[AR_PD_GAINS_IN_MASK]; 743 uint8_t pdadcs[AR_NUM_PDADC_VALUES]; 744 uint8_t xpdgains[AR9285_NUM_PD_GAINS]; 745 uint8_t overlap; 746 uint32_t reg; 747 int i, nxpdgains; 748 749 if (sc->eep_rev < AR_EEP_MINOR_VER_2) { 750 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5), 751 AR_PHY_TPCRG5_PD_GAIN_OVERLAP); 752 } else 753 overlap = eep->modalHeader.pdGainOverlap; 754 755 nxpdgains = 0; 756 memset(xpdgains, 0, sizeof(xpdgains)); 757 for (i = AR9285_PD_GAINS_IN_MASK - 1; i >= 0; i--) { 758 if (nxpdgains >= AR9285_NUM_PD_GAINS) 759 break; 760 if (eep->modalHeader.xpdGain & (1 << i)) 761 xpdgains[nxpdgains++] = i; 762 } 763 reg = AR_READ(sc, AR_PHY_TPCRG1); 764 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1); 765 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); 766 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]); 767 AR_WRITE(sc, AR_PHY_TPCRG1, reg); 768 769 /* NB: No open loop power control for AR9285. */ 770 ar9285_get_pdadcs(sc, c, nxpdgains, overlap, boundaries, pdadcs); 771 772 /* Write boundaries. */ 773 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, overlap); 774 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, boundaries[0]); 775 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, boundaries[1]); 776 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, boundaries[2]); 777 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, boundaries[3]); 778 AR_WRITE(sc, AR_PHY_TPCRG5, reg); 779 780 /* Write PDADC values. */ 781 for (i = 0; i < AR_NUM_PDADC_VALUES; i += 4) { 782 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + i, 783 pdadcs[i + 0] << 0 | 784 pdadcs[i + 1] << 8 | 785 pdadcs[i + 2] << 16 | 786 pdadcs[i + 3] << 24); 787 } 788 AR_WRITE_BARRIER(sc); 789 } 790 791 void 792 ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 793 struct ieee80211_channel *extc) 794 { 795 const struct ar9285_eeprom *eep = sc->eep; 796 const struct ar9285_modal_eep_header *modal = &eep->modalHeader; 797 uint8_t tpow_cck[4], tpow_ofdm[4]; 798 #ifndef IEEE80211_NO_HT 799 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4]; 800 uint8_t tpow_ht20[8], tpow_ht40[8]; 801 uint8_t ht40inc; 802 #endif 803 int16_t max_ant_gain, power[ATHN_POWER_COUNT]; 804 int i; 805 806 ar9285_set_power_calib(sc, c); 807 808 /* Compute transmit power reduction due to antenna gain. */ 809 max_ant_gain = modal->antennaGain; 810 /* XXX */ 811 812 /* Get CCK target powers. */ 813 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck, 814 AR9285_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 815 816 /* Get OFDM target powers. */ 817 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G, 818 AR9285_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 819 820 #ifndef IEEE80211_NO_HT 821 /* Get HT-20 target powers. */ 822 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20, 823 AR9285_NUM_2G_20_TARGET_POWERS, tpow_ht20); 824 825 if (extc != NULL) { 826 /* Get HT-40 target powers. */ 827 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40, 828 eep->calTargetPower2GHT40, AR9285_NUM_2G_40_TARGET_POWERS, 829 tpow_ht40); 830 831 /* Get secondary channel CCK target powers. */ 832 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B, 833 eep->calTargetPowerCck, AR9285_NUM_2G_CCK_TARGET_POWERS, 834 tpow_cck_ext); 835 836 /* Get secondary channel OFDM target powers. */ 837 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G, 838 eep->calTargetPower2G, AR9285_NUM_2G_20_TARGET_POWERS, 839 tpow_ofdm_ext); 840 } 841 #endif 842 843 memset(power, 0, sizeof(power)); 844 /* Shuffle target powers accross transmit rates. */ 845 power[ATHN_POWER_OFDM6 ] = 846 power[ATHN_POWER_OFDM9 ] = 847 power[ATHN_POWER_OFDM12 ] = 848 power[ATHN_POWER_OFDM18 ] = 849 power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0]; 850 power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1]; 851 power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2]; 852 power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3]; 853 power[ATHN_POWER_XR ] = tpow_ofdm[0]; 854 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0]; 855 power[ATHN_POWER_CCK2_LP ] = 856 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1]; 857 power[ATHN_POWER_CCK55_LP] = 858 power[ATHN_POWER_CCK55_SP] = tpow_cck[2]; 859 power[ATHN_POWER_CCK11_LP] = 860 power[ATHN_POWER_CCK11_SP] = tpow_cck[3]; 861 #ifndef IEEE80211_NO_HT 862 for (i = 0; i < nitems(tpow_ht20); i++) 863 power[ATHN_POWER_HT20(i)] = tpow_ht20[i]; 864 if (extc != NULL) { 865 /* Correct PAR difference between HT40 and HT20/Legacy. */ 866 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) 867 ht40inc = modal->ht40PowerIncForPdadc; 868 else 869 ht40inc = AR_HT40_POWER_INC_FOR_PDADC; 870 for (i = 0; i < nitems(tpow_ht40); i++) 871 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc; 872 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0]; 873 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0]; 874 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0]; 875 power[ATHN_POWER_CCK_EXT ] = tpow_cck_ext[0]; 876 } 877 #endif 878 879 for (i = 0; i < ATHN_POWER_COUNT; i++) { 880 power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */ 881 if (power[i] > AR_MAX_RATE_POWER) 882 power[i] = AR_MAX_RATE_POWER; 883 } 884 885 /* Commit transmit power values to hardware. */ 886 ar5008_write_txpower(sc, power); 887 } 888