1 /* $OpenBSD: ar9287.c,v 1.16 2010/12/31 17:50:48 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 * Routines for AR9227 and AR9287 chipsets. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 39 #include <machine/bus.h> 40 #include <machine/endian.h> 41 #include <machine/intr.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/if_ether.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/ic/athnreg.h> 63 #include <dev/ic/athnvar.h> 64 65 #include <dev/ic/ar5008reg.h> 66 #include <dev/ic/ar9280reg.h> 67 #include <dev/ic/ar9287reg.h> 68 69 int ar9287_attach(struct athn_softc *); 70 void ar9287_setup(struct athn_softc *); 71 void ar9287_swap_rom(struct athn_softc *); 72 const struct ar_spur_chan *ar9287_get_spur_chans(struct athn_softc *, int); 73 void ar9287_init_from_rom(struct athn_softc *, struct ieee80211_channel *, 74 struct ieee80211_channel *); 75 void ar9287_get_pdadcs(struct athn_softc *, struct ieee80211_channel *, 76 int, int, uint8_t, uint8_t *, uint8_t *); 77 void ar9287_olpc_get_pdgain(struct athn_softc *, struct ieee80211_channel *, 78 int, int8_t *); 79 void ar9287_set_power_calib(struct athn_softc *, 80 struct ieee80211_channel *); 81 void ar9287_set_txpower(struct athn_softc *, struct ieee80211_channel *, 82 struct ieee80211_channel *); 83 void ar9287_olpc_init(struct athn_softc *); 84 void ar9287_olpc_temp_compensation(struct athn_softc *); 85 void ar9287_1_3_enable_async_fifo(struct athn_softc *); 86 void ar9287_1_3_setup_async_fifo(struct athn_softc *); 87 88 /* Extern functions. */ 89 uint8_t athn_chan2fbin(struct ieee80211_channel *); 90 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *); 91 int ar5008_attach(struct athn_softc *); 92 void ar5008_write_txpower(struct athn_softc *, int16_t power[]); 93 void ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *, 94 struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *); 95 void ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *, 96 uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]); 97 void ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *, 98 uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]); 99 int ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *, 100 struct ieee80211_channel *); 101 void ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *, 102 struct ieee80211_channel *); 103 104 105 int 106 ar9287_attach(struct athn_softc *sc) 107 { 108 sc->eep_base = AR9287_EEP_START_LOC; 109 sc->eep_size = sizeof(struct ar9287_eeprom); 110 sc->def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE; 111 sc->ngpiopins = (sc->flags & ATHN_FLAG_USB) ? 16 : 11; 112 sc->led_pin = 8; 113 sc->workaround = AR9285_WA_DEFAULT; 114 sc->ops.setup = ar9287_setup; 115 sc->ops.swap_rom = ar9287_swap_rom; 116 sc->ops.init_from_rom = ar9287_init_from_rom; 117 sc->ops.set_txpower = ar9287_set_txpower; 118 sc->ops.set_synth = ar9280_set_synth; 119 sc->ops.spur_mitigate = ar9280_spur_mitigate; 120 sc->ops.get_spur_chans = ar9287_get_spur_chans; 121 sc->ops.olpc_init = ar9287_olpc_init; 122 sc->ops.olpc_temp_compensation = ar9287_olpc_temp_compensation; 123 sc->ini = &ar9287_1_1_ini; 124 sc->serdes = ar9280_2_0_serdes; 125 126 return (ar5008_attach(sc)); 127 } 128 129 void 130 ar9287_setup(struct athn_softc *sc) 131 { 132 const struct ar9287_eeprom *eep = sc->eep; 133 134 /* Determine if open loop power control should be used. */ 135 if (eep->baseEepHeader.openLoopPwrCntl) 136 sc->flags |= ATHN_FLAG_OLPC; 137 138 sc->rx_gain = &ar9287_1_1_rx_gain; 139 sc->tx_gain = &ar9287_1_1_tx_gain; 140 } 141 142 void 143 ar9287_swap_rom(struct athn_softc *sc) 144 { 145 struct ar9287_eeprom *eep = sc->eep; 146 int i; 147 148 eep->modalHeader.antCtrlCommon = 149 swap32(eep->modalHeader.antCtrlCommon); 150 151 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 152 eep->modalHeader.antCtrlChain[i] = 153 swap32(eep->modalHeader.antCtrlChain[i]); 154 } 155 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 156 eep->modalHeader.spurChans[i].spurChan = 157 swap16(eep->modalHeader.spurChans[i].spurChan); 158 } 159 } 160 161 const struct ar_spur_chan * 162 ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz) 163 { 164 const struct ar9287_eeprom *eep = sc->eep; 165 166 KASSERT(is2ghz); 167 return (eep->modalHeader.spurChans); 168 } 169 170 void 171 ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 172 struct ieee80211_channel *extc) 173 { 174 const struct ar9287_eeprom *eep = sc->eep; 175 const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 176 uint32_t reg, offset; 177 int i; 178 179 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 180 181 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 182 offset = i * 0x1000; 183 184 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, 185 modal->antCtrlChain[i]); 186 187 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); 188 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 189 modal->iqCalICh[i]); 190 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 191 modal->iqCalQCh[i]); 192 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); 193 194 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 195 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 196 modal->bswMargin[i]); 197 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 198 modal->bswAtten[i]); 199 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 200 201 reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 202 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, 203 modal->rxTxMarginCh[i]); 204 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, 205 modal->txRxAttenCh[i]); 206 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 207 } 208 209 reg = AR_READ(sc, AR_PHY_SETTLING); 210 #ifndef IEEE80211_NO_HT 211 if (extc != NULL) 212 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 213 else 214 #endif 215 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 216 AR_WRITE(sc, AR_PHY_SETTLING, reg); 217 218 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 219 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 220 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 221 222 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 223 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 224 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 225 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 226 AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 227 228 reg = AR_READ(sc, AR_PHY_RF_CTL3); 229 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 230 AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 231 232 reg = AR_READ(sc, AR_PHY_CCA(0)); 233 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); 234 AR_WRITE(sc, AR_PHY_CCA(0), reg); 235 236 reg = AR_READ(sc, AR_PHY_EXT_CCA0); 237 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); 238 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); 239 240 reg = AR_READ(sc, AR9287_AN_RF2G3_CH0); 241 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 242 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 243 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 244 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 245 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 246 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 247 AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg); 248 AR_WRITE_BARRIER(sc); 249 DELAY(100); 250 251 reg = AR_READ(sc, AR9287_AN_RF2G3_CH1); 252 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 253 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 254 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 255 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 256 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 257 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 258 AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg); 259 AR_WRITE_BARRIER(sc); 260 DELAY(100); 261 262 reg = AR_READ(sc, AR_PHY_RF_CTL2); 263 reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart); 264 reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); 265 AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 266 267 reg = AR_READ(sc, AR9287_AN_TOP2); 268 reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl); 269 AR_WRITE(sc, AR9287_AN_TOP2, reg); 270 AR_WRITE_BARRIER(sc); 271 DELAY(100); 272 } 273 274 void 275 ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 276 int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries, 277 uint8_t *pdadcs) 278 { 279 const struct ar9287_eeprom *eep = sc->eep; 280 const struct ar9287_cal_data_per_freq *pierdata; 281 const uint8_t *pierfreq; 282 struct athn_pier lopier, hipier; 283 int16_t delta; 284 uint8_t fbin; 285 int i, lo, hi, npiers; 286 287 pierfreq = eep->calFreqPier2G; 288 pierdata = (const struct ar9287_cal_data_per_freq *) 289 eep->calPierData2G[chain]; 290 npiers = AR9287_NUM_2G_CAL_PIERS; 291 292 /* Find channel in ROM pier table. */ 293 fbin = athn_chan2fbin(c); 294 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 295 296 lopier.fbin = pierfreq[lo]; 297 hipier.fbin = pierfreq[hi]; 298 for (i = 0; i < nxpdgains; i++) { 299 lopier.pwr[i] = pierdata[lo].pwrPdg[i]; 300 lopier.vpd[i] = pierdata[lo].vpdPdg[i]; 301 hipier.pwr[i] = pierdata[lo].pwrPdg[i]; 302 hipier.vpd[i] = pierdata[lo].vpdPdg[i]; 303 } 304 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains, 305 AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs); 306 307 delta = (eep->baseEepHeader.pwrTableOffset - 308 AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */ 309 if (delta != 0) { 310 /* Shift the PDADC table to start at the new offset. */ 311 /* XXX Our padding value differs from Linux. */ 312 for (i = 0; i < AR_NUM_PDADC_VALUES; i++) 313 pdadcs[i] = pdadcs[MIN(i + delta, 314 AR_NUM_PDADC_VALUES - 1)]; 315 } 316 } 317 318 void 319 ar9287_olpc_get_pdgain(struct athn_softc *sc, struct ieee80211_channel *c, 320 int chain, int8_t *pwr) 321 { 322 const struct ar9287_eeprom *eep = sc->eep; 323 const struct ar_cal_data_per_freq_olpc *pierdata; 324 const uint8_t *pierfreq; 325 uint8_t fbin; 326 int lo, hi, npiers; 327 328 pierfreq = eep->calFreqPier2G; 329 pierdata = (const struct ar_cal_data_per_freq_olpc *) 330 eep->calPierData2G[chain]; 331 npiers = AR9287_NUM_2G_CAL_PIERS; 332 333 /* Find channel in ROM pier table. */ 334 fbin = athn_chan2fbin(c); 335 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 336 337 #if 0 338 *pwr = athn_interpolate(fbin, 339 pierfreq[lo], pierdata[lo].pwrPdg[0][0], 340 pierfreq[hi], pierdata[hi].pwrPdg[0][0]); 341 #else 342 *pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2; 343 #endif 344 } 345 346 void 347 ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c) 348 { 349 const struct ar9287_eeprom *eep = sc->eep; 350 uint8_t boundaries[AR_PD_GAINS_IN_MASK]; 351 uint8_t pdadcs[AR_NUM_PDADC_VALUES]; 352 uint8_t xpdgains[AR9287_NUM_PD_GAINS]; 353 int8_t txpower; 354 uint8_t overlap; 355 uint32_t reg, offset; 356 int i, j, nxpdgains; 357 358 if (sc->eep_rev < AR_EEP_MINOR_VER_2) { 359 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5), 360 AR_PHY_TPCRG5_PD_GAIN_OVERLAP); 361 } else 362 overlap = eep->modalHeader.pdGainOverlap; 363 364 if (sc->flags & ATHN_FLAG_OLPC) { 365 /* XXX not here. */ 366 sc->pdadc = 367 ((const struct ar_cal_data_per_freq_olpc *) 368 eep->calPierData2G[0])->vpdPdg[0][0]; 369 } 370 371 nxpdgains = 0; 372 memset(xpdgains, 0, sizeof(xpdgains)); 373 for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) { 374 if (nxpdgains >= AR9287_NUM_PD_GAINS) 375 break; /* Can't happen. */ 376 if (eep->modalHeader.xpdGain & (1 << i)) 377 xpdgains[nxpdgains++] = i; 378 } 379 reg = AR_READ(sc, AR_PHY_TPCRG1); 380 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1); 381 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); 382 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]); 383 AR_WRITE(sc, AR_PHY_TPCRG1, reg); 384 AR_WRITE_BARRIER(sc); 385 386 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 387 if (!(sc->txchainmask & (1 << i))) 388 continue; 389 390 offset = i * 0x1000; 391 392 if (sc->flags & ATHN_FLAG_OLPC) { 393 ar9287_olpc_get_pdgain(sc, c, i, &txpower); 394 395 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0); 396 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 397 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg); 398 399 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1); 400 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 401 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg); 402 403 /* NB: txpower is in half dB. */ 404 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset); 405 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower); 406 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg); 407 408 AR_WRITE_BARRIER(sc); 409 continue; /* That's it for open loop mode. */ 410 } 411 412 /* Closed loop power control. */ 413 ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap, 414 boundaries, pdadcs); 415 416 /* Write boundaries. */ 417 if (i == 0) { 418 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, 419 overlap); 420 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, 421 boundaries[0]); 422 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, 423 boundaries[1]); 424 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, 425 boundaries[2]); 426 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, 427 boundaries[3]); 428 AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg); 429 } 430 /* Write PDADC values. */ 431 for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) { 432 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j, 433 pdadcs[j + 0] << 0 | 434 pdadcs[j + 1] << 8 | 435 pdadcs[j + 2] << 16 | 436 pdadcs[j + 3] << 24); 437 } 438 AR_WRITE_BARRIER(sc); 439 } 440 } 441 442 void 443 ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 444 struct ieee80211_channel *extc) 445 { 446 const struct ar9287_eeprom *eep = sc->eep; 447 const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 448 uint8_t tpow_cck[4], tpow_ofdm[4]; 449 #ifndef IEEE80211_NO_HT 450 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4]; 451 uint8_t tpow_ht20[8], tpow_ht40[8]; 452 uint8_t ht40inc; 453 #endif 454 int16_t pwr = 0, max_ant_gain, power[ATHN_POWER_COUNT]; 455 int i; 456 457 ar9287_set_power_calib(sc, c); 458 459 /* Compute transmit power reduction due to antenna gain. */ 460 max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]); 461 /* XXX */ 462 463 /* 464 * Reduce scaled power by number of active chains to get per-chain 465 * transmit power level. 466 */ 467 if (sc->ntxchains == 2) 468 pwr -= AR_PWR_DECREASE_FOR_2_CHAIN; 469 if (pwr < 0) 470 pwr = 0; 471 472 /* Get CCK target powers. */ 473 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck, 474 AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 475 476 /* Get OFDM target powers. */ 477 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G, 478 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 479 480 #ifndef IEEE80211_NO_HT 481 /* Get HT-20 target powers. */ 482 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20, 483 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20); 484 485 if (extc != NULL) { 486 /* Get HT-40 target powers. */ 487 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40, 488 eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS, 489 tpow_ht40); 490 491 /* Get secondary channel CCK target powers. */ 492 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B, 493 eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS, 494 tpow_cck_ext); 495 496 /* Get secondary channel OFDM target powers. */ 497 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G, 498 eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS, 499 tpow_ofdm_ext); 500 } 501 #endif 502 503 memset(power, 0, sizeof(power)); 504 /* Shuffle target powers accross transmit rates. */ 505 power[ATHN_POWER_OFDM6 ] = 506 power[ATHN_POWER_OFDM9 ] = 507 power[ATHN_POWER_OFDM12 ] = 508 power[ATHN_POWER_OFDM18 ] = 509 power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0]; 510 power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1]; 511 power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2]; 512 power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3]; 513 power[ATHN_POWER_XR ] = tpow_ofdm[0]; 514 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0]; 515 power[ATHN_POWER_CCK2_LP ] = 516 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1]; 517 power[ATHN_POWER_CCK55_LP] = 518 power[ATHN_POWER_CCK55_SP] = tpow_cck[2]; 519 power[ATHN_POWER_CCK11_LP] = 520 power[ATHN_POWER_CCK11_SP] = tpow_cck[3]; 521 #ifndef IEEE80211_NO_HT 522 for (i = 0; i < nitems(tpow_ht20); i++) 523 power[ATHN_POWER_HT20(i)] = tpow_ht20[i]; 524 if (extc != NULL) { 525 /* Correct PAR difference between HT40 and HT20/Legacy. */ 526 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) 527 ht40inc = modal->ht40PowerIncForPdadc; 528 else 529 ht40inc = AR_HT40_POWER_INC_FOR_PDADC; 530 for (i = 0; i < nitems(tpow_ht40); i++) 531 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc; 532 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0]; 533 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0]; 534 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0]; 535 if (IEEE80211_IS_CHAN_2GHZ(c)) 536 power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0]; 537 } 538 #endif 539 540 for (i = 0; i < ATHN_POWER_COUNT; i++) { 541 power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */ 542 if (power[i] > AR_MAX_RATE_POWER) 543 power[i] = AR_MAX_RATE_POWER; 544 } 545 /* Commit transmit power values to hardware. */ 546 ar5008_write_txpower(sc, power); 547 } 548 549 void 550 ar9287_olpc_init(struct athn_softc *sc) 551 { 552 uint32_t reg; 553 554 AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); 555 556 reg = AR_READ(sc, AR9287_AN_TXPC0); 557 reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE, 558 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); 559 AR_WRITE(sc, AR9287_AN_TXPC0, reg); 560 AR_WRITE_BARRIER(sc); 561 DELAY(100); 562 } 563 564 void 565 ar9287_olpc_temp_compensation(struct athn_softc *sc) 566 { 567 const struct ar9287_eeprom *eep = sc->eep; 568 int8_t pdadc, slope, tcomp; 569 uint32_t reg; 570 571 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4); 572 pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 573 DPRINTFN(3, ("PD Avg Out=%d\n", pdadc)); 574 575 if (sc->pdadc == 0 || pdadc == 0) 576 return; /* No frames transmitted yet. */ 577 578 /* Compute Tx gain temperature compensation. */ 579 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) 580 slope = eep->baseEepHeader.tempSensSlope; 581 else 582 slope = 0; 583 if (slope != 0) /* Prevents division by zero. */ 584 tcomp = ((pdadc - sc->pdadc) * 4) / slope; 585 else 586 tcomp = 0; 587 DPRINTFN(3, ("OLPC temp compensation=%d\n", tcomp)); 588 589 /* Write compensation value for both Tx chains. */ 590 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11); 591 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 592 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg); 593 594 reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11); 595 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 596 AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg); 597 AR_WRITE_BARRIER(sc); 598 } 599 600 void 601 ar9287_1_3_enable_async_fifo(struct athn_softc *sc) 602 { 603 /* Enable ASYNC FIFO. */ 604 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 605 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 606 AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 607 AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 608 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 609 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 610 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 611 AR_WRITE_BARRIER(sc); 612 } 613 614 void 615 ar9287_1_3_setup_async_fifo(struct athn_softc *sc) 616 { 617 uint32_t reg; 618 619 /* 620 * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is 621 * enabled, so the following counters have to be changed. 622 */ 623 AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 624 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 625 AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 626 627 AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 628 AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 629 630 AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER, 631 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 632 633 reg = AR_READ(sc, AR_AHB_MODE); 634 reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 635 AR_WRITE(sc, AR_AHB_MODE, reg); 636 637 AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 638 AR_WRITE_BARRIER(sc); 639 } 640