1 /* $OpenBSD: ar9287.c,v 1.20 2014/12/19 22:44:58 guenther Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 * Routines for AR9227 and AR9287 chipsets. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/endian.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_amrr.h> 57 #include <net80211/ieee80211_radiotap.h> 58 59 #include <dev/ic/athnreg.h> 60 #include <dev/ic/athnvar.h> 61 62 #include <dev/ic/ar5008reg.h> 63 #include <dev/ic/ar9280reg.h> 64 #include <dev/ic/ar9287reg.h> 65 66 int ar9287_attach(struct athn_softc *); 67 void ar9287_setup(struct athn_softc *); 68 void ar9287_swap_rom(struct athn_softc *); 69 const struct ar_spur_chan *ar9287_get_spur_chans(struct athn_softc *, int); 70 void ar9287_init_from_rom(struct athn_softc *, struct ieee80211_channel *, 71 struct ieee80211_channel *); 72 void ar9287_get_pdadcs(struct athn_softc *, struct ieee80211_channel *, 73 int, int, uint8_t, uint8_t *, uint8_t *); 74 void ar9287_olpc_get_pdgain(struct athn_softc *, struct ieee80211_channel *, 75 int, int8_t *); 76 void ar9287_set_power_calib(struct athn_softc *, 77 struct ieee80211_channel *); 78 void ar9287_set_txpower(struct athn_softc *, struct ieee80211_channel *, 79 struct ieee80211_channel *); 80 void ar9287_olpc_init(struct athn_softc *); 81 void ar9287_olpc_temp_compensation(struct athn_softc *); 82 void ar9287_1_3_enable_async_fifo(struct athn_softc *); 83 void ar9287_1_3_setup_async_fifo(struct athn_softc *); 84 85 /* Extern functions. */ 86 uint8_t athn_chan2fbin(struct ieee80211_channel *); 87 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *); 88 int ar5008_attach(struct athn_softc *); 89 void ar5008_write_txpower(struct athn_softc *, int16_t power[]); 90 void ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *, 91 struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *); 92 void ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *, 93 uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]); 94 void ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *, 95 uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]); 96 int ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *, 97 struct ieee80211_channel *); 98 void ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *, 99 struct ieee80211_channel *); 100 101 102 int 103 ar9287_attach(struct athn_softc *sc) 104 { 105 sc->eep_base = AR9287_EEP_START_LOC; 106 sc->eep_size = sizeof(struct ar9287_eeprom); 107 sc->def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE; 108 sc->ngpiopins = (sc->flags & ATHN_FLAG_USB) ? 16 : 11; 109 sc->led_pin = 8; 110 sc->workaround = AR9285_WA_DEFAULT; 111 sc->ops.setup = ar9287_setup; 112 sc->ops.swap_rom = ar9287_swap_rom; 113 sc->ops.init_from_rom = ar9287_init_from_rom; 114 sc->ops.set_txpower = ar9287_set_txpower; 115 sc->ops.set_synth = ar9280_set_synth; 116 sc->ops.spur_mitigate = ar9280_spur_mitigate; 117 sc->ops.get_spur_chans = ar9287_get_spur_chans; 118 sc->ops.olpc_init = ar9287_olpc_init; 119 sc->ops.olpc_temp_compensation = ar9287_olpc_temp_compensation; 120 sc->ini = &ar9287_1_1_ini; 121 sc->serdes = &ar9280_2_0_serdes; 122 123 return (ar5008_attach(sc)); 124 } 125 126 void 127 ar9287_setup(struct athn_softc *sc) 128 { 129 const struct ar9287_eeprom *eep = sc->eep; 130 131 /* Determine if open loop power control should be used. */ 132 if (eep->baseEepHeader.openLoopPwrCntl) 133 sc->flags |= ATHN_FLAG_OLPC; 134 135 sc->rx_gain = &ar9287_1_1_rx_gain; 136 sc->tx_gain = &ar9287_1_1_tx_gain; 137 } 138 139 void 140 ar9287_swap_rom(struct athn_softc *sc) 141 { 142 struct ar9287_eeprom *eep = sc->eep; 143 int i; 144 145 eep->modalHeader.antCtrlCommon = 146 swap32(eep->modalHeader.antCtrlCommon); 147 148 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 149 eep->modalHeader.antCtrlChain[i] = 150 swap32(eep->modalHeader.antCtrlChain[i]); 151 } 152 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 153 eep->modalHeader.spurChans[i].spurChan = 154 swap16(eep->modalHeader.spurChans[i].spurChan); 155 } 156 } 157 158 const struct ar_spur_chan * 159 ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz) 160 { 161 const struct ar9287_eeprom *eep = sc->eep; 162 163 KASSERT(is2ghz); 164 return (eep->modalHeader.spurChans); 165 } 166 167 void 168 ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, 169 struct ieee80211_channel *extc) 170 { 171 const struct ar9287_eeprom *eep = sc->eep; 172 const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 173 uint32_t reg, offset; 174 int i; 175 176 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); 177 178 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 179 offset = i * 0x1000; 180 181 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, 182 modal->antCtrlChain[i]); 183 184 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); 185 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 186 modal->iqCalICh[i]); 187 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 188 modal->iqCalQCh[i]); 189 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); 190 191 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); 192 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 193 modal->bswMargin[i]); 194 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 195 modal->bswAtten[i]); 196 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); 197 198 reg = AR_READ(sc, AR_PHY_RXGAIN + offset); 199 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, 200 modal->rxTxMarginCh[i]); 201 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, 202 modal->txRxAttenCh[i]); 203 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); 204 } 205 206 reg = AR_READ(sc, AR_PHY_SETTLING); 207 #ifndef IEEE80211_NO_HT 208 if (extc != NULL) 209 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 210 else 211 #endif 212 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 213 AR_WRITE(sc, AR_PHY_SETTLING, reg); 214 215 reg = AR_READ(sc, AR_PHY_DESIRED_SZ); 216 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 217 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); 218 219 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); 220 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); 221 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); 222 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); 223 AR_WRITE(sc, AR_PHY_RF_CTL4, reg); 224 225 reg = AR_READ(sc, AR_PHY_RF_CTL3); 226 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); 227 AR_WRITE(sc, AR_PHY_RF_CTL3, reg); 228 229 reg = AR_READ(sc, AR_PHY_CCA(0)); 230 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); 231 AR_WRITE(sc, AR_PHY_CCA(0), reg); 232 233 reg = AR_READ(sc, AR_PHY_EXT_CCA0); 234 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); 235 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); 236 237 reg = AR_READ(sc, AR9287_AN_RF2G3_CH0); 238 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 239 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 240 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 241 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 242 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 243 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 244 AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg); 245 AR_WRITE_BARRIER(sc); 246 DELAY(100); 247 248 reg = AR_READ(sc, AR9287_AN_RF2G3_CH1); 249 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); 250 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); 251 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); 252 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); 253 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); 254 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); 255 AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg); 256 AR_WRITE_BARRIER(sc); 257 DELAY(100); 258 259 reg = AR_READ(sc, AR_PHY_RF_CTL2); 260 reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart); 261 reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); 262 AR_WRITE(sc, AR_PHY_RF_CTL2, reg); 263 264 reg = AR_READ(sc, AR9287_AN_TOP2); 265 reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl); 266 AR_WRITE(sc, AR9287_AN_TOP2, reg); 267 AR_WRITE_BARRIER(sc); 268 DELAY(100); 269 } 270 271 void 272 ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c, 273 int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries, 274 uint8_t *pdadcs) 275 { 276 const struct ar9287_eeprom *eep = sc->eep; 277 const struct ar9287_cal_data_per_freq *pierdata; 278 const uint8_t *pierfreq; 279 struct athn_pier lopier, hipier; 280 int16_t delta; 281 uint8_t fbin; 282 int i, lo, hi, npiers; 283 284 pierfreq = eep->calFreqPier2G; 285 pierdata = (const struct ar9287_cal_data_per_freq *) 286 eep->calPierData2G[chain]; 287 npiers = AR9287_NUM_2G_CAL_PIERS; 288 289 /* Find channel in ROM pier table. */ 290 fbin = athn_chan2fbin(c); 291 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 292 293 lopier.fbin = pierfreq[lo]; 294 hipier.fbin = pierfreq[hi]; 295 for (i = 0; i < nxpdgains; i++) { 296 lopier.pwr[i] = pierdata[lo].pwrPdg[i]; 297 lopier.vpd[i] = pierdata[lo].vpdPdg[i]; 298 hipier.pwr[i] = pierdata[lo].pwrPdg[i]; 299 hipier.vpd[i] = pierdata[lo].vpdPdg[i]; 300 } 301 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains, 302 AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs); 303 304 delta = (eep->baseEepHeader.pwrTableOffset - 305 AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */ 306 if (delta != 0) { 307 /* Shift the PDADC table to start at the new offset. */ 308 /* XXX Our padding value differs from Linux. */ 309 for (i = 0; i < AR_NUM_PDADC_VALUES; i++) 310 pdadcs[i] = pdadcs[MIN(i + delta, 311 AR_NUM_PDADC_VALUES - 1)]; 312 } 313 } 314 315 void 316 ar9287_olpc_get_pdgain(struct athn_softc *sc, struct ieee80211_channel *c, 317 int chain, int8_t *pwr) 318 { 319 const struct ar9287_eeprom *eep = sc->eep; 320 const struct ar_cal_data_per_freq_olpc *pierdata; 321 const uint8_t *pierfreq; 322 uint8_t fbin; 323 int lo, hi, npiers; 324 325 pierfreq = eep->calFreqPier2G; 326 pierdata = (const struct ar_cal_data_per_freq_olpc *) 327 eep->calPierData2G[chain]; 328 npiers = AR9287_NUM_2G_CAL_PIERS; 329 330 /* Find channel in ROM pier table. */ 331 fbin = athn_chan2fbin(c); 332 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi); 333 334 #if 0 335 *pwr = athn_interpolate(fbin, 336 pierfreq[lo], pierdata[lo].pwrPdg[0][0], 337 pierfreq[hi], pierdata[hi].pwrPdg[0][0]); 338 #else 339 *pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2; 340 #endif 341 } 342 343 void 344 ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c) 345 { 346 const struct ar9287_eeprom *eep = sc->eep; 347 uint8_t boundaries[AR_PD_GAINS_IN_MASK]; 348 uint8_t pdadcs[AR_NUM_PDADC_VALUES]; 349 uint8_t xpdgains[AR9287_NUM_PD_GAINS]; 350 int8_t txpower; 351 uint8_t overlap; 352 uint32_t reg, offset; 353 int i, j, nxpdgains; 354 355 if (sc->eep_rev < AR_EEP_MINOR_VER_2) { 356 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5), 357 AR_PHY_TPCRG5_PD_GAIN_OVERLAP); 358 } else 359 overlap = eep->modalHeader.pdGainOverlap; 360 361 if (sc->flags & ATHN_FLAG_OLPC) { 362 /* XXX not here. */ 363 sc->pdadc = 364 ((const struct ar_cal_data_per_freq_olpc *) 365 eep->calPierData2G[0])->vpdPdg[0][0]; 366 } 367 368 nxpdgains = 0; 369 memset(xpdgains, 0, sizeof(xpdgains)); 370 for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) { 371 if (nxpdgains >= AR9287_NUM_PD_GAINS) 372 break; /* Can't happen. */ 373 if (eep->modalHeader.xpdGain & (1 << i)) 374 xpdgains[nxpdgains++] = i; 375 } 376 reg = AR_READ(sc, AR_PHY_TPCRG1); 377 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1); 378 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]); 379 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]); 380 AR_WRITE(sc, AR_PHY_TPCRG1, reg); 381 AR_WRITE_BARRIER(sc); 382 383 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 384 if (!(sc->txchainmask & (1 << i))) 385 continue; 386 387 offset = i * 0x1000; 388 389 if (sc->flags & ATHN_FLAG_OLPC) { 390 ar9287_olpc_get_pdgain(sc, c, i, &txpower); 391 392 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0); 393 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 394 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg); 395 396 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1); 397 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); 398 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg); 399 400 /* NB: txpower is in half dB. */ 401 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset); 402 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower); 403 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg); 404 405 AR_WRITE_BARRIER(sc); 406 continue; /* That's it for open loop mode. */ 407 } 408 409 /* Closed loop power control. */ 410 ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap, 411 boundaries, pdadcs); 412 413 /* Write boundaries. */ 414 if (i == 0) { 415 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, 416 overlap); 417 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, 418 boundaries[0]); 419 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, 420 boundaries[1]); 421 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, 422 boundaries[2]); 423 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, 424 boundaries[3]); 425 AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg); 426 } 427 /* Write PDADC values. */ 428 for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) { 429 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j, 430 pdadcs[j + 0] << 0 | 431 pdadcs[j + 1] << 8 | 432 pdadcs[j + 2] << 16 | 433 pdadcs[j + 3] << 24); 434 } 435 AR_WRITE_BARRIER(sc); 436 } 437 } 438 439 void 440 ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c, 441 struct ieee80211_channel *extc) 442 { 443 const struct ar9287_eeprom *eep = sc->eep; 444 const struct ar9287_modal_eep_header *modal = &eep->modalHeader; 445 uint8_t tpow_cck[4], tpow_ofdm[4]; 446 #ifndef IEEE80211_NO_HT 447 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4]; 448 uint8_t tpow_ht20[8], tpow_ht40[8]; 449 uint8_t ht40inc; 450 #endif 451 int16_t pwr = 0, max_ant_gain, power[ATHN_POWER_COUNT]; 452 int i; 453 454 ar9287_set_power_calib(sc, c); 455 456 /* Compute transmit power reduction due to antenna gain. */ 457 max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]); 458 /* XXX */ 459 460 /* 461 * Reduce scaled power by number of active chains to get per-chain 462 * transmit power level. 463 */ 464 if (sc->ntxchains == 2) 465 pwr -= AR_PWR_DECREASE_FOR_2_CHAIN; 466 if (pwr < 0) 467 pwr = 0; 468 469 /* Get CCK target powers. */ 470 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck, 471 AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck); 472 473 /* Get OFDM target powers. */ 474 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G, 475 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm); 476 477 #ifndef IEEE80211_NO_HT 478 /* Get HT-20 target powers. */ 479 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20, 480 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20); 481 482 if (extc != NULL) { 483 /* Get HT-40 target powers. */ 484 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40, 485 eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS, 486 tpow_ht40); 487 488 /* Get secondary channel CCK target powers. */ 489 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B, 490 eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS, 491 tpow_cck_ext); 492 493 /* Get secondary channel OFDM target powers. */ 494 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G, 495 eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS, 496 tpow_ofdm_ext); 497 } 498 #endif 499 500 memset(power, 0, sizeof(power)); 501 /* Shuffle target powers accross transmit rates. */ 502 power[ATHN_POWER_OFDM6 ] = 503 power[ATHN_POWER_OFDM9 ] = 504 power[ATHN_POWER_OFDM12 ] = 505 power[ATHN_POWER_OFDM18 ] = 506 power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0]; 507 power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1]; 508 power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2]; 509 power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3]; 510 power[ATHN_POWER_XR ] = tpow_ofdm[0]; 511 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0]; 512 power[ATHN_POWER_CCK2_LP ] = 513 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1]; 514 power[ATHN_POWER_CCK55_LP] = 515 power[ATHN_POWER_CCK55_SP] = tpow_cck[2]; 516 power[ATHN_POWER_CCK11_LP] = 517 power[ATHN_POWER_CCK11_SP] = tpow_cck[3]; 518 #ifndef IEEE80211_NO_HT 519 for (i = 0; i < nitems(tpow_ht20); i++) 520 power[ATHN_POWER_HT20(i)] = tpow_ht20[i]; 521 if (extc != NULL) { 522 /* Correct PAR difference between HT40 and HT20/Legacy. */ 523 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) 524 ht40inc = modal->ht40PowerIncForPdadc; 525 else 526 ht40inc = AR_HT40_POWER_INC_FOR_PDADC; 527 for (i = 0; i < nitems(tpow_ht40); i++) 528 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc; 529 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0]; 530 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0]; 531 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0]; 532 if (IEEE80211_IS_CHAN_2GHZ(c)) 533 power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0]; 534 } 535 #endif 536 537 for (i = 0; i < ATHN_POWER_COUNT; i++) { 538 power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */ 539 if (power[i] > AR_MAX_RATE_POWER) 540 power[i] = AR_MAX_RATE_POWER; 541 } 542 /* Commit transmit power values to hardware. */ 543 ar5008_write_txpower(sc, power); 544 } 545 546 void 547 ar9287_olpc_init(struct athn_softc *sc) 548 { 549 uint32_t reg; 550 551 AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL); 552 553 reg = AR_READ(sc, AR9287_AN_TXPC0); 554 reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE, 555 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE); 556 AR_WRITE(sc, AR9287_AN_TXPC0, reg); 557 AR_WRITE_BARRIER(sc); 558 DELAY(100); 559 } 560 561 void 562 ar9287_olpc_temp_compensation(struct athn_softc *sc) 563 { 564 const struct ar9287_eeprom *eep = sc->eep; 565 int8_t pdadc, slope, tcomp; 566 uint32_t reg; 567 568 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4); 569 pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 570 DPRINTFN(3, ("PD Avg Out=%d\n", pdadc)); 571 572 if (sc->pdadc == 0 || pdadc == 0) 573 return; /* No frames transmitted yet. */ 574 575 /* Compute Tx gain temperature compensation. */ 576 if (sc->eep_rev >= AR_EEP_MINOR_VER_2) 577 slope = eep->baseEepHeader.tempSensSlope; 578 else 579 slope = 0; 580 if (slope != 0) /* Prevents division by zero. */ 581 tcomp = ((pdadc - sc->pdadc) * 4) / slope; 582 else 583 tcomp = 0; 584 DPRINTFN(3, ("OLPC temp compensation=%d\n", tcomp)); 585 586 /* Write compensation value for both Tx chains. */ 587 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11); 588 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 589 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg); 590 591 reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11); 592 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp); 593 AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg); 594 AR_WRITE_BARRIER(sc); 595 } 596 597 void 598 ar9287_1_3_enable_async_fifo(struct athn_softc *sc) 599 { 600 /* Enable ASYNC FIFO. */ 601 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 602 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 603 AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 604 AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 605 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 606 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3, 607 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 608 AR_WRITE_BARRIER(sc); 609 } 610 611 void 612 ar9287_1_3_setup_async_fifo(struct athn_softc *sc) 613 { 614 uint32_t reg; 615 616 /* 617 * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is 618 * enabled, so the following counters have to be changed. 619 */ 620 AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 621 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 622 AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 623 624 AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 625 AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 626 627 AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER, 628 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 629 630 reg = AR_READ(sc, AR_AHB_MODE); 631 reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 632 AR_WRITE(sc, AR_AHB_MODE, reg); 633 634 AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 635 AR_WRITE_BARRIER(sc); 636 } 637