1 /* $OpenBSD: athn.c,v 1.38 2010/05/11 19:34:20 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/queue.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/stdint.h> /* uintptr_t */ 38 39 #include <machine/bus.h> 40 #include <machine/endian.h> 41 #include <machine/intr.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #include <netinet/in.h> 53 #include <netinet/in_systm.h> 54 #include <netinet/in_var.h> 55 #include <netinet/if_ether.h> 56 #include <netinet/ip.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/ic/athnreg.h> 63 #include <dev/ic/athnvar.h> 64 65 #ifdef ATHN_DEBUG 66 int athn_debug = 0; 67 #endif 68 69 void athn_radiotap_attach(struct athn_softc *); 70 void athn_get_chanlist(struct athn_softc *); 71 const char * athn_get_mac_name(struct athn_softc *); 72 const char * athn_get_rf_name(struct athn_softc *); 73 void athn_led_init(struct athn_softc *); 74 void athn_btcoex_init(struct athn_softc *); 75 void athn_btcoex_enable(struct athn_softc *); 76 void athn_btcoex_disable(struct athn_softc *); 77 void athn_set_rxfilter(struct athn_softc *, uint32_t); 78 void athn_get_chipid(struct athn_softc *); 79 int athn_reset_power_on(struct athn_softc *); 80 int athn_reset(struct athn_softc *, int); 81 void athn_init_pll(struct athn_softc *, 82 const struct ieee80211_channel *); 83 int athn_set_power_awake(struct athn_softc *); 84 void athn_set_power_sleep(struct athn_softc *); 85 void athn_write_serdes(struct athn_softc *, const uint32_t [9]); 86 void athn_config_pcie(struct athn_softc *); 87 void athn_config_nonpcie(struct athn_softc *); 88 int athn_set_chan(struct athn_softc *, struct ieee80211_channel *, 89 struct ieee80211_channel *); 90 int athn_switch_chan(struct athn_softc *, 91 struct ieee80211_channel *, struct ieee80211_channel *); 92 void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 93 void athn_reset_key(struct athn_softc *, int); 94 int athn_set_key(struct ieee80211com *, struct ieee80211_node *, 95 struct ieee80211_key *); 96 void athn_delete_key(struct ieee80211com *, struct ieee80211_node *, 97 struct ieee80211_key *); 98 void athn_iter_func(void *, struct ieee80211_node *); 99 void athn_calib_to(void *); 100 int athn_init_calib(struct athn_softc *, 101 struct ieee80211_channel *, struct ieee80211_channel *); 102 uint8_t athn_chan2fbin(struct ieee80211_channel *); 103 int athn_interpolate(int, int, int, int, int); 104 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, 105 int *); 106 void athn_init_dma(struct athn_softc *); 107 void athn_rx_start(struct athn_softc *); 108 void athn_inc_tx_trigger_level(struct athn_softc *); 109 int athn_stop_rx_dma(struct athn_softc *); 110 int athn_rx_abort(struct athn_softc *); 111 void athn_tx_reclaim(struct athn_softc *, int); 112 int athn_tx_pending(struct athn_softc *, int); 113 void athn_stop_tx_dma(struct athn_softc *, int); 114 int athn_txtime(struct athn_softc *, int, int, u_int); 115 void athn_set_beacon_timers(struct athn_softc *); 116 void athn_set_opmode(struct athn_softc *); 117 void athn_set_bss(struct athn_softc *, struct ieee80211_node *); 118 void athn_enable_interrupts(struct athn_softc *); 119 void athn_disable_interrupts(struct athn_softc *); 120 void athn_init_qos(struct athn_softc *); 121 int athn_hw_reset(struct athn_softc *, struct ieee80211_channel *, 122 struct ieee80211_channel *); 123 struct ieee80211_node *athn_node_alloc(struct ieee80211com *); 124 void athn_newassoc(struct ieee80211com *, struct ieee80211_node *, 125 int); 126 int athn_media_change(struct ifnet *); 127 void athn_next_scan(void *); 128 int athn_newstate(struct ieee80211com *, enum ieee80211_state, 129 int); 130 void athn_updateedca(struct ieee80211com *); 131 void athn_updateslot(struct ieee80211com *); 132 void athn_start(struct ifnet *); 133 void athn_watchdog(struct ifnet *); 134 void athn_set_multi(struct athn_softc *); 135 int athn_ioctl(struct ifnet *, u_long, caddr_t); 136 int athn_init(struct ifnet *); 137 void athn_stop(struct ifnet *, int); 138 void athn_init_tx_queues(struct athn_softc *); 139 int32_t athn_ani_get_rssi(struct athn_softc *); 140 void athn_ani_ofdm_err_trigger(struct athn_softc *); 141 void athn_ani_cck_err_trigger(struct athn_softc *); 142 void athn_ani_lower_immunity(struct athn_softc *); 143 void athn_ani_restart(struct athn_softc *); 144 void athn_ani_monitor(struct athn_softc *); 145 146 /* Extern functions. */ 147 int ar5416_attach(struct athn_softc *); 148 int ar9280_attach(struct athn_softc *); 149 int ar9285_attach(struct athn_softc *); 150 int ar9287_attach(struct athn_softc *); 151 int ar9380_attach(struct athn_softc *); 152 int ar5416_init_calib(struct athn_softc *, 153 struct ieee80211_channel *, struct ieee80211_channel *); 154 int ar9285_1_2_init_calib(struct athn_softc *, 155 struct ieee80211_channel *, struct ieee80211_channel *); 156 int ar9003_init_calib(struct athn_softc *); 157 void ar9285_pa_calib(struct athn_softc *); 158 void ar9287_1_2_enable_async_fifo(struct athn_softc *); 159 void ar9287_1_2_setup_async_fifo(struct athn_softc *); 160 void ar9003_reset_txsring(struct athn_softc *); 161 162 struct cfdriver athn_cd = { 163 NULL, "athn", DV_IFNET 164 }; 165 166 int 167 athn_attach(struct athn_softc *sc) 168 { 169 struct ieee80211com *ic = &sc->sc_ic; 170 struct ifnet *ifp = &ic->ic_if; 171 int error; 172 173 if ((error = athn_reset_power_on(sc)) != 0) { 174 printf(": could not reset chip\n"); 175 return (error); 176 } 177 178 if ((error = athn_set_power_awake(sc)) != 0) { 179 printf(": could not wakeup chip\n"); 180 return (error); 181 } 182 183 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 184 error = ar5416_attach(sc); 185 else if (AR_SREV_9280(sc)) 186 error = ar9280_attach(sc); 187 else if (AR_SREV_9285(sc)) 188 error = ar9285_attach(sc); 189 else if (AR_SREV_9287(sc)) 190 error = ar9287_attach(sc); 191 else if (AR_SREV_9380(sc)) 192 error = ar9380_attach(sc); 193 if (error != 0) { 194 printf(": could not attach chip\n"); 195 return (error); 196 } 197 198 /* We can put the chip in sleep state now. */ 199 athn_set_power_sleep(sc); 200 201 error = sc->ops.dma_alloc(sc); 202 if (error != 0) { 203 printf("%s: could not allocate DMA resources\n", 204 sc->sc_dev.dv_xname); 205 return (error); 206 } 207 208 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 209 210 if (sc->flags & ATHN_FLAG_RFSILENT) { 211 DPRINTF(("found RF switch connected to GPIO pin %d\n", 212 sc->rfsilent_pin)); 213 } 214 DPRINTF(("%d key cache entries\n", sc->kc_entries)); 215 216 /* 217 * In HostAP mode, the number of STAs that we can handle is 218 * limited by the number of entries in the HW key cache. 219 * XXX TKIP MMIC 220 */ 221 ic->ic_max_nnodes = sc->kc_entries - IEEE80211_GROUP_NKID; 222 223 DPRINTF(("using %s loop power control\n", 224 (sc->flags & ATHN_FLAG_OLPC) ? "open" : "closed")); 225 226 DPRINTF(("txchainmask=0x%x rxchainmask=0x%x\n", 227 sc->txchainmask, sc->rxchainmask)); 228 /* Count the number of bits set (in lowest 3 bits). */ 229 sc->ntxchains = 230 ((sc->txchainmask >> 2) & 1) + 231 ((sc->txchainmask >> 1) & 1) + 232 ((sc->txchainmask >> 0) & 1); 233 sc->nrxchains = 234 ((sc->rxchainmask >> 2) & 1) + 235 ((sc->rxchainmask >> 1) & 1) + 236 ((sc->rxchainmask >> 0) & 1); 237 238 if (AR_SINGLE_CHIP(sc)) { 239 printf("%s: %s rev %d (%dT%dR), ROM rev %d\n", 240 sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, 241 sc->ntxchains, sc->nrxchains, sc->eep_rev); 242 } else { 243 printf("%s: MAC %s rev %d, RF %s (%dT%dR), ROM rev %d\n", 244 sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, 245 athn_get_rf_name(sc), sc->ntxchains, sc->nrxchains, 246 sc->eep_rev); 247 } 248 249 timeout_set(&sc->scan_to, athn_next_scan, sc); 250 timeout_set(&sc->calib_to, athn_calib_to, sc); 251 252 sc->amrr.amrr_min_success_threshold = 1; 253 sc->amrr.amrr_max_success_threshold = 15; 254 255 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 256 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* Set device capabilities. */ 260 ic->ic_caps = 261 IEEE80211_C_WEP | /* WEP */ 262 IEEE80211_C_RSN | /* WPA/RSN */ 263 IEEE80211_C_MONITOR | /* monitor mode supported */ 264 IEEE80211_C_SHSLOT | /* short slot time supported */ 265 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 266 IEEE80211_C_PMGT; /* power saving supported */ 267 268 #ifndef IEEE80211_NO_HT 269 if (sc->flags & ATHN_FLAG_11N) { 270 int i, ntxstreams, nrxstreams; 271 272 /* Set HT capabilities. */ 273 ic->ic_htcaps = 274 IEEE80211_HTCAP_SMPS_DIS | 275 IEEE80211_HTCAP_CBW20_40 | 276 IEEE80211_HTCAP_SGI40 | 277 IEEE80211_HTCAP_DSSSCCK40; 278 if (AR_SREV_9380_10_OR_LATER(sc)) 279 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 280 if (AR_SREV_9280_10_OR_LATER(sc)) { 281 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 282 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 283 } 284 ntxstreams = sc->ntxchains; 285 nrxstreams = sc->nrxchains; 286 if (!AR_SREV_9380_10_OR_LATER(sc)) { 287 ntxstreams = MIN(ntxstreams, 2); 288 nrxstreams = MIN(nrxstreams, 2); 289 } 290 /* Set supported HT rates. */ 291 for (i = 0; i < nrxstreams; i++) 292 ic->ic_sup_mcs[i] = 0xff; 293 /* Set the "Tx MCS Set Defined" bit. */ 294 ic->ic_sup_mcs[12] |= 0x01; 295 if (ntxstreams != nrxstreams) { 296 /* Set "Tx Rx MCS Set Not Equal" bit. */ 297 ic->ic_sup_mcs[12] |= 0x02; 298 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 299 } 300 } 301 #endif 302 303 /* Set supported rates. */ 304 if (sc->flags & ATHN_FLAG_11G) { 305 ic->ic_sup_rates[IEEE80211_MODE_11B] = 306 ieee80211_std_rateset_11b; 307 ic->ic_sup_rates[IEEE80211_MODE_11G] = 308 ieee80211_std_rateset_11g; 309 } 310 if (sc->flags & ATHN_FLAG_11A) { 311 ic->ic_sup_rates[IEEE80211_MODE_11A] = 312 ieee80211_std_rateset_11a; 313 } 314 315 /* Get the list of auhtorized/supported channels. */ 316 athn_get_chanlist(sc); 317 318 /* IBSS channel undefined for now. */ 319 ic->ic_ibss_chan = &ic->ic_channels[0]; 320 321 ifp->if_softc = sc; 322 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 323 ifp->if_init = athn_init; 324 ifp->if_ioctl = athn_ioctl; 325 ifp->if_start = athn_start; 326 ifp->if_watchdog = athn_watchdog; 327 IFQ_SET_READY(&ifp->if_snd); 328 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 329 330 if_attach(ifp); 331 ieee80211_ifattach(ifp); 332 ic->ic_node_alloc = athn_node_alloc; 333 ic->ic_newassoc = athn_newassoc; 334 ic->ic_updateslot = athn_updateslot; 335 ic->ic_updateedca = athn_updateedca; 336 #ifdef notyet 337 ic->ic_set_key = athn_set_key; 338 ic->ic_delete_key = athn_delete_key; 339 #endif 340 341 /* Override 802.11 state transition machine. */ 342 sc->sc_newstate = ic->ic_newstate; 343 ic->ic_newstate = athn_newstate; 344 ieee80211_media_init(ifp, athn_media_change, ieee80211_media_status); 345 346 #if NBPFILTER > 0 347 athn_radiotap_attach(sc); 348 #endif 349 350 return (0); 351 } 352 353 void 354 athn_detach(struct athn_softc *sc) 355 { 356 struct ifnet *ifp = &sc->sc_ic.ic_if; 357 int qid; 358 359 timeout_del(&sc->scan_to); 360 timeout_del(&sc->calib_to); 361 362 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 363 athn_tx_reclaim(sc, qid); 364 365 /* Free Tx/Rx DMA resources. */ 366 sc->ops.dma_free(sc); 367 368 /* Free ROM copy. */ 369 if (sc->eep != NULL) 370 free(sc->eep, M_DEVBUF); 371 372 ieee80211_ifdetach(ifp); 373 if_detach(ifp); 374 } 375 376 #if NBPFILTER > 0 377 /* 378 * Attach the interface to 802.11 radiotap. 379 */ 380 void 381 athn_radiotap_attach(struct athn_softc *sc) 382 { 383 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 384 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 385 386 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 387 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 388 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 389 390 sc->sc_txtap_len = sizeof sc->sc_txtapu; 391 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 392 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 393 } 394 #endif 395 396 void 397 athn_get_chanlist(struct athn_softc *sc) 398 { 399 struct ieee80211com *ic = &sc->sc_ic; 400 uint8_t chan; 401 int i; 402 403 if (sc->flags & ATHN_FLAG_11G) { 404 for (i = 1; i <= 14; i++) { 405 chan = i; 406 ic->ic_channels[chan].ic_freq = 407 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 408 ic->ic_channels[chan].ic_flags = 409 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 410 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 411 } 412 } 413 if (sc->flags & ATHN_FLAG_11A) { 414 for (i = 0; i < nitems(athn_5ghz_chans); i++) { 415 chan = athn_5ghz_chans[i]; 416 ic->ic_channels[chan].ic_freq = 417 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 418 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 419 } 420 } 421 } 422 423 void 424 athn_rx_start(struct athn_softc *sc) 425 { 426 struct ieee80211com *ic = &sc->sc_ic; 427 uint32_t rfilt; 428 429 /* Setup Rx DMA descriptors. */ 430 sc->ops.rx_enable(sc); 431 432 /* Set Rx filter. */ 433 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 434 #ifndef IEEE80211_NO_HT 435 /* Want Compressed Block Ack Requests. */ 436 rfilt |= AR_RX_FILTER_COMPR_BAR; 437 #endif 438 if (ic->ic_opmode != IEEE80211_M_STA) { 439 rfilt |= AR_RX_FILTER_PROBEREQ; 440 if (ic->ic_opmode == IEEE80211_M_MONITOR) 441 rfilt |= AR_RX_FILTER_PROM; 442 #ifndef IEEE80211_STA_ONLY 443 if (AR_SREV_9280_10_OR_LATER(sc) && 444 ic->ic_opmode == IEEE80211_M_HOSTAP) 445 rfilt |= AR_RX_FILTER_PSPOLL; 446 #endif 447 rfilt |= AR_RX_FILTER_BEACON; 448 } else 449 rfilt |= AR_RX_FILTER_BEACON; /* XXX AR_RX_FILTER_MYBEACON */ 450 athn_set_rxfilter(sc, rfilt); 451 452 /* Set BSSID mask. */ 453 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 454 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 455 456 athn_set_opmode(sc); 457 458 /* Set multicast filter. */ 459 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 460 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 461 462 AR_WRITE(sc, AR_FILT_OFDM, 0); 463 AR_WRITE(sc, AR_FILT_CCK, 0); 464 AR_WRITE(sc, AR_MIBC, 0); 465 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 466 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 467 468 /* XXX ANI. */ 469 AR_WRITE(sc, AR_PHY_ERR_1, 0); 470 AR_WRITE(sc, AR_PHY_ERR_2, 0); 471 472 /* Disable HW crypto for now. */ 473 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 474 475 /* Start PCU Rx. */ 476 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 477 } 478 479 void 480 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 481 { 482 AR_WRITE(sc, AR_RX_FILTER, rfilt); 483 484 #ifdef notyet 485 reg = AR_READ(sc, AR_PHY_ERR); 486 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 487 AR_PHY_ERR_CCK_TIMING); 488 AR_WRITE(sc, AR_PHY_ERR, reg); 489 if (reg != 0) 490 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 491 else 492 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 493 #else 494 AR_WRITE(sc, AR_PHY_ERR, 0); 495 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 496 #endif 497 } 498 499 int 500 athn_intr(void *xsc) 501 { 502 struct athn_softc *sc = xsc; 503 struct ifnet *ifp = &sc->sc_ic.ic_if; 504 505 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) != 506 (IFF_UP | IFF_RUNNING)) 507 return (0); 508 509 return (sc->ops.intr(sc)); 510 } 511 512 void 513 athn_get_chipid(struct athn_softc *sc) 514 { 515 uint32_t reg; 516 517 reg = AR_READ(sc, AR_SREV); 518 if (MS(reg, AR_SREV_ID) == 0xff) { 519 sc->mac_ver = MS(reg, AR_SREV_VERSION2); 520 sc->mac_rev = MS(reg, AR_SREV_REVISION2); 521 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 522 sc->flags |= ATHN_FLAG_PCIE; 523 } else { 524 sc->mac_ver = MS(reg, AR_SREV_VERSION); 525 sc->mac_rev = MS(reg, AR_SREV_REVISION); 526 if (sc->mac_ver == AR_SREV_VERSION_5416_PCIE) 527 sc->flags |= ATHN_FLAG_PCIE; 528 } 529 } 530 531 const char * 532 athn_get_mac_name(struct athn_softc *sc) 533 { 534 switch (sc->mac_ver) { 535 case AR_SREV_VERSION_5416_PCI: 536 return ("AR5416"); 537 case AR_SREV_VERSION_5416_PCIE: 538 return ("AR5418"); 539 case AR_SREV_VERSION_9160: 540 return ("AR9160"); 541 case AR_SREV_VERSION_9280: 542 return ("AR9280"); 543 case AR_SREV_VERSION_9285: 544 return ("AR9285"); 545 case AR_SREV_VERSION_9287: 546 return ("AR9287"); 547 case AR_SREV_VERSION_9380: 548 return ("AR9380"); 549 } 550 return ("unknown"); 551 } 552 553 /* 554 * Return RF chip name (not for single-chip solutions.) 555 */ 556 const char * 557 athn_get_rf_name(struct athn_softc *sc) 558 { 559 KASSERT(!AR_SINGLE_CHIP(sc)); 560 561 switch (sc->rf_rev) { 562 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 563 return ("AR5133"); 564 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 565 return ("AR2133"); 566 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 567 return ("AR5122"); 568 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 569 return ("AR2122"); 570 } 571 return ("unknown"); 572 } 573 574 int 575 athn_reset_power_on(struct athn_softc *sc) 576 { 577 int ntries; 578 579 /* Set force wake. */ 580 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 581 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 582 583 /* XXX on first call, we do not know the chip id yet. */ 584 if (!AR_SREV_9380_10_OR_LATER(sc)) { 585 /* Make sure no DMA is active by doing an AHB reset. */ 586 AR_WRITE(sc, AR_RC, AR_RC_AHB); 587 } 588 /* RTC reset and clear. */ 589 AR_WRITE(sc, AR_RTC_RESET, 0); 590 DELAY(2); 591 if (!AR_SREV_9380_10_OR_LATER(sc)) 592 AR_WRITE(sc, AR_RC, 0); 593 AR_WRITE(sc, AR_RTC_RESET, 1); 594 595 /* Poll until RTC is ON. */ 596 for (ntries = 0; ntries < 1000; ntries++) { 597 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 598 AR_RTC_STATUS_ON) 599 break; 600 DELAY(10); 601 } 602 if (ntries == 1000) { 603 DPRINTF(("RTC not waking up\n")); 604 return (ETIMEDOUT); 605 } 606 607 /* Read hardware revision. */ 608 athn_get_chipid(sc); 609 610 return (athn_reset(sc, 0)); 611 } 612 613 int 614 athn_reset(struct athn_softc *sc, int cold) 615 { 616 int ntries; 617 618 /* Set force wake. */ 619 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 620 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 621 622 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 623 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 624 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 625 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 626 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 627 } else if (!AR_SREV_9380_10_OR_LATER(sc)) 628 AR_WRITE(sc, AR_RC, AR_RC_AHB); 629 630 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 631 (cold ? AR_RTC_RC_MAC_COLD : 0)); 632 DELAY(50); 633 AR_WRITE(sc, AR_RTC_RC, 0); 634 for (ntries = 0; ntries < 1000; ntries++) { 635 if (!(AR_READ(sc, AR_RTC_RC) & 636 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 637 break; 638 DELAY(10); 639 } 640 if (ntries == 1000) { 641 DPRINTF(("RTC stuck in MAC reset\n")); 642 return (ETIMEDOUT); 643 } 644 AR_WRITE(sc, AR_RC, 0); 645 return (0); 646 } 647 648 int 649 athn_set_power_awake(struct athn_softc *sc) 650 { 651 int ntries, error; 652 653 /* Do a Power-On-Reset if shutdown. */ 654 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 655 AR_RTC_STATUS_SHUTDOWN) { 656 if ((error = athn_reset_power_on(sc)) != 0) 657 return (error); 658 if (!AR_SREV_9380_10_OR_LATER(sc)) 659 athn_init_pll(sc, NULL); 660 } 661 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 662 DELAY(50); /* Give chip the chance to awake. */ 663 664 /* Poll until RTC is ON. */ 665 for (ntries = 0; ntries < 4000; ntries++) { 666 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 667 AR_RTC_STATUS_ON) 668 break; 669 DELAY(50); 670 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 671 } 672 if (ntries == 4000) { 673 DPRINTF(("RTC not waking up\n")); 674 return (ETIMEDOUT); 675 } 676 677 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 678 return (0); 679 } 680 681 void 682 athn_set_power_sleep(struct athn_softc *sc) 683 { 684 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 685 /* Allow the MAC to go to sleep. */ 686 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 687 if (!AR_SREV_9380_10_OR_LATER(sc)) 688 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 689 /* 690 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 691 * results in high power consumption on AR5416 chipsets. 692 */ 693 if (!AR_SREV_5416(sc)) 694 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 695 } 696 697 void 698 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 699 { 700 uint32_t pll; 701 702 if (AR_SREV_9380_10_OR_LATER(sc)) { 703 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 704 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 705 } else if (AR_SREV_9280_10_OR_LATER(sc)) { 706 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 707 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 708 if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK) 709 pll = 0x142c; 710 else if (AR_SREV_9280_20(sc)) 711 pll = 0x2850; 712 else 713 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 714 } else 715 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 716 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 717 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 718 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 719 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 720 else 721 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 722 } else { 723 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 724 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 725 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 726 else 727 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 728 } 729 DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll)); 730 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 731 DELAY(100); 732 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 733 } 734 735 void 736 athn_write_serdes(struct athn_softc *sc, const uint32_t val[9]) 737 { 738 int i; 739 740 /* Write 288-bit value to Serializer/Deserializer. */ 741 for (i = 0; i < 288 / 32; i++) 742 AR_WRITE(sc, AR_PCIE_SERDES, val[i]); 743 AR_WRITE(sc, AR_PCIE_SERDES2, 0); 744 } 745 746 void 747 athn_config_pcie(struct athn_softc *sc) 748 { 749 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 750 athn_write_serdes(sc, sc->serdes); 751 752 DELAY(1000); 753 /* Allow forcing of PCIe core into L1 state. */ 754 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 755 756 #ifndef ATHN_PCIE_WAEN 757 AR_WRITE(sc, AR_WA, sc->workaround); 758 #else 759 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 760 #endif 761 } 762 763 void 764 athn_config_nonpcie(struct athn_softc *sc) 765 { 766 athn_write_serdes(sc, ar_nonpcie_serdes); 767 } 768 769 int 770 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c, 771 struct ieee80211_channel *extc) 772 { 773 struct athn_ops *ops = &sc->ops; 774 int error, qid; 775 776 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 777 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 778 if (athn_tx_pending(sc, qid)) 779 return (EBUSY); 780 781 /* Request RF Bus grant. */ 782 if ((error = ops->rf_bus_request(sc)) != 0) 783 return (error); 784 785 ops->set_phy(sc, c, extc); 786 787 /* Change the synthesizer. */ 788 if ((error = ops->set_synth(sc, c, extc)) != 0) 789 return (error); 790 791 sc->curchan = c; 792 sc->curchanext = extc; 793 794 /* Set transmit power values for new channel. */ 795 ops->set_txpower(sc, c, extc); 796 797 /* Release the RF Bus grant. */ 798 ops->rf_bus_release(sc); 799 800 /* Write delta slope coeffs for modes where OFDM may be used. */ 801 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 802 ops->set_delta_slope(sc, c, extc); 803 804 ops->spur_mitigate(sc, c, extc); 805 /* XXX Load noisefloor values and start calibration. */ 806 807 return (0); 808 } 809 810 int 811 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c, 812 struct ieee80211_channel *extc) 813 { 814 int error, qid; 815 816 /* Disable interrupts. */ 817 athn_disable_interrupts(sc); 818 819 /* Stop all Tx queues. */ 820 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 821 athn_stop_tx_dma(sc, qid); 822 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 823 athn_tx_reclaim(sc, qid); 824 825 /* Stop Rx. */ 826 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS); 827 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 828 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 829 AR_WRITE(sc, AR_FILT_OFDM, 0); 830 AR_WRITE(sc, AR_FILT_CCK, 0); 831 athn_set_rxfilter(sc, 0); 832 error = athn_stop_rx_dma(sc); 833 if (error != 0) 834 goto reset; 835 836 /* AR9280 always needs a full reset. */ 837 /* if (AR_SREV_9280(sc))*/ 838 goto reset; 839 840 /* If band or bandwidth changes, we need to do a full reset. */ 841 if (c->ic_flags != sc->curchan->ic_flags || 842 ((extc != NULL) ^ (sc->curchanext != NULL))) { 843 DPRINTFN(2, ("channel band switch\n")); 844 goto reset; 845 } 846 error = athn_set_power_awake(sc); 847 if (error != 0) 848 goto reset; 849 850 error = athn_set_chan(sc, c, extc); 851 if (error != 0) { 852 reset: /* Error found, try a full reset. */ 853 DPRINTFN(3, ("needs a full reset\n")); 854 error = athn_hw_reset(sc, c, extc); 855 if (error != 0) /* Hopeless case. */ 856 return (error); 857 } 858 athn_rx_start(sc); 859 860 /* Re-enable interrupts. */ 861 athn_enable_interrupts(sc); 862 return (0); 863 } 864 865 void 866 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 867 { 868 #define COEFF_SCALE_SHIFT 24 869 uint32_t exp, man; 870 871 /* exponent = 14 - floor(log2(coeff)) */ 872 for (exp = 31; exp > 0; exp--) 873 if (coeff & (1 << exp)) 874 break; 875 exp = 14 - (exp - COEFF_SCALE_SHIFT); 876 877 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 878 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 879 880 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 881 *exponent = exp - 16; 882 #undef COEFF_SCALE_SHIFT 883 } 884 885 void 886 athn_reset_key(struct athn_softc *sc, int entry) 887 { 888 /* 889 * NB: Key cache registers access special memory area that requires 890 * two 32-bit writes to actually update the values in the internal 891 * memory. Consequently, writes must be grouped by pair. 892 */ 893 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 894 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 895 896 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 897 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 898 899 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 900 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 901 902 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 903 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 904 } 905 906 int 907 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 908 struct ieee80211_key *k) 909 { 910 struct athn_softc *sc = ic->ic_softc; 911 uint32_t type, lo, hi; 912 uint16_t keybuf[8], micbuf[8]; 913 const uint8_t *addr; 914 uintptr_t entry, micentry; 915 916 switch (k->k_cipher) { 917 case IEEE80211_CIPHER_WEP40: 918 type = AR_KEYTABLE_TYPE_40; 919 break; 920 case IEEE80211_CIPHER_WEP104: 921 type = AR_KEYTABLE_TYPE_104; 922 break; 923 case IEEE80211_CIPHER_TKIP: 924 type = AR_KEYTABLE_TYPE_TKIP; 925 break; 926 case IEEE80211_CIPHER_CCMP: 927 type = AR_KEYTABLE_TYPE_CCM; 928 break; 929 default: 930 /* Fallback to software crypto for other ciphers. */ 931 return (ieee80211_set_key(ic, ni, k)); 932 } 933 934 memset(keybuf, 0, sizeof keybuf); 935 memcpy(keybuf, k->k_key, MIN(k->k_len, 16)); 936 937 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 938 entry = IEEE80211_GROUP_NKID + IEEE80211_AID(ni->ni_associd); 939 else 940 entry = k->k_id; 941 k->k_priv = (void *)entry; 942 943 /* NB: See note about key cache registers access above. */ 944 if (type == AR_KEYTABLE_TYPE_TKIP) { 945 micentry = entry + 64; 946 947 /* XXX Split MIC. */ 948 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), 949 micbuf[0] | micbuf[1] << 16); 950 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), micbuf[2]); 951 952 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), 953 micbuf[3] | micbuf[4] << 16); 954 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), micbuf[5]); 955 956 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), 957 micbuf[6] | micbuf[7] << 16); 958 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 959 960 /* MAC address registers are reserved for the MIC entry. */ 961 AR_WRITE(sc, AR_KEYTABLE_MAC0(micentry), 0); 962 AR_WRITE(sc, AR_KEYTABLE_MAC1(micentry), 0); 963 } else { 964 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 965 keybuf[0] | keybuf[1] << 16); 966 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), keybuf[2]); 967 968 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 969 keybuf[3] | keybuf[4] << 16); 970 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), keybuf[5]); 971 972 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 973 keybuf[6] | keybuf[7] << 16); 974 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 975 } 976 977 /* Clear keys from the stack. */ 978 memset(keybuf, 0, sizeof keybuf); 979 memset(micbuf, 0, sizeof micbuf); 980 981 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 982 addr = ni->ni_macaddr; 983 lo = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 984 hi = addr[4] | addr[5] << 8; 985 lo = lo >> 1 | hi << 31; 986 hi = hi >> 1; 987 } else 988 lo = hi = 0; 989 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 990 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 991 return (0); 992 } 993 994 void 995 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 996 struct ieee80211_key *k) 997 { 998 struct athn_softc *sc = ic->ic_softc; 999 uintptr_t entry; 1000 1001 switch (k->k_cipher) { 1002 case IEEE80211_CIPHER_WEP40: 1003 case IEEE80211_CIPHER_WEP104: 1004 case IEEE80211_CIPHER_TKIP: 1005 case IEEE80211_CIPHER_CCMP: 1006 entry = (uintptr_t)k->k_priv; 1007 athn_reset_key(sc, entry); 1008 break; 1009 default: 1010 /* Fallback to software crypto for other ciphers. */ 1011 ieee80211_delete_key(ic, ni, k); 1012 } 1013 } 1014 1015 void 1016 athn_led_init(struct athn_softc *sc) 1017 { 1018 struct athn_ops *ops = &sc->ops; 1019 1020 ops->gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1021 /* LED off, active low. */ 1022 ops->gpio_write(sc, sc->led_pin, 1); 1023 } 1024 1025 #ifdef ATHN_BT_COEXISTENCE 1026 void 1027 athn_btcoex_init(struct athn_softc *sc) 1028 { 1029 struct athn_ops *ops = &sc->ops; 1030 uint32_t reg; 1031 1032 if (sc->flags & ATHN_FLAG_BTCOEX2WIRE) { 1033 /* Connect bt_active to baseband. */ 1034 AR_CLRBITS(sc, sc->gpio_input_en_off, 1035 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1036 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1037 AR_SETBITS(sc, sc->gpio_input_en_off, 1038 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1039 1040 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1041 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1042 AR_GPIO_BTACTIVE_PIN); 1043 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1044 1045 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1046 } else { /* 3-wire. */ 1047 AR_SETBITS(sc, sc->gpio_input_en_off, 1048 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1049 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1050 1051 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1052 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1053 AR_GPIO_BTACTIVE_PIN); 1054 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1055 AR_GPIO_BTPRIORITY_PIN); 1056 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1057 1058 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1059 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1060 } 1061 } 1062 1063 void 1064 athn_btcoex_enable(struct athn_softc *sc) 1065 { 1066 struct athn_ops *ops = &sc->ops; 1067 uint32_t reg; 1068 1069 if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) { 1070 AR_WRITE(sc, AR_BT_COEX_MODE, 1071 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1072 SM(AR_BT_PRIORITY_TIME, 2) | 1073 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1074 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1075 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1076 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1077 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1078 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1079 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1080 AR_WRITE(sc, AR_BT_COEX_MODE2, 1081 SM(AR_BT_BCN_MISS_THRESH, 50) | 1082 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1083 1084 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1085 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1086 1087 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1088 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1089 1090 } else { /* 2-wire. */ 1091 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1092 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1093 } 1094 reg = AR_READ(sc, AR_GPIO_PDPU); 1095 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1096 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1097 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1098 1099 /* Disable PCIe Active State Power Management (ASPM). */ 1100 if (sc->sc_disable_aspm != NULL) 1101 sc->sc_disable_aspm(sc); 1102 1103 /* XXX Start periodic timer. */ 1104 } 1105 1106 void 1107 athn_btcoex_disable(struct athn_softc *sc) 1108 { 1109 struct athn_ops *ops = &sc->ops; 1110 1111 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1112 1113 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1114 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1115 1116 if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) { 1117 AR_WRITE(sc, AR_BT_COEX_MODE, 1118 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1119 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1120 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1121 /* XXX Stop periodic timer. */ 1122 } 1123 /* XXX Restore ASPM setting? */ 1124 } 1125 #endif 1126 1127 void 1128 athn_iter_func(void *arg, struct ieee80211_node *ni) 1129 { 1130 struct athn_softc *sc = arg; 1131 struct athn_node *an = (struct athn_node *)ni; 1132 1133 ieee80211_amrr_choose(&sc->amrr, ni, &an->amn); 1134 } 1135 1136 void 1137 athn_calib_to(void *arg) 1138 { 1139 struct athn_softc *sc = arg; 1140 struct ieee80211com *ic = &sc->sc_ic; 1141 int s; 1142 1143 s = splnet(); 1144 #ifdef notyet 1145 /* XXX ANI. */ 1146 athn_ani_monitor(sc); 1147 /* XXX OLPC temperature compensation. */ 1148 1149 sc->ops.next_calib(sc); 1150 #endif 1151 if (ic->ic_fixed_rate == -1) { 1152 if (ic->ic_opmode == IEEE80211_M_STA) 1153 athn_iter_func(sc, ic->ic_bss); 1154 else 1155 ieee80211_iterate_nodes(ic, athn_iter_func, sc); 1156 } 1157 timeout_add_msec(&sc->calib_to, 500); 1158 splx(s); 1159 } 1160 1161 int 1162 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, 1163 struct ieee80211_channel *extc) 1164 { 1165 struct athn_ops *ops = &sc->ops; 1166 int error; 1167 1168 if (AR_SREV_9380_10_OR_LATER(sc)) 1169 error = ar9003_init_calib(sc); 1170 else if (AR_SREV_9285_12_OR_LATER(sc)) 1171 error = ar9285_1_2_init_calib(sc, c, extc); 1172 else 1173 error = ar5416_init_calib(sc, c, extc); 1174 if (error != 0) 1175 return (error); 1176 1177 /* Do PA calibration. */ 1178 if (AR_SREV_9285_11_OR_LATER(sc)) 1179 ar9285_pa_calib(sc); 1180 1181 /* Do noisefloor calibration. */ 1182 ops->noisefloor_calib(sc); 1183 1184 if (!AR_SREV_9160_10_OR_LATER(sc)) 1185 return (0); 1186 1187 /* Enable IQ calibration. */ 1188 sc->calib_mask = ATHN_CAL_IQ; 1189 1190 if (!AR_SREV_9380_10_OR_LATER(sc) && 1191 (IEEE80211_IS_CHAN_5GHZ(c) || extc != NULL)) { 1192 /* Enable ADC gain and ADC DC offset calibrations. */ 1193 sc->calib_mask |= ATHN_CAL_ADC_GAIN | ATHN_CAL_ADC_DC; 1194 } 1195 1196 ops->do_calib(sc); 1197 return (0); 1198 } 1199 1200 /* 1201 * Adaptive noise immunity. 1202 */ 1203 int32_t 1204 athn_ani_get_rssi(struct athn_softc *sc) 1205 { 1206 return (0); /* XXX */ 1207 } 1208 1209 void 1210 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1211 { 1212 struct athn_ani *ani = &sc->ani; 1213 struct athn_ops *ops = &sc->ops; 1214 int32_t rssi; 1215 1216 /* First, raise noise immunity level, up to max. */ 1217 if (ani->noise_immunity_level < 4) { 1218 ani->noise_immunity_level++; 1219 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1220 return; 1221 } 1222 1223 /* Then, raise our spur immunity level, up to max. */ 1224 if (ani->spur_immunity_level < 7) { 1225 ani->spur_immunity_level++; 1226 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1227 return; 1228 } 1229 1230 #ifndef IEEE80211_STA_ONLY 1231 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1232 if (ani->firstep_level < 2) { 1233 ani->firstep_level++; 1234 ops->set_firstep_level(sc, ani->firstep_level); 1235 } 1236 return; 1237 } 1238 #endif 1239 rssi = athn_ani_get_rssi(sc); 1240 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1241 /* 1242 * Beacon RSSI is high, turn off OFDM weak signal detection 1243 * or raise first step level as last resort. 1244 */ 1245 if (ani->ofdm_weak_signal) { 1246 ani->ofdm_weak_signal = 0; 1247 ops->disable_ofdm_weak_signal(sc); 1248 ani->spur_immunity_level = 0; 1249 ops->set_spur_immunity_level(sc, 0); 1250 } else if (ani->firstep_level < 2) { 1251 ani->firstep_level++; 1252 ops->set_firstep_level(sc, ani->firstep_level); 1253 } 1254 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1255 /* 1256 * Beacon RSSI is in mid range, we need OFDM weak signal 1257 * detection but we can raise first step level. 1258 */ 1259 if (!ani->ofdm_weak_signal) { 1260 ani->ofdm_weak_signal = 1; 1261 ops->enable_ofdm_weak_signal(sc); 1262 } 1263 if (ani->firstep_level < 2) { 1264 ani->firstep_level++; 1265 ops->set_firstep_level(sc, ani->firstep_level); 1266 } 1267 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1268 /* 1269 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1270 * signal detection and zero first step level to maximize 1271 * CCK sensitivity. 1272 */ 1273 if (ani->ofdm_weak_signal) { 1274 ani->ofdm_weak_signal = 0; 1275 ops->disable_ofdm_weak_signal(sc); 1276 } 1277 if (ani->firstep_level > 0) { 1278 ani->firstep_level = 0; 1279 ops->set_firstep_level(sc, 0); 1280 } 1281 } 1282 } 1283 1284 void 1285 athn_ani_cck_err_trigger(struct athn_softc *sc) 1286 { 1287 struct athn_ani *ani = &sc->ani; 1288 struct athn_ops *ops = &sc->ops; 1289 int32_t rssi; 1290 1291 /* Raise noise immunity level, up to max. */ 1292 if (ani->noise_immunity_level < 4) { 1293 ani->noise_immunity_level++; 1294 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1295 return; 1296 } 1297 1298 #ifndef IEEE80211_STA_ONLY 1299 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1300 if (ani->firstep_level < 2) { 1301 ani->firstep_level++; 1302 ops->set_firstep_level(sc, ani->firstep_level); 1303 } 1304 return; 1305 } 1306 #endif 1307 rssi = athn_ani_get_rssi(sc); 1308 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1309 /* 1310 * Beacon RSSI is in mid or high range, raise first step 1311 * level. 1312 */ 1313 if (ani->firstep_level < 2) { 1314 ani->firstep_level++; 1315 ops->set_firstep_level(sc, ani->firstep_level); 1316 } 1317 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1318 /* 1319 * Beacon RSSI is low, zero first step level to maximize 1320 * CCK sensitivity. 1321 */ 1322 if (ani->firstep_level > 0) { 1323 ani->firstep_level = 0; 1324 ops->set_firstep_level(sc, 0); 1325 } 1326 } 1327 } 1328 1329 void 1330 athn_ani_lower_immunity(struct athn_softc *sc) 1331 { 1332 struct athn_ani *ani = &sc->ani; 1333 struct athn_ops *ops = &sc->ops; 1334 int32_t rssi; 1335 1336 #ifndef IEEE80211_STA_ONLY 1337 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1338 if (ani->firstep_level > 0) { 1339 ani->firstep_level--; 1340 ops->set_firstep_level(sc, ani->firstep_level); 1341 } 1342 return; 1343 } 1344 #endif 1345 rssi = athn_ani_get_rssi(sc); 1346 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1347 /* 1348 * Beacon RSSI is high, leave OFDM weak signal detection 1349 * off or it may oscillate. 1350 */ 1351 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1352 /* 1353 * Beacon RSSI is in mid range, turn on OFDM weak signal 1354 * detection or lower first step level. 1355 */ 1356 if (!ani->ofdm_weak_signal) { 1357 ani->ofdm_weak_signal = 1; 1358 ops->enable_ofdm_weak_signal(sc); 1359 return; 1360 } 1361 if (ani->firstep_level > 0) { 1362 ani->firstep_level--; 1363 ops->set_firstep_level(sc, ani->firstep_level); 1364 return; 1365 } 1366 } else { 1367 /* Beacon RSSI is low, lower first step level. */ 1368 if (ani->firstep_level > 0) { 1369 ani->firstep_level--; 1370 ops->set_firstep_level(sc, ani->firstep_level); 1371 return; 1372 } 1373 } 1374 /* 1375 * Lower spur immunity level down to zero, or if all else fails, 1376 * lower noise immunity level down to zero. 1377 */ 1378 if (ani->spur_immunity_level > 0) { 1379 ani->spur_immunity_level--; 1380 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1381 } else if (ani->noise_immunity_level > 0) { 1382 ani->noise_immunity_level--; 1383 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1384 } 1385 } 1386 1387 void 1388 athn_ani_restart(struct athn_softc *sc) 1389 { 1390 struct athn_ani *ani = &sc->ani; 1391 1392 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1393 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1394 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1395 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1396 1397 ani->listen_time = 0; 1398 ani->ofdm_phy_err_count = 0; 1399 ani->cck_phy_err_count = 0; 1400 } 1401 1402 void 1403 athn_ani_monitor(struct athn_softc *sc) 1404 { 1405 struct athn_ani *ani = &sc->ani; 1406 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1407 int32_t cycdelta, txfdelta, rxfdelta; 1408 int32_t listen_time; 1409 1410 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1411 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1412 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1413 1414 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1415 cycdelta = cyccnt - ani->cyccnt; 1416 txfdelta = txfcnt - ani->txfcnt; 1417 rxfdelta = rxfcnt - ani->rxfcnt; 1418 listen_time = (cycdelta - txfdelta - rxfdelta) / 44000; 1419 } else 1420 listen_time = 0; 1421 1422 ani->cyccnt = cyccnt; 1423 ani->txfcnt = txfcnt; 1424 ani->rxfcnt = rxfcnt; 1425 1426 if (listen_time < 0) { 1427 athn_ani_restart(sc); 1428 return; 1429 } 1430 ani->listen_time += listen_time; 1431 1432 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1433 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1434 1435 if (phy1 < ani->ofdm_phy_err_base) { 1436 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1437 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1438 } 1439 if (phy2 < ani->cck_phy_err_base) { 1440 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1441 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1442 } 1443 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) 1444 return; 1445 1446 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1447 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1448 1449 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1450 /* Check to see if we need to lower immunity. */ 1451 if (ani->ofdm_phy_err_count <= 1452 ani->listen_time * ani->ofdm_trig_low / 1000 && 1453 ani->cck_phy_err_count <= 1454 ani->listen_time * ani->cck_trig_low / 1000) 1455 athn_ani_lower_immunity(sc); 1456 athn_ani_restart(sc); 1457 1458 } else if (ani->listen_time > ATHN_ANI_PERIOD) { 1459 /* Check to see if we need to raise immunity. */ 1460 if (ani->ofdm_phy_err_count > 1461 ani->listen_time * ani->ofdm_trig_high / 1000) { 1462 athn_ani_ofdm_err_trigger(sc); 1463 athn_ani_restart(sc); 1464 } else if (ani->cck_phy_err_count > 1465 ani->listen_time * ani->cck_trig_high / 1000) { 1466 athn_ani_cck_err_trigger(sc); 1467 athn_ani_restart(sc); 1468 } 1469 } 1470 } 1471 1472 uint8_t 1473 athn_chan2fbin(struct ieee80211_channel *c) 1474 { 1475 if (IEEE80211_IS_CHAN_2GHZ(c)) 1476 return (c->ic_freq - 2300); 1477 else 1478 return ((c->ic_freq - 4800) / 5); 1479 } 1480 1481 int 1482 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1483 { 1484 if (x1 == x2) /* Prevents division by zero. */ 1485 return (y1); 1486 /* Linear interpolation. */ 1487 return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1)); 1488 } 1489 1490 void 1491 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1492 int *lo, int *hi) 1493 { 1494 int i; 1495 1496 for (i = 0; i < npiers; i++) 1497 if (pierfreq[i] == AR_BCHAN_UNUSED || 1498 pierfreq[i] > fbin) 1499 break; 1500 *hi = i; 1501 *lo = *hi - 1; 1502 if (*lo == -1) 1503 *lo = *hi; 1504 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1505 *hi = *lo; 1506 } 1507 1508 void 1509 athn_init_dma(struct athn_softc *sc) 1510 { 1511 uint32_t reg; 1512 1513 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1514 /* Set AHB not to do cacheline prefetches. */ 1515 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1516 } 1517 reg = AR_READ(sc, AR_TXCFG); 1518 /* Let MAC DMA reads be in 128-byte chunks. */ 1519 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1520 1521 /* Set initial Tx trigger level. */ 1522 if (AR_SREV_9285(sc)) 1523 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1524 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1525 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1526 AR_WRITE(sc, AR_TXCFG, reg); 1527 1528 /* Let MAC DMA writes be in 128-byte chunks. */ 1529 reg = AR_READ(sc, AR_RXCFG); 1530 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1531 AR_WRITE(sc, AR_RXCFG, reg); 1532 1533 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1534 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1535 1536 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1537 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, AR_SREV_9285(sc) ? 1538 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE : 1539 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1540 1541 /* Reset Tx status ring. */ 1542 if (AR_SREV_9380_10_OR_LATER(sc)) 1543 ar9003_reset_txsring(sc); 1544 } 1545 1546 void 1547 athn_inc_tx_trigger_level(struct athn_softc *sc) 1548 { 1549 uint32_t reg, ftrig; 1550 1551 reg = AR_READ(sc, AR_TXCFG); 1552 ftrig = MS(reg, AR_TXCFG_FTRIG); 1553 /* 1554 * NB: The AR9285 and all single-stream parts have an issue that 1555 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1556 */ 1557 if (ftrig == (AR_SREV_9285(sc) ? 0x1f : 0x3f)) 1558 return; /* Already at max. */ 1559 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1560 AR_WRITE(sc, AR_TXCFG, reg); 1561 } 1562 1563 int 1564 athn_stop_rx_dma(struct athn_softc *sc) 1565 { 1566 int ntries; 1567 1568 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1569 /* Wait for Rx enable bit to go low. */ 1570 for (ntries = 0; ntries < 100; ntries++) { 1571 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1572 return (0); 1573 DELAY(100); 1574 } 1575 DPRINTF(("Rx DMA failed to stop\n")); 1576 return (ETIMEDOUT); 1577 } 1578 1579 int 1580 athn_rx_abort(struct athn_softc *sc) 1581 { 1582 int ntries; 1583 1584 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1585 for (ntries = 0; ntries < 1000; ntries++) { 1586 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1587 return (0); 1588 DELAY(10); 1589 } 1590 DPRINTF(("Rx failed to go idle in 10ms\n")); 1591 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1592 return (ETIMEDOUT); 1593 } 1594 1595 void 1596 athn_tx_reclaim(struct athn_softc *sc, int qid) 1597 { 1598 struct athn_txq *txq = &sc->txq[qid]; 1599 struct athn_tx_buf *bf; 1600 1601 /* Reclaim all buffers queued in the specified Tx queue. */ 1602 /* NB: Tx DMA must be stopped. */ 1603 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1604 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1605 1606 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1607 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1608 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1609 m_freem(bf->bf_m); 1610 bf->bf_m = NULL; 1611 bf->bf_ni = NULL; /* Nodes already freed! */ 1612 1613 /* Link Tx buffer back to global free list. */ 1614 SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list); 1615 } 1616 } 1617 1618 int 1619 athn_tx_pending(struct athn_softc *sc, int qid) 1620 { 1621 return (MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1622 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0); 1623 } 1624 1625 void 1626 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1627 { 1628 uint32_t tsflo; 1629 int ntries, i; 1630 1631 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1632 for (ntries = 0; ntries < 40; ntries++) { 1633 if (!athn_tx_pending(sc, qid)) 1634 break; 1635 DELAY(100); 1636 } 1637 if (ntries == 40) { 1638 for (i = 0; i < 2; i++) { 1639 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1640 AR_WRITE(sc, AR_QUIET2, 1641 SM(AR_QUIET2_QUIET_DUR, 10)); 1642 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1643 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1644 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1645 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1646 break; 1647 } 1648 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1649 DELAY(200); 1650 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1651 1652 for (ntries = 0; ntries < 40; ntries++) { 1653 if (!athn_tx_pending(sc, qid)) 1654 break; 1655 DELAY(100); 1656 } 1657 1658 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1659 } 1660 AR_WRITE(sc, AR_Q_TXD, 0); 1661 } 1662 1663 int 1664 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1665 { 1666 #define divround(a, b) (((a) + (b) - 1) / (b)) 1667 int txtime; 1668 1669 /* XXX HT. */ 1670 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1671 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1672 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1673 txtime = 16 + 4 + 4 * txtime + 16; 1674 } else { 1675 txtime = divround(16 * len, athn_rates[ridx].rate); 1676 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1677 txtime += 72 + 24; 1678 else 1679 txtime += 144 + 48; 1680 txtime += 10; /* 10us SIFS. */ 1681 } 1682 return (txtime); 1683 #undef divround 1684 } 1685 1686 void 1687 athn_init_tx_queues(struct athn_softc *sc) 1688 { 1689 uint32_t reg; 1690 int qid; 1691 1692 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1693 SIMPLEQ_INIT(&sc->txq[qid].head); 1694 sc->txq[qid].lastds = NULL; 1695 1696 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1697 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1698 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1699 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1700 AR_WRITE(sc, AR_QMISC(qid), 1701 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1702 AR_WRITE(sc, AR_DMISC(qid), 1703 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1704 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1705 } 1706 1707 /* Init beacon queue. */ 1708 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1709 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1710 AR_Q_MISC_CBR_INCR_DIS1); 1711 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1712 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1713 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1714 AR_D_MISC_BEACON_USE | 1715 AR_D_MISC_POST_FR_BKOFF_DIS); 1716 if (AR_SREV_9380_10_OR_LATER(sc)) { 1717 /* CWmin and CWmax should be 0 for beacon queue. */ 1718 reg = AR_READ(sc, AR_DLCL_IFS(ATHN_QID_BEACON)); 1719 reg = RW(reg, AR_D_LCL_IFS_CWMIN, 0); 1720 reg = RW(reg, AR_D_LCL_IFS_CWMAX, 0); 1721 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), reg); 1722 } 1723 1724 /* Init CAB (Content After Beacon) queue. */ 1725 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1726 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1727 AR_Q_MISC_CBR_INCR_DIS0); 1728 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1729 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1730 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1731 1732 /* Init PS-Poll queue. */ 1733 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1734 AR_Q_MISC_CBR_INCR_DIS1); 1735 1736 /* Init UAPSD queue. */ 1737 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1738 AR_D_MISC_POST_FR_BKOFF_DIS); 1739 1740 if (AR_SREV_9380_10_OR_LATER(sc)) { 1741 /* Enable MAC descriptor CRC check. */ 1742 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1743 } 1744 /* Enable DESC interrupts for all Tx queues. */ 1745 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1746 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1747 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1748 } 1749 1750 void 1751 athn_set_beacon_timers(struct athn_softc *sc) 1752 { 1753 struct ieee80211com *ic = &sc->sc_ic; 1754 struct ieee80211_node *ni = ic->ic_bss; 1755 uint32_t tsfhi, tsflo, tsftu, reg; 1756 uint32_t intval, next_tbtt, next_dtim; 1757 int dtim_period, dtim_count, rem_dtim_count; 1758 1759 tsfhi = AR_READ(sc, AR_TSF_U32); 1760 tsflo = AR_READ(sc, AR_TSF_L32); 1761 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1762 1763 /* Beacon interval in TU. */ 1764 intval = ni->ni_intval; 1765 1766 next_tbtt = roundup(tsftu, intval); 1767 #ifdef notyet 1768 dtim_period = ic->ic_dtim_period; 1769 if (dtim_period <= 0) 1770 #endif 1771 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 1772 1773 #ifdef notyet 1774 dtim_count = ic->ic_dtim_count; 1775 if (dtim_count >= dtim_period) /* Should not happen. */ 1776 #endif 1777 dtim_count = 0; /* Assume last TIM was a DTIM. */ 1778 1779 /* Compute number of remaining TIMs until next DTIM. */ 1780 rem_dtim_count = 0; /* XXX */ 1781 next_dtim = next_tbtt + rem_dtim_count * intval; 1782 1783 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 1784 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1785 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1786 1787 /* 1788 * Set the number of consecutive beacons to miss before raising 1789 * a BMISS interrupt to 10. 1790 */ 1791 reg = AR_READ(sc, AR_RSSI_THR); 1792 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 1793 AR_WRITE(sc, AR_RSSI_THR, reg); 1794 1795 AR_WRITE(sc, AR_NEXT_DTIM, 1796 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1797 AR_WRITE(sc, AR_NEXT_TIM, 1798 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1799 1800 /* CAB timeout is in 1/8 TU. */ 1801 AR_WRITE(sc, AR_SLEEP1, 1802 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 1803 AR_SLEEP1_ASSUME_DTIM); 1804 AR_WRITE(sc, AR_SLEEP2, 1805 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 1806 1807 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 1808 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 1809 1810 AR_SETBITS(sc, AR_TIMER_MODE, 1811 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 1812 1813 /* Set TSF out-of-range threshold (fixed at 16k us). */ 1814 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 1815 } 1816 1817 void 1818 athn_set_opmode(struct athn_softc *sc) 1819 { 1820 uint32_t reg; 1821 1822 switch (sc->sc_ic.ic_opmode) { 1823 #ifndef IEEE80211_STA_ONLY 1824 case IEEE80211_M_HOSTAP: 1825 reg = AR_READ(sc, AR_STA_ID1); 1826 reg &= ~AR_STA_ID1_ADHOC; 1827 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 1828 AR_WRITE(sc, AR_STA_ID1, reg); 1829 1830 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1831 break; 1832 case IEEE80211_M_IBSS: 1833 case IEEE80211_M_AHDEMO: 1834 reg = AR_READ(sc, AR_STA_ID1); 1835 reg &= ~AR_STA_ID1_STA_AP; 1836 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 1837 AR_WRITE(sc, AR_STA_ID1, reg); 1838 1839 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1840 break; 1841 #endif 1842 default: 1843 reg = AR_READ(sc, AR_STA_ID1); 1844 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 1845 reg |= AR_STA_ID1_KSRCH_MODE; 1846 AR_WRITE(sc, AR_STA_ID1, reg); 1847 break; 1848 } 1849 } 1850 1851 void 1852 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 1853 { 1854 const uint8_t *bssid = ni->ni_bssid; 1855 1856 AR_WRITE(sc, AR_BSS_ID0, bssid[0] | bssid[1] << 8 | 1857 bssid[2] << 16 | bssid[3] << 24); 1858 AR_WRITE(sc, AR_BSS_ID1, bssid[4] | bssid[5] << 8 | 1859 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 1860 } 1861 1862 void 1863 athn_enable_interrupts(struct athn_softc *sc) 1864 { 1865 uint32_t mask, mask2; 1866 1867 athn_disable_interrupts(sc); /* XXX */ 1868 1869 /* XXX cleanup, use sc->imask */ 1870 mask = AR_IMR_TXDESC | AR_IMR_TXEOL | AR_IMR_RXERR | AR_IMR_RXEOL | 1871 AR_IMR_RXORN | AR_IMR_GENTMR | AR_IMR_BCNMISC | AR_IMR_RXMINTR | 1872 AR_IMR_RXINTM; 1873 if (AR_SREV_9380_10_OR_LATER(sc)) 1874 mask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 1875 AR_WRITE(sc, AR_IMR, mask); 1876 1877 mask2 = AR_READ(sc, AR_IMR_S2); 1878 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 1879 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 1880 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 1881 AR_WRITE(sc, AR_IMR_S2, mask2); 1882 1883 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 1884 1885 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 1886 1887 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 1888 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 1889 1890 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync); 1891 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync); 1892 } 1893 1894 void 1895 athn_disable_interrupts(struct athn_softc *sc) 1896 { 1897 AR_WRITE(sc, AR_IER, 0); 1898 (void)AR_READ(sc, AR_IER); 1899 1900 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 1901 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 1902 1903 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 1904 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 1905 1906 AR_WRITE(sc, AR_IMR, 0); 1907 1908 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 1909 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 1910 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 1911 1912 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 1913 } 1914 1915 void 1916 athn_init_qos(struct athn_softc *sc) 1917 { 1918 /* Initialize QoS settings. */ 1919 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 1920 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 1921 AR_WRITE(sc, AR_QOS_NO_ACK, 1922 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 1923 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 1924 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 1925 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 1926 /* Initialize TXOP for all TIDs. */ 1927 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 1928 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 1929 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 1930 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 1931 } 1932 1933 int 1934 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c, 1935 struct ieee80211_channel *extc) 1936 { 1937 struct ieee80211com *ic = &sc->sc_ic; 1938 struct athn_ops *ops = &sc->ops; 1939 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 1940 int i, error; 1941 1942 /* XXX not if already awake */ 1943 if ((error = athn_set_power_awake(sc)) != 0) { 1944 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 1945 return (error); 1946 } 1947 1948 /* Preserve the antenna on a channel switch. */ 1949 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 1950 def_ant = 1; 1951 /* Preserve other registers. */ 1952 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1953 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 1954 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 1955 AR_CFG_LED_BLINK_SLOW); 1956 1957 /* Mark PHY as inactive. */ 1958 ops->disable_phy(sc); 1959 1960 if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) { 1961 /* Save TSF before it gets cleared. */ 1962 tsfhi = AR_READ(sc, AR_TSF_U32); 1963 tsflo = AR_READ(sc, AR_TSF_L32); 1964 1965 /* NB: RTC reset clears TSF. */ 1966 error = athn_reset_power_on(sc); 1967 } else 1968 error = athn_reset(sc, 0); 1969 if (error != 0) { 1970 printf("%s: could not reset chip (error=%d)\n", 1971 sc->sc_dev.dv_xname); 1972 return (error); 1973 } 1974 1975 /* XXX not if already awake */ 1976 if ((error = athn_set_power_awake(sc)) != 0) { 1977 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 1978 return (error); 1979 } 1980 1981 athn_init_pll(sc, c); 1982 ops->set_rf_mode(sc, c); 1983 1984 if (sc->flags & ATHN_FLAG_RFSILENT) { 1985 /* Check that the radio is not disabled by hardware switch. */ 1986 reg = ops->gpio_read(sc, sc->rfsilent_pin); 1987 if (sc->flags & ATHN_FLAG_RFSILENT_REVERSED) 1988 reg = !reg; 1989 if (!reg) { 1990 printf("%s: radio is disabled by hardware switch\n", 1991 sc->sc_dev.dv_xname); 1992 return (EPERM); 1993 } 1994 } 1995 if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) { 1996 /* Restore TSF if it got cleared. */ 1997 AR_WRITE(sc, AR_TSF_L32, tsflo); 1998 AR_WRITE(sc, AR_TSF_U32, tsfhi); 1999 } 2000 2001 if (AR_SREV_9280_10_OR_LATER(sc)) 2002 AR_SETBITS(sc, sc->gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2003 2004 if (AR_SREV_9287_12_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2005 ar9287_1_2_enable_async_fifo(sc); 2006 2007 /* Write init values to hardware. */ 2008 ops->hw_init(sc, c, extc); 2009 2010 /* 2011 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2012 * management frames using CCMP. 2013 */ 2014 if (AR_SREV_9280_20_OR_LATER(sc)) { 2015 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2016 /* Do not mask the subtype field in management frames. */ 2017 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2018 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2019 ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2020 IEEE80211_FC1_MORE_DATA)); 2021 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2022 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 2023 /* Disable hardware crypto for management frames. */ 2024 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2025 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2026 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2027 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2028 } 2029 2030 if (ic->ic_curmode != IEEE80211_MODE_11B) 2031 ops->set_delta_slope(sc, c, extc); 2032 2033 ops->spur_mitigate(sc, c, extc); 2034 ops->init_from_rom(sc, c, extc); 2035 2036 AR_WRITE(sc, AR_STA_ID0, 2037 ic->ic_myaddr[0] << 0 | ic->ic_myaddr[1] << 8 | 2038 ic->ic_myaddr[2] << 16 | ic->ic_myaddr[3] << 24); 2039 /* XXX */ 2040 AR_WRITE(sc, AR_STA_ID1, 2041 ic->ic_myaddr[4] << 0 | ic->ic_myaddr[5] << 8 | 2042 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2043 2044 athn_set_opmode(sc); 2045 2046 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2047 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2048 2049 /* Restore previous antenna. */ 2050 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2051 2052 AR_WRITE(sc, AR_BSS_ID0, 0); 2053 AR_WRITE(sc, AR_BSS_ID1, 0); 2054 2055 AR_WRITE(sc, AR_ISR, 0xffffffff); 2056 2057 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2058 2059 if ((error = ops->set_synth(sc, c, extc)) != 0) { 2060 printf("%s: could not set channel\n", sc->sc_dev.dv_xname); 2061 return (error); 2062 } 2063 sc->curchan = c; 2064 sc->curchanext = extc; 2065 2066 for (i = 0; i < AR_NUM_DCU; i++) 2067 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2068 2069 athn_init_tx_queues(sc); 2070 2071 /* Initialize interrupt mask. */ 2072 sc->imask = AR_IMR_DEFAULT; 2073 if (AR_SREV_9380_10_OR_LATER(sc)) 2074 sc->imask |= AR_IMR_HP_RXOK; 2075 #ifndef IEEE80211_STA_ONLY 2076 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2077 sc->imask |= AR_IMR_MIB; 2078 #endif 2079 AR_WRITE(sc, AR_IMR, sc->imask); 2080 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2081 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2082 sc->isync = AR_INTR_SYNC_DEFAULT; 2083 if (sc->flags & ATHN_FLAG_RFSILENT) 2084 sc->isync |= AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin); 2085 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync); 2086 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2087 if (AR_SREV_9380_10_OR_LATER(sc)) { 2088 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2089 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2090 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2091 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2092 } 2093 2094 athn_init_qos(sc); 2095 2096 if (!AR_SREV_9280_10(sc)) 2097 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2098 2099 if (AR_SREV_9287_12_OR_LATER(sc)) 2100 ar9287_1_2_setup_async_fifo(sc); 2101 2102 /* Disable sequence number generation in hardware. */ 2103 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2104 2105 athn_init_dma(sc); 2106 2107 /* Program observation bus to see MAC interrupts. */ 2108 AR_WRITE(sc, sc->obs_off, 8); 2109 2110 /* Setup Rx interrupt mitigation. */ 2111 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2112 2113 ops->init_baseband(sc); 2114 2115 if ((error = athn_init_calib(sc, c, extc)) != 0) { 2116 printf("%s: could not initialize calibration\n", 2117 sc->sc_dev.dv_xname); 2118 return (error); 2119 } 2120 2121 ops->set_rxchains(sc); 2122 2123 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2124 2125 #if BYTE_ORDER == BIG_ENDIAN 2126 /* Default is little-endian, turn on swapping for big-endian. */ 2127 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2128 #endif 2129 return (0); 2130 } 2131 2132 struct ieee80211_node * 2133 athn_node_alloc(struct ieee80211com *ic) 2134 { 2135 return (malloc(sizeof (struct athn_node), M_DEVBUF, 2136 M_NOWAIT | M_ZERO)); 2137 } 2138 2139 void 2140 athn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2141 { 2142 struct athn_softc *sc = ic->ic_softc; 2143 struct athn_node *an = (void *)ni; 2144 struct ieee80211_rateset *rs = &ni->ni_rates; 2145 uint8_t rate; 2146 int ridx, i, j; 2147 2148 ieee80211_amrr_node_init(&sc->amrr, &an->amn); 2149 /* Start at lowest available bit-rate, AMRR will raise. */ 2150 ni->ni_txrate = 0; 2151 2152 for (i = 0; i < rs->rs_nrates; i++) { 2153 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2154 2155 /* Map 802.11 rate to HW rate index. */ 2156 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2157 if (athn_rates[ridx].rate == rate) 2158 break; 2159 an->ridx[i] = ridx; 2160 DPRINTFN(2, ("rate %d index %d\n", rate, ridx)); 2161 2162 /* Compute fallback rate for retries. */ 2163 an->fallback[i] = i; 2164 for (j = i - 1; j >= 0; j--) { 2165 if (athn_rates[an->ridx[j]].phy == 2166 athn_rates[an->ridx[i]].phy) { 2167 an->fallback[i] = j; 2168 break; 2169 } 2170 } 2171 DPRINTFN(2, ("%d fallbacks to %d\n", i, an->fallback[i])); 2172 } 2173 } 2174 2175 int 2176 athn_media_change(struct ifnet *ifp) 2177 { 2178 struct athn_softc *sc = ifp->if_softc; 2179 struct ieee80211com *ic = &sc->sc_ic; 2180 uint8_t rate, ridx; 2181 int error; 2182 2183 error = ieee80211_media_change(ifp); 2184 if (error != ENETRESET) 2185 return (error); 2186 2187 if (ic->ic_fixed_rate != -1) { 2188 rate = ic->ic_sup_rates[ic->ic_curmode]. 2189 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2190 /* Map 802.11 rate to HW rate index. */ 2191 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2192 if (athn_rates[ridx].rate == rate) 2193 break; 2194 sc->fixed_ridx = ridx; 2195 } 2196 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2197 (IFF_UP | IFF_RUNNING)) { 2198 athn_stop(ifp, 0); 2199 error = athn_init(ifp); 2200 } 2201 return (error); 2202 } 2203 2204 void 2205 athn_next_scan(void *arg) 2206 { 2207 struct athn_softc *sc = arg; 2208 struct ieee80211com *ic = &sc->sc_ic; 2209 int s; 2210 2211 s = splnet(); 2212 if (ic->ic_state == IEEE80211_S_SCAN) 2213 ieee80211_next_scan(&ic->ic_if); 2214 splx(s); 2215 } 2216 2217 int 2218 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2219 { 2220 struct ifnet *ifp = &ic->ic_if; 2221 struct athn_softc *sc = ifp->if_softc; 2222 struct athn_ops *ops = &sc->ops; 2223 int error; 2224 2225 timeout_del(&sc->calib_to); 2226 if (nstate != IEEE80211_S_SCAN) 2227 ops->gpio_write(sc, sc->led_pin, 1); 2228 2229 switch (nstate) { 2230 case IEEE80211_S_INIT: 2231 break; 2232 case IEEE80211_S_SCAN: 2233 /* Make the LED blink while scanning. */ 2234 ops->gpio_write(sc, sc->led_pin, 2235 !ops->gpio_read(sc, sc->led_pin)); 2236 error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL); 2237 if (error != 0) 2238 return (error); 2239 timeout_add_msec(&sc->scan_to, 200); 2240 break; 2241 case IEEE80211_S_AUTH: 2242 error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL); 2243 if (error != 0) 2244 return (error); 2245 break; 2246 case IEEE80211_S_ASSOC: 2247 break; 2248 case IEEE80211_S_RUN: 2249 ops->gpio_write(sc, sc->led_pin, 0); 2250 2251 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2252 break; 2253 2254 /* Fake a join to initialize the Tx rate. */ 2255 athn_newassoc(ic, ic->ic_bss, 1); 2256 2257 athn_set_bss(sc, ic->ic_bss); 2258 athn_disable_interrupts(sc); 2259 athn_set_beacon_timers(sc); 2260 /* XXX Enable BMISS interrupts. */ 2261 athn_enable_interrupts(sc); 2262 /* XXX Start ANI. */ 2263 2264 timeout_add_msec(&sc->calib_to, 500); 2265 break; 2266 } 2267 2268 return (sc->sc_newstate(ic, nstate, arg)); 2269 } 2270 2271 void 2272 athn_updateedca(struct ieee80211com *ic) 2273 { 2274 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2275 struct athn_softc *sc = ic->ic_softc; 2276 const struct ieee80211_edca_ac_params *ac; 2277 int aci, qid; 2278 2279 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2280 ac = &ic->ic_edca_ac[aci]; 2281 qid = athn_ac2qid[aci]; 2282 2283 AR_WRITE(sc, AR_DLCL_IFS(qid), 2284 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2285 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2286 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2287 if (ac->ac_txoplimit != 0) { 2288 AR_WRITE(sc, AR_DCHNTIME(qid), 2289 SM(AR_D_CHNTIME_DUR, 2290 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2291 AR_D_CHNTIME_EN); 2292 } else 2293 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2294 } 2295 #undef ATHN_EXP2 2296 } 2297 2298 void 2299 athn_updateslot(struct ieee80211com *ic) 2300 { 2301 struct athn_softc *sc = ic->ic_softc; 2302 uint32_t clks; 2303 2304 if (ic->ic_curmode == IEEE80211_MODE_11B) 2305 clks = AR_CLOCK_RATE_CCK; 2306 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2307 clks = AR_CLOCK_RATE_5GHZ_OFDM; 2308 else 2309 clks = AR_CLOCK_RATE_2GHZ_OFDM; 2310 clks *= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2311 2312 /* XXX 40MHz. */ 2313 2314 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, clks); 2315 } 2316 2317 void 2318 athn_start(struct ifnet *ifp) 2319 { 2320 struct athn_softc *sc = ifp->if_softc; 2321 struct ieee80211com *ic = &sc->sc_ic; 2322 struct ieee80211_node *ni; 2323 struct mbuf *m; 2324 2325 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2326 return; 2327 2328 for (;;) { 2329 if (SIMPLEQ_EMPTY(&sc->txbufs)) { 2330 ifp->if_flags |= IFF_OACTIVE; 2331 break; 2332 } 2333 /* Send pending management frames first. */ 2334 IF_DEQUEUE(&ic->ic_mgtq, m); 2335 if (m != NULL) { 2336 ni = (void *)m->m_pkthdr.rcvif; 2337 goto sendit; 2338 } 2339 if (ic->ic_state != IEEE80211_S_RUN) 2340 break; 2341 2342 /* Encapsulate and send data frames. */ 2343 IFQ_DEQUEUE(&ifp->if_snd, m); 2344 if (m == NULL) 2345 break; 2346 #if NBPFILTER > 0 2347 if (ifp->if_bpf != NULL) 2348 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2349 #endif 2350 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2351 continue; 2352 sendit: 2353 #if NBPFILTER > 0 2354 if (ic->ic_rawbpf != NULL) 2355 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2356 #endif 2357 if (sc->ops.tx(sc, m, ni) != 0) { 2358 ieee80211_release_node(ic, ni); 2359 ifp->if_oerrors++; 2360 continue; 2361 } 2362 2363 sc->sc_tx_timer = 5; 2364 ifp->if_timer = 1; 2365 } 2366 } 2367 2368 void 2369 athn_watchdog(struct ifnet *ifp) 2370 { 2371 struct athn_softc *sc = ifp->if_softc; 2372 2373 ifp->if_timer = 0; 2374 2375 if (sc->sc_tx_timer > 0) { 2376 if (--sc->sc_tx_timer == 0) { 2377 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2378 athn_stop(ifp, 1); 2379 (void)athn_init(ifp); 2380 ifp->if_oerrors++; 2381 return; 2382 } 2383 ifp->if_timer = 1; 2384 } 2385 2386 ieee80211_watchdog(ifp); 2387 } 2388 2389 void 2390 athn_set_multi(struct athn_softc *sc) 2391 { 2392 struct arpcom *ac = &sc->sc_ic.ic_ac; 2393 struct ifnet *ifp = &ac->ac_if; 2394 struct ether_multi *enm; 2395 struct ether_multistep step; 2396 const uint8_t *addr; 2397 uint32_t val, lo, hi; 2398 uint8_t bit; 2399 2400 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2401 lo = hi = 0xffffffff; 2402 goto done; 2403 } 2404 lo = hi = 0; 2405 ETHER_FIRST_MULTI(step, ac, enm); 2406 while (enm != NULL) { 2407 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2408 ifp->if_flags |= IFF_ALLMULTI; 2409 lo = hi = 0xffffffff; 2410 goto done; 2411 } 2412 addr = enm->enm_addrlo; 2413 /* Calculate the XOR value of all eight 6-bit words. */ 2414 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2415 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2416 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2417 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2418 bit &= 0x3f; 2419 if (bit < 32) 2420 lo |= 1 << bit; 2421 else 2422 hi |= 1 << (bit - 32); 2423 ETHER_NEXT_MULTI(step, enm); 2424 } 2425 done: 2426 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2427 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2428 } 2429 2430 int 2431 athn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2432 { 2433 struct athn_softc *sc = ifp->if_softc; 2434 struct ieee80211com *ic = &sc->sc_ic; 2435 struct ifaddr *ifa; 2436 struct ifreq *ifr; 2437 int s, error = 0; 2438 2439 s = splnet(); 2440 2441 switch (cmd) { 2442 case SIOCSIFADDR: 2443 ifa = (struct ifaddr *)data; 2444 ifp->if_flags |= IFF_UP; 2445 #ifdef INET 2446 if (ifa->ifa_addr->sa_family == AF_INET) 2447 arp_ifinit(&ic->ic_ac, ifa); 2448 #endif 2449 /* FALLTHROUGH */ 2450 case SIOCSIFFLAGS: 2451 if (ifp->if_flags & IFF_UP) { 2452 if ((ifp->if_flags & IFF_RUNNING) && 2453 ((ifp->if_flags ^ sc->sc_if_flags) & 2454 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2455 athn_set_multi(sc); 2456 } else if (!(ifp->if_flags & IFF_RUNNING)) 2457 error = athn_init(ifp); 2458 } else { 2459 if (ifp->if_flags & IFF_RUNNING) 2460 athn_stop(ifp, 1); 2461 } 2462 sc->sc_if_flags = ifp->if_flags; 2463 break; 2464 2465 case SIOCADDMULTI: 2466 case SIOCDELMULTI: 2467 ifr = (struct ifreq *)data; 2468 error = (cmd == SIOCADDMULTI) ? 2469 ether_addmulti(ifr, &ic->ic_ac) : 2470 ether_delmulti(ifr, &ic->ic_ac); 2471 if (error == ENETRESET) { 2472 athn_set_multi(sc); 2473 error = 0; 2474 } 2475 break; 2476 2477 case SIOCS80211CHANNEL: 2478 error = ieee80211_ioctl(ifp, cmd, data); 2479 if (error == ENETRESET && 2480 ic->ic_opmode == IEEE80211_M_MONITOR) { 2481 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2482 (IFF_UP | IFF_RUNNING)) 2483 athn_switch_chan(sc, ic->ic_ibss_chan, NULL); 2484 error = 0; 2485 } 2486 break; 2487 2488 default: 2489 error = ieee80211_ioctl(ifp, cmd, data); 2490 } 2491 2492 if (error == ENETRESET) { 2493 error = 0; 2494 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2495 (IFF_UP | IFF_RUNNING)) { 2496 athn_stop(ifp, 0); 2497 error = athn_init(ifp); 2498 } 2499 } 2500 2501 splx(s); 2502 return (error); 2503 } 2504 2505 int 2506 athn_init(struct ifnet *ifp) 2507 { 2508 struct athn_softc *sc = ifp->if_softc; 2509 struct athn_ops *ops = &sc->ops; 2510 struct ieee80211com *ic = &sc->sc_ic; 2511 struct ieee80211_channel *c, *extc; 2512 int i, error; 2513 2514 c = ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2515 extc = NULL; 2516 2517 /* In case a new MAC address has been configured. */ 2518 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2519 2520 /* For CardBus, power on the socket. */ 2521 if (sc->sc_enable != NULL) { 2522 if ((error = sc->sc_enable(sc)) != 0) { 2523 printf("%s: could not enable device\n", 2524 sc->sc_dev.dv_xname); 2525 goto fail; 2526 } 2527 if ((error = athn_reset_power_on(sc)) != 0) { 2528 printf("%s: could not power on device\n", 2529 sc->sc_dev.dv_xname); 2530 goto fail; 2531 } 2532 } 2533 if (!(sc->flags & ATHN_FLAG_PCIE)) 2534 athn_config_nonpcie(sc); 2535 else 2536 athn_config_pcie(sc); 2537 2538 /* Reset HW key cache entries. */ 2539 for (i = 0; i < sc->kc_entries; i++) 2540 athn_reset_key(sc, i); 2541 2542 ops->enable_antenna_diversity(sc); 2543 2544 #ifdef ATHN_BT_COEXISTENCE 2545 /* Configure bluetooth coexistence for combo chips. */ 2546 if (sc->flags & ATHN_FLAG_BTCOEX) 2547 athn_btcoex_init(sc); 2548 #endif 2549 2550 /* Configure LED. */ 2551 athn_led_init(sc); 2552 2553 /* Configure hardware radio switch. */ 2554 if (sc->flags & ATHN_FLAG_RFSILENT) 2555 ops->rfsilent_init(sc); 2556 2557 if ((error = athn_hw_reset(sc, c, extc)) != 0) { 2558 printf("%s: unable to reset hardware; reset status %d\n", 2559 sc->sc_dev.dv_xname, error); 2560 goto fail; 2561 } 2562 2563 /* Enable Rx. */ 2564 athn_rx_start(sc); 2565 2566 /* Enable interrupts. */ 2567 athn_enable_interrupts(sc); 2568 2569 #ifdef ATHN_BT_COEXISTENCE 2570 /* Enable bluetooth coexistence for combo chips. */ 2571 if (sc->flags & ATHN_FLAG_BTCOEX) 2572 athn_btcoex_enable(sc); 2573 #endif 2574 2575 ifp->if_flags &= ~IFF_OACTIVE; 2576 ifp->if_flags |= IFF_RUNNING; 2577 2578 #ifdef notyet 2579 if (ic->ic_flags & IEEE80211_F_WEPON) { 2580 /* Configure WEP keys. */ 2581 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2582 (void)athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2583 } 2584 #endif 2585 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2586 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2587 else 2588 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2589 2590 return (0); 2591 fail: 2592 athn_stop(ifp, 1); 2593 return (error); 2594 } 2595 2596 void 2597 athn_stop(struct ifnet *ifp, int disable) 2598 { 2599 struct athn_softc *sc = ifp->if_softc; 2600 struct ieee80211com *ic = &sc->sc_ic; 2601 int qid; 2602 2603 ifp->if_timer = sc->sc_tx_timer = 0; 2604 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2605 2606 timeout_del(&sc->scan_to); 2607 /* In case we were scanning, release the scan "lock". */ 2608 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2609 2610 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2611 2612 #ifdef ATHN_BT_COEXISTENCE 2613 /* Disable bluetooth coexistence for combo chips. */ 2614 if (sc->flags & ATHN_FLAG_BTCOEX) 2615 athn_btcoex_disable(sc); 2616 #endif 2617 2618 /* Disable interrupts. */ 2619 athn_disable_interrupts(sc); 2620 /* Acknowledge interrupts (avoids interrupt storms.) */ 2621 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2622 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2623 2624 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2625 athn_stop_tx_dma(sc, qid); 2626 /* XXX call athn_hw_reset if Tx still pending? */ 2627 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2628 athn_tx_reclaim(sc, qid); 2629 2630 /* Stop Rx. */ 2631 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS); 2632 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2633 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2634 AR_WRITE(sc, AR_FILT_OFDM, 0); 2635 AR_WRITE(sc, AR_FILT_CCK, 0); 2636 athn_set_rxfilter(sc, 0); 2637 athn_stop_rx_dma(sc); 2638 2639 athn_reset(sc, 0); 2640 athn_init_pll(sc, NULL); 2641 athn_set_power_awake(sc); 2642 athn_reset(sc, 1); 2643 athn_init_pll(sc, NULL); 2644 2645 athn_set_power_sleep(sc); 2646 2647 /* For CardBus, power down the socket. */ 2648 if (disable && sc->sc_disable != NULL) 2649 sc->sc_disable(sc); 2650 } 2651