1 /* $OpenBSD: athn.c,v 1.71 2011/01/08 15:05:24 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2010 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Atheros 802.11a/g/n chipsets. 22 */ 23 24 #include "athn_usb.h" 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/stdint.h> /* uintptr_t */ 39 40 #include <machine/bus.h> 41 #include <machine/endian.h> 42 #include <machine/intr.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/in_var.h> 56 #include <netinet/if_ether.h> 57 #include <netinet/ip.h> 58 59 #include <net80211/ieee80211_var.h> 60 #include <net80211/ieee80211_amrr.h> 61 #include <net80211/ieee80211_radiotap.h> 62 63 #include <dev/ic/athnreg.h> 64 #include <dev/ic/athnvar.h> 65 66 #ifdef ATHN_DEBUG 67 int athn_debug = 0; 68 #endif 69 70 void athn_radiotap_attach(struct athn_softc *); 71 void athn_get_chanlist(struct athn_softc *); 72 const char * athn_get_mac_name(struct athn_softc *); 73 const char * athn_get_rf_name(struct athn_softc *); 74 void athn_led_init(struct athn_softc *); 75 void athn_set_led(struct athn_softc *, int); 76 void athn_btcoex_init(struct athn_softc *); 77 void athn_btcoex_enable(struct athn_softc *); 78 void athn_btcoex_disable(struct athn_softc *); 79 void athn_set_rxfilter(struct athn_softc *, uint32_t); 80 void athn_get_chipid(struct athn_softc *); 81 int athn_reset_power_on(struct athn_softc *); 82 int athn_reset(struct athn_softc *, int); 83 void athn_init_pll(struct athn_softc *, 84 const struct ieee80211_channel *); 85 int athn_set_power_awake(struct athn_softc *); 86 void athn_set_power_sleep(struct athn_softc *); 87 void athn_write_serdes(struct athn_softc *, const uint32_t [9]); 88 void athn_config_pcie(struct athn_softc *); 89 void athn_config_nonpcie(struct athn_softc *); 90 int athn_set_chan(struct athn_softc *, struct ieee80211_channel *, 91 struct ieee80211_channel *); 92 int athn_switch_chan(struct athn_softc *, 93 struct ieee80211_channel *, struct ieee80211_channel *); 94 void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 95 void athn_reset_key(struct athn_softc *, int); 96 int athn_set_key(struct ieee80211com *, struct ieee80211_node *, 97 struct ieee80211_key *); 98 void athn_delete_key(struct ieee80211com *, struct ieee80211_node *, 99 struct ieee80211_key *); 100 void athn_iter_func(void *, struct ieee80211_node *); 101 void athn_calib_to(void *); 102 int athn_init_calib(struct athn_softc *, 103 struct ieee80211_channel *, struct ieee80211_channel *); 104 uint8_t athn_chan2fbin(struct ieee80211_channel *); 105 int athn_interpolate(int, int, int, int, int); 106 void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, 107 int *); 108 void athn_init_dma(struct athn_softc *); 109 void athn_rx_start(struct athn_softc *); 110 void athn_inc_tx_trigger_level(struct athn_softc *); 111 int athn_stop_rx_dma(struct athn_softc *); 112 int athn_rx_abort(struct athn_softc *); 113 void athn_tx_reclaim(struct athn_softc *, int); 114 int athn_tx_pending(struct athn_softc *, int); 115 void athn_stop_tx_dma(struct athn_softc *, int); 116 int athn_txtime(struct athn_softc *, int, int, u_int); 117 void athn_set_sta_timers(struct athn_softc *); 118 void athn_set_hostap_timers(struct athn_softc *); 119 void athn_set_opmode(struct athn_softc *); 120 void athn_set_bss(struct athn_softc *, struct ieee80211_node *); 121 void athn_enable_interrupts(struct athn_softc *); 122 void athn_disable_interrupts(struct athn_softc *); 123 void athn_init_qos(struct athn_softc *); 124 int athn_hw_reset(struct athn_softc *, struct ieee80211_channel *, 125 struct ieee80211_channel *, int); 126 struct ieee80211_node *athn_node_alloc(struct ieee80211com *); 127 void athn_newassoc(struct ieee80211com *, struct ieee80211_node *, 128 int); 129 int athn_media_change(struct ifnet *); 130 void athn_next_scan(void *); 131 int athn_newstate(struct ieee80211com *, enum ieee80211_state, 132 int); 133 void athn_updateedca(struct ieee80211com *); 134 int athn_clock_rate(struct athn_softc *); 135 void athn_updateslot(struct ieee80211com *); 136 void athn_start(struct ifnet *); 137 void athn_watchdog(struct ifnet *); 138 void athn_set_multi(struct athn_softc *); 139 int athn_ioctl(struct ifnet *, u_long, caddr_t); 140 int athn_init(struct ifnet *); 141 void athn_stop(struct ifnet *, int); 142 void athn_init_tx_queues(struct athn_softc *); 143 int32_t athn_ani_get_rssi(struct athn_softc *); 144 void athn_ani_ofdm_err_trigger(struct athn_softc *); 145 void athn_ani_cck_err_trigger(struct athn_softc *); 146 void athn_ani_lower_immunity(struct athn_softc *); 147 void athn_ani_restart(struct athn_softc *); 148 void athn_ani_monitor(struct athn_softc *); 149 150 /* Extern functions. */ 151 int ar5416_attach(struct athn_softc *); 152 int ar9280_attach(struct athn_softc *); 153 int ar9285_attach(struct athn_softc *); 154 int ar9287_attach(struct athn_softc *); 155 int ar9380_attach(struct athn_softc *); 156 int ar5416_init_calib(struct athn_softc *, 157 struct ieee80211_channel *, struct ieee80211_channel *); 158 int ar9285_init_calib(struct athn_softc *, 159 struct ieee80211_channel *, struct ieee80211_channel *); 160 int ar9003_init_calib(struct athn_softc *); 161 void ar9285_pa_calib(struct athn_softc *); 162 void ar9271_pa_calib(struct athn_softc *); 163 void ar9287_1_3_enable_async_fifo(struct athn_softc *); 164 void ar9287_1_3_setup_async_fifo(struct athn_softc *); 165 void ar9003_reset_txsring(struct athn_softc *); 166 167 struct cfdriver athn_cd = { 168 NULL, "athn", DV_IFNET 169 }; 170 171 int 172 athn_attach(struct athn_softc *sc) 173 { 174 struct ieee80211com *ic = &sc->sc_ic; 175 struct ifnet *ifp = &ic->ic_if; 176 int error; 177 178 /* Read hardware revision. */ 179 athn_get_chipid(sc); 180 181 if ((error = athn_reset_power_on(sc)) != 0) { 182 printf("%s: could not reset chip\n", sc->sc_dev.dv_xname); 183 return (error); 184 } 185 186 if ((error = athn_set_power_awake(sc)) != 0) { 187 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 188 return (error); 189 } 190 191 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 192 error = ar5416_attach(sc); 193 else if (AR_SREV_9280(sc)) 194 error = ar9280_attach(sc); 195 else if (AR_SREV_9285(sc)) 196 error = ar9285_attach(sc); 197 #if NATHN_USB > 0 198 else if (AR_SREV_9271(sc)) 199 error = ar9285_attach(sc); 200 #endif 201 else if (AR_SREV_9287(sc)) 202 error = ar9287_attach(sc); 203 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 204 error = ar9380_attach(sc); 205 else 206 error = ENOTSUP; 207 if (error != 0) { 208 printf("%s: could not attach chip\n", sc->sc_dev.dv_xname); 209 return (error); 210 } 211 212 /* We can put the chip in sleep state now. */ 213 athn_set_power_sleep(sc); 214 215 if (!(sc->flags & ATHN_FLAG_USB)) { 216 error = sc->ops.dma_alloc(sc); 217 if (error != 0) { 218 printf("%s: could not allocate DMA resources\n", 219 sc->sc_dev.dv_xname); 220 return (error); 221 } 222 /* Steal one Tx buffer for beacons. */ 223 sc->bcnbuf = SIMPLEQ_FIRST(&sc->txbufs); 224 SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list); 225 } 226 227 if (sc->flags & ATHN_FLAG_RFSILENT) { 228 DPRINTF(("found RF switch connected to GPIO pin %d\n", 229 sc->rfsilent_pin)); 230 } 231 DPRINTF(("%d key cache entries\n", sc->kc_entries)); 232 /* 233 * In HostAP mode, the number of STAs that we can handle is 234 * limited by the number of entries in the HW key cache. 235 * TKIP keys consume 2 entries in the cache. 236 */ 237 ic->ic_max_nnodes = (sc->kc_entries / 2) - IEEE80211_WEP_NKID; 238 if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE) 239 ic->ic_max_nnodes = IEEE80211_CACHE_SIZE; 240 241 DPRINTF(("using %s loop power control\n", 242 (sc->flags & ATHN_FLAG_OLPC) ? "open" : "closed")); 243 244 DPRINTF(("txchainmask=0x%x rxchainmask=0x%x\n", 245 sc->txchainmask, sc->rxchainmask)); 246 /* Count the number of bits set (in lowest 3 bits). */ 247 sc->ntxchains = 248 ((sc->txchainmask >> 2) & 1) + 249 ((sc->txchainmask >> 1) & 1) + 250 ((sc->txchainmask >> 0) & 1); 251 sc->nrxchains = 252 ((sc->rxchainmask >> 2) & 1) + 253 ((sc->rxchainmask >> 1) & 1) + 254 ((sc->rxchainmask >> 0) & 1); 255 256 if (AR_SINGLE_CHIP(sc)) { 257 printf("%s: %s rev %d (%dT%dR), ROM rev %d, address %s\n", 258 sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, 259 sc->ntxchains, sc->nrxchains, sc->eep_rev, 260 ether_sprintf(ic->ic_myaddr)); 261 } else { 262 printf("%s: MAC %s rev %d, RF %s (%dT%dR), ROM rev %d, " 263 "address %s\n", 264 sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev, 265 athn_get_rf_name(sc), sc->ntxchains, sc->nrxchains, 266 sc->eep_rev, ether_sprintf(ic->ic_myaddr)); 267 } 268 269 timeout_set(&sc->scan_to, athn_next_scan, sc); 270 timeout_set(&sc->calib_to, athn_calib_to, sc); 271 272 sc->amrr.amrr_min_success_threshold = 1; 273 sc->amrr.amrr_max_success_threshold = 15; 274 275 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 276 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 277 ic->ic_state = IEEE80211_S_INIT; 278 279 /* Set device capabilities. */ 280 ic->ic_caps = 281 IEEE80211_C_WEP | /* WEP. */ 282 IEEE80211_C_RSN | /* WPA/RSN. */ 283 #ifndef IEEE80211_STA_ONLY 284 IEEE80211_C_HOSTAP | /* Host Ap mode supported. */ 285 #endif 286 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 287 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 288 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 289 IEEE80211_C_PMGT; /* Power saving supported. */ 290 291 #ifndef IEEE80211_NO_HT 292 if (sc->flags & ATHN_FLAG_11N) { 293 int i, ntxstreams, nrxstreams; 294 295 /* Set HT capabilities. */ 296 ic->ic_htcaps = 297 IEEE80211_HTCAP_SMPS_DIS | 298 IEEE80211_HTCAP_CBW20_40 | 299 IEEE80211_HTCAP_SGI40 | 300 IEEE80211_HTCAP_DSSSCCK40; 301 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 302 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 303 if (AR_SREV_9380_10_OR_LATER(sc)) 304 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 305 if (AR_SREV_9280_10_OR_LATER(sc)) { 306 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 307 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 308 } 309 ntxstreams = sc->ntxchains; 310 nrxstreams = sc->nrxchains; 311 if (!AR_SREV_9380_10_OR_LATER(sc)) { 312 ntxstreams = MIN(ntxstreams, 2); 313 nrxstreams = MIN(nrxstreams, 2); 314 } 315 /* Set supported HT rates. */ 316 for (i = 0; i < nrxstreams; i++) 317 ic->ic_sup_mcs[i] = 0xff; 318 /* Set the "Tx MCS Set Defined" bit. */ 319 ic->ic_sup_mcs[12] |= 0x01; 320 if (ntxstreams != nrxstreams) { 321 /* Set "Tx Rx MCS Set Not Equal" bit. */ 322 ic->ic_sup_mcs[12] |= 0x02; 323 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 324 } 325 } 326 #endif 327 328 /* Set supported rates. */ 329 if (sc->flags & ATHN_FLAG_11G) { 330 ic->ic_sup_rates[IEEE80211_MODE_11B] = 331 ieee80211_std_rateset_11b; 332 ic->ic_sup_rates[IEEE80211_MODE_11G] = 333 ieee80211_std_rateset_11g; 334 } 335 if (sc->flags & ATHN_FLAG_11A) { 336 ic->ic_sup_rates[IEEE80211_MODE_11A] = 337 ieee80211_std_rateset_11a; 338 } 339 340 /* Get the list of authorized/supported channels. */ 341 athn_get_chanlist(sc); 342 343 /* IBSS channel undefined for now. */ 344 ic->ic_ibss_chan = &ic->ic_channels[0]; 345 346 ifp->if_softc = sc; 347 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 348 ifp->if_ioctl = athn_ioctl; 349 ifp->if_start = athn_start; 350 ifp->if_watchdog = athn_watchdog; 351 IFQ_SET_READY(&ifp->if_snd); 352 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 353 354 if_attach(ifp); 355 ieee80211_ifattach(ifp); 356 ic->ic_node_alloc = athn_node_alloc; 357 ic->ic_newassoc = athn_newassoc; 358 ic->ic_updateslot = athn_updateslot; 359 ic->ic_updateedca = athn_updateedca; 360 #ifdef notyet 361 ic->ic_set_key = athn_set_key; 362 ic->ic_delete_key = athn_delete_key; 363 #endif 364 365 /* Override 802.11 state transition machine. */ 366 sc->sc_newstate = ic->ic_newstate; 367 ic->ic_newstate = athn_newstate; 368 ieee80211_media_init(ifp, athn_media_change, ieee80211_media_status); 369 370 #if NBPFILTER > 0 371 athn_radiotap_attach(sc); 372 #endif 373 374 return (0); 375 } 376 377 void 378 athn_detach(struct athn_softc *sc) 379 { 380 struct ifnet *ifp = &sc->sc_ic.ic_if; 381 int qid; 382 383 timeout_del(&sc->scan_to); 384 timeout_del(&sc->calib_to); 385 386 if (!(sc->flags & ATHN_FLAG_USB)) { 387 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 388 athn_tx_reclaim(sc, qid); 389 390 /* Free Tx/Rx DMA resources. */ 391 sc->ops.dma_free(sc); 392 } 393 /* Free ROM copy. */ 394 if (sc->eep != NULL) 395 free(sc->eep, M_DEVBUF); 396 397 ieee80211_ifdetach(ifp); 398 if_detach(ifp); 399 } 400 401 #if NBPFILTER > 0 402 /* 403 * Attach the interface to 802.11 radiotap. 404 */ 405 void 406 athn_radiotap_attach(struct athn_softc *sc) 407 { 408 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 409 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 410 411 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 412 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 413 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 414 415 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 416 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 417 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 418 } 419 #endif 420 421 void 422 athn_get_chanlist(struct athn_softc *sc) 423 { 424 struct ieee80211com *ic = &sc->sc_ic; 425 uint8_t chan; 426 int i; 427 428 if (sc->flags & ATHN_FLAG_11G) { 429 for (i = 1; i <= 14; i++) { 430 chan = i; 431 ic->ic_channels[chan].ic_freq = 432 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 433 ic->ic_channels[chan].ic_flags = 434 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 435 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 436 } 437 } 438 if (sc->flags & ATHN_FLAG_11A) { 439 for (i = 0; i < nitems(athn_5ghz_chans); i++) { 440 chan = athn_5ghz_chans[i]; 441 ic->ic_channels[chan].ic_freq = 442 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 443 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 444 } 445 } 446 } 447 448 void 449 athn_rx_start(struct athn_softc *sc) 450 { 451 struct ieee80211com *ic = &sc->sc_ic; 452 uint32_t rfilt; 453 454 /* Setup Rx DMA descriptors. */ 455 sc->ops.rx_enable(sc); 456 457 /* Set Rx filter. */ 458 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 459 #ifndef IEEE80211_NO_HT 460 /* Want Compressed Block Ack Requests. */ 461 rfilt |= AR_RX_FILTER_COMPR_BAR; 462 #endif 463 rfilt |= AR_RX_FILTER_BEACON; 464 if (ic->ic_opmode != IEEE80211_M_STA) { 465 rfilt |= AR_RX_FILTER_PROBEREQ; 466 if (ic->ic_opmode == IEEE80211_M_MONITOR) 467 rfilt |= AR_RX_FILTER_PROM; 468 #ifndef IEEE80211_STA_ONLY 469 if (AR_SREV_9280_10_OR_LATER(sc) && 470 ic->ic_opmode == IEEE80211_M_HOSTAP) 471 rfilt |= AR_RX_FILTER_PSPOLL; 472 #endif 473 } 474 athn_set_rxfilter(sc, rfilt); 475 476 /* Set BSSID mask. */ 477 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 478 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 479 480 athn_set_opmode(sc); 481 482 /* Set multicast filter. */ 483 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 484 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 485 486 AR_WRITE(sc, AR_FILT_OFDM, 0); 487 AR_WRITE(sc, AR_FILT_CCK, 0); 488 AR_WRITE(sc, AR_MIBC, 0); 489 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 490 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 491 492 /* XXX ANI. */ 493 AR_WRITE(sc, AR_PHY_ERR_1, 0); 494 AR_WRITE(sc, AR_PHY_ERR_2, 0); 495 496 /* Disable HW crypto for now. */ 497 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 498 499 /* Start PCU Rx. */ 500 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 501 AR_WRITE_BARRIER(sc); 502 } 503 504 void 505 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 506 { 507 AR_WRITE(sc, AR_RX_FILTER, rfilt); 508 509 #ifdef notyet 510 reg = AR_READ(sc, AR_PHY_ERR); 511 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 512 AR_PHY_ERR_CCK_TIMING); 513 AR_WRITE(sc, AR_PHY_ERR, reg); 514 if (reg != 0) 515 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 516 else 517 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 518 #else 519 AR_WRITE(sc, AR_PHY_ERR, 0); 520 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 521 #endif 522 AR_WRITE_BARRIER(sc); 523 } 524 525 int 526 athn_intr(void *xsc) 527 { 528 struct athn_softc *sc = xsc; 529 struct ifnet *ifp = &sc->sc_ic.ic_if; 530 531 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) != 532 (IFF_UP | IFF_RUNNING)) 533 return (0); 534 535 return (sc->ops.intr(sc)); 536 } 537 538 void 539 athn_get_chipid(struct athn_softc *sc) 540 { 541 uint32_t reg; 542 543 reg = AR_READ(sc, AR_SREV); 544 if (MS(reg, AR_SREV_ID) == 0xff) { 545 sc->mac_ver = MS(reg, AR_SREV_VERSION2); 546 sc->mac_rev = MS(reg, AR_SREV_REVISION2); 547 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 548 sc->flags |= ATHN_FLAG_PCIE; 549 } else { 550 sc->mac_ver = MS(reg, AR_SREV_VERSION); 551 sc->mac_rev = MS(reg, AR_SREV_REVISION); 552 if (sc->mac_ver == AR_SREV_VERSION_5416_PCIE) 553 sc->flags |= ATHN_FLAG_PCIE; 554 } 555 } 556 557 const char * 558 athn_get_mac_name(struct athn_softc *sc) 559 { 560 switch (sc->mac_ver) { 561 case AR_SREV_VERSION_5416_PCI: 562 return ("AR5416"); 563 case AR_SREV_VERSION_5416_PCIE: 564 return ("AR5418"); 565 case AR_SREV_VERSION_9160: 566 return ("AR9160"); 567 case AR_SREV_VERSION_9280: 568 return ("AR9280"); 569 case AR_SREV_VERSION_9285: 570 return ("AR9285"); 571 case AR_SREV_VERSION_9271: 572 return ("AR9271"); 573 case AR_SREV_VERSION_9287: 574 return ("AR9287"); 575 case AR_SREV_VERSION_9380: 576 return ("AR9380"); 577 case AR_SREV_VERSION_9485: 578 return ("AR9485"); 579 } 580 return ("unknown"); 581 } 582 583 /* 584 * Return RF chip name (not for single-chip solutions). 585 */ 586 const char * 587 athn_get_rf_name(struct athn_softc *sc) 588 { 589 KASSERT(!AR_SINGLE_CHIP(sc)); 590 591 switch (sc->rf_rev) { 592 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 593 return ("AR5133"); 594 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 595 return ("AR2133"); 596 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 597 return ("AR5122"); 598 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 599 return ("AR2122"); 600 } 601 return ("unknown"); 602 } 603 604 int 605 athn_reset_power_on(struct athn_softc *sc) 606 { 607 int ntries; 608 609 /* Set force wake. */ 610 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 611 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 612 613 if (!AR_SREV_9380_10_OR_LATER(sc)) { 614 /* Make sure no DMA is active by doing an AHB reset. */ 615 AR_WRITE(sc, AR_RC, AR_RC_AHB); 616 } 617 /* RTC reset and clear. */ 618 AR_WRITE(sc, AR_RTC_RESET, 0); 619 AR_WRITE_BARRIER(sc); 620 DELAY(2); 621 if (!AR_SREV_9380_10_OR_LATER(sc)) 622 AR_WRITE(sc, AR_RC, 0); 623 AR_WRITE(sc, AR_RTC_RESET, 1); 624 625 /* Poll until RTC is ON. */ 626 for (ntries = 0; ntries < 1000; ntries++) { 627 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 628 AR_RTC_STATUS_ON) 629 break; 630 DELAY(10); 631 } 632 if (ntries == 1000) { 633 DPRINTF(("RTC not waking up\n")); 634 return (ETIMEDOUT); 635 } 636 return (athn_reset(sc, 0)); 637 } 638 639 int 640 athn_reset(struct athn_softc *sc, int cold) 641 { 642 int ntries; 643 644 /* Set force wake. */ 645 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 646 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 647 648 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 649 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 650 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 651 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 652 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 653 } else if (!AR_SREV_9380_10_OR_LATER(sc)) 654 AR_WRITE(sc, AR_RC, AR_RC_AHB); 655 656 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 657 (cold ? AR_RTC_RC_MAC_COLD : 0)); 658 AR_WRITE_BARRIER(sc); 659 DELAY(50); 660 AR_WRITE(sc, AR_RTC_RC, 0); 661 for (ntries = 0; ntries < 1000; ntries++) { 662 if (!(AR_READ(sc, AR_RTC_RC) & 663 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 664 break; 665 DELAY(10); 666 } 667 if (ntries == 1000) { 668 DPRINTF(("RTC stuck in MAC reset\n")); 669 return (ETIMEDOUT); 670 } 671 AR_WRITE(sc, AR_RC, 0); 672 AR_WRITE_BARRIER(sc); 673 return (0); 674 } 675 676 int 677 athn_set_power_awake(struct athn_softc *sc) 678 { 679 int ntries, error; 680 681 /* Do a Power-On-Reset if shutdown. */ 682 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 683 AR_RTC_STATUS_SHUTDOWN) { 684 if ((error = athn_reset_power_on(sc)) != 0) 685 return (error); 686 if (!AR_SREV_9380_10_OR_LATER(sc)) 687 athn_init_pll(sc, NULL); 688 } 689 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 690 AR_WRITE_BARRIER(sc); 691 DELAY(50); /* Give chip the chance to awake. */ 692 693 /* Poll until RTC is ON. */ 694 for (ntries = 0; ntries < 4000; ntries++) { 695 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 696 AR_RTC_STATUS_ON) 697 break; 698 DELAY(50); 699 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 700 } 701 if (ntries == 4000) { 702 DPRINTF(("RTC not waking up\n")); 703 return (ETIMEDOUT); 704 } 705 706 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 707 AR_WRITE_BARRIER(sc); 708 return (0); 709 } 710 711 void 712 athn_set_power_sleep(struct athn_softc *sc) 713 { 714 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 715 /* Allow the MAC to go to sleep. */ 716 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 717 if (!AR_SREV_9380_10_OR_LATER(sc)) 718 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 719 /* 720 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 721 * results in high power consumption on AR5416 chipsets. 722 */ 723 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 724 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 725 AR_WRITE_BARRIER(sc); 726 } 727 728 void 729 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 730 { 731 uint32_t pll; 732 733 if (AR_SREV_9380_10_OR_LATER(sc)) { 734 if (AR_SREV_9485(sc)) 735 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 736 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 737 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 738 } else if (AR_SREV_9280_10_OR_LATER(sc)) { 739 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 740 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 741 if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK) 742 pll = 0x142c; 743 else if (AR_SREV_9280_20(sc)) 744 pll = 0x2850; 745 else 746 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 747 } else 748 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 749 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 750 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 751 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 752 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 753 else 754 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 755 } else { 756 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 757 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 758 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 759 else 760 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 761 } 762 DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll)); 763 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 764 if (AR_SREV_9271(sc)) { 765 /* Switch core clock to 117MHz. */ 766 AR_WRITE_BARRIER(sc); 767 DELAY(500); 768 AR_WRITE(sc, 0x50050, 0x304); 769 } 770 AR_WRITE_BARRIER(sc); 771 DELAY(100); 772 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 773 AR_WRITE_BARRIER(sc); 774 } 775 776 void 777 athn_write_serdes(struct athn_softc *sc, const uint32_t val[9]) 778 { 779 int i; 780 781 /* Write 288-bit value to Serializer/Deserializer. */ 782 for (i = 0; i < 288 / 32; i++) 783 AR_WRITE(sc, AR_PCIE_SERDES, val[i]); 784 AR_WRITE(sc, AR_PCIE_SERDES2, 0); 785 AR_WRITE_BARRIER(sc); 786 } 787 788 void 789 athn_config_pcie(struct athn_softc *sc) 790 { 791 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 792 athn_write_serdes(sc, sc->serdes); 793 794 DELAY(1000); 795 /* Allow forcing of PCIe core into L1 state. */ 796 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 797 798 #ifndef ATHN_PCIE_WAEN 799 AR_WRITE(sc, AR_WA, sc->workaround); 800 #else 801 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 802 #endif 803 AR_WRITE_BARRIER(sc); 804 } 805 806 void 807 athn_config_nonpcie(struct athn_softc *sc) 808 { 809 athn_write_serdes(sc, ar_nonpcie_serdes); 810 } 811 812 int 813 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c, 814 struct ieee80211_channel *extc) 815 { 816 struct athn_ops *ops = &sc->ops; 817 int error, qid; 818 819 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 820 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 821 if (athn_tx_pending(sc, qid)) 822 return (EBUSY); 823 824 /* Request RF Bus grant. */ 825 if ((error = ops->rf_bus_request(sc)) != 0) 826 return (error); 827 828 ops->set_phy(sc, c, extc); 829 830 /* Change the synthesizer. */ 831 if ((error = ops->set_synth(sc, c, extc)) != 0) 832 return (error); 833 834 sc->curchan = c; 835 sc->curchanext = extc; 836 837 /* Set transmit power values for new channel. */ 838 ops->set_txpower(sc, c, extc); 839 840 /* Release the RF Bus grant. */ 841 ops->rf_bus_release(sc); 842 843 /* Write delta slope coeffs for modes where OFDM may be used. */ 844 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 845 ops->set_delta_slope(sc, c, extc); 846 847 ops->spur_mitigate(sc, c, extc); 848 /* XXX Load noisefloor values and start calibration. */ 849 850 return (0); 851 } 852 853 int 854 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c, 855 struct ieee80211_channel *extc) 856 { 857 int error, qid; 858 859 /* Disable interrupts. */ 860 athn_disable_interrupts(sc); 861 862 /* Stop all Tx queues. */ 863 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 864 athn_stop_tx_dma(sc, qid); 865 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 866 athn_tx_reclaim(sc, qid); 867 868 /* Stop Rx. */ 869 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 870 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 871 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 872 AR_WRITE(sc, AR_FILT_OFDM, 0); 873 AR_WRITE(sc, AR_FILT_CCK, 0); 874 athn_set_rxfilter(sc, 0); 875 error = athn_stop_rx_dma(sc); 876 if (error != 0) 877 goto reset; 878 879 #ifdef notyet 880 /* AR9280 needs a full reset. */ 881 if (AR_SREV_9280(sc)) 882 #endif 883 goto reset; 884 885 /* If band or bandwidth changes, we need to do a full reset. */ 886 if (c->ic_flags != sc->curchan->ic_flags || 887 ((extc != NULL) ^ (sc->curchanext != NULL))) { 888 DPRINTFN(2, ("channel band switch\n")); 889 goto reset; 890 } 891 error = athn_set_power_awake(sc); 892 if (error != 0) 893 goto reset; 894 895 error = athn_set_chan(sc, c, extc); 896 if (error != 0) { 897 reset: /* Error found, try a full reset. */ 898 DPRINTFN(3, ("needs a full reset\n")); 899 error = athn_hw_reset(sc, c, extc, 0); 900 if (error != 0) /* Hopeless case. */ 901 return (error); 902 } 903 athn_rx_start(sc); 904 905 /* Re-enable interrupts. */ 906 athn_enable_interrupts(sc); 907 return (0); 908 } 909 910 void 911 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 912 { 913 #define COEFF_SCALE_SHIFT 24 914 uint32_t exp, man; 915 916 /* exponent = 14 - floor(log2(coeff)) */ 917 for (exp = 31; exp > 0; exp--) 918 if (coeff & (1 << exp)) 919 break; 920 exp = 14 - (exp - COEFF_SCALE_SHIFT); 921 922 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 923 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 924 925 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 926 *exponent = exp - 16; 927 #undef COEFF_SCALE_SHIFT 928 } 929 930 void 931 athn_reset_key(struct athn_softc *sc, int entry) 932 { 933 /* 934 * NB: Key cache registers access special memory area that requires 935 * two 32-bit writes to actually update the values in the internal 936 * memory. Consequently, writes must be grouped by pair. 937 */ 938 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 939 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 940 941 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 942 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 943 944 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 945 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 946 947 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 948 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 949 950 AR_WRITE_BARRIER(sc); 951 } 952 953 int 954 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 955 struct ieee80211_key *k) 956 { 957 struct athn_softc *sc = ic->ic_softc; 958 const uint8_t *txmic, *rxmic, *key, *addr; 959 uintptr_t entry, micentry; 960 uint32_t type, lo, hi; 961 962 switch (k->k_cipher) { 963 case IEEE80211_CIPHER_WEP40: 964 type = AR_KEYTABLE_TYPE_40; 965 break; 966 case IEEE80211_CIPHER_WEP104: 967 type = AR_KEYTABLE_TYPE_104; 968 break; 969 case IEEE80211_CIPHER_TKIP: 970 type = AR_KEYTABLE_TYPE_TKIP; 971 break; 972 case IEEE80211_CIPHER_CCMP: 973 type = AR_KEYTABLE_TYPE_CCM; 974 break; 975 default: 976 /* Fallback to software crypto for other ciphers. */ 977 return (ieee80211_set_key(ic, ni, k)); 978 } 979 980 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 981 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 982 else 983 entry = k->k_id; 984 k->k_priv = (void *)entry; 985 986 /* NB: See note about key cache registers access above. */ 987 key = k->k_key; 988 if (type == AR_KEYTABLE_TYPE_TKIP) { 989 #ifndef IEEE80211_STA_ONLY 990 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 991 txmic = &key[16]; 992 rxmic = &key[24]; 993 } else 994 #endif 995 { 996 rxmic = &key[16]; 997 txmic = &key[24]; 998 } 999 /* Tx+Rx MIC key is at entry + 64. */ 1000 micentry = entry + 64; 1001 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1002 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1003 1004 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1005 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1006 1007 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1008 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1009 } 1010 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1011 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1012 1013 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1014 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1015 1016 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1017 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1018 1019 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1020 addr = ni->ni_macaddr; 1021 lo = LE_READ_4(&addr[0]); 1022 hi = LE_READ_2(&addr[4]); 1023 lo = lo >> 1 | hi << 31; 1024 hi = hi >> 1; 1025 } else 1026 lo = hi = 0; 1027 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1028 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1029 AR_WRITE_BARRIER(sc); 1030 return (0); 1031 } 1032 1033 void 1034 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1035 struct ieee80211_key *k) 1036 { 1037 struct athn_softc *sc = ic->ic_softc; 1038 uintptr_t entry; 1039 1040 switch (k->k_cipher) { 1041 case IEEE80211_CIPHER_WEP40: 1042 case IEEE80211_CIPHER_WEP104: 1043 case IEEE80211_CIPHER_CCMP: 1044 entry = (uintptr_t)k->k_priv; 1045 athn_reset_key(sc, entry); 1046 break; 1047 case IEEE80211_CIPHER_TKIP: 1048 entry = (uintptr_t)k->k_priv; 1049 athn_reset_key(sc, entry); 1050 athn_reset_key(sc, entry + 64); 1051 break; 1052 default: 1053 /* Fallback to software crypto for other ciphers. */ 1054 ieee80211_delete_key(ic, ni, k); 1055 } 1056 } 1057 1058 void 1059 athn_led_init(struct athn_softc *sc) 1060 { 1061 struct athn_ops *ops = &sc->ops; 1062 1063 ops->gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1064 /* LED off, active low. */ 1065 athn_set_led(sc, 0); 1066 } 1067 1068 void 1069 athn_set_led(struct athn_softc *sc, int on) 1070 { 1071 struct athn_ops *ops = &sc->ops; 1072 1073 sc->led_state = on; 1074 ops->gpio_write(sc, sc->led_pin, !sc->led_state); 1075 } 1076 1077 #ifdef ATHN_BT_COEXISTENCE 1078 void 1079 athn_btcoex_init(struct athn_softc *sc) 1080 { 1081 struct athn_ops *ops = &sc->ops; 1082 uint32_t reg; 1083 1084 if (sc->flags & ATHN_FLAG_BTCOEX2WIRE) { 1085 /* Connect bt_active to baseband. */ 1086 AR_CLRBITS(sc, sc->gpio_input_en_off, 1087 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1088 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1089 AR_SETBITS(sc, sc->gpio_input_en_off, 1090 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1091 1092 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1093 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1094 AR_GPIO_BTACTIVE_PIN); 1095 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1096 AR_WRITE_BARRIER(sc); 1097 1098 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1099 } else { /* 3-wire. */ 1100 AR_SETBITS(sc, sc->gpio_input_en_off, 1101 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1102 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1103 1104 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1105 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1106 AR_GPIO_BTACTIVE_PIN); 1107 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1108 AR_GPIO_BTPRIORITY_PIN); 1109 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1110 AR_WRITE_BARRIER(sc); 1111 1112 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1113 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1114 } 1115 } 1116 1117 void 1118 athn_btcoex_enable(struct athn_softc *sc) 1119 { 1120 struct athn_ops *ops = &sc->ops; 1121 uint32_t reg; 1122 1123 if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) { 1124 AR_WRITE(sc, AR_BT_COEX_MODE, 1125 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1126 SM(AR_BT_PRIORITY_TIME, 2) | 1127 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1128 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1129 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1130 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1131 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1132 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1133 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1134 AR_WRITE(sc, AR_BT_COEX_MODE2, 1135 SM(AR_BT_BCN_MISS_THRESH, 50) | 1136 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1137 1138 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1139 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1140 AR_WRITE_BARRIER(sc); 1141 1142 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1143 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1144 1145 } else { /* 2-wire. */ 1146 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1147 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1148 } 1149 reg = AR_READ(sc, AR_GPIO_PDPU); 1150 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1151 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1152 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1153 AR_WRITE_BARRIER(sc); 1154 1155 /* Disable PCIe Active State Power Management (ASPM). */ 1156 if (sc->sc_disable_aspm != NULL) 1157 sc->sc_disable_aspm(sc); 1158 1159 /* XXX Start periodic timer. */ 1160 } 1161 1162 void 1163 athn_btcoex_disable(struct athn_softc *sc) 1164 { 1165 struct athn_ops *ops = &sc->ops; 1166 1167 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1168 1169 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1170 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1171 1172 if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) { 1173 AR_WRITE(sc, AR_BT_COEX_MODE, 1174 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1175 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1176 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1177 /* XXX Stop periodic timer. */ 1178 } 1179 AR_WRITE_BARRIER(sc); 1180 /* XXX Restore ASPM setting? */ 1181 } 1182 #endif 1183 1184 void 1185 athn_iter_func(void *arg, struct ieee80211_node *ni) 1186 { 1187 struct athn_softc *sc = arg; 1188 struct athn_node *an = (struct athn_node *)ni; 1189 1190 ieee80211_amrr_choose(&sc->amrr, ni, &an->amn); 1191 } 1192 1193 void 1194 athn_calib_to(void *arg) 1195 { 1196 extern int ticks; 1197 struct athn_softc *sc = arg; 1198 struct athn_ops *ops = &sc->ops; 1199 struct ieee80211com *ic = &sc->sc_ic; 1200 int s; 1201 1202 s = splnet(); 1203 1204 /* Do periodic (every 4 minutes) PA calibration. */ 1205 if (AR_SREV_9285_11_OR_LATER(sc) && 1206 !AR_SREV_9380_10_OR_LATER(sc) && 1207 ticks >= sc->pa_calib_ticks + 240 * hz) { 1208 sc->pa_calib_ticks = ticks; 1209 if (AR_SREV_9271(sc)) 1210 ar9271_pa_calib(sc); 1211 else 1212 ar9285_pa_calib(sc); 1213 } 1214 1215 /* Do periodic (every 30 seconds) temperature compensation. */ 1216 if ((sc->flags & ATHN_FLAG_OLPC) && 1217 ticks >= sc->olpc_ticks + 30 * hz) { 1218 sc->olpc_ticks = ticks; 1219 ops->olpc_temp_compensation(sc); 1220 } 1221 1222 #ifdef notyet 1223 /* XXX ANI. */ 1224 athn_ani_monitor(sc); 1225 1226 ops->next_calib(sc); 1227 #endif 1228 if (ic->ic_fixed_rate == -1) { 1229 if (ic->ic_opmode == IEEE80211_M_STA) 1230 athn_iter_func(sc, ic->ic_bss); 1231 else 1232 ieee80211_iterate_nodes(ic, athn_iter_func, sc); 1233 } 1234 timeout_add_msec(&sc->calib_to, 500); 1235 splx(s); 1236 } 1237 1238 int 1239 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c, 1240 struct ieee80211_channel *extc) 1241 { 1242 struct athn_ops *ops = &sc->ops; 1243 int error; 1244 1245 if (AR_SREV_9380_10_OR_LATER(sc)) 1246 error = ar9003_init_calib(sc); 1247 else if (AR_SREV_9285_10_OR_LATER(sc)) 1248 error = ar9285_init_calib(sc, c, extc); 1249 else 1250 error = ar5416_init_calib(sc, c, extc); 1251 if (error != 0) 1252 return (error); 1253 1254 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1255 /* Do PA calibration. */ 1256 if (AR_SREV_9285_11_OR_LATER(sc)) { 1257 extern int ticks; 1258 sc->pa_calib_ticks = ticks; 1259 if (AR_SREV_9271(sc)) 1260 ar9271_pa_calib(sc); 1261 else 1262 ar9285_pa_calib(sc); 1263 } 1264 /* Do noisefloor calibration. */ 1265 ops->noisefloor_calib(sc); 1266 } 1267 if (AR_SREV_9160_10_OR_LATER(sc)) { 1268 /* Support IQ calibration. */ 1269 sc->sup_calib_mask = ATHN_CAL_IQ; 1270 if (AR_SREV_9380_10_OR_LATER(sc)) { 1271 /* Support temperature compensation calibration. */ 1272 sc->sup_calib_mask |= ATHN_CAL_TEMP; 1273 } else if (IEEE80211_IS_CHAN_5GHZ(c) || extc != NULL) { 1274 /* 1275 * ADC gain calibration causes uplink throughput 1276 * drops in HT40 mode on AR9287. 1277 */ 1278 if (!AR_SREV_9287(sc)) { 1279 /* Support ADC gain calibration. */ 1280 sc->sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1281 } 1282 /* Support ADC DC offset calibration. */ 1283 sc->sup_calib_mask |= ATHN_CAL_ADC_DC; 1284 } 1285 } 1286 return (0); 1287 } 1288 1289 /* 1290 * Adaptive noise immunity. 1291 */ 1292 int32_t 1293 athn_ani_get_rssi(struct athn_softc *sc) 1294 { 1295 return (0); /* XXX */ 1296 } 1297 1298 void 1299 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1300 { 1301 struct athn_ani *ani = &sc->ani; 1302 struct athn_ops *ops = &sc->ops; 1303 int32_t rssi; 1304 1305 /* First, raise noise immunity level, up to max. */ 1306 if (ani->noise_immunity_level < 4) { 1307 ani->noise_immunity_level++; 1308 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1309 return; 1310 } 1311 1312 /* Then, raise our spur immunity level, up to max. */ 1313 if (ani->spur_immunity_level < 7) { 1314 ani->spur_immunity_level++; 1315 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1316 return; 1317 } 1318 1319 #ifndef IEEE80211_STA_ONLY 1320 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1321 if (ani->firstep_level < 2) { 1322 ani->firstep_level++; 1323 ops->set_firstep_level(sc, ani->firstep_level); 1324 } 1325 return; 1326 } 1327 #endif 1328 rssi = athn_ani_get_rssi(sc); 1329 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1330 /* 1331 * Beacon RSSI is high, turn off OFDM weak signal detection 1332 * or raise first step level as last resort. 1333 */ 1334 if (ani->ofdm_weak_signal) { 1335 ani->ofdm_weak_signal = 0; 1336 ops->disable_ofdm_weak_signal(sc); 1337 ani->spur_immunity_level = 0; 1338 ops->set_spur_immunity_level(sc, 0); 1339 } else if (ani->firstep_level < 2) { 1340 ani->firstep_level++; 1341 ops->set_firstep_level(sc, ani->firstep_level); 1342 } 1343 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1344 /* 1345 * Beacon RSSI is in mid range, we need OFDM weak signal 1346 * detection but we can raise first step level. 1347 */ 1348 if (!ani->ofdm_weak_signal) { 1349 ani->ofdm_weak_signal = 1; 1350 ops->enable_ofdm_weak_signal(sc); 1351 } 1352 if (ani->firstep_level < 2) { 1353 ani->firstep_level++; 1354 ops->set_firstep_level(sc, ani->firstep_level); 1355 } 1356 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1357 /* 1358 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1359 * signal detection and zero first step level to maximize 1360 * CCK sensitivity. 1361 */ 1362 if (ani->ofdm_weak_signal) { 1363 ani->ofdm_weak_signal = 0; 1364 ops->disable_ofdm_weak_signal(sc); 1365 } 1366 if (ani->firstep_level > 0) { 1367 ani->firstep_level = 0; 1368 ops->set_firstep_level(sc, 0); 1369 } 1370 } 1371 } 1372 1373 void 1374 athn_ani_cck_err_trigger(struct athn_softc *sc) 1375 { 1376 struct athn_ani *ani = &sc->ani; 1377 struct athn_ops *ops = &sc->ops; 1378 int32_t rssi; 1379 1380 /* Raise noise immunity level, up to max. */ 1381 if (ani->noise_immunity_level < 4) { 1382 ani->noise_immunity_level++; 1383 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1384 return; 1385 } 1386 1387 #ifndef IEEE80211_STA_ONLY 1388 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1389 if (ani->firstep_level < 2) { 1390 ani->firstep_level++; 1391 ops->set_firstep_level(sc, ani->firstep_level); 1392 } 1393 return; 1394 } 1395 #endif 1396 rssi = athn_ani_get_rssi(sc); 1397 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1398 /* 1399 * Beacon RSSI is in mid or high range, raise first step 1400 * level. 1401 */ 1402 if (ani->firstep_level < 2) { 1403 ani->firstep_level++; 1404 ops->set_firstep_level(sc, ani->firstep_level); 1405 } 1406 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1407 /* 1408 * Beacon RSSI is low, zero first step level to maximize 1409 * CCK sensitivity. 1410 */ 1411 if (ani->firstep_level > 0) { 1412 ani->firstep_level = 0; 1413 ops->set_firstep_level(sc, 0); 1414 } 1415 } 1416 } 1417 1418 void 1419 athn_ani_lower_immunity(struct athn_softc *sc) 1420 { 1421 struct athn_ani *ani = &sc->ani; 1422 struct athn_ops *ops = &sc->ops; 1423 int32_t rssi; 1424 1425 #ifndef IEEE80211_STA_ONLY 1426 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1427 if (ani->firstep_level > 0) { 1428 ani->firstep_level--; 1429 ops->set_firstep_level(sc, ani->firstep_level); 1430 } 1431 return; 1432 } 1433 #endif 1434 rssi = athn_ani_get_rssi(sc); 1435 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1436 /* 1437 * Beacon RSSI is high, leave OFDM weak signal detection 1438 * off or it may oscillate. 1439 */ 1440 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1441 /* 1442 * Beacon RSSI is in mid range, turn on OFDM weak signal 1443 * detection or lower first step level. 1444 */ 1445 if (!ani->ofdm_weak_signal) { 1446 ani->ofdm_weak_signal = 1; 1447 ops->enable_ofdm_weak_signal(sc); 1448 return; 1449 } 1450 if (ani->firstep_level > 0) { 1451 ani->firstep_level--; 1452 ops->set_firstep_level(sc, ani->firstep_level); 1453 return; 1454 } 1455 } else { 1456 /* Beacon RSSI is low, lower first step level. */ 1457 if (ani->firstep_level > 0) { 1458 ani->firstep_level--; 1459 ops->set_firstep_level(sc, ani->firstep_level); 1460 return; 1461 } 1462 } 1463 /* 1464 * Lower spur immunity level down to zero, or if all else fails, 1465 * lower noise immunity level down to zero. 1466 */ 1467 if (ani->spur_immunity_level > 0) { 1468 ani->spur_immunity_level--; 1469 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1470 } else if (ani->noise_immunity_level > 0) { 1471 ani->noise_immunity_level--; 1472 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1473 } 1474 } 1475 1476 void 1477 athn_ani_restart(struct athn_softc *sc) 1478 { 1479 struct athn_ani *ani = &sc->ani; 1480 1481 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1482 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1483 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1484 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1485 AR_WRITE_BARRIER(sc); 1486 1487 ani->listen_time = 0; 1488 ani->ofdm_phy_err_count = 0; 1489 ani->cck_phy_err_count = 0; 1490 } 1491 1492 void 1493 athn_ani_monitor(struct athn_softc *sc) 1494 { 1495 struct athn_ani *ani = &sc->ani; 1496 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1497 int32_t cycdelta, txfdelta, rxfdelta; 1498 int32_t listen_time; 1499 1500 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1501 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1502 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1503 1504 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1505 cycdelta = cyccnt - ani->cyccnt; 1506 txfdelta = txfcnt - ani->txfcnt; 1507 rxfdelta = rxfcnt - ani->rxfcnt; 1508 1509 listen_time = (cycdelta - txfdelta - rxfdelta) / 1510 (athn_clock_rate(sc) * 1000); 1511 } else 1512 listen_time = 0; 1513 1514 ani->cyccnt = cyccnt; 1515 ani->txfcnt = txfcnt; 1516 ani->rxfcnt = rxfcnt; 1517 1518 if (listen_time < 0) { 1519 athn_ani_restart(sc); 1520 return; 1521 } 1522 ani->listen_time += listen_time; 1523 1524 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1525 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1526 1527 if (phy1 < ani->ofdm_phy_err_base) { 1528 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1529 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1530 } 1531 if (phy2 < ani->cck_phy_err_base) { 1532 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1533 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1534 } 1535 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1536 AR_WRITE_BARRIER(sc); 1537 return; 1538 } 1539 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1540 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1541 1542 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1543 /* Check to see if we need to lower immunity. */ 1544 if (ani->ofdm_phy_err_count <= 1545 ani->listen_time * ani->ofdm_trig_low / 1000 && 1546 ani->cck_phy_err_count <= 1547 ani->listen_time * ani->cck_trig_low / 1000) 1548 athn_ani_lower_immunity(sc); 1549 athn_ani_restart(sc); 1550 1551 } else if (ani->listen_time > ATHN_ANI_PERIOD) { 1552 /* Check to see if we need to raise immunity. */ 1553 if (ani->ofdm_phy_err_count > 1554 ani->listen_time * ani->ofdm_trig_high / 1000) { 1555 athn_ani_ofdm_err_trigger(sc); 1556 athn_ani_restart(sc); 1557 } else if (ani->cck_phy_err_count > 1558 ani->listen_time * ani->cck_trig_high / 1000) { 1559 athn_ani_cck_err_trigger(sc); 1560 athn_ani_restart(sc); 1561 } 1562 } 1563 } 1564 1565 uint8_t 1566 athn_chan2fbin(struct ieee80211_channel *c) 1567 { 1568 if (IEEE80211_IS_CHAN_2GHZ(c)) 1569 return (c->ic_freq - 2300); 1570 else 1571 return ((c->ic_freq - 4800) / 5); 1572 } 1573 1574 int 1575 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1576 { 1577 if (x1 == x2) /* Prevents division by zero. */ 1578 return (y1); 1579 /* Linear interpolation. */ 1580 return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1)); 1581 } 1582 1583 void 1584 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1585 int *lo, int *hi) 1586 { 1587 int i; 1588 1589 for (i = 0; i < npiers; i++) 1590 if (pierfreq[i] == AR_BCHAN_UNUSED || 1591 pierfreq[i] > fbin) 1592 break; 1593 *hi = i; 1594 *lo = *hi - 1; 1595 if (*lo == -1) 1596 *lo = *hi; 1597 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1598 *hi = *lo; 1599 } 1600 1601 void 1602 athn_init_dma(struct athn_softc *sc) 1603 { 1604 uint32_t reg; 1605 1606 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1607 /* Set AHB not to do cacheline prefetches. */ 1608 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1609 } 1610 reg = AR_READ(sc, AR_TXCFG); 1611 /* Let MAC DMA reads be in 128-byte chunks. */ 1612 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1613 1614 /* Set initial Tx trigger level. */ 1615 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1616 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1617 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1618 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1619 AR_WRITE(sc, AR_TXCFG, reg); 1620 1621 /* Let MAC DMA writes be in 128-byte chunks. */ 1622 reg = AR_READ(sc, AR_RXCFG); 1623 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1624 AR_WRITE(sc, AR_RXCFG, reg); 1625 1626 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1627 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1628 1629 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1630 if (AR_SREV_9285(sc)) { 1631 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1632 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1633 } else if (!AR_SREV_9271(sc)) { 1634 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1635 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1636 } 1637 AR_WRITE_BARRIER(sc); 1638 1639 /* Reset Tx status ring. */ 1640 if (AR_SREV_9380_10_OR_LATER(sc)) 1641 ar9003_reset_txsring(sc); 1642 } 1643 1644 void 1645 athn_inc_tx_trigger_level(struct athn_softc *sc) 1646 { 1647 uint32_t reg, ftrig; 1648 1649 reg = AR_READ(sc, AR_TXCFG); 1650 ftrig = MS(reg, AR_TXCFG_FTRIG); 1651 /* 1652 * NB: The AR9285 and all single-stream parts have an issue that 1653 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1654 */ 1655 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1656 return; /* Already at max. */ 1657 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1658 AR_WRITE(sc, AR_TXCFG, reg); 1659 AR_WRITE_BARRIER(sc); 1660 } 1661 1662 int 1663 athn_stop_rx_dma(struct athn_softc *sc) 1664 { 1665 int ntries; 1666 1667 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1668 /* Wait for Rx enable bit to go low. */ 1669 for (ntries = 0; ntries < 100; ntries++) { 1670 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1671 return (0); 1672 DELAY(100); 1673 } 1674 DPRINTF(("Rx DMA failed to stop\n")); 1675 return (ETIMEDOUT); 1676 } 1677 1678 int 1679 athn_rx_abort(struct athn_softc *sc) 1680 { 1681 int ntries; 1682 1683 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1684 for (ntries = 0; ntries < 1000; ntries++) { 1685 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1686 return (0); 1687 DELAY(10); 1688 } 1689 DPRINTF(("Rx failed to go idle in 10ms\n")); 1690 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1691 AR_WRITE_BARRIER(sc); 1692 return (ETIMEDOUT); 1693 } 1694 1695 void 1696 athn_tx_reclaim(struct athn_softc *sc, int qid) 1697 { 1698 struct athn_txq *txq = &sc->txq[qid]; 1699 struct athn_tx_buf *bf; 1700 1701 /* Reclaim all buffers queued in the specified Tx queue. */ 1702 /* NB: Tx DMA must be stopped. */ 1703 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1704 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1705 1706 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1707 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1708 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1709 m_freem(bf->bf_m); 1710 bf->bf_m = NULL; 1711 bf->bf_ni = NULL; /* Nodes already freed! */ 1712 1713 /* Link Tx buffer back to global free list. */ 1714 SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list); 1715 } 1716 } 1717 1718 int 1719 athn_tx_pending(struct athn_softc *sc, int qid) 1720 { 1721 return (MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1722 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0); 1723 } 1724 1725 void 1726 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1727 { 1728 uint32_t tsflo; 1729 int ntries, i; 1730 1731 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1732 for (ntries = 0; ntries < 40; ntries++) { 1733 if (!athn_tx_pending(sc, qid)) 1734 break; 1735 DELAY(100); 1736 } 1737 if (ntries == 40) { 1738 for (i = 0; i < 2; i++) { 1739 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1740 AR_WRITE(sc, AR_QUIET2, 1741 SM(AR_QUIET2_QUIET_DUR, 10)); 1742 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1743 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1744 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1745 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1746 break; 1747 } 1748 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1749 AR_WRITE_BARRIER(sc); 1750 DELAY(200); 1751 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1752 AR_WRITE_BARRIER(sc); 1753 1754 for (ntries = 0; ntries < 40; ntries++) { 1755 if (!athn_tx_pending(sc, qid)) 1756 break; 1757 DELAY(100); 1758 } 1759 1760 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1761 } 1762 AR_WRITE(sc, AR_Q_TXD, 0); 1763 AR_WRITE_BARRIER(sc); 1764 } 1765 1766 int 1767 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1768 { 1769 #define divround(a, b) (((a) + (b) - 1) / (b)) 1770 int txtime; 1771 1772 /* XXX HT. */ 1773 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1774 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1775 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1776 txtime = 16 + 4 + 4 * txtime + 16; 1777 } else { 1778 txtime = divround(16 * len, athn_rates[ridx].rate); 1779 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1780 txtime += 72 + 24; 1781 else 1782 txtime += 144 + 48; 1783 txtime += 10; /* 10us SIFS. */ 1784 } 1785 return (txtime); 1786 #undef divround 1787 } 1788 1789 void 1790 athn_init_tx_queues(struct athn_softc *sc) 1791 { 1792 int qid; 1793 1794 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1795 SIMPLEQ_INIT(&sc->txq[qid].head); 1796 sc->txq[qid].lastds = NULL; 1797 sc->txq[qid].wait = NULL; 1798 sc->txq[qid].queued = 0; 1799 1800 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1801 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1802 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1803 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1804 AR_WRITE(sc, AR_QMISC(qid), 1805 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1806 AR_WRITE(sc, AR_DMISC(qid), 1807 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1808 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1809 } 1810 1811 /* Init beacon queue. */ 1812 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1813 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1814 AR_Q_MISC_CBR_INCR_DIS1); 1815 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1816 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1817 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1818 AR_D_MISC_BEACON_USE | 1819 AR_D_MISC_POST_FR_BKOFF_DIS); 1820 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1821 SM(AR_D_LCL_IFS_CWMIN, 0) | 1822 SM(AR_D_LCL_IFS_CWMAX, 0) | 1823 SM(AR_D_LCL_IFS_AIFS, 1)); 1824 1825 /* Init CAB (Content After Beacon) queue. */ 1826 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1827 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1828 AR_Q_MISC_CBR_INCR_DIS0); 1829 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1830 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1831 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1832 1833 /* Init PS-Poll queue. */ 1834 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1835 AR_Q_MISC_CBR_INCR_DIS1); 1836 1837 /* Init UAPSD queue. */ 1838 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1839 AR_D_MISC_POST_FR_BKOFF_DIS); 1840 1841 if (AR_SREV_9380_10_OR_LATER(sc)) { 1842 /* Enable MAC descriptor CRC check. */ 1843 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1844 } 1845 /* Enable DESC interrupts for all Tx queues. */ 1846 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1847 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1848 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1849 AR_WRITE_BARRIER(sc); 1850 } 1851 1852 void 1853 athn_set_sta_timers(struct athn_softc *sc) 1854 { 1855 struct ieee80211com *ic = &sc->sc_ic; 1856 uint32_t tsfhi, tsflo, tsftu, reg; 1857 uint32_t intval, next_tbtt, next_dtim; 1858 int dtim_period, dtim_count, rem_dtim_count; 1859 1860 tsfhi = AR_READ(sc, AR_TSF_U32); 1861 tsflo = AR_READ(sc, AR_TSF_L32); 1862 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1863 1864 /* Beacon interval in TU. */ 1865 intval = ic->ic_bss->ni_intval; 1866 1867 next_tbtt = roundup(tsftu, intval); 1868 #ifdef notyet 1869 dtim_period = ic->ic_dtim_period; 1870 if (dtim_period <= 0) 1871 #endif 1872 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 1873 1874 #ifdef notyet 1875 dtim_count = ic->ic_dtim_count; 1876 if (dtim_count >= dtim_period) /* Should not happen. */ 1877 #endif 1878 dtim_count = 0; /* Assume last TIM was a DTIM. */ 1879 1880 /* Compute number of remaining TIMs until next DTIM. */ 1881 rem_dtim_count = 0; /* XXX */ 1882 next_dtim = next_tbtt + rem_dtim_count * intval; 1883 1884 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 1885 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1886 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1887 1888 /* 1889 * Set the number of consecutive beacons to miss before raising 1890 * a BMISS interrupt to 10. 1891 */ 1892 reg = AR_READ(sc, AR_RSSI_THR); 1893 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 1894 AR_WRITE(sc, AR_RSSI_THR, reg); 1895 1896 AR_WRITE(sc, AR_NEXT_DTIM, 1897 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1898 AR_WRITE(sc, AR_NEXT_TIM, 1899 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 1900 1901 /* CAB timeout is in 1/8 TU. */ 1902 AR_WRITE(sc, AR_SLEEP1, 1903 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 1904 AR_SLEEP1_ASSUME_DTIM); 1905 AR_WRITE(sc, AR_SLEEP2, 1906 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 1907 1908 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 1909 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 1910 1911 AR_SETBITS(sc, AR_TIMER_MODE, 1912 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 1913 1914 /* Set TSF out-of-range threshold (fixed at 16k us). */ 1915 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 1916 1917 AR_WRITE_BARRIER(sc); 1918 } 1919 1920 #ifndef IEEE80211_STA_ONLY 1921 void 1922 athn_set_hostap_timers(struct athn_softc *sc) 1923 { 1924 struct ieee80211com *ic = &sc->sc_ic; 1925 uint32_t intval, next_tbtt; 1926 1927 /* Beacon interval in TU. */ 1928 intval = ic->ic_bss->ni_intval; 1929 next_tbtt = intval; 1930 1931 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 1932 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 1933 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 1934 AR_WRITE(sc, AR_NEXT_CFP, 1935 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 1936 1937 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1938 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 1939 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 1940 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 1941 1942 AR_WRITE(sc, AR_TIMER_MODE, 1943 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 1944 1945 AR_WRITE_BARRIER(sc); 1946 } 1947 #endif 1948 1949 void 1950 athn_set_opmode(struct athn_softc *sc) 1951 { 1952 uint32_t reg; 1953 1954 switch (sc->sc_ic.ic_opmode) { 1955 #ifndef IEEE80211_STA_ONLY 1956 case IEEE80211_M_HOSTAP: 1957 reg = AR_READ(sc, AR_STA_ID1); 1958 reg &= ~AR_STA_ID1_ADHOC; 1959 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 1960 AR_WRITE(sc, AR_STA_ID1, reg); 1961 1962 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1963 break; 1964 case IEEE80211_M_IBSS: 1965 case IEEE80211_M_AHDEMO: 1966 reg = AR_READ(sc, AR_STA_ID1); 1967 reg &= ~AR_STA_ID1_STA_AP; 1968 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 1969 AR_WRITE(sc, AR_STA_ID1, reg); 1970 1971 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1972 break; 1973 #endif 1974 default: 1975 reg = AR_READ(sc, AR_STA_ID1); 1976 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 1977 reg |= AR_STA_ID1_KSRCH_MODE; 1978 AR_WRITE(sc, AR_STA_ID1, reg); 1979 break; 1980 } 1981 AR_WRITE_BARRIER(sc); 1982 } 1983 1984 void 1985 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 1986 { 1987 const uint8_t *bssid = ni->ni_bssid; 1988 1989 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 1990 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 1991 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 1992 AR_WRITE_BARRIER(sc); 1993 } 1994 1995 void 1996 athn_enable_interrupts(struct athn_softc *sc) 1997 { 1998 uint32_t mask2; 1999 2000 athn_disable_interrupts(sc); /* XXX */ 2001 2002 AR_WRITE(sc, AR_IMR, sc->imask); 2003 2004 mask2 = AR_READ(sc, AR_IMR_S2); 2005 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2006 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2007 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2008 AR_WRITE(sc, AR_IMR_S2, mask2); 2009 2010 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2011 2012 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2013 2014 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2015 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2016 2017 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync); 2018 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync); 2019 AR_WRITE_BARRIER(sc); 2020 } 2021 2022 void 2023 athn_disable_interrupts(struct athn_softc *sc) 2024 { 2025 AR_WRITE(sc, AR_IER, 0); 2026 (void)AR_READ(sc, AR_IER); 2027 2028 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2029 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2030 2031 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2032 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2033 2034 AR_WRITE(sc, AR_IMR, 0); 2035 2036 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2037 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2038 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2039 2040 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2041 AR_WRITE_BARRIER(sc); 2042 } 2043 2044 void 2045 athn_init_qos(struct athn_softc *sc) 2046 { 2047 /* Initialize QoS settings. */ 2048 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2049 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2050 AR_WRITE(sc, AR_QOS_NO_ACK, 2051 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2052 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2053 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2054 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2055 /* Initialize TXOP for all TIDs. */ 2056 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2057 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2058 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2059 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2060 AR_WRITE_BARRIER(sc); 2061 } 2062 2063 int 2064 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c, 2065 struct ieee80211_channel *extc, int init) 2066 { 2067 struct ieee80211com *ic = &sc->sc_ic; 2068 struct athn_ops *ops = &sc->ops; 2069 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2070 int i, error; 2071 2072 /* XXX not if already awake */ 2073 if ((error = athn_set_power_awake(sc)) != 0) { 2074 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 2075 return (error); 2076 } 2077 2078 /* Preserve the antenna on a channel switch. */ 2079 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2080 def_ant = 1; 2081 /* Preserve other registers. */ 2082 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2083 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2084 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2085 AR_CFG_LED_BLINK_SLOW); 2086 2087 /* Mark PHY as inactive. */ 2088 ops->disable_phy(sc); 2089 2090 if (init && AR_SREV_9271(sc)) { 2091 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2092 AR9271_RADIO_RF_RST); 2093 DELAY(50); 2094 } 2095 if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) { 2096 /* Save TSF before it gets cleared. */ 2097 tsfhi = AR_READ(sc, AR_TSF_U32); 2098 tsflo = AR_READ(sc, AR_TSF_L32); 2099 2100 /* NB: RTC reset clears TSF. */ 2101 error = athn_reset_power_on(sc); 2102 } else 2103 error = athn_reset(sc, 0); 2104 if (error != 0) { 2105 printf("%s: could not reset chip (error=%d)\n", 2106 sc->sc_dev.dv_xname, error); 2107 return (error); 2108 } 2109 2110 /* XXX not if already awake */ 2111 if ((error = athn_set_power_awake(sc)) != 0) { 2112 printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname); 2113 return (error); 2114 } 2115 2116 athn_init_pll(sc, c); 2117 ops->set_rf_mode(sc, c); 2118 2119 if (sc->flags & ATHN_FLAG_RFSILENT) { 2120 /* Check that the radio is not disabled by hardware switch. */ 2121 reg = ops->gpio_read(sc, sc->rfsilent_pin); 2122 if (sc->flags & ATHN_FLAG_RFSILENT_REVERSED) 2123 reg = !reg; 2124 if (!reg) { 2125 printf("%s: radio is disabled by hardware switch\n", 2126 sc->sc_dev.dv_xname); 2127 return (EPERM); 2128 } 2129 } 2130 if (init && AR_SREV_9271(sc)) { 2131 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2132 AR9271_GATE_MAC_CTL); 2133 DELAY(50); 2134 } 2135 if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) { 2136 /* Restore TSF if it got cleared. */ 2137 AR_WRITE(sc, AR_TSF_L32, tsflo); 2138 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2139 } 2140 2141 if (AR_SREV_9280_10_OR_LATER(sc)) 2142 AR_SETBITS(sc, sc->gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2143 2144 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2145 ar9287_1_3_enable_async_fifo(sc); 2146 2147 /* Write init values to hardware. */ 2148 ops->hw_init(sc, c, extc); 2149 2150 /* 2151 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2152 * management frames using CCMP. 2153 */ 2154 if (AR_SREV_9280_20_OR_LATER(sc)) { 2155 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2156 /* Do not mask the subtype field in management frames. */ 2157 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2158 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2159 ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2160 IEEE80211_FC1_MORE_DATA)); 2161 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2162 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 2163 /* Disable hardware crypto for management frames. */ 2164 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2165 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2166 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2167 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2168 } 2169 2170 if (ic->ic_curmode != IEEE80211_MODE_11B) 2171 ops->set_delta_slope(sc, c, extc); 2172 2173 ops->spur_mitigate(sc, c, extc); 2174 ops->init_from_rom(sc, c, extc); 2175 2176 /* XXX */ 2177 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2178 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2179 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2180 2181 athn_set_opmode(sc); 2182 2183 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2184 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2185 2186 /* Restore previous antenna. */ 2187 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2188 2189 AR_WRITE(sc, AR_BSS_ID0, 0); 2190 AR_WRITE(sc, AR_BSS_ID1, 0); 2191 2192 AR_WRITE(sc, AR_ISR, 0xffffffff); 2193 2194 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2195 2196 if ((error = ops->set_synth(sc, c, extc)) != 0) { 2197 printf("%s: could not set channel\n", sc->sc_dev.dv_xname); 2198 return (error); 2199 } 2200 sc->curchan = c; 2201 sc->curchanext = extc; 2202 2203 for (i = 0; i < AR_NUM_DCU; i++) 2204 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2205 2206 athn_init_tx_queues(sc); 2207 2208 /* Initialize interrupt mask. */ 2209 sc->imask = 2210 AR_IMR_TXDESC | AR_IMR_TXEOL | 2211 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2212 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2213 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2214 if (AR_SREV_9380_10_OR_LATER(sc)) 2215 sc->imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2216 #ifndef IEEE80211_STA_ONLY 2217 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2218 sc->imask |= AR_IMR_MIB; 2219 #endif 2220 AR_WRITE(sc, AR_IMR, sc->imask); 2221 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2222 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2223 sc->isync = AR_INTR_SYNC_DEFAULT; 2224 if (sc->flags & ATHN_FLAG_RFSILENT) 2225 sc->isync |= AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin); 2226 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync); 2227 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2228 if (AR_SREV_9380_10_OR_LATER(sc)) { 2229 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2230 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2231 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2232 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2233 } 2234 2235 athn_init_qos(sc); 2236 2237 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2238 2239 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2240 ar9287_1_3_setup_async_fifo(sc); 2241 2242 /* Disable sequence number generation in hardware. */ 2243 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2244 2245 athn_init_dma(sc); 2246 2247 /* Program observation bus to see MAC interrupts. */ 2248 AR_WRITE(sc, sc->obs_off, 8); 2249 2250 /* Setup Rx interrupt mitigation. */ 2251 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2252 2253 ops->init_baseband(sc); 2254 2255 if ((error = athn_init_calib(sc, c, extc)) != 0) { 2256 printf("%s: could not initialize calibration\n", 2257 sc->sc_dev.dv_xname); 2258 return (error); 2259 } 2260 2261 ops->set_rxchains(sc); 2262 2263 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2264 2265 if (sc->flags & ATHN_FLAG_USB) { 2266 if (AR_SREV_9271(sc)) 2267 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2268 else 2269 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2270 } 2271 #if BYTE_ORDER == BIG_ENDIAN 2272 else { 2273 /* Default is LE, turn on swapping for BE. */ 2274 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2275 } 2276 #endif 2277 AR_WRITE_BARRIER(sc); 2278 2279 return (0); 2280 } 2281 2282 struct ieee80211_node * 2283 athn_node_alloc(struct ieee80211com *ic) 2284 { 2285 return (malloc(sizeof(struct athn_node), M_DEVBUF, M_NOWAIT | M_ZERO)); 2286 } 2287 2288 void 2289 athn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2290 { 2291 struct athn_softc *sc = ic->ic_softc; 2292 struct athn_node *an = (void *)ni; 2293 struct ieee80211_rateset *rs = &ni->ni_rates; 2294 uint8_t rate; 2295 int ridx, i, j; 2296 2297 ieee80211_amrr_node_init(&sc->amrr, &an->amn); 2298 /* Start at lowest available bit-rate, AMRR will raise. */ 2299 ni->ni_txrate = 0; 2300 2301 for (i = 0; i < rs->rs_nrates; i++) { 2302 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2303 2304 /* Map 802.11 rate to HW rate index. */ 2305 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2306 if (athn_rates[ridx].rate == rate) 2307 break; 2308 an->ridx[i] = ridx; 2309 DPRINTFN(2, ("rate %d index %d\n", rate, ridx)); 2310 2311 /* Compute fallback rate for retries. */ 2312 an->fallback[i] = i; 2313 for (j = i - 1; j >= 0; j--) { 2314 if (athn_rates[an->ridx[j]].phy == 2315 athn_rates[an->ridx[i]].phy) { 2316 an->fallback[i] = j; 2317 break; 2318 } 2319 } 2320 DPRINTFN(2, ("%d fallbacks to %d\n", i, an->fallback[i])); 2321 } 2322 } 2323 2324 int 2325 athn_media_change(struct ifnet *ifp) 2326 { 2327 struct athn_softc *sc = ifp->if_softc; 2328 struct ieee80211com *ic = &sc->sc_ic; 2329 uint8_t rate, ridx; 2330 int error; 2331 2332 error = ieee80211_media_change(ifp); 2333 if (error != ENETRESET) 2334 return (error); 2335 2336 if (ic->ic_fixed_rate != -1) { 2337 rate = ic->ic_sup_rates[ic->ic_curmode]. 2338 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2339 /* Map 802.11 rate to HW rate index. */ 2340 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2341 if (athn_rates[ridx].rate == rate) 2342 break; 2343 sc->fixed_ridx = ridx; 2344 } 2345 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2346 (IFF_UP | IFF_RUNNING)) { 2347 athn_stop(ifp, 0); 2348 error = athn_init(ifp); 2349 } 2350 return (error); 2351 } 2352 2353 void 2354 athn_next_scan(void *arg) 2355 { 2356 struct athn_softc *sc = arg; 2357 struct ieee80211com *ic = &sc->sc_ic; 2358 int s; 2359 2360 s = splnet(); 2361 if (ic->ic_state == IEEE80211_S_SCAN) 2362 ieee80211_next_scan(&ic->ic_if); 2363 splx(s); 2364 } 2365 2366 int 2367 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2368 { 2369 struct ifnet *ifp = &ic->ic_if; 2370 struct athn_softc *sc = ifp->if_softc; 2371 uint32_t reg; 2372 int error; 2373 2374 timeout_del(&sc->calib_to); 2375 2376 switch (nstate) { 2377 case IEEE80211_S_INIT: 2378 athn_set_led(sc, 0); 2379 break; 2380 case IEEE80211_S_SCAN: 2381 /* Make the LED blink while scanning. */ 2382 athn_set_led(sc, !sc->led_state); 2383 error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL); 2384 if (error != 0) 2385 return (error); 2386 timeout_add_msec(&sc->scan_to, 200); 2387 break; 2388 case IEEE80211_S_AUTH: 2389 athn_set_led(sc, 0); 2390 error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL); 2391 if (error != 0) 2392 return (error); 2393 break; 2394 case IEEE80211_S_ASSOC: 2395 break; 2396 case IEEE80211_S_RUN: 2397 athn_set_led(sc, 1); 2398 2399 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2400 break; 2401 2402 /* Fake a join to initialize the Tx rate. */ 2403 athn_newassoc(ic, ic->ic_bss, 1); 2404 2405 athn_set_bss(sc, ic->ic_bss); 2406 athn_disable_interrupts(sc); 2407 #ifndef IEEE80211_STA_ONLY 2408 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2409 athn_set_hostap_timers(sc); 2410 /* Enable sotfware beacon alert interrupts. */ 2411 sc->imask |= AR_IMR_SWBA; 2412 } else 2413 #endif 2414 { 2415 athn_set_sta_timers(sc); 2416 /* Enable beacon miss interrupts. */ 2417 sc->imask |= AR_IMR_BMISS; 2418 2419 /* Stop receiving beacons from other BSS. */ 2420 reg = AR_READ(sc, AR_RX_FILTER); 2421 reg = (reg & ~AR_RX_FILTER_BEACON) | 2422 AR_RX_FILTER_MYBEACON; 2423 AR_WRITE(sc, AR_RX_FILTER, reg); 2424 AR_WRITE_BARRIER(sc); 2425 } 2426 athn_enable_interrupts(sc); 2427 2428 if (sc->sup_calib_mask != 0) { 2429 memset(&sc->calib, 0, sizeof(sc->calib)); 2430 sc->cur_calib_mask = sc->sup_calib_mask; 2431 /* ops->do_calib(sc); */ 2432 } 2433 /* XXX Start ANI. */ 2434 2435 timeout_add_msec(&sc->calib_to, 500); 2436 break; 2437 } 2438 2439 return (sc->sc_newstate(ic, nstate, arg)); 2440 } 2441 2442 void 2443 athn_updateedca(struct ieee80211com *ic) 2444 { 2445 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2446 struct athn_softc *sc = ic->ic_softc; 2447 const struct ieee80211_edca_ac_params *ac; 2448 int aci, qid; 2449 2450 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2451 ac = &ic->ic_edca_ac[aci]; 2452 qid = athn_ac2qid[aci]; 2453 2454 AR_WRITE(sc, AR_DLCL_IFS(qid), 2455 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2456 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2457 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2458 if (ac->ac_txoplimit != 0) { 2459 AR_WRITE(sc, AR_DCHNTIME(qid), 2460 SM(AR_D_CHNTIME_DUR, 2461 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2462 AR_D_CHNTIME_EN); 2463 } else 2464 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2465 } 2466 AR_WRITE_BARRIER(sc); 2467 #undef ATHN_EXP2 2468 } 2469 2470 int 2471 athn_clock_rate(struct athn_softc *sc) 2472 { 2473 struct ieee80211com *ic = &sc->sc_ic; 2474 int clockrate; /* MHz. */ 2475 2476 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2477 if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK) 2478 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2479 else 2480 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2481 } else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2482 clockrate = AR_CLOCK_RATE_CCK; 2483 } else 2484 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2485 #ifndef IEEE80211_NO_HT 2486 if (sc->curchanext != NULL) 2487 clockrate *= 2; 2488 #endif 2489 return (clockrate); 2490 } 2491 2492 void 2493 athn_updateslot(struct ieee80211com *ic) 2494 { 2495 struct athn_softc *sc = ic->ic_softc; 2496 int slot; 2497 2498 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2499 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2500 AR_WRITE_BARRIER(sc); 2501 } 2502 2503 void 2504 athn_start(struct ifnet *ifp) 2505 { 2506 struct athn_softc *sc = ifp->if_softc; 2507 struct ieee80211com *ic = &sc->sc_ic; 2508 struct ieee80211_node *ni; 2509 struct mbuf *m; 2510 2511 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2512 return; 2513 2514 for (;;) { 2515 if (SIMPLEQ_EMPTY(&sc->txbufs)) { 2516 ifp->if_flags |= IFF_OACTIVE; 2517 break; 2518 } 2519 /* Send pending management frames first. */ 2520 IF_DEQUEUE(&ic->ic_mgtq, m); 2521 if (m != NULL) { 2522 ni = (void *)m->m_pkthdr.rcvif; 2523 goto sendit; 2524 } 2525 if (ic->ic_state != IEEE80211_S_RUN) 2526 break; 2527 2528 /* Encapsulate and send data frames. */ 2529 IFQ_DEQUEUE(&ifp->if_snd, m); 2530 if (m == NULL) 2531 break; 2532 #if NBPFILTER > 0 2533 if (ifp->if_bpf != NULL) 2534 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2535 #endif 2536 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2537 continue; 2538 sendit: 2539 #if NBPFILTER > 0 2540 if (ic->ic_rawbpf != NULL) 2541 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2542 #endif 2543 if (sc->ops.tx(sc, m, ni, 0) != 0) { 2544 ieee80211_release_node(ic, ni); 2545 ifp->if_oerrors++; 2546 continue; 2547 } 2548 2549 sc->sc_tx_timer = 5; 2550 ifp->if_timer = 1; 2551 } 2552 } 2553 2554 void 2555 athn_watchdog(struct ifnet *ifp) 2556 { 2557 struct athn_softc *sc = ifp->if_softc; 2558 2559 ifp->if_timer = 0; 2560 2561 if (sc->sc_tx_timer > 0) { 2562 if (--sc->sc_tx_timer == 0) { 2563 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2564 athn_stop(ifp, 1); 2565 (void)athn_init(ifp); 2566 ifp->if_oerrors++; 2567 return; 2568 } 2569 ifp->if_timer = 1; 2570 } 2571 2572 ieee80211_watchdog(ifp); 2573 } 2574 2575 void 2576 athn_set_multi(struct athn_softc *sc) 2577 { 2578 struct arpcom *ac = &sc->sc_ic.ic_ac; 2579 struct ifnet *ifp = &ac->ac_if; 2580 struct ether_multi *enm; 2581 struct ether_multistep step; 2582 const uint8_t *addr; 2583 uint32_t val, lo, hi; 2584 uint8_t bit; 2585 2586 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2587 lo = hi = 0xffffffff; 2588 goto done; 2589 } 2590 lo = hi = 0; 2591 ETHER_FIRST_MULTI(step, ac, enm); 2592 while (enm != NULL) { 2593 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2594 ifp->if_flags |= IFF_ALLMULTI; 2595 lo = hi = 0xffffffff; 2596 goto done; 2597 } 2598 addr = enm->enm_addrlo; 2599 /* Calculate the XOR value of all eight 6-bit words. */ 2600 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2601 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2602 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2603 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2604 bit &= 0x3f; 2605 if (bit < 32) 2606 lo |= 1 << bit; 2607 else 2608 hi |= 1 << (bit - 32); 2609 ETHER_NEXT_MULTI(step, enm); 2610 } 2611 done: 2612 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2613 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2614 AR_WRITE_BARRIER(sc); 2615 } 2616 2617 int 2618 athn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2619 { 2620 struct athn_softc *sc = ifp->if_softc; 2621 struct ieee80211com *ic = &sc->sc_ic; 2622 struct ifaddr *ifa; 2623 struct ifreq *ifr; 2624 int s, error = 0; 2625 2626 s = splnet(); 2627 2628 switch (cmd) { 2629 case SIOCSIFADDR: 2630 ifa = (struct ifaddr *)data; 2631 ifp->if_flags |= IFF_UP; 2632 #ifdef INET 2633 if (ifa->ifa_addr->sa_family == AF_INET) 2634 arp_ifinit(&ic->ic_ac, ifa); 2635 #endif 2636 /* FALLTHROUGH */ 2637 case SIOCSIFFLAGS: 2638 if (ifp->if_flags & IFF_UP) { 2639 if ((ifp->if_flags & IFF_RUNNING) && 2640 ((ifp->if_flags ^ sc->sc_if_flags) & 2641 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2642 athn_set_multi(sc); 2643 } else if (!(ifp->if_flags & IFF_RUNNING)) 2644 error = athn_init(ifp); 2645 } else { 2646 if (ifp->if_flags & IFF_RUNNING) 2647 athn_stop(ifp, 1); 2648 } 2649 sc->sc_if_flags = ifp->if_flags; 2650 break; 2651 2652 case SIOCADDMULTI: 2653 case SIOCDELMULTI: 2654 ifr = (struct ifreq *)data; 2655 error = (cmd == SIOCADDMULTI) ? 2656 ether_addmulti(ifr, &ic->ic_ac) : 2657 ether_delmulti(ifr, &ic->ic_ac); 2658 if (error == ENETRESET) { 2659 athn_set_multi(sc); 2660 error = 0; 2661 } 2662 break; 2663 2664 case SIOCS80211CHANNEL: 2665 error = ieee80211_ioctl(ifp, cmd, data); 2666 if (error == ENETRESET && 2667 ic->ic_opmode == IEEE80211_M_MONITOR) { 2668 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2669 (IFF_UP | IFF_RUNNING)) 2670 athn_switch_chan(sc, ic->ic_ibss_chan, NULL); 2671 error = 0; 2672 } 2673 break; 2674 2675 default: 2676 error = ieee80211_ioctl(ifp, cmd, data); 2677 } 2678 2679 if (error == ENETRESET) { 2680 error = 0; 2681 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2682 (IFF_UP | IFF_RUNNING)) { 2683 athn_stop(ifp, 0); 2684 error = athn_init(ifp); 2685 } 2686 } 2687 2688 splx(s); 2689 return (error); 2690 } 2691 2692 int 2693 athn_init(struct ifnet *ifp) 2694 { 2695 struct athn_softc *sc = ifp->if_softc; 2696 struct athn_ops *ops = &sc->ops; 2697 struct ieee80211com *ic = &sc->sc_ic; 2698 struct ieee80211_channel *c, *extc; 2699 int i, error; 2700 2701 c = ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2702 extc = NULL; 2703 2704 /* In case a new MAC address has been configured. */ 2705 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2706 2707 /* For CardBus, power on the socket. */ 2708 if (sc->sc_enable != NULL) { 2709 if ((error = sc->sc_enable(sc)) != 0) { 2710 printf("%s: could not enable device\n", 2711 sc->sc_dev.dv_xname); 2712 goto fail; 2713 } 2714 if ((error = athn_reset_power_on(sc)) != 0) { 2715 printf("%s: could not power on device\n", 2716 sc->sc_dev.dv_xname); 2717 goto fail; 2718 } 2719 } 2720 if (!(sc->flags & ATHN_FLAG_PCIE)) 2721 athn_config_nonpcie(sc); 2722 else 2723 athn_config_pcie(sc); 2724 2725 /* Reset HW key cache entries. */ 2726 for (i = 0; i < sc->kc_entries; i++) 2727 athn_reset_key(sc, i); 2728 2729 ops->enable_antenna_diversity(sc); 2730 2731 #ifdef ATHN_BT_COEXISTENCE 2732 /* Configure bluetooth coexistence for combo chips. */ 2733 if (sc->flags & ATHN_FLAG_BTCOEX) 2734 athn_btcoex_init(sc); 2735 #endif 2736 2737 /* Configure LED. */ 2738 athn_led_init(sc); 2739 2740 /* Configure hardware radio switch. */ 2741 if (sc->flags & ATHN_FLAG_RFSILENT) 2742 ops->rfsilent_init(sc); 2743 2744 if ((error = athn_hw_reset(sc, c, extc, 1)) != 0) { 2745 printf("%s: unable to reset hardware; reset status %d\n", 2746 sc->sc_dev.dv_xname, error); 2747 goto fail; 2748 } 2749 2750 /* Enable Rx. */ 2751 athn_rx_start(sc); 2752 2753 /* Enable interrupts. */ 2754 athn_enable_interrupts(sc); 2755 2756 #ifdef ATHN_BT_COEXISTENCE 2757 /* Enable bluetooth coexistence for combo chips. */ 2758 if (sc->flags & ATHN_FLAG_BTCOEX) 2759 athn_btcoex_enable(sc); 2760 #endif 2761 2762 ifp->if_flags &= ~IFF_OACTIVE; 2763 ifp->if_flags |= IFF_RUNNING; 2764 2765 #ifdef notyet 2766 if (ic->ic_flags & IEEE80211_F_WEPON) { 2767 /* Configure WEP keys. */ 2768 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2769 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2770 } 2771 #endif 2772 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2773 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2774 else 2775 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2776 2777 return (0); 2778 fail: 2779 athn_stop(ifp, 1); 2780 return (error); 2781 } 2782 2783 void 2784 athn_stop(struct ifnet *ifp, int disable) 2785 { 2786 struct athn_softc *sc = ifp->if_softc; 2787 struct ieee80211com *ic = &sc->sc_ic; 2788 int qid; 2789 2790 ifp->if_timer = sc->sc_tx_timer = 0; 2791 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2792 2793 timeout_del(&sc->scan_to); 2794 /* In case we were scanning, release the scan "lock". */ 2795 ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; 2796 2797 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2798 2799 #ifdef ATHN_BT_COEXISTENCE 2800 /* Disable bluetooth coexistence for combo chips. */ 2801 if (sc->flags & ATHN_FLAG_BTCOEX) 2802 athn_btcoex_disable(sc); 2803 #endif 2804 2805 /* Disable interrupts. */ 2806 athn_disable_interrupts(sc); 2807 /* Acknowledge interrupts (avoids interrupt storms). */ 2808 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2809 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2810 2811 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2812 athn_stop_tx_dma(sc, qid); 2813 /* XXX call athn_hw_reset if Tx still pending? */ 2814 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2815 athn_tx_reclaim(sc, qid); 2816 2817 /* Stop Rx. */ 2818 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2819 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2820 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2821 AR_WRITE(sc, AR_FILT_OFDM, 0); 2822 AR_WRITE(sc, AR_FILT_CCK, 0); 2823 AR_WRITE_BARRIER(sc); 2824 athn_set_rxfilter(sc, 0); 2825 athn_stop_rx_dma(sc); 2826 2827 athn_reset(sc, 0); 2828 athn_init_pll(sc, NULL); 2829 athn_set_power_awake(sc); 2830 athn_reset(sc, 1); 2831 athn_init_pll(sc, NULL); 2832 2833 athn_set_power_sleep(sc); 2834 2835 /* For CardBus, power down the socket. */ 2836 if (disable && sc->sc_disable != NULL) 2837 sc->sc_disable(sc); 2838 } 2839 2840 void 2841 athn_suspend(struct athn_softc *sc) 2842 { 2843 struct ifnet *ifp = &sc->sc_ic.ic_if; 2844 2845 if (ifp->if_flags & IFF_RUNNING) 2846 athn_stop(ifp, 1); 2847 } 2848 2849 void 2850 athn_resume(struct athn_softc *sc) 2851 { 2852 struct ifnet *ifp = &sc->sc_ic.ic_if; 2853 2854 if (ifp->if_flags & IFF_UP) 2855 athn_init(ifp); 2856 } 2857