1 /* $OpenBSD: athnvar.h,v 1.35 2013/12/06 21:03:02 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifdef notyet 20 #define ATHN_BT_COEXISTENCE 1 21 #endif 22 23 #ifdef ATHN_DEBUG 24 #define DPRINTF(x) do { if (athn_debug > 0) printf x; } while (0) 25 #define DPRINTFN(n, x) do { if (athn_debug >= (n)) printf x; } while (0) 26 extern int athn_debug; 27 #else 28 #define DPRINTF(x) 29 #define DPRINTFN(n, x) 30 #endif 31 32 #define LE_READ_4(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 33 #define LE_READ_2(p) ((p)[0] | (p)[1] << 8) 34 35 #define ATHN_RXBUFSZ 3872 36 #define ATHN_TXBUFSZ 4096 37 38 #define ATHN_NRXBUFS 64 39 #define ATHN_NTXBUFS 64 /* Shared between all Tx queues. */ 40 41 struct athn_rx_radiotap_header { 42 struct ieee80211_radiotap_header wr_ihdr; 43 uint64_t wr_tsft; 44 uint8_t wr_flags; 45 uint8_t wr_rate; 46 uint16_t wr_chan_freq; 47 uint16_t wr_chan_flags; 48 int8_t wr_dbm_antsignal; 49 uint8_t wr_antenna; 50 } __packed; 51 52 #define ATHN_RX_RADIOTAP_PRESENT \ 53 (1 << IEEE80211_RADIOTAP_TSFT | \ 54 1 << IEEE80211_RADIOTAP_FLAGS | \ 55 1 << IEEE80211_RADIOTAP_RATE | \ 56 1 << IEEE80211_RADIOTAP_CHANNEL | \ 57 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | \ 58 1 << IEEE80211_RADIOTAP_ANTENNA) 59 60 struct athn_tx_radiotap_header { 61 struct ieee80211_radiotap_header wt_ihdr; 62 uint8_t wt_flags; 63 uint8_t wt_rate; 64 uint16_t wt_chan_freq; 65 uint16_t wt_chan_flags; 66 uint8_t wt_hwqueue; 67 } __packed; 68 69 #define ATHN_TX_RADIOTAP_PRESENT \ 70 (1 << IEEE80211_RADIOTAP_FLAGS | \ 71 1 << IEEE80211_RADIOTAP_RATE | \ 72 1 << IEEE80211_RADIOTAP_CHANNEL | \ 73 1 << IEEE80211_RADIOTAP_HWQUEUE) 74 75 struct athn_tx_buf { 76 SIMPLEQ_ENTRY(athn_tx_buf) bf_list; 77 78 void *bf_descs; 79 bus_dmamap_t bf_map; 80 bus_addr_t bf_daddr; 81 82 struct mbuf *bf_m; 83 struct ieee80211_node *bf_ni; 84 int bf_txflags; 85 #define ATHN_TXFLAG_PAPRD (1 << 0) 86 #define ATHN_TXFLAG_CAB (1 << 1) 87 }; 88 89 struct athn_txq { 90 SIMPLEQ_HEAD(, athn_tx_buf) head; 91 void *lastds; 92 struct athn_tx_buf *wait; 93 int queued; 94 }; 95 96 struct athn_rx_buf { 97 SIMPLEQ_ENTRY(athn_rx_buf) bf_list; 98 99 void *bf_desc; 100 bus_dmamap_t bf_map; 101 102 struct mbuf *bf_m; 103 bus_addr_t bf_daddr; 104 }; 105 106 struct athn_rxq { 107 struct athn_rx_buf *bf; 108 109 void *descs; 110 void *lastds; 111 bus_dmamap_t map; 112 bus_dma_segment_t seg; 113 int count; 114 115 SIMPLEQ_HEAD(, athn_rx_buf) head; 116 }; 117 118 /* Software rate indexes. */ 119 #define ATHN_RIDX_CCK1 0 120 #define ATHN_RIDX_CCK2 1 121 #define ATHN_RIDX_OFDM6 4 122 #define ATHN_RIDX_MCS0 12 123 #define ATHN_RIDX_MCS15 27 124 #define ATHN_RIDX_MAX 27 125 #define ATHN_IS_HT_RIDX(ridx) ((ridx) >= ATHN_RIDX_MCS0) 126 127 static const struct athn_rate { 128 uint8_t rate; /* Rate in 500Kbps unit or MCS if 0x80. */ 129 uint8_t hwrate; /* HW representation. */ 130 uint8_t rspridx; /* Control Response Frame rate index. */ 131 enum ieee80211_phytype phy; 132 } athn_rates[] = { 133 { 2, 0x1b, 0, IEEE80211_T_DS }, 134 { 4, 0x1a, 1, IEEE80211_T_DS }, 135 { 11, 0x19, 1, IEEE80211_T_DS }, 136 { 22, 0x18, 1, IEEE80211_T_DS }, 137 { 12, 0x0b, 4, IEEE80211_T_OFDM }, 138 { 18, 0x0f, 4, IEEE80211_T_OFDM }, 139 { 24, 0x0a, 6, IEEE80211_T_OFDM }, 140 { 36, 0x0e, 6, IEEE80211_T_OFDM }, 141 { 48, 0x09, 8, IEEE80211_T_OFDM }, 142 { 72, 0x0d, 8, IEEE80211_T_OFDM }, 143 { 96, 0x08, 8, IEEE80211_T_OFDM }, 144 { 108, 0x0c, 8, IEEE80211_T_OFDM }, 145 { 0x80, 0x80, 8, IEEE80211_T_OFDM }, 146 { 0x81, 0x81, 8, IEEE80211_T_OFDM }, 147 { 0x82, 0x82, 8, IEEE80211_T_OFDM }, 148 { 0x83, 0x83, 8, IEEE80211_T_OFDM }, 149 { 0x84, 0x84, 8, IEEE80211_T_OFDM }, 150 { 0x85, 0x85, 8, IEEE80211_T_OFDM }, 151 { 0x86, 0x86, 8, IEEE80211_T_OFDM }, 152 { 0x87, 0x87, 8, IEEE80211_T_OFDM }, 153 { 0x88, 0x88, 8, IEEE80211_T_OFDM }, 154 { 0x89, 0x89, 8, IEEE80211_T_OFDM }, 155 { 0x8a, 0x8a, 8, IEEE80211_T_OFDM }, 156 { 0x8b, 0x8b, 8, IEEE80211_T_OFDM }, 157 { 0x8c, 0x8c, 8, IEEE80211_T_OFDM }, 158 { 0x8d, 0x8d, 8, IEEE80211_T_OFDM }, 159 { 0x8e, 0x8e, 8, IEEE80211_T_OFDM }, 160 { 0x8f, 0x8f, 8, IEEE80211_T_OFDM } 161 }; 162 163 struct athn_series { 164 uint16_t dur; 165 uint8_t hwrate; 166 }; 167 168 struct athn_pier { 169 uint8_t fbin; 170 const uint8_t *pwr[AR_PD_GAINS_IN_MASK]; 171 const uint8_t *vpd[AR_PD_GAINS_IN_MASK]; 172 }; 173 174 /* 175 * Structures used to store initialization values. 176 */ 177 struct athn_ini { 178 int nregs; 179 const uint16_t *regs; 180 const uint32_t *vals_5g20; 181 #ifndef IEEE80211_NO_HT 182 const uint32_t *vals_5g40; 183 const uint32_t *vals_2g40; 184 #endif 185 const uint32_t *vals_2g20; 186 int ncmregs; 187 const uint16_t *cmregs; 188 const uint32_t *cmvals; 189 int nfastregs; 190 const uint16_t *fastregs; 191 const uint32_t *fastvals_5g20; 192 #ifndef IEEE80211_NO_HT 193 const uint32_t *fastvals_5g40; 194 #endif 195 }; 196 197 struct athn_gain { 198 int nregs; 199 const uint16_t *regs; 200 const uint32_t *vals_5g; 201 const uint32_t *vals_2g; 202 }; 203 204 struct athn_addac { 205 int nvals; 206 const uint32_t *vals; 207 }; 208 209 struct athn_serdes { 210 int nvals; 211 const uint32_t *regs; 212 const uint32_t *vals; 213 }; 214 215 /* Rx queue software indexes. */ 216 #define ATHN_QID_LP 0 217 #define ATHN_QID_HP 1 218 219 /* Tx queue software indexes. */ 220 #define ATHN_QID_AC_BE 0 221 #define ATHN_QID_PSPOLL 1 222 #define ATHN_QID_AC_BK 2 223 #define ATHN_QID_AC_VI 3 224 #define ATHN_QID_AC_VO 4 225 #define ATHN_QID_UAPSD 5 226 #define ATHN_QID_CAB 6 227 #define ATHN_QID_BEACON 7 228 #define ATHN_QID_COUNT 8 229 230 /* Map Access Category to Tx queue Id. */ 231 static const uint8_t athn_ac2qid[EDCA_NUM_AC] = { 232 ATHN_QID_AC_BE, /* EDCA_AC_BE */ 233 ATHN_QID_AC_BK, /* EDCA_AC_BK */ 234 ATHN_QID_AC_VI, /* EDCA_AC_VI */ 235 ATHN_QID_AC_VO /* EDCA_AC_VO */ 236 }; 237 238 static const uint8_t athn_5ghz_chans[] = { 239 /* UNII 1. */ 240 36, 40, 44, 48, 241 /* UNII 2. */ 242 52, 56, 60, 64, 243 /* Middle band. */ 244 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 245 /* UNII 3. */ 246 149, 153, 157, 161, 165 247 }; 248 249 /* Number of data bits per OFDM symbol for MCS[0-15]. */ 250 /* See tables 20-29, 20-30, 20-33, 20-34. */ 251 static const uint16_t ar_mcs_ndbps[][2] = { 252 /* 20MHz 40MHz */ 253 { 26, 54 }, /* MCS0 */ 254 { 52, 108 }, /* MCS1 */ 255 { 78, 162 }, /* MCS2 */ 256 { 104, 216 }, /* MCS3 */ 257 { 156, 324 }, /* MCS4 */ 258 { 208, 432 }, /* MCS5 */ 259 { 234, 486 }, /* MCS6 */ 260 { 260, 540 }, /* MCS7 */ 261 { 26, 108 }, /* MCS8 */ 262 { 52, 216 }, /* MCS9 */ 263 { 78, 324 }, /* MCS10 */ 264 { 104, 432 }, /* MCS11 */ 265 { 156, 648 }, /* MCS12 */ 266 { 208, 864 }, /* MCS13 */ 267 { 234, 972 }, /* MCS14 */ 268 { 260, 1080 } /* MCS15 */ 269 }; 270 271 #define ATHN_POWER_OFDM6 0 272 #define ATHN_POWER_OFDM9 1 273 #define ATHN_POWER_OFDM12 2 274 #define ATHN_POWER_OFDM18 3 275 #define ATHN_POWER_OFDM24 4 276 #define ATHN_POWER_OFDM36 5 277 #define ATHN_POWER_OFDM48 6 278 #define ATHN_POWER_OFDM54 7 279 #define ATHN_POWER_CCK1_LP 8 280 #define ATHN_POWER_CCK2_LP 9 281 #define ATHN_POWER_CCK2_SP 10 282 #define ATHN_POWER_CCK55_LP 11 283 #define ATHN_POWER_CCK55_SP 12 284 #define ATHN_POWER_CCK11_LP 13 285 #define ATHN_POWER_CCK11_SP 14 286 #define ATHN_POWER_XR 15 287 #define ATHN_POWER_HT20(mcs) (16 + (mcs)) 288 #define ATHN_POWER_HT40(mcs) (40 + (mcs)) 289 #define ATHN_POWER_CCK_DUP 64 290 #define ATHN_POWER_OFDM_DUP 65 291 #define ATHN_POWER_CCK_EXT 66 292 #define ATHN_POWER_OFDM_EXT 67 293 #define ATHN_POWER_COUNT 68 294 295 struct athn_node { 296 struct ieee80211_node ni; 297 struct ieee80211_amrr_node amn; 298 uint8_t ridx[IEEE80211_RATE_MAXSIZE]; 299 uint8_t fallback[IEEE80211_RATE_MAXSIZE]; 300 uint8_t sta_index; 301 }; 302 303 /* 304 * Adaptive noise immunity state. 305 */ 306 #define ATHN_ANI_PERIOD 100 307 #define ATHN_ANI_RSSI_THR_HIGH 40 308 #define ATHN_ANI_RSSI_THR_LOW 7 309 struct athn_ani { 310 uint8_t noise_immunity_level; 311 uint8_t spur_immunity_level; 312 uint8_t firstep_level; 313 uint8_t ofdm_weak_signal; 314 uint8_t cck_weak_signal; 315 316 uint32_t listen_time; 317 318 uint32_t ofdm_trig_high; 319 uint32_t ofdm_trig_low; 320 321 int32_t cck_trig_high; 322 int32_t cck_trig_low; 323 324 uint32_t ofdm_phy_err_base; 325 uint32_t cck_phy_err_base; 326 uint32_t ofdm_phy_err_count; 327 uint32_t cck_phy_err_count; 328 329 uint32_t cyccnt; 330 uint32_t txfcnt; 331 uint32_t rxfcnt; 332 }; 333 334 struct athn_iq_cal { 335 uint32_t pwr_meas_i; 336 uint32_t pwr_meas_q; 337 int32_t iq_corr_meas; 338 }; 339 340 struct athn_adc_cal { 341 uint32_t pwr_meas_odd_i; 342 uint32_t pwr_meas_even_i; 343 uint32_t pwr_meas_odd_q; 344 uint32_t pwr_meas_even_q; 345 }; 346 347 struct athn_calib { 348 int nsamples; 349 struct athn_iq_cal iq[AR_MAX_CHAINS]; 350 struct athn_adc_cal adc_gain[AR_MAX_CHAINS]; 351 struct athn_adc_cal adc_dc_offset[AR_MAX_CHAINS]; 352 }; 353 354 #define ATHN_NF_CAL_HIST_MAX 5 355 356 struct athn_softc; 357 358 struct athn_ops { 359 /* Bus callbacks. */ 360 uint32_t (*read)(struct athn_softc *, uint32_t); 361 void (*write)(struct athn_softc *, uint32_t, uint32_t); 362 void (*write_barrier)(struct athn_softc *); 363 364 void (*setup)(struct athn_softc *); 365 void (*set_txpower)(struct athn_softc *, struct ieee80211_channel *, 366 struct ieee80211_channel *); 367 void (*spur_mitigate)(struct athn_softc *, 368 struct ieee80211_channel *, struct ieee80211_channel *); 369 const struct ar_spur_chan * 370 (*get_spur_chans)(struct athn_softc *, int); 371 void (*init_from_rom)(struct athn_softc *, 372 struct ieee80211_channel *, struct ieee80211_channel *); 373 int (*set_synth)(struct athn_softc *, struct ieee80211_channel *, 374 struct ieee80211_channel *); 375 int (*read_rom_data)(struct athn_softc *, uint32_t, void *, int); 376 const uint8_t * 377 (*get_rom_template)(struct athn_softc *, uint8_t); 378 void (*swap_rom)(struct athn_softc *); 379 void (*olpc_init)(struct athn_softc *); 380 void (*olpc_temp_compensation)(struct athn_softc *); 381 /* GPIO callbacks. */ 382 int (*gpio_read)(struct athn_softc *, int); 383 void (*gpio_write)(struct athn_softc *, int, int); 384 void (*gpio_config_input)(struct athn_softc *, int); 385 void (*gpio_config_output)(struct athn_softc *, int, int); 386 void (*rfsilent_init)(struct athn_softc *); 387 /* DMA callbacks. */ 388 int (*dma_alloc)(struct athn_softc *); 389 void (*dma_free)(struct athn_softc *); 390 void (*rx_enable)(struct athn_softc *); 391 int (*intr)(struct athn_softc *); 392 int (*tx)(struct athn_softc *, struct mbuf *, 393 struct ieee80211_node *, int); 394 /* PHY callbacks. */ 395 void (*set_rf_mode)(struct athn_softc *, 396 struct ieee80211_channel *); 397 int (*rf_bus_request)(struct athn_softc *); 398 void (*rf_bus_release)(struct athn_softc *); 399 void (*set_phy)(struct athn_softc *, struct ieee80211_channel *, 400 struct ieee80211_channel *); 401 void (*set_delta_slope)(struct athn_softc *, 402 struct ieee80211_channel *, struct ieee80211_channel *); 403 void (*enable_antenna_diversity)(struct athn_softc *); 404 void (*init_baseband)(struct athn_softc *); 405 void (*disable_phy)(struct athn_softc *); 406 void (*set_rxchains)(struct athn_softc *); 407 void (*noisefloor_calib)(struct athn_softc *); 408 void (*do_calib)(struct athn_softc *); 409 void (*next_calib)(struct athn_softc *); 410 void (*hw_init)(struct athn_softc *, struct ieee80211_channel *, 411 struct ieee80211_channel *); 412 void (*get_paprd_masks)(struct athn_softc *sc, 413 struct ieee80211_channel *, uint32_t *, uint32_t *); 414 /* ANI callbacks. */ 415 void (*set_noise_immunity_level)(struct athn_softc *, int); 416 void (*enable_ofdm_weak_signal)(struct athn_softc *); 417 void (*disable_ofdm_weak_signal)(struct athn_softc *); 418 void (*set_cck_weak_signal)(struct athn_softc *, int); 419 void (*set_firstep_level)(struct athn_softc *, int); 420 void (*set_spur_immunity_level)(struct athn_softc *, int); 421 }; 422 423 struct athn_softc { 424 struct device sc_dev; 425 struct ieee80211com sc_ic; 426 427 int (*sc_enable)(struct athn_softc *); 428 void (*sc_disable)(struct athn_softc *); 429 void (*sc_power)(struct athn_softc *, int); 430 void (*sc_disable_aspm)(struct athn_softc *); 431 void (*sc_enable_extsynch)( 432 struct athn_softc *); 433 434 int (*sc_newstate)(struct ieee80211com *, 435 enum ieee80211_state, int); 436 437 bus_dma_tag_t sc_dmat; 438 439 struct timeout scan_to; 440 struct timeout calib_to; 441 struct ieee80211_amrr amrr; 442 443 u_int flags; 444 #define ATHN_FLAG_PCIE (1 << 0) 445 #define ATHN_FLAG_USB (1 << 1) 446 #define ATHN_FLAG_OLPC (1 << 2) 447 #define ATHN_FLAG_PAPRD (1 << 3) 448 #define ATHN_FLAG_FAST_PLL_CLOCK (1 << 4) 449 #define ATHN_FLAG_RFSILENT (1 << 5) 450 #define ATHN_FLAG_RFSILENT_REVERSED (1 << 6) 451 #define ATHN_FLAG_BTCOEX2WIRE (1 << 7) 452 #define ATHN_FLAG_BTCOEX3WIRE (1 << 8) 453 /* Shortcut. */ 454 #define ATHN_FLAG_BTCOEX (ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE) 455 #define ATHN_FLAG_11A (1 << 9) 456 #define ATHN_FLAG_11G (1 << 10) 457 #define ATHN_FLAG_11N (1 << 11) 458 #define ATHN_FLAG_AN_TOP2_FIXUP (1 << 12) 459 #define ATHN_FLAG_NON_ENTERPRISE (1 << 13) 460 #define ATHN_FLAG_3TREDUCE_CHAIN (1 << 14) 461 462 uint8_t ngpiopins; 463 int led_pin; 464 int rfsilent_pin; 465 int led_state; 466 uint32_t isync; 467 uint32_t imask; 468 469 uint16_t mac_ver; 470 uint8_t mac_rev; 471 uint8_t rf_rev; 472 uint16_t eep_rev; 473 474 uint8_t txchainmask; 475 uint8_t rxchainmask; 476 uint8_t ntxchains; 477 uint8_t nrxchains; 478 479 uint8_t sup_calib_mask; 480 uint8_t cur_calib_mask; 481 #define ATHN_CAL_IQ (1 << 0) 482 #define ATHN_CAL_ADC_GAIN (1 << 1) 483 #define ATHN_CAL_ADC_DC (1 << 2) 484 #define ATHN_CAL_TEMP (1 << 3) 485 486 struct ieee80211_channel *curchan; 487 struct ieee80211_channel *curchanext; 488 489 /* Open Loop Power Control. */ 490 int8_t tx_gain_tbl[AR9280_TX_GAIN_TABLE_SIZE]; 491 int8_t pdadc; 492 int8_t tcomp; 493 int olpc_ticks; 494 495 /* PA predistortion. */ 496 uint16_t gain1[AR_MAX_CHAINS]; 497 uint32_t txgain[AR9003_TX_GAIN_TABLE_SIZE]; 498 int16_t pa_in[AR_MAX_CHAINS] 499 [AR9003_PAPRD_MEM_TAB_SIZE]; 500 int16_t angle[AR_MAX_CHAINS] 501 [AR9003_PAPRD_MEM_TAB_SIZE]; 502 int32_t trainpow; 503 uint8_t paprd_curchain; 504 505 uint32_t rwbuf[64]; 506 507 int kc_entries; 508 509 void *eep; 510 const void *eep_def; 511 uint32_t eep_base; 512 uint32_t eep_size; 513 514 struct athn_rxq rxq[2]; 515 struct athn_txq txq[31]; 516 517 void *descs; 518 bus_dmamap_t map; 519 bus_dma_segment_t seg; 520 SIMPLEQ_HEAD(, athn_tx_buf) txbufs; 521 struct athn_tx_buf *bcnbuf; 522 struct athn_tx_buf txpool[ATHN_NTXBUFS]; 523 524 bus_dmamap_t txsmap; 525 bus_dma_segment_t txsseg; 526 void *txsring; 527 int txscur; 528 529 int sc_if_flags; 530 int sc_tx_timer; 531 532 const struct athn_ini *ini; 533 const struct athn_gain *rx_gain; 534 const struct athn_gain *tx_gain; 535 const struct athn_addac *addac; 536 const struct athn_serdes *serdes; 537 uint32_t workaround; 538 uint32_t obs_off; 539 uint32_t gpio_input_en_off; 540 541 struct athn_ops ops; 542 543 int fixed_ridx; 544 545 int16_t cca_min_2g; 546 int16_t cca_max_2g; 547 int16_t cca_min_5g; 548 int16_t cca_max_5g; 549 int16_t def_nf; 550 struct { 551 int16_t nf[AR_MAX_CHAINS]; 552 int16_t nf_ext[AR_MAX_CHAINS]; 553 } nf_hist[ATHN_NF_CAL_HIST_MAX]; 554 int nf_hist_cur; 555 int16_t nf_priv[AR_MAX_CHAINS]; 556 int16_t nf_ext_priv[AR_MAX_CHAINS]; 557 int pa_calib_ticks; 558 559 struct athn_calib calib; 560 struct athn_ani ani; 561 562 #if NBPFILTER > 0 563 caddr_t sc_drvbpf; 564 565 union { 566 struct athn_rx_radiotap_header th; 567 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 568 } sc_rxtapu; 569 #define sc_rxtap sc_rxtapu.th 570 int sc_rxtap_len; 571 572 union { 573 struct athn_tx_radiotap_header th; 574 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 575 } sc_txtapu; 576 #define sc_txtap sc_txtapu.th 577 int sc_txtap_len; 578 #endif 579 }; 580 581 extern int athn_attach(struct athn_softc *); 582 extern void athn_detach(struct athn_softc *); 583 extern void athn_suspend(struct athn_softc *); 584 extern void athn_wakeup(struct athn_softc *); 585 extern int athn_intr(void *); 586