1 /* $OpenBSD: atw.c,v 1.76 2011/04/05 19:54:35 jasper Exp $ */ 2 /* $NetBSD: atw.c,v 1.69 2004/07/23 07:07:55 dyoung Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/ioctl.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 #include <sys/time.h> 49 50 #include <machine/endian.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #endif 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/if_ether.h> 65 #endif 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <machine/bus.h> 71 #include <machine/intr.h> 72 73 #include <dev/ic/atwreg.h> 74 #include <dev/ic/rf3000reg.h> 75 #include <dev/ic/si4136reg.h> 76 #include <dev/ic/atwvar.h> 77 #include <dev/ic/smc93cx6var.h> 78 79 /* XXX TBD open questions 80 * 81 * 82 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 83 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 84 * handle this for me? 85 * 86 */ 87 /* device attachment 88 * 89 * print TOFS[012] 90 * 91 * device initialization 92 * 93 * clear ATW_FRCTL_MAXPSP to disable max power saving 94 * set ATW_TXBR_ALCUPDATE to enable ALC 95 * set TOFS[012]? (hope not) 96 * disable rx/tx 97 * set ATW_PAR_SWR (software reset) 98 * wait for ATW_PAR_SWR clear 99 * disable interrupts 100 * ack status register 101 * enable interrupts 102 * 103 * rx/tx initialization 104 * 105 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 106 * allocate and init descriptor rings 107 * write ATW_PAR_DSL (descriptor skip length) 108 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 109 * write ATW_NAR_SQ for one/both transmit descriptor rings 110 * write ATW_NAR_SQ for one/both transmit descriptor rings 111 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 112 * 113 * rx/tx end 114 * 115 * stop DMA 116 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 117 * flush tx w/ ATW_NAR_HF 118 * 119 * scan 120 * 121 * initialize rx/tx 122 * 123 * BSS join: (re)association response 124 * 125 * set ATW_FRCTL_AID 126 * 127 * optimizations ??? 128 * 129 */ 130 131 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 132 133 int atw_bbp_io_enable_delay = 20 * 1000; 134 int atw_bbp_io_disable_delay = 2 * 1000; 135 int atw_writewep_delay = 1000; 136 int atw_beacon_len_adjust = 4; 137 int atw_dwelltime = 200; 138 int atw_xindiv2 = 0; 139 140 #ifdef ATW_DEBUG 141 int atw_debug = 0; 142 143 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 144 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 145 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 146 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 147 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 148 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 149 void atw_print_regs(struct atw_softc *, const char *); 150 void atw_dump_pkt(struct ifnet *, struct mbuf *); 151 152 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 153 # ifdef ATW_BBPDEBUG 154 int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 155 void atw_rf3000_print(struct atw_softc *); 156 # endif /* ATW_BBPDEBUG */ 157 158 # ifdef ATW_SYNDEBUG 159 int atw_si4126_read(struct atw_softc *, u_int, u_int *); 160 void atw_si4126_print(struct atw_softc *); 161 # endif /* ATW_SYNDEBUG */ 162 163 #else 164 #define ATW_DPRINTF(x) 165 #define ATW_DPRINTF2(x) 166 #define ATW_DPRINTF3(x) 167 #define DPRINTF(sc, x) /* nothing */ 168 #define DPRINTF2(sc, x) /* nothing */ 169 #define DPRINTF3(sc, x) /* nothing */ 170 #endif 171 172 #ifdef ATW_STATS 173 void atw_print_stats(struct atw_softc *); 174 #endif 175 176 const char *atw_printmac(u_int8_t); 177 178 /* ifnet methods */ 179 void atw_start(struct ifnet *); 180 void atw_watchdog(struct ifnet *); 181 int atw_ioctl(struct ifnet *, u_long, caddr_t); 182 int atw_init(struct ifnet *); 183 void atw_stop(struct ifnet *, int); 184 185 /* Rx/Tx process */ 186 void atw_rxdrain(struct atw_softc *); 187 void atw_txdrain(struct atw_softc *); 188 int atw_add_rxbuf(struct atw_softc *, int); 189 void atw_idle(struct atw_softc *, u_int32_t); 190 191 /* Device (de)activation and power state */ 192 void atw_disable(struct atw_softc *); 193 void atw_reset(struct atw_softc *); 194 195 /* Interrupt handlers */ 196 void atw_rxintr(struct atw_softc *); 197 void atw_txintr(struct atw_softc *); 198 void atw_linkintr(struct atw_softc *, u_int32_t); 199 200 /* 802.11 state machine */ 201 int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 202 int atw_tune(struct atw_softc *); 203 #ifndef IEEE80211_STA_ONLY 204 void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 205 struct ieee80211_node *, struct ieee80211_rxinfo *, int); 206 #endif 207 void atw_next_scan(void *); 208 209 /* Device initialization */ 210 void atw_wcsr_init(struct atw_softc *); 211 void atw_cmdr_init(struct atw_softc *); 212 void atw_tofs2_init(struct atw_softc *); 213 void atw_txlmt_init(struct atw_softc *); 214 void atw_test1_init(struct atw_softc *); 215 void atw_rf_reset(struct atw_softc *); 216 void atw_cfp_init(struct atw_softc *); 217 void atw_tofs0_init(struct atw_softc *); 218 void atw_ifs_init(struct atw_softc *); 219 void atw_response_times_init(struct atw_softc *); 220 void atw_bbp_io_init(struct atw_softc *); 221 void atw_nar_init(struct atw_softc *); 222 223 /* RAM/ROM utilities */ 224 void atw_clear_sram(struct atw_softc *); 225 void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 226 int atw_read_srom(struct atw_softc *); 227 228 /* BSS setup */ 229 void atw_predict_beacon(struct atw_softc *sc); 230 void atw_start_beacon(struct atw_softc *, int); 231 void atw_write_bssid(struct atw_softc *); 232 void atw_write_ssid(struct atw_softc *); 233 void atw_write_sup_rates(struct atw_softc *); 234 void atw_write_wep(struct atw_softc *); 235 236 /* Media */ 237 int atw_media_change(struct ifnet *); 238 void atw_media_status(struct ifnet *, struct ifmediareq *); 239 240 void atw_filter_setup(struct atw_softc *); 241 242 /* 802.11 utilities */ 243 struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 244 void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 245 static __inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, uint32_t); 246 uint64_t atw_get_tsft(struct atw_softc *sc); 247 void atw_change_ibss(struct atw_softc *); 248 int atw_compute_duration1(int, int, uint32_t, int, struct atw_duration *); 249 int atw_compute_duration(struct ieee80211_frame *, int, uint32_t, int, 250 int, struct atw_duration *, struct atw_duration *, int *, int); 251 252 /* 253 * Tuner/transceiver/modem 254 */ 255 void atw_bbp_io_enable(struct atw_softc *, int); 256 257 /* RFMD RF3000 Baseband Processor */ 258 int atw_rf3000_init(struct atw_softc *); 259 int atw_rf3000_tune(struct atw_softc *, u_int); 260 int atw_rf3000_write(struct atw_softc *, u_int, u_int); 261 262 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 263 void atw_si4126_tune(struct atw_softc *, u_int); 264 void atw_si4126_write(struct atw_softc *, u_int, u_int); 265 void atw_si4126_init(struct atw_softc *); 266 267 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = { 268 { ATW_NAR_TR_L64, "64 bytes" }, 269 { ATW_NAR_TR_L160, "160 bytes" }, 270 { ATW_NAR_TR_L192, "192 bytes" }, 271 { ATW_NAR_SF, "store and forward" }, 272 { 0, NULL } 273 }; 274 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = { 275 { ATW_NAR_TR_H96, "96 bytes" }, 276 { ATW_NAR_TR_H288, "288 bytes" }, 277 { ATW_NAR_TR_H544, "544 bytes" }, 278 { ATW_NAR_SF, "store and forward" }, 279 { 0, NULL } 280 }; 281 282 struct cfdriver atw_cd = { 283 NULL, "atw", DV_IFNET 284 }; 285 286 static const u_int atw_rfmd2958_ifn[] = { 287 0x22bd, 0x22d2, 0x22e8, 0x22fe, 0x2314, 0x232a, 0x2340, 288 0x2355, 0x236b, 0x2381, 0x2397, 0x23ad, 0x23c2, 0x23f7 289 }; 290 291 static const u_int atw_rfmd2958_rf1r[] = { 292 0x05d17, 0x3a2e8, 0x2e8ba, 0x22e8b, 0x1745d, 0x0ba2e, 0x00000, 293 0x345d1, 0x28ba2, 0x1d174, 0x11745, 0x05d17, 0x3a2e8, 0x11745 294 }; 295 296 297 #ifdef ATW_DEBUG 298 299 const char *atw_tx_state[] = { 300 "STOPPED", 301 "RUNNING - read descriptor", 302 "RUNNING - transmitting", 303 "RUNNING - filling fifo", /* XXX */ 304 "SUSPENDED", 305 "RUNNING -- write descriptor", 306 "RUNNING -- write last descriptor", 307 "RUNNING - fifo full" 308 }; 309 310 const char *atw_rx_state[] = { 311 "STOPPED", 312 "RUNNING - read descriptor", 313 "RUNNING - check this packet, pre-fetch next", 314 "RUNNING - wait for reception", 315 "SUSPENDED", 316 "RUNNING - write descriptor", 317 "RUNNING - flush fifo", 318 "RUNNING - fifo drain" 319 }; 320 321 #endif 322 323 /* 324 * atw_enable: 325 * 326 * Enable the ADM8211 chip. 327 */ 328 int 329 atw_enable(struct atw_softc *sc) 330 { 331 332 if (ATW_IS_ENABLED(sc) == 0) { 333 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 334 printf("%s: device enable failed\n", 335 sc->sc_dev.dv_xname); 336 return (EIO); 337 } 338 sc->sc_flags |= ATWF_ENABLED; 339 } 340 return (0); 341 } 342 343 /* 344 * atw_disable: 345 * 346 * Disable the ADM8211 chip. 347 */ 348 void 349 atw_disable(struct atw_softc *sc) 350 { 351 if (!ATW_IS_ENABLED(sc)) 352 return; 353 if (sc->sc_disable != NULL) 354 (*sc->sc_disable)(sc); 355 sc->sc_flags &= ~ATWF_ENABLED; 356 } 357 358 /* Returns -1 on failure. */ 359 int 360 atw_read_srom(struct atw_softc *sc) 361 { 362 struct seeprom_descriptor sd; 363 u_int32_t test0, fail_bits; 364 365 (void)memset(&sd, 0, sizeof(sd)); 366 367 test0 = ATW_READ(sc, ATW_TEST0); 368 369 switch (sc->sc_rev) { 370 case ATW_REVISION_BA: 371 case ATW_REVISION_CA: 372 fail_bits = ATW_TEST0_EPNE; 373 break; 374 default: 375 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 376 break; 377 } 378 if ((test0 & fail_bits) != 0) { 379 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 380 return -1; 381 } 382 383 switch (test0 & ATW_TEST0_EPTYP_MASK) { 384 case ATW_TEST0_EPTYP_93c66: 385 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 386 sc->sc_sromsz = 512; 387 sd.sd_chip = C56_66; 388 break; 389 case ATW_TEST0_EPTYP_93c46: 390 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 391 sc->sc_sromsz = 128; 392 sd.sd_chip = C46; 393 break; 394 default: 395 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 396 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 397 return -1; 398 } 399 400 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT | M_ZERO); 401 if (sc->sc_srom == NULL) { 402 printf("%s: unable to allocate SROM buffer\n", 403 sc->sc_dev.dv_xname); 404 return -1; 405 } 406 407 /* 408 * ADM8211 has a single 32-bit register for controlling the 409 * 93cx6 SROM. Bit SRS enables the serial port. There is no 410 * "ready" bit. The ADM8211 input/output sense is the reverse 411 * of read_seeprom's. 412 */ 413 sd.sd_tag = sc->sc_st; 414 sd.sd_bsh = sc->sc_sh; 415 sd.sd_regsize = 4; 416 sd.sd_control_offset = ATW_SPR; 417 sd.sd_status_offset = ATW_SPR; 418 sd.sd_dataout_offset = ATW_SPR; 419 sd.sd_CK = ATW_SPR_SCLK; 420 sd.sd_CS = ATW_SPR_SCS; 421 sd.sd_DI = ATW_SPR_SDO; 422 sd.sd_DO = ATW_SPR_SDI; 423 sd.sd_MS = ATW_SPR_SRS; 424 sd.sd_RDY = 0; 425 426 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 427 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 428 free(sc->sc_srom, M_DEVBUF); 429 return -1; 430 } 431 #ifdef ATW_DEBUG 432 { 433 int i; 434 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 435 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 436 if (((i % 8) == 0) && (i != 0)) { 437 ATW_DPRINTF(("\n\t")); 438 } 439 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 440 } 441 ATW_DPRINTF(("\n")); 442 } 443 #endif /* ATW_DEBUG */ 444 return 0; 445 } 446 447 #ifdef ATW_DEBUG 448 void 449 atw_print_regs(struct atw_softc *sc, const char *where) 450 { 451 #define PRINTREG(sc, reg) \ 452 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 453 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 454 455 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 456 457 PRINTREG(sc, ATW_PAR); 458 PRINTREG(sc, ATW_FRCTL); 459 PRINTREG(sc, ATW_TDR); 460 PRINTREG(sc, ATW_WTDP); 461 PRINTREG(sc, ATW_RDR); 462 PRINTREG(sc, ATW_WRDP); 463 PRINTREG(sc, ATW_RDB); 464 PRINTREG(sc, ATW_CSR3A); 465 PRINTREG(sc, ATW_TDBD); 466 PRINTREG(sc, ATW_TDBP); 467 PRINTREG(sc, ATW_STSR); 468 PRINTREG(sc, ATW_CSR5A); 469 PRINTREG(sc, ATW_NAR); 470 PRINTREG(sc, ATW_CSR6A); 471 PRINTREG(sc, ATW_IER); 472 PRINTREG(sc, ATW_CSR7A); 473 PRINTREG(sc, ATW_LPC); 474 PRINTREG(sc, ATW_TEST1); 475 PRINTREG(sc, ATW_SPR); 476 PRINTREG(sc, ATW_TEST0); 477 PRINTREG(sc, ATW_WCSR); 478 PRINTREG(sc, ATW_WPDR); 479 PRINTREG(sc, ATW_GPTMR); 480 PRINTREG(sc, ATW_GPIO); 481 PRINTREG(sc, ATW_BBPCTL); 482 PRINTREG(sc, ATW_SYNCTL); 483 PRINTREG(sc, ATW_PLCPHD); 484 PRINTREG(sc, ATW_MMIWADDR); 485 PRINTREG(sc, ATW_MMIRADDR1); 486 PRINTREG(sc, ATW_MMIRADDR2); 487 PRINTREG(sc, ATW_TXBR); 488 PRINTREG(sc, ATW_CSR15A); 489 PRINTREG(sc, ATW_ALCSTAT); 490 PRINTREG(sc, ATW_TOFS2); 491 PRINTREG(sc, ATW_CMDR); 492 PRINTREG(sc, ATW_PCIC); 493 PRINTREG(sc, ATW_PMCSR); 494 PRINTREG(sc, ATW_PAR0); 495 PRINTREG(sc, ATW_PAR1); 496 PRINTREG(sc, ATW_MAR0); 497 PRINTREG(sc, ATW_MAR1); 498 PRINTREG(sc, ATW_ATIMDA0); 499 PRINTREG(sc, ATW_ABDA1); 500 PRINTREG(sc, ATW_BSSID0); 501 PRINTREG(sc, ATW_TXLMT); 502 PRINTREG(sc, ATW_MIBCNT); 503 PRINTREG(sc, ATW_BCNT); 504 PRINTREG(sc, ATW_TSFTH); 505 PRINTREG(sc, ATW_TSC); 506 PRINTREG(sc, ATW_SYNRF); 507 PRINTREG(sc, ATW_BPLI); 508 PRINTREG(sc, ATW_CAP0); 509 PRINTREG(sc, ATW_CAP1); 510 PRINTREG(sc, ATW_RMD); 511 PRINTREG(sc, ATW_CFPP); 512 PRINTREG(sc, ATW_TOFS0); 513 PRINTREG(sc, ATW_TOFS1); 514 PRINTREG(sc, ATW_IFST); 515 PRINTREG(sc, ATW_RSPT); 516 PRINTREG(sc, ATW_TSFTL); 517 PRINTREG(sc, ATW_WEPCTL); 518 PRINTREG(sc, ATW_WESK); 519 PRINTREG(sc, ATW_WEPCNT); 520 PRINTREG(sc, ATW_MACTEST); 521 PRINTREG(sc, ATW_FER); 522 PRINTREG(sc, ATW_FEMR); 523 PRINTREG(sc, ATW_FPSR); 524 PRINTREG(sc, ATW_FFER); 525 #undef PRINTREG 526 } 527 #endif /* ATW_DEBUG */ 528 529 const char* 530 atw_printmac(u_int8_t rev) { 531 switch (rev) { 532 case ATW_REVISION_AB: 533 return "ADM8211AB"; 534 case ATW_REVISION_AF: 535 return "ADM8211AF"; 536 case ATW_REVISION_BA: 537 return "ADM8211BA"; 538 case ATW_REVISION_CA: 539 return "ADM8211CA"; 540 default: 541 return "unknown"; 542 } 543 } 544 545 /* 546 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 547 */ 548 void 549 atw_attach(struct atw_softc *sc) 550 { 551 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 552 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 553 }; 554 struct ieee80211com *ic = &sc->sc_ic; 555 struct ifnet *ifp = &ic->ic_if; 556 int country_code, error, i, srom_major; 557 u_int32_t reg; 558 static const char *type_strings[] = {"Intersil (not supported)", 559 "RFMD", "Marvel (not supported)"}; 560 561 sc->sc_txth = atw_txthresh_tab_lo; 562 563 SIMPLEQ_INIT(&sc->sc_txfreeq); 564 SIMPLEQ_INIT(&sc->sc_txdirtyq); 565 566 #ifdef ATW_DEBUG 567 atw_print_regs(sc, "atw_attach"); 568 #endif /* ATW_DEBUG */ 569 570 /* 571 * Allocate the control data structures, and create and load the 572 * DMA map for it. 573 */ 574 if ((error = bus_dmamem_alloc(sc->sc_dmat, 575 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 576 1, &sc->sc_cdnseg, 0)) != 0) { 577 printf("%s: unable to allocate control data, error = %d\n", 578 sc->sc_dev.dv_xname, error); 579 goto fail_0; 580 } 581 582 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 583 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 584 BUS_DMA_COHERENT)) != 0) { 585 printf("%s: unable to map control data, error = %d\n", 586 sc->sc_dev.dv_xname, error); 587 goto fail_1; 588 } 589 590 if ((error = bus_dmamap_create(sc->sc_dmat, 591 sizeof(struct atw_control_data), 1, 592 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 593 printf("%s: unable to create control data DMA map, " 594 "error = %d\n", sc->sc_dev.dv_xname, error); 595 goto fail_2; 596 } 597 598 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 599 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 600 0)) != 0) { 601 printf("%s: unable to load control data DMA map, error = %d\n", 602 sc->sc_dev.dv_xname, error); 603 goto fail_3; 604 } 605 606 /* 607 * Create the transmit buffer DMA maps. 608 */ 609 sc->sc_ntxsegs = ATW_NTXSEGS; 610 for (i = 0; i < ATW_TXQUEUELEN; i++) { 611 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 612 sc->sc_ntxsegs, MCLBYTES, 0, 0, 613 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 614 printf("%s: unable to create tx DMA map %d, " 615 "error = %d\n", sc->sc_dev.dv_xname, i, error); 616 goto fail_4; 617 } 618 } 619 620 /* 621 * Create the receive buffer DMA maps. 622 */ 623 for (i = 0; i < ATW_NRXDESC; i++) { 624 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 625 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 626 printf("%s: unable to create rx DMA map %d, " 627 "error = %d\n", sc->sc_dev.dv_xname, i, error); 628 goto fail_5; 629 } 630 } 631 for (i = 0; i < ATW_NRXDESC; i++) { 632 sc->sc_rxsoft[i].rxs_mbuf = NULL; 633 } 634 635 switch (sc->sc_rev) { 636 case ATW_REVISION_AB: 637 case ATW_REVISION_AF: 638 sc->sc_sramlen = ATW_SRAM_A_SIZE; 639 break; 640 case ATW_REVISION_BA: 641 case ATW_REVISION_CA: 642 sc->sc_sramlen = ATW_SRAM_B_SIZE; 643 break; 644 } 645 646 /* Reset the chip to a known state. */ 647 atw_reset(sc); 648 649 if (atw_read_srom(sc) == -1) 650 return; 651 652 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 653 ATW_SR_RFTYPE_MASK); 654 655 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 656 ATW_SR_BBPTYPE_MASK); 657 658 if (sc->sc_rftype >= nitems(type_strings)) { 659 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 660 return; 661 } 662 if (sc->sc_bbptype >= nitems(type_strings)) { 663 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 664 return; 665 } 666 667 printf("%s: MAC %s, BBP %s, RF %s", sc->sc_dev.dv_xname, 668 atw_printmac(sc->sc_rev), type_strings[sc->sc_bbptype], 669 type_strings[sc->sc_rftype]); 670 671 /* XXX There exists a Linux driver which seems to use RFType = 0 for 672 * MARVEL. My bug, or theirs? 673 */ 674 675 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 676 677 switch (sc->sc_rftype) { 678 case ATW_RFTYPE_INTERSIL: 679 reg |= ATW_SYNCTL_CS1; 680 break; 681 case ATW_RFTYPE_RFMD: 682 reg |= ATW_SYNCTL_CS0; 683 break; 684 case ATW_RFTYPE_MARVEL: 685 break; 686 } 687 688 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 689 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 690 691 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 692 693 switch (sc->sc_bbptype) { 694 case ATW_BBPTYPE_INTERSIL: 695 reg |= ATW_BBPCTL_TWI; 696 break; 697 case ATW_BBPTYPE_RFMD: 698 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 699 ATW_BBPCTL_CCA_ACTLO; 700 break; 701 case ATW_BBPTYPE_MARVEL: 702 break; 703 case ATW_C_BBPTYPE_RFMD: 704 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 705 sc->sc_dev.dv_xname); 706 break; 707 } 708 709 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 710 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 711 712 /* 713 * From this point forward, the attachment cannot fail. A failure 714 * before this point releases all resources that may have been 715 * allocated. 716 */ 717 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 718 719 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 720 htole16(sc->sc_srom[ATW_SR_MAC00]), 721 htole16(sc->sc_srom[ATW_SR_MAC01]), 722 htole16(sc->sc_srom[ATW_SR_MAC10]))); 723 724 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 725 ATW_SR_MAJOR_MASK); 726 727 if (srom_major < 2) 728 sc->sc_rf3000_options1 = 0; 729 else if (sc->sc_rev == ATW_REVISION_BA) { 730 sc->sc_rf3000_options1 = 731 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 732 ATW_SR_CR28_MASK); 733 } else 734 sc->sc_rf3000_options1 = 0; 735 736 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 737 ATW_SR_CR29_MASK); 738 739 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 740 ATW_SR_CTRY_MASK); 741 742 #define ADD_CHANNEL(_ic, _chan) do { \ 743 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 744 _ic->ic_channels[_chan].ic_freq = \ 745 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 746 } while (0) 747 748 /* Find available channels */ 749 switch (country_code) { 750 case COUNTRY_MMK2: /* 1-14 */ 751 ADD_CHANNEL(ic, 14); 752 /*FALLTHROUGH*/ 753 case COUNTRY_ETSI: /* 1-13 */ 754 for (i = 1; i <= 13; i++) 755 ADD_CHANNEL(ic, i); 756 break; 757 case COUNTRY_FCC: /* 1-11 */ 758 case COUNTRY_IC: /* 1-11 */ 759 for (i = 1; i <= 11; i++) 760 ADD_CHANNEL(ic, i); 761 break; 762 case COUNTRY_MMK: /* 14 */ 763 ADD_CHANNEL(ic, 14); 764 break; 765 case COUNTRY_FRANCE: /* 10-13 */ 766 for (i = 10; i <= 13; i++) 767 ADD_CHANNEL(ic, i); 768 break; 769 default: /* assume channels 10-11 */ 770 case COUNTRY_SPAIN: /* 10-11 */ 771 for (i = 10; i <= 11; i++) 772 ADD_CHANNEL(ic, i); 773 break; 774 } 775 776 /* Read the MAC address. */ 777 reg = ATW_READ(sc, ATW_PAR0); 778 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 779 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 780 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 781 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 782 reg = ATW_READ(sc, ATW_PAR1); 783 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 784 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 785 786 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 787 printf(" could not get mac address, attach failed\n"); 788 return; 789 } 790 791 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 792 793 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 794 ifp->if_softc = sc; 795 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST | 796 IFF_NOTRAILERS; 797 ifp->if_ioctl = atw_ioctl; 798 ifp->if_start = atw_start; 799 ifp->if_watchdog = atw_watchdog; 800 IFQ_SET_READY(&ifp->if_snd); 801 802 ic->ic_phytype = IEEE80211_T_DS; 803 ic->ic_opmode = IEEE80211_M_STA; 804 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 805 #ifndef IEEE80211_STA_ONLY 806 ic->ic_caps |= IEEE80211_C_IBSS; 807 #endif 808 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 809 810 /* 811 * Call MI attach routines. 812 */ 813 814 if_attach(ifp); 815 ieee80211_ifattach(ifp); 816 817 sc->sc_newstate = ic->ic_newstate; 818 ic->ic_newstate = atw_newstate; 819 820 #ifndef IEEE80211_STA_ONLY 821 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 822 ic->ic_recv_mgmt = atw_recv_mgmt; 823 #endif 824 825 sc->sc_node_free = ic->ic_node_free; 826 ic->ic_node_free = atw_node_free; 827 828 sc->sc_node_alloc = ic->ic_node_alloc; 829 ic->ic_node_alloc = atw_node_alloc; 830 831 /* possibly we should fill in our own sc_send_prresp, since 832 * the ADM8211 is probably sending probe responses in ad hoc 833 * mode. 834 */ 835 836 /* complete initialization */ 837 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 838 timeout_set(&sc->sc_scan_to, atw_next_scan, sc); 839 840 #if NBPFILTER > 0 841 bpfattach(&sc->sc_radiobpf, ifp, DLT_IEEE802_11_RADIO, 842 sizeof(struct ieee80211_frame) + 64); 843 #endif 844 845 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 846 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 847 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 848 849 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 850 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 851 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 852 853 return; 854 855 /* 856 * Free any resources we've allocated during the failed attach 857 * attempt. Do this in reverse order and fall through. 858 */ 859 fail_5: 860 for (i = 0; i < ATW_NRXDESC; i++) { 861 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 862 continue; 863 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 864 } 865 fail_4: 866 for (i = 0; i < ATW_TXQUEUELEN; i++) { 867 if (sc->sc_txsoft[i].txs_dmamap == NULL) 868 continue; 869 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 870 } 871 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 872 fail_3: 873 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 874 fail_2: 875 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 876 sizeof(struct atw_control_data)); 877 fail_1: 878 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 879 fail_0: 880 return; 881 } 882 883 struct ieee80211_node * 884 atw_node_alloc(struct ieee80211com *ic) 885 { 886 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 887 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 888 889 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 890 return ni; 891 } 892 893 void 894 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 895 { 896 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 897 898 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 899 ether_sprintf(ni->ni_bssid))); 900 (*sc->sc_node_free)(ic, ni); 901 } 902 903 904 static void 905 atw_test1_reset(struct atw_softc *sc) 906 { 907 switch (sc->sc_rev) { 908 case ATW_REVISION_BA: 909 if (1 /* XXX condition on transceiver type */) { 910 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 911 } 912 break; 913 case ATW_REVISION_CA: 914 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 915 break; 916 default: 917 break; 918 } 919 } 920 921 /* 922 * atw_reset: 923 * 924 * Perform a soft reset on the ADM8211. 925 */ 926 void 927 atw_reset(struct atw_softc *sc) 928 { 929 int i; 930 uint32_t lpc; 931 932 ATW_WRITE(sc, ATW_NAR, 0x0); 933 DELAY(20 * 1000); 934 935 /* Reference driver has a cryptic remark indicating that this might 936 * power-on the chip. I know that it turns off power-saving.... 937 */ 938 ATW_WRITE(sc, ATW_FRCTL, 0x0); 939 940 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 941 942 for (i = 0; i < 50; i++) { 943 if (ATW_READ(sc, ATW_PAR) == 0) 944 break; 945 DELAY(1000); 946 } 947 948 /* ... and then pause 100ms longer for good measure. */ 949 DELAY(100 * 1000); 950 951 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 952 953 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 954 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 955 956 atw_test1_reset(sc); 957 /* 958 * Initialize the PCI Access Register. 959 */ 960 sc->sc_busmode = ATW_PAR_PBL_8DW; 961 962 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 963 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 964 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 965 966 /* Turn off maximum power saving, etc. 967 * 968 * XXX Following example of reference driver, should I set 969 * an AID of 1? It didn't seem to help.... 970 */ 971 ATW_WRITE(sc, ATW_FRCTL, 0x0); 972 973 DELAY(100 * 1000); 974 975 /* Recall EEPROM. */ 976 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 977 978 DELAY(10 * 1000); 979 980 lpc = ATW_READ(sc, ATW_LPC); 981 982 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 983 984 /* A reset seems to affect the SRAM contents, so put them into 985 * a known state. 986 */ 987 atw_clear_sram(sc); 988 989 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 990 } 991 992 void 993 atw_clear_sram(struct atw_softc *sc) 994 { 995 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 996 /* XXX not for revision 0x20. */ 997 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 998 } 999 1000 /* TBD atw_init 1001 * 1002 * set MAC based on ic->ic_bss->myaddr 1003 * write WEP keys 1004 * set TX rate 1005 */ 1006 1007 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 1008 * without receiving a beacon with the preferred BSSID & SSID. 1009 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 1010 */ 1011 void 1012 atw_wcsr_init(struct atw_softc *sc) 1013 { 1014 uint32_t wcsr; 1015 1016 wcsr = ATW_READ(sc, ATW_WCSR); 1017 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1018 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1019 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1020 1021 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1022 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1023 } 1024 1025 /* Turn off power management. Set Rx store-and-forward mode. */ 1026 void 1027 atw_cmdr_init(struct atw_softc *sc) 1028 { 1029 uint32_t cmdr; 1030 cmdr = ATW_READ(sc, ATW_CMDR); 1031 cmdr &= ~ATW_CMDR_APM; 1032 cmdr |= ATW_CMDR_RTE; 1033 cmdr &= ~ATW_CMDR_DRT_MASK; 1034 cmdr |= ATW_CMDR_DRT_SF; 1035 1036 ATW_WRITE(sc, ATW_CMDR, cmdr); 1037 } 1038 1039 void 1040 atw_tofs2_init(struct atw_softc *sc) 1041 { 1042 uint32_t tofs2; 1043 /* XXX this magic can probably be figured out from the RFMD docs */ 1044 #ifndef ATW_REFSLAVE 1045 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1046 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1047 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1048 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1049 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1050 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1051 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1052 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1053 #else 1054 /* XXX new magic from reference driver source */ 1055 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1056 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1057 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1058 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1059 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1060 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1061 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1062 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1063 #endif 1064 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1065 } 1066 1067 void 1068 atw_nar_init(struct atw_softc *sc) 1069 { 1070 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1071 } 1072 1073 void 1074 atw_txlmt_init(struct atw_softc *sc) 1075 { 1076 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1077 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1078 } 1079 1080 void 1081 atw_test1_init(struct atw_softc *sc) 1082 { 1083 uint32_t test1; 1084 1085 test1 = ATW_READ(sc, ATW_TEST1); 1086 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1087 /* XXX magic 0x1 */ 1088 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1089 ATW_WRITE(sc, ATW_TEST1, test1); 1090 } 1091 1092 void 1093 atw_rf_reset(struct atw_softc *sc) 1094 { 1095 /* XXX this resets an Intersil RF front-end? */ 1096 /* TBD condition on Intersil RFType? */ 1097 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1098 DELAY(10 * 1000); 1099 ATW_WRITE(sc, ATW_SYNRF, 0); 1100 DELAY(5 * 1000); 1101 } 1102 1103 /* Set 16 TU max duration for the contention-free period (CFP). */ 1104 void 1105 atw_cfp_init(struct atw_softc *sc) 1106 { 1107 uint32_t cfpp; 1108 1109 cfpp = ATW_READ(sc, ATW_CFPP); 1110 cfpp &= ~ATW_CFPP_CFPMD; 1111 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1112 ATW_WRITE(sc, ATW_CFPP, cfpp); 1113 } 1114 1115 void 1116 atw_tofs0_init(struct atw_softc *sc) 1117 { 1118 /* XXX I guess that the Cardbus clock is 22MHz? 1119 * I am assuming that the role of ATW_TOFS0_USCNT is 1120 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1121 * very clear on this point. It says in the datasheet that it is 1122 * possible for the ADM8211 to accomodate bus speeds between 22MHz 1123 * and 33MHz; maybe this is the way? I see a binary-only driver write 1124 * these values. These values are also the power-on default. 1125 */ 1126 ATW_WRITE(sc, ATW_TOFS0, 1127 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1128 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1129 } 1130 1131 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1132 void 1133 atw_ifs_init(struct atw_softc *sc) 1134 { 1135 uint32_t ifst; 1136 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1137 * Go figure. 1138 */ 1139 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1140 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1141 ATW_IFST_SIFS_MASK) | 1142 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1143 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1144 1145 ATW_WRITE(sc, ATW_IFST, ifst); 1146 } 1147 1148 void 1149 atw_response_times_init(struct atw_softc *sc) 1150 { 1151 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1152 * indicate that the MAC expects at least SIFS + MIRT microseconds 1153 * to pass after it transmits a frame that requires a response; 1154 * it waits at most SIFS + MART microseconds for the response. 1155 * Surely this is not the ACK timeout? 1156 */ 1157 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1158 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1159 } 1160 1161 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1162 * engines read and write baseband registers after Rx and before 1163 * Tx, respectively. 1164 */ 1165 void 1166 atw_bbp_io_init(struct atw_softc *sc) 1167 { 1168 uint32_t mmiraddr2; 1169 1170 /* XXX The reference driver does this, but is it *really* 1171 * necessary? 1172 */ 1173 switch (sc->sc_rev) { 1174 case ATW_REVISION_AB: 1175 case ATW_REVISION_AF: 1176 mmiraddr2 = 0x0; 1177 break; 1178 default: 1179 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1180 mmiraddr2 &= 1181 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1182 break; 1183 } 1184 1185 switch (sc->sc_bbptype) { 1186 case ATW_BBPTYPE_INTERSIL: 1187 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1188 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1189 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1190 break; 1191 case ATW_BBPTYPE_MARVEL: 1192 /* TBD find out the Marvel settings. */ 1193 break; 1194 case ATW_BBPTYPE_RFMD: 1195 default: 1196 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1197 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1198 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1199 break; 1200 } 1201 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1202 1203 atw_si4126_init(sc); 1204 1205 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1206 } 1207 1208 void 1209 atw_si4126_init(struct atw_softc *sc) 1210 { 1211 switch (sc->sc_rftype) { 1212 case ATW_RFTYPE_RFMD: 1213 if (sc->sc_rev >= ATW_REVISION_BA) { 1214 atw_si4126_write(sc, 0x1f, 0x00000); 1215 atw_si4126_write(sc, 0x0c, 0x3001f); 1216 atw_si4126_write(sc, SI4126_GAIN, 0x29c03); 1217 atw_si4126_write(sc, SI4126_RF1N, 0x1ff6f); 1218 atw_si4126_write(sc, SI4126_RF2N, 0x29403); 1219 atw_si4126_write(sc, SI4126_RF2R, 0x1456f); 1220 atw_si4126_write(sc, 0x09, 0x10050); 1221 atw_si4126_write(sc, SI4126_IFR, 0x3fff8); 1222 } 1223 break; 1224 default: 1225 break; 1226 } 1227 } 1228 1229 /* 1230 * atw_init: [ ifnet interface function ] 1231 * 1232 * Initialize the interface. Must be called at splnet(). 1233 */ 1234 int 1235 atw_init(struct ifnet *ifp) 1236 { 1237 struct atw_softc *sc = ifp->if_softc; 1238 struct ieee80211com *ic = &sc->sc_ic; 1239 struct atw_txsoft *txs; 1240 struct atw_rxsoft *rxs; 1241 int i, error = 0; 1242 1243 if ((error = atw_enable(sc)) != 0) 1244 goto out; 1245 1246 /* 1247 * Cancel any pending I/O. This also resets. 1248 */ 1249 atw_stop(ifp, 0); 1250 1251 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 1252 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1253 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 1254 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 1255 1256 atw_wcsr_init(sc); 1257 1258 atw_cmdr_init(sc); 1259 1260 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1261 * 1262 * XXX Set transmit power for ATIM, RTS, Beacon. 1263 */ 1264 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1265 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1266 1267 atw_tofs2_init(sc); 1268 1269 atw_nar_init(sc); 1270 1271 atw_txlmt_init(sc); 1272 1273 atw_test1_init(sc); 1274 1275 atw_rf_reset(sc); 1276 1277 atw_cfp_init(sc); 1278 1279 atw_tofs0_init(sc); 1280 1281 atw_ifs_init(sc); 1282 1283 /* XXX Fall asleep after one second of inactivity. 1284 * XXX A frame may only dribble in for 65536us. 1285 */ 1286 ATW_WRITE(sc, ATW_RMD, 1287 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1288 1289 atw_response_times_init(sc); 1290 1291 atw_bbp_io_init(sc); 1292 1293 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1294 1295 if ((error = atw_rf3000_init(sc)) != 0) 1296 goto out; 1297 1298 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1299 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1300 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1301 1302 /* 1303 * Initialize the transmit descriptor ring. 1304 */ 1305 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1306 for (i = 0; i < ATW_NTXDESC; i++) { 1307 sc->sc_txdescs[i].at_ctl = 0; 1308 /* no transmit chaining */ 1309 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1310 sc->sc_txdescs[i].at_buf2 = 1311 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1312 } 1313 /* use ring mode */ 1314 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1315 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1316 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1317 sc->sc_txfree = ATW_NTXDESC; 1318 sc->sc_txnext = 0; 1319 1320 /* 1321 * Initialize the transmit job descriptors. 1322 */ 1323 SIMPLEQ_INIT(&sc->sc_txfreeq); 1324 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1325 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1326 txs = &sc->sc_txsoft[i]; 1327 txs->txs_mbuf = NULL; 1328 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1329 } 1330 1331 /* 1332 * Initialize the receive descriptor and receive job 1333 * descriptor rings. 1334 */ 1335 for (i = 0; i < ATW_NRXDESC; i++) { 1336 rxs = &sc->sc_rxsoft[i]; 1337 if (rxs->rxs_mbuf == NULL) { 1338 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1339 printf("%s: unable to allocate or map rx " 1340 "buffer %d, error = %d\n", 1341 sc->sc_dev.dv_xname, i, error); 1342 /* 1343 * XXX Should attempt to run with fewer receive 1344 * XXX buffers instead of just failing. 1345 */ 1346 atw_rxdrain(sc); 1347 goto out; 1348 } 1349 } else 1350 ATW_INIT_RXDESC(sc, i); 1351 } 1352 sc->sc_rxptr = 0; 1353 1354 /* 1355 * Initialize the interrupt mask and enable interrupts. 1356 */ 1357 /* normal interrupts */ 1358 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1359 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1360 1361 /* abnormal interrupts */ 1362 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1363 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1364 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1365 1366 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1367 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1368 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1369 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1370 ATW_INTR_TRT; 1371 1372 sc->sc_linkint_mask &= sc->sc_inten; 1373 sc->sc_rxint_mask &= sc->sc_inten; 1374 sc->sc_txint_mask &= sc->sc_inten; 1375 1376 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1377 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1378 1379 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1380 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1381 1382 /* 1383 * Give the transmit and receive rings to the ADM8211. 1384 */ 1385 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1386 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1387 1388 sc->sc_txthresh = 0; 1389 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1390 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1391 1392 /* common 802.11 configuration */ 1393 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1394 switch (ic->ic_opmode) { 1395 case IEEE80211_M_STA: 1396 break; 1397 #ifndef IEEE80211_STA_ONLY 1398 case IEEE80211_M_AHDEMO: /* XXX */ 1399 case IEEE80211_M_IBSS: 1400 ic->ic_flags |= IEEE80211_F_IBSSON; 1401 /*FALLTHROUGH*/ 1402 #endif 1403 default: /* XXX */ 1404 break; 1405 } 1406 1407 #ifndef IEEE80211_STA_ONLY 1408 switch (ic->ic_opmode) { 1409 case IEEE80211_M_AHDEMO: 1410 ic->ic_bss->ni_intval = ic->ic_lintval; 1411 ic->ic_bss->ni_rssi = 0; 1412 ic->ic_bss->ni_rstamp = 0; 1413 break; 1414 default: /* XXX */ 1415 break; 1416 } 1417 #endif 1418 sc->sc_wepctl = 0; 1419 1420 atw_write_ssid(sc); 1421 atw_write_sup_rates(sc); 1422 if (ic->ic_caps & IEEE80211_C_WEP) 1423 atw_write_wep(sc); 1424 1425 ic->ic_state = IEEE80211_S_INIT; 1426 1427 /* 1428 * Set the receive filter. This will start the transmit and 1429 * receive processes. 1430 */ 1431 atw_filter_setup(sc); 1432 1433 /* 1434 * Start the receive process. 1435 */ 1436 ATW_WRITE(sc, ATW_RDR, 0x1); 1437 1438 /* 1439 * Note that the interface is now running. 1440 */ 1441 ifp->if_flags |= IFF_RUNNING; 1442 ifp->if_flags &= ~IFF_OACTIVE; 1443 1444 /* send no beacons, yet. */ 1445 atw_start_beacon(sc, 0); 1446 1447 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1448 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1449 else 1450 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1451 out: 1452 if (error) { 1453 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1454 ifp->if_timer = 0; 1455 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1456 } 1457 #ifdef ATW_DEBUG 1458 atw_print_regs(sc, "end of init"); 1459 #endif /* ATW_DEBUG */ 1460 1461 return (error); 1462 } 1463 1464 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1465 * 0: MAC control of RF3000/Si4126. 1466 * 1467 * Applies power, or selects RF front-end? Sets reset condition. 1468 * 1469 * TBD support non-RFMD BBP, non-SiLabs synth. 1470 */ 1471 void 1472 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1473 { 1474 if (enable) { 1475 ATW_WRITE(sc, ATW_SYNRF, 1476 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1477 DELAY(atw_bbp_io_enable_delay); 1478 } else { 1479 ATW_WRITE(sc, ATW_SYNRF, 0); 1480 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1481 } 1482 } 1483 1484 int 1485 atw_tune(struct atw_softc *sc) 1486 { 1487 int rc; 1488 u_int chan; 1489 struct ieee80211com *ic = &sc->sc_ic; 1490 1491 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1492 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1493 return 0; 1494 1495 if (chan == sc->sc_cur_chan) 1496 return 0; 1497 1498 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1499 sc->sc_cur_chan, chan)); 1500 1501 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1502 1503 atw_si4126_tune(sc, chan); 1504 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1505 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1506 chan); 1507 1508 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1509 DELAY(20 * 1000); 1510 ATW_WRITE(sc, ATW_RDR, 0x1); 1511 1512 if (rc == 0) 1513 sc->sc_cur_chan = chan; 1514 1515 return rc; 1516 } 1517 1518 #ifdef ATW_SYNDEBUG 1519 void 1520 atw_si4126_print(struct atw_softc *sc) 1521 { 1522 struct ifnet *ifp = &sc->sc_ic.ic_if; 1523 u_int addr, val; 1524 1525 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1526 return; 1527 1528 for (addr = 0; addr <= 8; addr++) { 1529 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1530 if (atw_si4126_read(sc, addr, &val) == 0) { 1531 printf("<unknown> (quitting print-out)\n"); 1532 break; 1533 } 1534 printf("%05x\n", val); 1535 } 1536 } 1537 #endif /* ATW_SYNDEBUG */ 1538 1539 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1540 * 1541 * The RF/IF synthesizer produces two reference frequencies for 1542 * the RF2948B transceiver. The first frequency the RF2948B requires 1543 * is two times the so-called "intermediate frequency" (IF). Since 1544 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1545 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1546 * frequency required by the transceiver is the radio frequency 1547 * (RF). This is a superheterodyne transceiver; for f(chan) the 1548 * center frequency of the channel we are tuning, RF = f(chan) - 1549 * IF. 1550 * 1551 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1552 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1553 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1554 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1555 */ 1556 void 1557 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1558 { 1559 u_int mhz; 1560 u_int R; 1561 u_int32_t gpio; 1562 u_int16_t gain; 1563 1564 #ifdef ATW_SYNDEBUG 1565 atw_si4126_print(sc); 1566 #endif /* ATW_SYNDEBUG */ 1567 1568 if (sc->sc_rev >= ATW_REVISION_BA) { 1569 atw_si4126_write(sc, SI4126_MAIN, 0x04007); 1570 atw_si4126_write(sc, SI4126_POWER, 0x00033); 1571 atw_si4126_write(sc, SI4126_IFN, 1572 atw_rfmd2958_ifn[chan - 1]); 1573 atw_si4126_write(sc, SI4126_RF1R, 1574 atw_rfmd2958_rf1r[chan - 1]); 1575 #ifdef NOTYET 1576 /* set TX POWER? */ 1577 atw_si4126_write(sc, 0x0a, 1578 (sc->sc_srom[ATW_SR_CSR20] & mask) | 1579 power << 9); 1580 #endif 1581 /* set TX GAIN */ 1582 atw_si4126_write(sc, 0x09, 0x00050 | 1583 sc->sc_srom[ATW_SR_TXPOWER(chan - 1)]); 1584 /* wait 100us from power-up for RF, IF to settle */ 1585 DELAY(100); 1586 1587 return; 1588 } 1589 1590 if (chan == 14) 1591 mhz = 2484; 1592 else 1593 mhz = 2412 + 5 * (chan - 1); 1594 1595 /* Tune IF to 748MHz to suit the IF LO input of the 1596 * RF2494B, which is 2 x IF. No need to set an IF divider 1597 * because an IF in 526MHz - 952MHz is allowed. 1598 * 1599 * XIN is 44.000MHz, so divide it by two to get allowable 1600 * range of 2-25MHz. SiLabs tells me that this is not 1601 * strictly necessary. 1602 */ 1603 1604 if (atw_xindiv2) 1605 R = 44; 1606 else 1607 R = 88; 1608 1609 /* Power-up RF, IF synthesizers. */ 1610 atw_si4126_write(sc, SI4126_POWER, 1611 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1612 1613 /* set LPWR, too? */ 1614 atw_si4126_write(sc, SI4126_MAIN, 1615 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1616 1617 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1618 * set KP2 to 1. 1619 * 1620 * REFDIF This is different from the reference driver, which 1621 * always sets SI4126_GAIN to 0. 1622 */ 1623 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1624 1625 atw_si4126_write(sc, SI4126_GAIN, gain); 1626 1627 /* XIN = 44MHz. 1628 * 1629 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1630 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1631 * 1632 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1633 * so that 1496/88 * 44MHz = 748MHz. 1634 */ 1635 atw_si4126_write(sc, SI4126_IFN, 1496); 1636 1637 atw_si4126_write(sc, SI4126_IFR, R); 1638 1639 #ifndef ATW_REFSLAVE 1640 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1641 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1642 * which has no RF1! 1643 */ 1644 atw_si4126_write(sc, SI4126_RF1R, R); 1645 1646 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1647 #endif 1648 1649 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1650 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1651 * Now let's multiply it to mhz. So mhz - IF = N. 1652 */ 1653 atw_si4126_write(sc, SI4126_RF2R, R); 1654 1655 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1656 1657 /* wait 100us from power-up for RF, IF to settle */ 1658 DELAY(100); 1659 1660 gpio = ATW_READ(sc, ATW_GPIO); 1661 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1662 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1663 1664 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1665 /* Set a Prism RF front-end to a special mode for channel 14? 1666 * 1667 * Apparently the SMC2635W needs this, although I don't think 1668 * it has a Prism RF. 1669 */ 1670 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1671 } 1672 ATW_WRITE(sc, ATW_GPIO, gpio); 1673 1674 #ifdef ATW_SYNDEBUG 1675 atw_si4126_print(sc); 1676 #endif /* ATW_SYNDEBUG */ 1677 } 1678 1679 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1680 * diversity. 1681 * 1682 * !!! 1683 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1684 * !!! 1685 */ 1686 int 1687 atw_rf3000_init(struct atw_softc *sc) 1688 { 1689 int rc = 0; 1690 1691 atw_bbp_io_enable(sc, 1); 1692 1693 /* CCA is acquisition sensitive */ 1694 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1695 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1696 1697 if (rc != 0) 1698 goto out; 1699 1700 /* enable diversity */ 1701 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1702 1703 if (rc != 0) 1704 goto out; 1705 1706 /* sensible setting from a binary-only driver */ 1707 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1708 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1709 1710 if (rc != 0) 1711 goto out; 1712 1713 /* magic from a binary-only driver */ 1714 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1715 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1716 1717 if (rc != 0) 1718 goto out; 1719 1720 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1721 1722 if (rc != 0) 1723 goto out; 1724 1725 /* 1726 * XXX Reference driver remarks that Abocom sets this to 50. 1727 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1728 * in the "reserved" area of register RF3000_OPTIONS1. 1729 */ 1730 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1731 1732 if (rc != 0) 1733 goto out; 1734 1735 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1736 1737 if (rc != 0) 1738 goto out; 1739 1740 out: 1741 atw_bbp_io_enable(sc, 0); 1742 return rc; 1743 } 1744 1745 #ifdef ATW_BBPDEBUG 1746 void 1747 atw_rf3000_print(struct atw_softc *sc) 1748 { 1749 struct ifnet *ifp = &sc->sc_ic.ic_if; 1750 u_int addr, val; 1751 1752 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1753 return; 1754 1755 for (addr = 0x01; addr <= 0x15; addr++) { 1756 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1757 if (atw_rf3000_read(sc, addr, &val) != 0) { 1758 printf("<unknown> (quitting print-out)\n"); 1759 break; 1760 } 1761 printf("%08x\n", val); 1762 } 1763 } 1764 #endif /* ATW_BBPDEBUG */ 1765 1766 /* Set the power settings on the BBP for channel `chan'. */ 1767 int 1768 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1769 { 1770 int rc = 0; 1771 u_int32_t reg; 1772 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1773 1774 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1775 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1776 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1777 1778 /* odd channels: LSB, even channels: MSB */ 1779 if (chan % 2 == 1) { 1780 txpower &= 0xFF; 1781 lpf_cutoff &= 0xFF; 1782 lna_gs_thresh &= 0xFF; 1783 } else { 1784 txpower >>= 8; 1785 lpf_cutoff >>= 8; 1786 lna_gs_thresh >>= 8; 1787 } 1788 1789 #ifdef ATW_BBPDEBUG 1790 atw_rf3000_print(sc); 1791 #endif /* ATW_BBPDEBUG */ 1792 1793 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1794 "lna_gs_thresh %02x\n", 1795 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1796 1797 atw_bbp_io_enable(sc, 1); 1798 1799 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1800 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1801 goto out; 1802 1803 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1804 goto out; 1805 1806 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1807 goto out; 1808 1809 if ((rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0)) != 0) 1810 goto out; 1811 1812 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1813 if (rc != 0) 1814 goto out; 1815 1816 #ifdef ATW_BBPDEBUG 1817 atw_rf3000_print(sc); 1818 #endif /* ATW_BBPDEBUG */ 1819 1820 out: 1821 atw_bbp_io_enable(sc, 0); 1822 1823 /* set beacon, rts, atim transmit power */ 1824 reg = ATW_READ(sc, ATW_PLCPHD); 1825 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1826 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1827 ATW_PLCPHD_SERVICE_MASK); 1828 ATW_WRITE(sc, ATW_PLCPHD, reg); 1829 DELAY(2 * 1000); 1830 1831 return rc; 1832 } 1833 1834 /* Write a register on the RF3000 baseband processor using the 1835 * registers provided by the ADM8211 for this purpose. 1836 * 1837 * Return 0 on success. 1838 */ 1839 int 1840 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1841 { 1842 u_int32_t reg; 1843 int i; 1844 1845 reg = sc->sc_bbpctl_wr | 1846 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1847 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1848 1849 for (i = 10; --i >= 0; ) { 1850 ATW_WRITE(sc, ATW_BBPCTL, reg); 1851 DELAY(2000); 1852 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1853 break; 1854 } 1855 1856 if (i < 0) { 1857 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1858 return ETIMEDOUT; 1859 } 1860 return 0; 1861 } 1862 1863 /* Read a register on the RF3000 baseband processor using the registers 1864 * the ADM8211 provides for this purpose. 1865 * 1866 * The 7-bit register address is addr. Record the 8-bit data in the register 1867 * in *val. 1868 * 1869 * Return 0 on success. 1870 * 1871 * XXX This does not seem to work. The ADM8211 must require more or 1872 * different magic to read the chip than to write it. Possibly some 1873 * of the magic I have derived from a binary-only driver concerns 1874 * the "chip address" (see the RF3000 manual). 1875 */ 1876 #ifdef ATW_BBPDEBUG 1877 int 1878 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1879 { 1880 u_int32_t reg; 1881 int i; 1882 1883 for (i = 1000; --i >= 0; ) { 1884 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1885 break; 1886 DELAY(100); 1887 } 1888 1889 if (i < 0) { 1890 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1891 sc->sc_dev.dv_xname); 1892 return ETIMEDOUT; 1893 } 1894 1895 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1896 1897 ATW_WRITE(sc, ATW_BBPCTL, reg); 1898 1899 for (i = 1000; --i >= 0; ) { 1900 DELAY(100); 1901 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1902 break; 1903 } 1904 1905 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1906 1907 if (i < 0) { 1908 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1909 sc->sc_dev.dv_xname, reg); 1910 return ETIMEDOUT; 1911 } 1912 if (val != NULL) 1913 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1914 return 0; 1915 } 1916 #endif /* ATW_BBPDEBUG */ 1917 1918 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1919 * provided by the ADM8211 for that purpose. 1920 * 1921 * val is 18 bits of data, and val is the 4-bit address of the register. 1922 * 1923 * Return 0 on success. 1924 */ 1925 void 1926 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1927 { 1928 uint32_t bits, mask, reg; 1929 int nbits; 1930 1931 if (sc->sc_rev >= ATW_REVISION_BA) { 1932 nbits = 24; 1933 1934 val &= 0x3ffff; 1935 addr &= 0x1f; 1936 bits = val | (addr << 18); 1937 } else { 1938 nbits = 22; 1939 1940 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1941 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1942 1943 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1944 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1945 } 1946 1947 reg = ATW_SYNRF_SELSYN; 1948 /* reference driver: reset Si4126 serial bus to initial 1949 * conditions? 1950 */ 1951 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1952 ATW_WRITE(sc, ATW_SYNRF, reg); 1953 1954 for (mask = (1 << (nbits - 1)); mask != 0; mask >>= 1) { 1955 if ((bits & mask) != 0) 1956 reg |= ATW_SYNRF_SYNDATA; 1957 else 1958 reg &= ~ATW_SYNRF_SYNDATA; 1959 ATW_WRITE(sc, ATW_SYNRF, reg); 1960 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1961 ATW_WRITE(sc, ATW_SYNRF, reg); 1962 } 1963 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1964 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1965 } 1966 1967 /* Read 18-bit data from the 4-bit address addr in Si4126 1968 * RF synthesizer and write the data to *val. Return 0 on success. 1969 * 1970 * XXX This does not seem to work. The ADM8211 must require more or 1971 * different magic to read the chip than to write it. 1972 */ 1973 #ifdef ATW_SYNDEBUG 1974 int 1975 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1976 { 1977 u_int32_t reg; 1978 int i; 1979 1980 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1981 1982 for (i = 1000; --i >= 0; ) { 1983 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1984 break; 1985 DELAY(100); 1986 } 1987 1988 if (i < 0) { 1989 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1990 sc->sc_dev.dv_xname); 1991 return ETIMEDOUT; 1992 } 1993 1994 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1995 1996 ATW_WRITE(sc, ATW_SYNCTL, reg); 1997 1998 for (i = 1000; --i >= 0; ) { 1999 DELAY(100); 2000 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 2001 break; 2002 } 2003 2004 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 2005 2006 if (i < 0) { 2007 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 2008 sc->sc_dev.dv_xname, reg); 2009 return ETIMEDOUT; 2010 } 2011 if (val != NULL) 2012 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 2013 ATW_SYNCTL_DATA_MASK); 2014 return 0; 2015 } 2016 #endif /* ATW_SYNDEBUG */ 2017 2018 /* XXX is the endianness correct? test. */ 2019 #define atw_calchash(addr) \ 2020 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & 0x3f) 2021 2022 /* 2023 * atw_filter_setup: 2024 * 2025 * Set the ADM8211's receive filter. 2026 */ 2027 void 2028 atw_filter_setup(struct atw_softc *sc) 2029 { 2030 struct ieee80211com *ic = &sc->sc_ic; 2031 struct arpcom *ec = &ic->ic_ac; 2032 struct ifnet *ifp = &sc->sc_ic.ic_if; 2033 int hash; 2034 u_int32_t hashes[2]; 2035 struct ether_multi *enm; 2036 struct ether_multistep step; 2037 2038 /* According to comments in tlp_al981_filter_setup 2039 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2040 * multicast filter to be set while it is running. Hopefully 2041 * the ADM8211 is not the same! 2042 */ 2043 if ((ifp->if_flags & IFF_RUNNING) != 0) 2044 atw_idle(sc, ATW_NAR_SR); 2045 2046 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2047 2048 /* XXX in scan mode, do not filter packets. Maybe this is 2049 * unnecessary. 2050 */ 2051 if (ic->ic_state == IEEE80211_S_SCAN || 2052 (ifp->if_flags & IFF_PROMISC) != 0) { 2053 sc->sc_opmode |= ATW_NAR_PR; 2054 goto allmulti; 2055 } 2056 2057 hashes[0] = hashes[1] = 0x0; 2058 2059 /* 2060 * Program the 64-bit multicast hash filter. 2061 */ 2062 ETHER_FIRST_MULTI(step, ec, enm); 2063 while (enm != NULL) { 2064 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2065 ETHER_ADDR_LEN) != 0) 2066 goto allmulti; 2067 2068 hash = atw_calchash(enm->enm_addrlo); 2069 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2070 ETHER_NEXT_MULTI(step, enm); 2071 sc->sc_opmode |= ATW_NAR_MM; 2072 } 2073 ifp->if_flags &= ~IFF_ALLMULTI; 2074 goto setit; 2075 2076 allmulti: 2077 sc->sc_opmode |= ATW_NAR_MM; 2078 ifp->if_flags |= IFF_ALLMULTI; 2079 hashes[0] = hashes[1] = 0xffffffff; 2080 2081 setit: 2082 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2083 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2084 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2085 DELAY(20 * 1000); 2086 ATW_WRITE(sc, ATW_RDR, 0x1); 2087 2088 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2089 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2090 } 2091 2092 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2093 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2094 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2095 * no beacon with the preferred BSSID and SSID in the number of 2096 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2097 */ 2098 void 2099 atw_write_bssid(struct atw_softc *sc) 2100 { 2101 struct ieee80211com *ic = &sc->sc_ic; 2102 u_int8_t *bssid; 2103 2104 bssid = ic->ic_bss->ni_bssid; 2105 2106 ATW_WRITE(sc, ATW_BSSID0, 2107 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2108 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2109 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2110 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2111 2112 ATW_WRITE(sc, ATW_ABDA1, 2113 (ATW_READ(sc, ATW_ABDA1) & 2114 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2115 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2116 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2117 2118 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2119 ether_sprintf(sc->sc_bssid))); 2120 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2121 2122 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2123 } 2124 2125 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2126 * 16-bit word. 2127 */ 2128 void 2129 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2130 { 2131 u_int i; 2132 u_int8_t *ptr; 2133 2134 memcpy(&sc->sc_sram[ofs], buf, buflen); 2135 2136 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2137 2138 KASSERT(buflen + ofs <= sc->sc_sramlen); 2139 2140 ptr = &sc->sc_sram[ofs]; 2141 2142 for (i = 0; i < buflen; i += 2) { 2143 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2144 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2145 DELAY(atw_writewep_delay); 2146 2147 ATW_WRITE(sc, ATW_WESK, 2148 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2149 DELAY(atw_writewep_delay); 2150 } 2151 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2152 2153 if (sc->sc_if.if_flags & IFF_DEBUG) { 2154 int n_octets = 0; 2155 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2156 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2157 for (i = 0; i < buflen; i++) { 2158 printf(" %02x", ptr[i]); 2159 if (++n_octets % 24 == 0) 2160 printf("\n"); 2161 } 2162 if (n_octets % 24 != 0) 2163 printf("\n"); 2164 } 2165 } 2166 2167 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2168 void 2169 atw_write_wep(struct atw_softc *sc) 2170 { 2171 struct ieee80211com *ic = &sc->sc_ic; 2172 #if 0 2173 u_int32_t reg; 2174 int i; 2175 #endif 2176 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2177 u_int8_t buf[IEEE80211_WEP_NKID] 2178 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2179 2180 sc->sc_wepctl = 0; 2181 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2182 2183 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2184 return; 2185 2186 memset(&buf[0][0], 0, sizeof(buf)); 2187 2188 #if 0 2189 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2190 if (ic->ic_nw_keys[i].k_len > 5) { 2191 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2192 } else if (ic->ic_nw_keys[i].k_len != 0) { 2193 buf[i][1] = ATW_WEP_ENABLED; 2194 } else { 2195 buf[i][1] = 0; 2196 continue; 2197 } 2198 buf[i][0] = ic->ic_nw_keys[i].k_key[0]; 2199 memcpy(&buf[i][2], &ic->ic_nw_keys[i].k_key[1], 2200 ic->ic_nw_keys[i].k_len - 1); 2201 } 2202 2203 reg = ATW_READ(sc, ATW_MACTEST); 2204 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2205 reg &= ~ATW_MACTEST_KEYID_MASK; 2206 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2207 ATW_WRITE(sc, ATW_MACTEST, reg); 2208 2209 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE; 2210 2211 switch (sc->sc_rev) { 2212 case ATW_REVISION_AB: 2213 case ATW_REVISION_AF: 2214 /* Bypass WEP on Rx. */ 2215 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2216 break; 2217 default: 2218 break; 2219 } 2220 #endif 2221 2222 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2223 sizeof(buf)); 2224 } 2225 2226 void 2227 atw_change_ibss(struct atw_softc *sc) 2228 { 2229 atw_predict_beacon(sc); 2230 atw_write_bssid(sc); 2231 atw_start_beacon(sc, 1); 2232 } 2233 2234 #ifndef IEEE80211_STA_ONLY 2235 void 2236 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2237 struct ieee80211_node *ni, struct ieee80211_rxinfo *rxi, int subtype) 2238 { 2239 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2240 2241 /* The ADM8211A answers probe requests. */ 2242 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ && 2243 sc->sc_rev < ATW_REVISION_BA) 2244 return; 2245 2246 (*sc->sc_recv_mgmt)(ic, m, ni, rxi, subtype); 2247 2248 switch (subtype) { 2249 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2250 case IEEE80211_FC0_SUBTYPE_BEACON: 2251 if (ic->ic_opmode != IEEE80211_M_IBSS || 2252 ic->ic_state != IEEE80211_S_RUN) 2253 break; 2254 if (ieee80211_ibss_merge(ic, ni, atw_get_tsft(sc)) == ENETRESET) 2255 atw_change_ibss(sc); 2256 break; 2257 default: 2258 break; 2259 } 2260 return; 2261 } 2262 #endif 2263 2264 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2265 * In ad hoc mode, the SSID is written to the beacons sent by the 2266 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2267 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2268 * indications. 2269 */ 2270 void 2271 atw_write_ssid(struct atw_softc *sc) 2272 { 2273 struct ieee80211com *ic = &sc->sc_ic; 2274 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2275 * it only expects the element length, not its ID. 2276 */ 2277 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2278 2279 memset(buf, 0, sizeof(buf)); 2280 buf[0] = ic->ic_bss->ni_esslen; 2281 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2282 2283 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2284 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2285 } 2286 2287 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2288 * In ad hoc mode, the supported rates are written to beacons sent by the 2289 * ADM8211. 2290 */ 2291 void 2292 atw_write_sup_rates(struct atw_softc *sc) 2293 { 2294 struct ieee80211com *ic = &sc->sc_ic; 2295 /* 2296 * There is not enough space in the ADM8211 SRAM for the 2297 * full IEEE80211_RATE_MAXSIZE 2298 */ 2299 u_int8_t buf[12]; 2300 u_int8_t nrates; 2301 2302 memset(buf, 0, sizeof(buf)); 2303 if (ic->ic_bss->ni_rates.rs_nrates > sizeof(buf) - 1) 2304 nrates = sizeof(buf) - 1; 2305 else 2306 nrates = ic->ic_bss->ni_rates.rs_nrates; 2307 buf[0] = nrates; 2308 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, nrates); 2309 2310 /* XXX deal with rev BA bug linux driver talks of? */ 2311 2312 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2313 } 2314 2315 /* Start/stop sending beacons. */ 2316 void 2317 atw_start_beacon(struct atw_softc *sc, int start) 2318 { 2319 struct ieee80211com *ic = &sc->sc_ic; 2320 #ifndef IEEE80211_STA_ONLY 2321 uint16_t chan; 2322 uint32_t bpli; 2323 #endif 2324 uint32_t bcnt, cap0, cap1, capinfo; 2325 size_t len; 2326 2327 if (ATW_IS_ENABLED(sc) == 0) 2328 return; 2329 2330 /* start beacons */ 2331 len = sizeof(struct ieee80211_frame) + 2332 8 /* timestamp */ + 2 /* beacon interval */ + 2333 2 /* capability info */ + 2334 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2335 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2336 3 /* DS parameters */ + 2337 IEEE80211_CRC_LEN; 2338 2339 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2340 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2341 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2342 2343 ATW_WRITE(sc, ATW_BCNT, bcnt); 2344 ATW_WRITE(sc, ATW_CAP1, cap1); 2345 2346 if (!start) 2347 return; 2348 2349 /* TBD use ni_capinfo */ 2350 2351 capinfo = 0; 2352 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2353 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2354 if (ic->ic_flags & IEEE80211_F_WEPON) 2355 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2356 2357 #ifndef IEEE80211_STA_ONLY 2358 switch (ic->ic_opmode) { 2359 case IEEE80211_M_IBSS: 2360 len += 4; /* IBSS parameters */ 2361 capinfo |= IEEE80211_CAPINFO_IBSS; 2362 break; 2363 default: 2364 return; 2365 } 2366 2367 /* set listen interval 2368 * XXX do software units agree w/ hardware? 2369 */ 2370 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2371 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2372 2373 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2374 2375 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2376 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2377 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2378 2379 ATW_WRITE(sc, ATW_BCNT, bcnt); 2380 ATW_WRITE(sc, ATW_BPLI, bpli); 2381 ATW_WRITE(sc, ATW_CAP0, cap0); 2382 ATW_WRITE(sc, ATW_CAP1, cap1); 2383 2384 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2385 sc->sc_dev.dv_xname, bcnt)); 2386 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2387 sc->sc_dev.dv_xname, cap1)); 2388 #endif 2389 } 2390 2391 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2392 static __inline uint32_t 2393 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2394 { 2395 /* Following the reference driver's lead, I compute 2396 * 2397 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2398 * 2399 * without using 64-bit arithmetic, using the following 2400 * relationship: 2401 * 2402 * (0x100000000 * H + L) % m 2403 * = ((0x100000000 % m) * H + L) % m 2404 * = (((0xffffffff + 1) % m) * H + L) % m 2405 * = ((0xffffffff % m + 1 % m) * H + L) % m 2406 * = ((0xffffffff % m + 1) * H + L) % m 2407 */ 2408 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2409 } 2410 2411 uint64_t 2412 atw_get_tsft(struct atw_softc *sc) 2413 { 2414 int i; 2415 uint32_t tsfth, tsftl; 2416 for (i = 0; i < 2; i++) { 2417 tsfth = ATW_READ(sc, ATW_TSFTH); 2418 tsftl = ATW_READ(sc, ATW_TSFTL); 2419 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2420 break; 2421 } 2422 return ((uint64_t)tsfth << 32) | tsftl; 2423 } 2424 2425 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2426 * the ieee80211com. 2427 * 2428 * Predict the next target beacon transmission time (TBTT) and 2429 * write it to the ADM8211. 2430 */ 2431 void 2432 atw_predict_beacon(struct atw_softc *sc) 2433 { 2434 #define TBTTOFS 20 /* TU */ 2435 2436 struct ieee80211com *ic = &sc->sc_ic; 2437 uint64_t tsft; 2438 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2439 union { 2440 uint64_t word; 2441 uint8_t tstamp[8]; 2442 } u; 2443 2444 #ifndef IEEE80211_STA_ONLY 2445 if ((ic->ic_opmode == IEEE80211_M_IBSS) && 2446 (ic->ic_flags & IEEE80211_F_SIBSS)) { 2447 tsft = atw_get_tsft(sc); 2448 u.word = htole64(tsft); 2449 (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u.tstamp[0], 2450 sizeof(ic->ic_bss->ni_tstamp)); 2451 } else 2452 #endif 2453 { 2454 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2455 tsft = letoh64(u.word); 2456 } 2457 2458 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2459 2460 tsftl = tsft & 0xFFFFFFFF; 2461 tsfth = tsft >> 32; 2462 2463 /* We sent/received the last beacon `past' microseconds 2464 * after the interval divided the TSF timer. 2465 */ 2466 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2467 2468 /* Skip ten beacons so that the TBTT cannot pass before 2469 * we've programmed it. Ten is an arbitrary number. 2470 */ 2471 tbtt = past_even + ival * 10; 2472 2473 ATW_WRITE(sc, ATW_TOFS1, 2474 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2475 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2476 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2477 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2478 #undef TBTTOFS 2479 } 2480 2481 void 2482 atw_next_scan(void *arg) 2483 { 2484 struct atw_softc *sc = arg; 2485 struct ieee80211com *ic = &sc->sc_ic; 2486 struct ifnet *ifp = &ic->ic_if; 2487 int s; 2488 2489 /* don't call atw_start w/o network interrupts blocked */ 2490 s = splnet(); 2491 if (ic->ic_state == IEEE80211_S_SCAN) 2492 ieee80211_next_scan(ifp); 2493 splx(s); 2494 } 2495 2496 /* Synchronize the hardware state with the software state. */ 2497 int 2498 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2499 { 2500 struct ifnet *ifp = &ic->ic_if; 2501 struct atw_softc *sc = ifp->if_softc; 2502 enum ieee80211_state ostate = ic->ic_state; 2503 int error; 2504 2505 if (nstate == IEEE80211_S_INIT) { 2506 timeout_del(&sc->sc_scan_to); 2507 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2508 atw_start_beacon(sc, 0); 2509 return (*sc->sc_newstate)(ic, nstate, arg); 2510 } 2511 2512 if ((error = atw_tune(sc)) != 0) 2513 return error; 2514 2515 switch (nstate) { 2516 case IEEE80211_S_ASSOC: 2517 break; 2518 case IEEE80211_S_INIT: 2519 panic("%s: unexpected state IEEE80211_S_INIT", __func__); 2520 break; 2521 case IEEE80211_S_SCAN: 2522 timeout_add_msec(&sc->sc_scan_to, atw_dwelltime); 2523 break; 2524 case IEEE80211_S_RUN: 2525 if (ic->ic_opmode == IEEE80211_M_STA) 2526 break; 2527 /*FALLTHROUGH*/ 2528 case IEEE80211_S_AUTH: 2529 atw_write_bssid(sc); 2530 atw_write_ssid(sc); 2531 atw_write_sup_rates(sc); 2532 2533 if ( 2534 #ifndef IEEE80211_STA_ONLY 2535 ic->ic_opmode == IEEE80211_M_AHDEMO || 2536 #endif 2537 ic->ic_opmode == IEEE80211_M_MONITOR) 2538 break; 2539 2540 /* set listen interval 2541 * XXX do software units agree w/ hardware? 2542 */ 2543 ATW_WRITE(sc, ATW_BPLI, 2544 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2545 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2546 ATW_BPLI_LI_MASK)); 2547 2548 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2549 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2550 2551 atw_predict_beacon(sc); 2552 break; 2553 } 2554 2555 if (nstate != IEEE80211_S_SCAN) 2556 timeout_del(&sc->sc_scan_to); 2557 2558 #ifndef IEEE80211_STA_ONLY 2559 if (nstate == IEEE80211_S_RUN && 2560 ic->ic_opmode == IEEE80211_M_IBSS) 2561 atw_start_beacon(sc, 1); 2562 else 2563 #endif 2564 atw_start_beacon(sc, 0); 2565 2566 error = (*sc->sc_newstate)(ic, nstate, arg); 2567 2568 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2569 atw_write_bssid(sc); 2570 2571 return error; 2572 } 2573 2574 /* 2575 * atw_add_rxbuf: 2576 * 2577 * Add a receive buffer to the indicated descriptor. 2578 */ 2579 int 2580 atw_add_rxbuf(struct atw_softc *sc, int idx) 2581 { 2582 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2583 struct mbuf *m; 2584 int error; 2585 2586 MGETHDR(m, M_DONTWAIT, MT_DATA); 2587 if (m == NULL) 2588 return (ENOBUFS); 2589 2590 MCLGET(m, M_DONTWAIT); 2591 if ((m->m_flags & M_EXT) == 0) { 2592 m_freem(m); 2593 return (ENOBUFS); 2594 } 2595 2596 if (rxs->rxs_mbuf != NULL) 2597 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2598 2599 rxs->rxs_mbuf = m; 2600 2601 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2602 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2603 BUS_DMA_READ|BUS_DMA_NOWAIT); 2604 if (error) { 2605 printf("%s: can't load rx DMA map %d, error = %d\n", 2606 sc->sc_dev.dv_xname, idx, error); 2607 panic("atw_add_rxbuf"); /* XXX */ 2608 } 2609 2610 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2611 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2612 2613 ATW_INIT_RXDESC(sc, idx); 2614 2615 return (0); 2616 } 2617 2618 /* 2619 * Release any queued transmit buffers. 2620 */ 2621 void 2622 atw_txdrain(struct atw_softc *sc) 2623 { 2624 struct atw_txsoft *txs; 2625 2626 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2627 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2628 if (txs->txs_mbuf != NULL) { 2629 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2630 m_freem(txs->txs_mbuf); 2631 txs->txs_mbuf = NULL; 2632 } 2633 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2634 } 2635 sc->sc_tx_timer = 0; 2636 } 2637 2638 /* 2639 * atw_stop: [ ifnet interface function ] 2640 * 2641 * Stop transmission on the interface. 2642 */ 2643 void 2644 atw_stop(struct ifnet *ifp, int disable) 2645 { 2646 struct atw_softc *sc = ifp->if_softc; 2647 struct ieee80211com *ic = &sc->sc_ic; 2648 2649 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2650 2651 /* 2652 * Mark the interface down and cancel the watchdog timer. 2653 */ 2654 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2655 ifp->if_timer = 0; 2656 2657 /* Disable interrupts. */ 2658 ATW_WRITE(sc, ATW_IER, 0); 2659 2660 /* Stop the transmit and receive processes. */ 2661 sc->sc_opmode = 0; 2662 ATW_WRITE(sc, ATW_NAR, 0); 2663 DELAY(20 * 1000); 2664 ATW_WRITE(sc, ATW_TDBD, 0); 2665 ATW_WRITE(sc, ATW_TDBP, 0); 2666 ATW_WRITE(sc, ATW_RDB, 0); 2667 2668 atw_txdrain(sc); 2669 2670 if (disable) { 2671 atw_rxdrain(sc); 2672 atw_disable(sc); 2673 } 2674 2675 if (!disable) 2676 atw_reset(sc); 2677 } 2678 2679 /* 2680 * atw_rxdrain: 2681 * 2682 * Drain the receive queue. 2683 */ 2684 void 2685 atw_rxdrain(struct atw_softc *sc) 2686 { 2687 struct atw_rxsoft *rxs; 2688 int i; 2689 2690 for (i = 0; i < ATW_NRXDESC; i++) { 2691 rxs = &sc->sc_rxsoft[i]; 2692 if (rxs->rxs_mbuf == NULL) 2693 continue; 2694 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2695 m_freem(rxs->rxs_mbuf); 2696 rxs->rxs_mbuf = NULL; 2697 } 2698 } 2699 2700 /* 2701 * atw_detach: 2702 * 2703 * Detach an ADM8211 interface. 2704 */ 2705 int 2706 atw_detach(struct atw_softc *sc) 2707 { 2708 struct ifnet *ifp = &sc->sc_ic.ic_if; 2709 struct atw_rxsoft *rxs; 2710 struct atw_txsoft *txs; 2711 int i; 2712 2713 /* 2714 * Succeed now if there isn't any work to do. 2715 */ 2716 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2717 return (0); 2718 2719 timeout_del(&sc->sc_scan_to); 2720 2721 ieee80211_ifdetach(ifp); 2722 if_detach(ifp); 2723 2724 for (i = 0; i < ATW_NRXDESC; i++) { 2725 rxs = &sc->sc_rxsoft[i]; 2726 if (rxs->rxs_mbuf != NULL) { 2727 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2728 m_freem(rxs->rxs_mbuf); 2729 rxs->rxs_mbuf = NULL; 2730 } 2731 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2732 } 2733 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2734 txs = &sc->sc_txsoft[i]; 2735 if (txs->txs_mbuf != NULL) { 2736 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2737 m_freem(txs->txs_mbuf); 2738 txs->txs_mbuf = NULL; 2739 } 2740 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2741 } 2742 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2743 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2744 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2745 sizeof(struct atw_control_data)); 2746 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2747 2748 if (sc->sc_srom) 2749 free(sc->sc_srom, M_DEVBUF); 2750 2751 return (0); 2752 } 2753 2754 int 2755 atw_intr(void *arg) 2756 { 2757 struct atw_softc *sc = arg; 2758 struct ifnet *ifp = &sc->sc_ic.ic_if; 2759 u_int32_t status, rxstatus, txstatus, linkstatus; 2760 int handled = 0, txthresh; 2761 2762 #ifdef DEBUG 2763 if (ATW_IS_ENABLED(sc) == 0) 2764 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2765 #endif 2766 2767 /* 2768 * If the interface isn't running, the interrupt couldn't 2769 * possibly have come from us. 2770 */ 2771 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2772 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2773 return (0); 2774 2775 for (;;) { 2776 status = ATW_READ(sc, ATW_STSR); 2777 2778 if (status) 2779 ATW_WRITE(sc, ATW_STSR, status); 2780 2781 #ifdef ATW_DEBUG 2782 #define PRINTINTR(flag) do { \ 2783 if ((status & flag) != 0) { \ 2784 printf("%s" #flag, delim); \ 2785 delim = ","; \ 2786 } \ 2787 } while (0) 2788 2789 if (atw_debug > 1 && status) { 2790 const char *delim = "<"; 2791 2792 printf("%s: reg[STSR] = %x", 2793 sc->sc_dev.dv_xname, status); 2794 2795 PRINTINTR(ATW_INTR_FBE); 2796 PRINTINTR(ATW_INTR_LINKOFF); 2797 PRINTINTR(ATW_INTR_LINKON); 2798 PRINTINTR(ATW_INTR_RCI); 2799 PRINTINTR(ATW_INTR_RDU); 2800 PRINTINTR(ATW_INTR_REIS); 2801 PRINTINTR(ATW_INTR_RPS); 2802 PRINTINTR(ATW_INTR_TCI); 2803 PRINTINTR(ATW_INTR_TDU); 2804 PRINTINTR(ATW_INTR_TLT); 2805 PRINTINTR(ATW_INTR_TPS); 2806 PRINTINTR(ATW_INTR_TRT); 2807 PRINTINTR(ATW_INTR_TUF); 2808 PRINTINTR(ATW_INTR_BCNTC); 2809 PRINTINTR(ATW_INTR_ATIME); 2810 PRINTINTR(ATW_INTR_TBTT); 2811 PRINTINTR(ATW_INTR_TSCZ); 2812 PRINTINTR(ATW_INTR_TSFTF); 2813 printf(">\n"); 2814 } 2815 #undef PRINTINTR 2816 #endif /* ATW_DEBUG */ 2817 2818 if ((status & sc->sc_inten) == 0) 2819 break; 2820 2821 handled = 1; 2822 2823 rxstatus = status & sc->sc_rxint_mask; 2824 txstatus = status & sc->sc_txint_mask; 2825 linkstatus = status & sc->sc_linkint_mask; 2826 2827 if (linkstatus) { 2828 atw_linkintr(sc, linkstatus); 2829 } 2830 2831 if (rxstatus) { 2832 /* Grab any new packets. */ 2833 atw_rxintr(sc); 2834 2835 if (rxstatus & ATW_INTR_RDU) { 2836 printf("%s: receive ring overrun\n", 2837 sc->sc_dev.dv_xname); 2838 /* Get the receive process going again. */ 2839 ATW_WRITE(sc, ATW_RDR, 0x1); 2840 break; 2841 } 2842 } 2843 2844 if (txstatus) { 2845 /* Sweep up transmit descriptors. */ 2846 atw_txintr(sc); 2847 2848 if (txstatus & ATW_INTR_TLT) 2849 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2850 sc->sc_dev.dv_xname)); 2851 2852 if (txstatus & ATW_INTR_TRT) 2853 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2854 sc->sc_dev.dv_xname)); 2855 2856 /* If Tx under-run, increase our transmit threshold 2857 * if another is available. 2858 */ 2859 txthresh = sc->sc_txthresh + 1; 2860 if ((txstatus & ATW_INTR_TUF) && 2861 sc->sc_txth[txthresh].txth_name != NULL) { 2862 /* Idle the transmit process. */ 2863 atw_idle(sc, ATW_NAR_ST); 2864 2865 sc->sc_txthresh = txthresh; 2866 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2867 sc->sc_opmode |= 2868 sc->sc_txth[txthresh].txth_opmode; 2869 printf("%s: transmit underrun; new " 2870 "threshold: %s\n", sc->sc_dev.dv_xname, 2871 sc->sc_txth[txthresh].txth_name); 2872 2873 /* Set the new threshold and restart 2874 * the transmit process. 2875 */ 2876 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2877 DELAY(20 * 1000); 2878 ATW_WRITE(sc, ATW_RDR, 0x1); 2879 /* XXX Log every Nth underrun from 2880 * XXX now on? 2881 */ 2882 } 2883 } 2884 2885 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2886 if (status & ATW_INTR_TPS) 2887 printf("%s: transmit process stopped\n", 2888 sc->sc_dev.dv_xname); 2889 if (status & ATW_INTR_RPS) 2890 printf("%s: receive process stopped\n", 2891 sc->sc_dev.dv_xname); 2892 (void)atw_init(ifp); 2893 break; 2894 } 2895 2896 if (status & ATW_INTR_FBE) { 2897 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2898 (void)atw_init(ifp); 2899 break; 2900 } 2901 2902 /* 2903 * Not handled: 2904 * 2905 * Transmit buffer unavailable -- normal 2906 * condition, nothing to do, really. 2907 * 2908 * Early receive interrupt -- not available on 2909 * all chips, we just use RI. We also only 2910 * use single-segment receive DMA, so this 2911 * is mostly useless. 2912 * 2913 * TBD others 2914 */ 2915 } 2916 2917 /* Try to get more packets going. */ 2918 atw_start(ifp); 2919 2920 return (handled); 2921 } 2922 2923 /* 2924 * atw_idle: 2925 * 2926 * Cause the transmit and/or receive processes to go idle. 2927 * 2928 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2929 * process in STSR if I clear SR or ST after the process has already 2930 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2931 * do not seem to be too reliable. Perhaps I have the sense of the 2932 * Rx bits switched with the Tx bits? 2933 */ 2934 void 2935 atw_idle(struct atw_softc *sc, u_int32_t bits) 2936 { 2937 u_int32_t ackmask = 0, opmode, stsr, test0; 2938 int i, s; 2939 2940 s = splnet(); 2941 2942 opmode = sc->sc_opmode & ~bits; 2943 2944 if (bits & ATW_NAR_SR) 2945 ackmask |= ATW_INTR_RPS; 2946 2947 if (bits & ATW_NAR_ST) { 2948 ackmask |= ATW_INTR_TPS; 2949 /* set ATW_NAR_HF to flush TX FIFO. */ 2950 opmode |= ATW_NAR_HF; 2951 } 2952 2953 ATW_WRITE(sc, ATW_NAR, opmode); 2954 DELAY(20 * 1000); 2955 2956 for (i = 0; i < 10; i++) { 2957 stsr = ATW_READ(sc, ATW_STSR); 2958 if ((stsr & ackmask) == ackmask) 2959 break; 2960 DELAY(1000); 2961 } 2962 2963 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2964 2965 if ((stsr & ackmask) == ackmask) 2966 goto out; 2967 2968 test0 = ATW_READ(sc, ATW_TEST0); 2969 2970 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2971 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2972 DPRINTF2(sc, ("%s: transmit process not idle [%s]\n", 2973 sc->sc_dev.dv_xname, 2974 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)])); 2975 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2976 sc->sc_dev.dv_xname, bits, test0, stsr)); 2977 } 2978 2979 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2980 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2981 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2982 sc->sc_dev.dv_xname, 2983 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2984 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2985 sc->sc_dev.dv_xname, bits, test0, stsr)); 2986 } 2987 out: 2988 if ((bits & ATW_NAR_ST) != 0) 2989 atw_txdrain(sc); 2990 splx(s); 2991 return; 2992 } 2993 2994 /* 2995 * atw_linkintr: 2996 * 2997 * Helper; handle link-status interrupts. 2998 */ 2999 void 3000 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 3001 { 3002 struct ieee80211com *ic = &sc->sc_ic; 3003 3004 if (ic->ic_state != IEEE80211_S_RUN) 3005 return; 3006 3007 if (linkstatus & ATW_INTR_LINKON) { 3008 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 3009 sc->sc_rescan_timer = 0; 3010 } else if (linkstatus & ATW_INTR_LINKOFF) { 3011 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3012 if (ic->ic_opmode != IEEE80211_M_STA) 3013 return; 3014 sc->sc_rescan_timer = 3; 3015 ic->ic_if.if_timer = 1; 3016 } 3017 } 3018 3019 static __inline int 3020 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame *wh) 3021 { 3022 if ((sc->sc_ic.ic_flags & IEEE80211_F_WEPON) == 0) 3023 return 0; 3024 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3025 return 0; 3026 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3027 } 3028 3029 /* 3030 * atw_rxintr: 3031 * 3032 * Helper; handle receive interrupts. 3033 */ 3034 void 3035 atw_rxintr(struct atw_softc *sc) 3036 { 3037 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3038 struct ieee80211com *ic = &sc->sc_ic; 3039 struct ieee80211_rxinfo rxi; 3040 struct ieee80211_node *ni; 3041 struct ieee80211_frame *wh; 3042 struct ifnet *ifp = &ic->ic_if; 3043 struct atw_rxsoft *rxs; 3044 struct mbuf *m; 3045 u_int32_t rxstat; 3046 int i, len, rate, rate0; 3047 u_int32_t rssi, rssi0; 3048 3049 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3050 rxs = &sc->sc_rxsoft[i]; 3051 3052 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3053 3054 rxstat = letoh32(sc->sc_rxdescs[i].ar_stat); 3055 rssi0 = letoh32(sc->sc_rxdescs[i].ar_rssi); 3056 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3057 3058 if (rxstat & ATW_RXSTAT_OWN) 3059 break; /* We have processed all receive buffers. */ 3060 3061 DPRINTF3(sc, 3062 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3063 sc->sc_dev.dv_xname, 3064 rxstat, rssi0, 3065 letoh32(sc->sc_rxdescs[i].ar_buf1), 3066 letoh32(sc->sc_rxdescs[i].ar_buf2))); 3067 3068 /* 3069 * Make sure the packet fits in one buffer. This should 3070 * always be the case. 3071 */ 3072 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3073 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3074 printf("%s: incoming packet spilled, resetting\n", 3075 sc->sc_dev.dv_xname); 3076 (void)atw_init(ifp); 3077 return; 3078 } 3079 3080 /* 3081 * If an error occurred, update stats, clear the status 3082 * word, and leave the packet buffer in place. It will 3083 * simply be reused the next time the ring comes around. 3084 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3085 * error. 3086 */ 3087 3088 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3089 ((sc->sc_ic.ic_if.if_capabilities & IFCAP_VLAN_MTU) == 0 || 3090 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3091 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3092 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3093 ATW_RXSTAT_ICVE)) != 0)) { 3094 #define PRINTERR(bit, str) \ 3095 if (rxstat & (bit)) \ 3096 printf("%s: receive error: %s\n", \ 3097 sc->sc_dev.dv_xname, str) 3098 ifp->if_ierrors++; 3099 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3100 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3101 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3102 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3103 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3104 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3105 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3106 #undef PRINTERR 3107 ATW_INIT_RXDESC(sc, i); 3108 continue; 3109 } 3110 3111 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3112 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3113 3114 /* 3115 * No errors; receive the packet. Note the ADM8211 3116 * includes the CRC in promiscuous mode. 3117 */ 3118 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3119 3120 /* 3121 * Allocate a new mbuf cluster. If that fails, we are 3122 * out of memory, and must drop the packet and recycle 3123 * the buffer that's already attached to this descriptor. 3124 */ 3125 m = rxs->rxs_mbuf; 3126 if (atw_add_rxbuf(sc, i) != 0) { 3127 ifp->if_ierrors++; 3128 ATW_INIT_RXDESC(sc, i); 3129 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3130 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3131 continue; 3132 } 3133 3134 if (sc->sc_opmode & ATW_NAR_PR) 3135 len -= IEEE80211_CRC_LEN; 3136 m->m_pkthdr.rcvif = ifp; 3137 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3138 3139 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3140 rate = 0; 3141 else 3142 rate = rate_tbl[rate0]; 3143 3144 /* The RSSI comes straight from a register in the 3145 * baseband processor. I know that for the RF3000, 3146 * the RSSI register also contains the antenna-selection 3147 * bits. Mask those off. 3148 * 3149 * TBD Treat other basebands. 3150 */ 3151 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3152 rssi = rssi0 & RF3000_RSSI_MASK; 3153 else 3154 rssi = rssi0; 3155 3156 #if NBPFILTER > 0 3157 /* Pass this up to any BPF listeners. */ 3158 if (sc->sc_radiobpf != NULL) { 3159 struct mbuf mb; 3160 3161 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3162 3163 tap->ar_rate = rate; 3164 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3165 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3166 3167 /* TBD verify units are dB */ 3168 tap->ar_antsignal = (int)rssi; 3169 /* TBD tap->ar_flags */ 3170 3171 mb.m_data = (caddr_t)tap; 3172 mb.m_len = tap->ar_ihdr.it_len; 3173 mb.m_next = m; 3174 mb.m_nextpkt = NULL; 3175 mb.m_type = 0; 3176 mb.m_flags = 0; 3177 bpf_mtap(sc->sc_radiobpf, &mb, BPF_DIRECTION_IN); 3178 } 3179 #endif /* NBPFILTER > 0 */ 3180 3181 wh = mtod(m, struct ieee80211_frame *); 3182 ni = ieee80211_find_rxnode(ic, wh); 3183 rxi.rxi_flags = 0; 3184 #if 0 3185 if (atw_hw_decrypted(sc, wh)) { 3186 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3187 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 3188 } 3189 #endif 3190 rxi.rxi_rssi = (int)rssi; 3191 rxi.rxi_tstamp = 0; 3192 ieee80211_input(ifp, m, ni, &rxi); 3193 /* 3194 * The frame may have caused the node to be marked for 3195 * reclamation (e.g. in response to a DEAUTH message) 3196 * so use release_node here instead of unref_node. 3197 */ 3198 ieee80211_release_node(ic, ni); 3199 } 3200 3201 /* Update the receive pointer. */ 3202 sc->sc_rxptr = i; 3203 } 3204 3205 /* 3206 * atw_txintr: 3207 * 3208 * Helper; handle transmit interrupts. 3209 */ 3210 void 3211 atw_txintr(struct atw_softc *sc) 3212 { 3213 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3214 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3215 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3216 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3217 struct ifnet *ifp = &sc->sc_ic.ic_if; 3218 struct atw_txsoft *txs; 3219 u_int32_t txstat; 3220 3221 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3222 sc->sc_dev.dv_xname, sc->sc_flags)); 3223 3224 ifp->if_flags &= ~IFF_OACTIVE; 3225 3226 /* 3227 * Go through our Tx list and free mbufs for those 3228 * frames that have been transmitted. 3229 */ 3230 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3231 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3232 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3233 3234 #ifdef ATW_DEBUG 3235 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3236 int i; 3237 printf(" txsoft %p transmit chain:\n", txs); 3238 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3239 txs->txs_ndescs - 1, 3240 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3241 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3242 printf(" descriptor %d:\n", i); 3243 printf(" at_status: 0x%08x\n", 3244 letoh32(sc->sc_txdescs[i].at_stat)); 3245 printf(" at_flags: 0x%08x\n", 3246 letoh32(sc->sc_txdescs[i].at_flags)); 3247 printf(" at_buf1: 0x%08x\n", 3248 letoh32(sc->sc_txdescs[i].at_buf1)); 3249 printf(" at_buf2: 0x%08x\n", 3250 letoh32(sc->sc_txdescs[i].at_buf2)); 3251 if (i == txs->txs_lastdesc) 3252 break; 3253 } 3254 } 3255 #endif 3256 3257 txstat = letoh32(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3258 if (txstat & ATW_TXSTAT_OWN) 3259 break; 3260 3261 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3262 3263 sc->sc_txfree += txs->txs_ndescs; 3264 3265 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3266 0, txs->txs_dmamap->dm_mapsize, 3267 BUS_DMASYNC_POSTWRITE); 3268 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3269 m_freem(txs->txs_mbuf); 3270 txs->txs_mbuf = NULL; 3271 3272 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3273 3274 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3275 (txstat & TXSTAT_ERRMASK) != 0) { 3276 printf("%s: txstat %b %d\n", sc->sc_dev.dv_xname, 3277 txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3278 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3279 } 3280 3281 /* 3282 * Check for errors and collisions. 3283 */ 3284 if (txstat & ATW_TXSTAT_TUF) 3285 sc->sc_stats.ts_tx_tuf++; 3286 if (txstat & ATW_TXSTAT_TLT) 3287 sc->sc_stats.ts_tx_tlt++; 3288 if (txstat & ATW_TXSTAT_TRT) 3289 sc->sc_stats.ts_tx_trt++; 3290 if (txstat & ATW_TXSTAT_TRO) 3291 sc->sc_stats.ts_tx_tro++; 3292 if (txstat & ATW_TXSTAT_SOFBR) { 3293 sc->sc_stats.ts_tx_sofbr++; 3294 } 3295 3296 if ((txstat & ATW_TXSTAT_ES) == 0) 3297 ifp->if_collisions += 3298 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3299 else 3300 ifp->if_oerrors++; 3301 3302 ifp->if_opackets++; 3303 } 3304 3305 /* 3306 * If there are no more pending transmissions, cancel the watchdog 3307 * timer. 3308 */ 3309 if (txs == NULL) 3310 sc->sc_tx_timer = 0; 3311 #undef TXSTAT_ERRMASK 3312 #undef TXSTAT_FMT 3313 } 3314 3315 /* 3316 * atw_watchdog: [ifnet interface function] 3317 * 3318 * Watchdog timer handler. 3319 */ 3320 void 3321 atw_watchdog(struct ifnet *ifp) 3322 { 3323 struct atw_softc *sc = ifp->if_softc; 3324 struct ieee80211com *ic = &sc->sc_ic; 3325 uint32_t test1, rra, rwa; 3326 3327 ifp->if_timer = 0; 3328 if (ATW_IS_ENABLED(sc) == 0) 3329 return; 3330 3331 if (sc->sc_rescan_timer) { 3332 if (--sc->sc_rescan_timer == 0) 3333 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3334 } 3335 if (sc->sc_tx_timer) { 3336 if (--sc->sc_tx_timer == 0 && 3337 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3338 printf("%s: transmit timeout\n", ifp->if_xname); 3339 ifp->if_oerrors++; 3340 (void)atw_init(ifp); 3341 atw_start(ifp); 3342 } 3343 } 3344 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3345 ifp->if_timer = 1; 3346 3347 /* 3348 * ADM8211B seems to stall every so often, check for this. 3349 * These bits are what the Linux driver checks, they don't 3350 * seem to be documented by ADMTek/Infineon? 3351 */ 3352 if (sc->sc_rev == ATW_REVISION_BA) { 3353 test1 = ATW_READ(sc, ATW_TEST1); 3354 rra = (test1 >> 12) & 0x1ff; 3355 rwa = (test1 >> 2) & 0x1ff; 3356 3357 if ((rra != rwa) && !(test1 & 0x2)) { 3358 atw_init(ifp); 3359 atw_start(ifp); 3360 } 3361 } 3362 3363 ieee80211_watchdog(ifp); 3364 } 3365 3366 /* 3367 * Arguments in: 3368 * 3369 * paylen: payload length (no FCS, no WEP header) 3370 * 3371 * hdrlen: header length 3372 * 3373 * rate: MSDU speed, units 500kb/s 3374 * 3375 * flags: IEEE80211_F_SHPREAMBLE (use short preamble), 3376 * IEEE80211_F_SHSLOT (use short slot length) 3377 * 3378 * Arguments out: 3379 * 3380 * d: 802.11 Duration field for RTS, 3381 * 802.11 Duration field for data frame, 3382 * PLCP Length for data frame, 3383 * residual octets at end of data slot 3384 */ 3385 int 3386 atw_compute_duration1(int len, int use_ack, uint32_t flags, int rate, 3387 struct atw_duration *d) 3388 { 3389 int pre, ctsrate; 3390 int ack, bitlen, data_dur, remainder; 3391 3392 /* RTS reserves medium for SIFS | CTS | SIFS | (DATA) | SIFS | ACK 3393 * DATA reserves medium for SIFS | ACK 3394 * 3395 * XXXMYC: no ACK on multicast/broadcast or control packets 3396 */ 3397 3398 bitlen = len * 8; 3399 3400 pre = IEEE80211_DUR_DS_SIFS; 3401 if ((flags & IEEE80211_F_SHPREAMBLE) != 0) 3402 pre += IEEE80211_DUR_DS_SHORT_PREAMBLE + 3403 IEEE80211_DUR_DS_FAST_PLCPHDR; 3404 else 3405 pre += IEEE80211_DUR_DS_LONG_PREAMBLE + 3406 IEEE80211_DUR_DS_SLOW_PLCPHDR; 3407 3408 d->d_residue = 0; 3409 data_dur = (bitlen * 2) / rate; 3410 remainder = (bitlen * 2) % rate; 3411 if (remainder != 0) { 3412 d->d_residue = (rate - remainder) / 16; 3413 data_dur++; 3414 } 3415 3416 switch (rate) { 3417 case 2: /* 1 Mb/s */ 3418 case 4: /* 2 Mb/s */ 3419 /* 1 - 2 Mb/s WLAN: send ACK/CTS at 1 Mb/s */ 3420 ctsrate = 2; 3421 break; 3422 case 11: /* 5.5 Mb/s */ 3423 case 22: /* 11 Mb/s */ 3424 case 44: /* 22 Mb/s */ 3425 /* 5.5 - 11 Mb/s WLAN: send ACK/CTS at 2 Mb/s */ 3426 ctsrate = 4; 3427 break; 3428 default: 3429 /* TBD */ 3430 return -1; 3431 } 3432 3433 d->d_plcp_len = data_dur; 3434 3435 ack = (use_ack) ? pre + (IEEE80211_DUR_DS_SLOW_ACK * 2) / ctsrate : 0; 3436 3437 d->d_rts_dur = 3438 pre + (IEEE80211_DUR_DS_SLOW_CTS * 2) / ctsrate + 3439 pre + data_dur + 3440 ack; 3441 3442 d->d_data_dur = ack; 3443 3444 return 0; 3445 } 3446 3447 /* 3448 * Arguments in: 3449 * 3450 * wh: 802.11 header 3451 * 3452 * len: packet length 3453 * 3454 * rate: MSDU speed, units 500kb/s 3455 * 3456 * fraglen: fragment length, set to maximum (or higher) for no 3457 * fragmentation 3458 * 3459 * flags: IEEE80211_F_WEPON (hardware adds WEP), 3460 * IEEE80211_F_SHPREAMBLE (use short preamble), 3461 * IEEE80211_F_SHSLOT (use short slot length) 3462 * 3463 * Arguments out: 3464 * 3465 * d0: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields 3466 * of first/only fragment 3467 * 3468 * dn: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields 3469 * of first/only fragment 3470 */ 3471 int 3472 atw_compute_duration(struct ieee80211_frame *wh, int len, uint32_t flags, 3473 int fraglen, int rate, struct atw_duration *d0, struct atw_duration *dn, 3474 int *npktp, int debug) 3475 { 3476 int ack, rc; 3477 int firstlen, hdrlen, lastlen, lastlen0, npkt, overlen, paylen; 3478 3479 if ((wh->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 3480 hdrlen = sizeof(struct ieee80211_frame_addr4); 3481 else 3482 hdrlen = sizeof(struct ieee80211_frame); 3483 3484 paylen = len - hdrlen; 3485 3486 if ((flags & IEEE80211_F_WEPON) != 0) 3487 overlen = IEEE80211_WEP_TOTLEN + IEEE80211_CRC_LEN; 3488 else 3489 overlen = IEEE80211_CRC_LEN; 3490 3491 npkt = paylen / fraglen; 3492 lastlen0 = paylen % fraglen; 3493 3494 if (npkt == 0) /* no fragments */ 3495 lastlen = paylen + overlen; 3496 else if (lastlen0 != 0) { /* a short "tail" fragment */ 3497 lastlen = lastlen0 + overlen; 3498 npkt++; 3499 } else /* full-length "tail" fragment */ 3500 lastlen = fraglen + overlen; 3501 3502 if (npktp != NULL) 3503 *npktp = npkt; 3504 3505 if (npkt > 1) 3506 firstlen = fraglen + overlen; 3507 else 3508 firstlen = paylen + overlen; 3509 3510 if (debug) { 3511 printf("%s: npkt %d firstlen %d lastlen0 %d lastlen %d " 3512 "fraglen %d overlen %d len %d rate %d flags %08x\n", 3513 __func__, npkt, firstlen, lastlen0, lastlen, fraglen, 3514 overlen, len, rate, flags); 3515 } 3516 3517 ack = !IEEE80211_IS_MULTICAST(wh->i_addr1) && 3518 (wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL; 3519 3520 rc = atw_compute_duration1(firstlen + hdrlen, ack, flags, rate, d0); 3521 if (rc == -1) 3522 return rc; 3523 3524 if (npkt <= 1) { 3525 *dn = *d0; 3526 return 0; 3527 } 3528 return atw_compute_duration1(lastlen + hdrlen, ack, flags, rate, dn); 3529 } 3530 3531 #ifdef ATW_DEBUG 3532 void 3533 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3534 { 3535 struct atw_softc *sc = ifp->if_softc; 3536 struct mbuf *m; 3537 int i, noctets = 0; 3538 3539 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3540 m0->m_pkthdr.len); 3541 3542 for (m = m0; m; m = m->m_next) { 3543 if (m->m_len == 0) 3544 continue; 3545 for (i = 0; i < m->m_len; i++) { 3546 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3547 if (++noctets % 24 == 0) 3548 printf("\n"); 3549 } 3550 } 3551 printf("%s%s: %d bytes emitted\n", 3552 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3553 } 3554 #endif /* ATW_DEBUG */ 3555 3556 /* 3557 * atw_start: [ifnet interface function] 3558 * 3559 * Start packet transmission on the interface. 3560 */ 3561 void 3562 atw_start(struct ifnet *ifp) 3563 { 3564 struct atw_softc *sc = ifp->if_softc; 3565 struct ieee80211com *ic = &sc->sc_ic; 3566 struct ieee80211_node *ni; 3567 struct ieee80211_frame *wh; 3568 struct ieee80211_key *k; 3569 struct atw_frame *hh; 3570 struct mbuf *m0, *m; 3571 struct atw_txsoft *txs, *last_txs; 3572 struct atw_txdesc *txd; 3573 int do_encrypt, npkt, rate; 3574 bus_dmamap_t dmamap; 3575 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3576 3577 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3578 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3579 3580 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3581 return; 3582 3583 /* 3584 * Remember the previous number of free descriptors and 3585 * the first descriptor we'll use. 3586 */ 3587 ofree = sc->sc_txfree; 3588 firsttx = sc->sc_txnext; 3589 3590 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3591 sc->sc_dev.dv_xname, ofree, firsttx)); 3592 3593 /* 3594 * Loop through the send queue, setting up transmit descriptors 3595 * until we drain the queue, or use up all available transmit 3596 * descriptors. 3597 */ 3598 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3599 sc->sc_txfree != 0) { 3600 3601 /* 3602 * Grab a packet off the management queue, if it 3603 * is not empty. Otherwise, from the data queue. 3604 */ 3605 IF_DEQUEUE(&ic->ic_mgtq, m0); 3606 if (m0 != NULL) { 3607 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 3608 m0->m_pkthdr.rcvif = NULL; 3609 } else { 3610 /* send no data packets until we are associated */ 3611 if (ic->ic_state != IEEE80211_S_RUN) 3612 break; 3613 IFQ_DEQUEUE(&ifp->if_snd, m0); 3614 if (m0 == NULL) 3615 break; 3616 #if NBPFILTER > 0 3617 if (ifp->if_bpf != NULL) 3618 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 3619 #endif /* NBPFILTER > 0 */ 3620 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3621 ifp->if_oerrors++; 3622 break; 3623 } 3624 3625 if (ic->ic_flags & IEEE80211_F_WEPON) { 3626 wh = mtod(m0, struct ieee80211_frame *); 3627 k = ieee80211_get_txkey(ic, wh, ni); 3628 m0 = ieee80211_encrypt(ic, m0, k); 3629 if (m0 == NULL) { 3630 ifp->if_oerrors++; 3631 break; 3632 } 3633 } 3634 } 3635 3636 wh = mtod(m0, struct ieee80211_frame *); 3637 3638 /* XXX do real rate control */ 3639 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3640 IEEE80211_FC0_TYPE_MGT) 3641 rate = 2; 3642 else 3643 rate = MAX(2, ieee80211_get_rate(ic)); 3644 3645 if (atw_compute_duration(wh, m0->m_pkthdr.len, 3646 ic->ic_flags & ~IEEE80211_F_WEPON, ic->ic_fragthreshold, 3647 rate, &txs->txs_d0, &txs->txs_dn, &npkt, 3648 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 3649 (IFF_DEBUG|IFF_LINK2)) == -1) { 3650 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3651 m_freem(m0); 3652 break; 3653 } 3654 3655 /* 3656 * XXX Misleading if fragmentation is enabled. Better 3657 * to fragment in software? 3658 */ 3659 *(uint16_t *)wh->i_dur = htole16(txs->txs_d0.d_rts_dur); 3660 3661 #if NBPFILTER > 0 3662 /* 3663 * Pass the packet to any BPF listeners. 3664 */ 3665 if (ic->ic_rawbpf != NULL) 3666 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 3667 3668 if (sc->sc_radiobpf != NULL) { 3669 struct mbuf mb; 3670 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3671 3672 tap->at_rate = rate; 3673 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3674 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3675 3676 /* TBD tap->at_flags */ 3677 3678 mb.m_data = (caddr_t)tap; 3679 mb.m_len = tap->at_ihdr.it_len; 3680 mb.m_next = m0; 3681 mb.m_nextpkt = NULL; 3682 mb.m_type = 0; 3683 mb.m_flags = 0; 3684 bpf_mtap(sc->sc_radiobpf, &mb, BPF_DIRECTION_OUT); 3685 } 3686 #endif /* NBPFILTER > 0 */ 3687 3688 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3689 3690 if (ni != NULL) 3691 ieee80211_release_node(ic, ni); 3692 3693 if (m0 == NULL) { 3694 ifp->if_oerrors++; 3695 break; 3696 } 3697 3698 /* just to make sure. */ 3699 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3700 3701 if (m0 == NULL) { 3702 ifp->if_oerrors++; 3703 break; 3704 } 3705 3706 hh = mtod(m0, struct atw_frame *); 3707 wh = &hh->atw_ihdr; 3708 3709 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3710 3711 /* Copy everything we need from the 802.11 header: 3712 * Frame Control; address 1, address 3, or addresses 3713 * 3 and 4. NIC fills in BSSID, SA. 3714 */ 3715 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3716 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3717 panic("%s: illegal WDS frame", 3718 sc->sc_dev.dv_xname); 3719 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3720 } else 3721 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3722 3723 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3724 3725 /* initialize remaining Tx parameters */ 3726 memset(&hh->u, 0, sizeof(hh->u)); 3727 3728 hh->atw_rate = rate * 5; 3729 /* XXX this could be incorrect if M_FCS. _encap should 3730 * probably strip FCS just in case it sticks around in 3731 * bridged packets. 3732 */ 3733 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3734 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3735 sizeof(struct atw_frame)); 3736 3737 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3738 hh->atw_rtylmt = 3; 3739 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3740 #if 0 3741 if (do_encrypt) { 3742 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3743 hh->atw_keyid = ic->ic_wep_txkey; 3744 } 3745 #endif 3746 3747 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3748 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3749 if (txs->txs_d0.d_residue) 3750 hh->atw_head_plcplen |= htole16(0x8000); 3751 if (txs->txs_dn.d_residue) 3752 hh->atw_tail_plcplen |= htole16(0x8000); 3753 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3754 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3755 3756 /* never fragment multicast frames */ 3757 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3758 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3759 } else if (sc->sc_flags & ATWF_RTSCTS) { 3760 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3761 } 3762 3763 #ifdef ATW_DEBUG 3764 hh->atw_fragnum = 0; 3765 3766 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3767 printf("%s: dst = %s, rate = 0x%02x, " 3768 "service = 0x%02x, paylen = 0x%04x\n", 3769 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3770 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3771 3772 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3773 "dur1 = 0x%04x, dur2 = 0x%04x, " 3774 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3775 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3776 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3777 hh->atw_tail_dur, hh->atw_head_dur); 3778 3779 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3780 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3781 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3782 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3783 3784 printf("%s: keyid = %d\n", 3785 sc->sc_dev.dv_xname, hh->atw_keyid); 3786 3787 atw_dump_pkt(ifp, m0); 3788 } 3789 #endif /* ATW_DEBUG */ 3790 3791 dmamap = txs->txs_dmamap; 3792 3793 /* 3794 * Load the DMA map. Copy and try (once) again if the packet 3795 * didn't fit in the alloted number of segments. 3796 */ 3797 for (first = 1; 3798 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3799 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3800 first = 0) { 3801 MGETHDR(m, M_DONTWAIT, MT_DATA); 3802 if (m == NULL) { 3803 printf("%s: unable to allocate Tx mbuf\n", 3804 sc->sc_dev.dv_xname); 3805 break; 3806 } 3807 if (m0->m_pkthdr.len > MHLEN) { 3808 MCLGET(m, M_DONTWAIT); 3809 if ((m->m_flags & M_EXT) == 0) { 3810 printf("%s: unable to allocate Tx " 3811 "cluster\n", sc->sc_dev.dv_xname); 3812 m_freem(m); 3813 break; 3814 } 3815 } 3816 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3817 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3818 m_freem(m0); 3819 m0 = m; 3820 m = NULL; 3821 } 3822 if (error != 0) { 3823 printf("%s: unable to load Tx buffer, " 3824 "error = %d\n", sc->sc_dev.dv_xname, error); 3825 m_freem(m0); 3826 break; 3827 } 3828 3829 /* 3830 * Ensure we have enough descriptors free to describe 3831 * the packet. 3832 */ 3833 if (dmamap->dm_nsegs > sc->sc_txfree) { 3834 /* 3835 * Not enough free descriptors to transmit 3836 * this packet. Unload the DMA map and 3837 * drop the packet. Notify the upper layer 3838 * that there are no more slots left. 3839 * 3840 * XXX We could allocate an mbuf and copy, but 3841 * XXX it is worth it? 3842 */ 3843 ifp->if_flags |= IFF_OACTIVE; 3844 bus_dmamap_unload(sc->sc_dmat, dmamap); 3845 m_freem(m0); 3846 break; 3847 } 3848 3849 /* 3850 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3851 */ 3852 3853 /* Sync the DMA map. */ 3854 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3855 BUS_DMASYNC_PREWRITE); 3856 3857 /* XXX arbitrary retry limit; 8 because I have seen it in 3858 * use already and maybe 0 means "no tries" ! 3859 */ 3860 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3861 3862 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3863 sc->sc_dev.dv_xname, rate * 5)); 3864 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3865 3866 /* 3867 * Initialize the transmit descriptors. 3868 */ 3869 for (nexttx = sc->sc_txnext, seg = 0; 3870 seg < dmamap->dm_nsegs; 3871 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3872 /* 3873 * If this is the first descriptor we're 3874 * enqueueing, don't set the OWN bit just 3875 * yet. That could cause a race condition. 3876 * We'll do it below. 3877 */ 3878 txd = &sc->sc_txdescs[nexttx]; 3879 txd->at_ctl = ctl | 3880 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3881 3882 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3883 txd->at_flags = 3884 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3885 ATW_TXFLAG_TBS1_MASK)) | 3886 ((nexttx == (ATW_NTXDESC - 1)) 3887 ? htole32(ATW_TXFLAG_TER) : 0); 3888 lasttx = nexttx; 3889 } 3890 3891 if (lasttx == -1) 3892 panic("%s: bad lastx", ifp->if_xname); 3893 /* Set `first segment' and `last segment' appropriately. */ 3894 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3895 htole32(ATW_TXFLAG_FS); 3896 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3897 3898 #ifdef ATW_DEBUG 3899 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3900 printf(" txsoft %p transmit chain:\n", txs); 3901 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3902 printf(" descriptor %d:\n", seg); 3903 printf(" at_ctl: 0x%08x\n", 3904 letoh32(sc->sc_txdescs[seg].at_ctl)); 3905 printf(" at_flags: 0x%08x\n", 3906 letoh32(sc->sc_txdescs[seg].at_flags)); 3907 printf(" at_buf1: 0x%08x\n", 3908 letoh32(sc->sc_txdescs[seg].at_buf1)); 3909 printf(" at_buf2: 0x%08x\n", 3910 letoh32(sc->sc_txdescs[seg].at_buf2)); 3911 if (seg == lasttx) 3912 break; 3913 } 3914 } 3915 #endif 3916 3917 /* Sync the descriptors we're using. */ 3918 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3919 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3920 3921 /* 3922 * Store a pointer to the packet so we can free it later, 3923 * and remember what txdirty will be once the packet is 3924 * done. 3925 */ 3926 txs->txs_mbuf = m0; 3927 txs->txs_firstdesc = sc->sc_txnext; 3928 txs->txs_lastdesc = lasttx; 3929 txs->txs_ndescs = dmamap->dm_nsegs; 3930 3931 /* Advance the tx pointer. */ 3932 sc->sc_txfree -= dmamap->dm_nsegs; 3933 sc->sc_txnext = nexttx; 3934 3935 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3936 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3937 3938 last_txs = txs; 3939 } 3940 3941 if (txs == NULL || sc->sc_txfree == 0) { 3942 /* No more slots left; notify upper layer. */ 3943 ifp->if_flags |= IFF_OACTIVE; 3944 } 3945 3946 if (sc->sc_txfree != ofree) { 3947 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3948 sc->sc_dev.dv_xname, lasttx, firsttx)); 3949 /* 3950 * Cause a transmit interrupt to happen on the 3951 * last packet we enqueued. 3952 */ 3953 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3954 ATW_CDTXSYNC(sc, lasttx, 1, 3955 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3956 3957 /* 3958 * The entire packet chain is set up. Give the 3959 * first descriptor to the chip now. 3960 */ 3961 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3962 ATW_CDTXSYNC(sc, firsttx, 1, 3963 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3964 3965 /* Wake up the transmitter. */ 3966 ATW_WRITE(sc, ATW_TDR, 0x1); 3967 3968 /* Set a watchdog timer in case the chip flakes out. */ 3969 sc->sc_tx_timer = 5; 3970 ifp->if_timer = 1; 3971 } 3972 } 3973 3974 int 3975 atw_activate(struct device *self, int act) 3976 { 3977 struct atw_softc *sc = (struct atw_softc *)self; 3978 struct ifnet *ifp = &sc->sc_ic.ic_if; 3979 3980 switch (act) { 3981 case DVACT_SUSPEND: 3982 if (ifp->if_flags & IFF_RUNNING) 3983 atw_stop(ifp, 1); 3984 if (sc->sc_power != NULL) 3985 (*sc->sc_power)(sc, act); 3986 break; 3987 case DVACT_RESUME: 3988 workq_queue_task(NULL, &sc->sc_resume_wqt, 0, 3989 atw_resume, sc, NULL); 3990 break; 3991 } 3992 return 0; 3993 } 3994 3995 void 3996 atw_resume(void *arg1, void *arg2) 3997 { 3998 struct atw_softc *sc = (struct atw_softc *)arg1; 3999 struct ifnet *ifp = &sc->sc_ic.ic_if; 4000 4001 if (sc->sc_power != NULL) 4002 (*sc->sc_power)(sc, DVACT_RESUME); 4003 if (ifp->if_flags & IFF_UP) 4004 atw_init(ifp); 4005 } 4006 4007 /* 4008 * atw_ioctl: [ifnet interface function] 4009 * 4010 * Handle control requests from the operator. 4011 */ 4012 int 4013 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4014 { 4015 struct atw_softc *sc = ifp->if_softc; 4016 struct ieee80211com *ic = &sc->sc_ic; 4017 struct ifreq *ifr = (struct ifreq *)data; 4018 struct ifaddr *ifa = (struct ifaddr *)data; 4019 int s, error = 0; 4020 4021 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 4022 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 4023 return ENXIO; 4024 4025 s = splnet(); 4026 4027 switch (cmd) { 4028 case SIOCSIFADDR: 4029 ifp->if_flags |= IFF_UP; 4030 #ifdef INET 4031 if (ifa->ifa_addr->sa_family == AF_INET) { 4032 arp_ifinit(&ic->ic_ac, ifa); 4033 } 4034 #endif /* INET */ 4035 /* FALLTHROUGH */ 4036 4037 case SIOCSIFFLAGS: 4038 if (ifp->if_flags & IFF_UP) { 4039 if (ATW_IS_ENABLED(sc)) { 4040 /* 4041 * To avoid rescanning another access point, 4042 * do not call atw_init() here. Instead, 4043 * only reflect media settings. 4044 */ 4045 atw_filter_setup(sc); 4046 } else 4047 error = atw_init(ifp); 4048 } else if (ATW_IS_ENABLED(sc)) 4049 atw_stop(ifp, 1); 4050 break; 4051 4052 case SIOCADDMULTI: 4053 case SIOCDELMULTI: 4054 error = (cmd == SIOCADDMULTI) ? 4055 ether_addmulti(ifr, &sc->sc_ic.ic_ac) : 4056 ether_delmulti(ifr, &sc->sc_ic.ic_ac); 4057 4058 if (error == ENETRESET) { 4059 if (ifp->if_flags & IFF_RUNNING) 4060 atw_filter_setup(sc); /* do not rescan */ 4061 error = 0; 4062 } 4063 break; 4064 4065 default: 4066 error = ieee80211_ioctl(ifp, cmd, data); 4067 if (error == ENETRESET) { 4068 if (ATW_IS_ENABLED(sc)) 4069 error = atw_init(ifp); 4070 else 4071 error = 0; 4072 } 4073 break; 4074 } 4075 4076 /* Try to get more packets going. */ 4077 if (ATW_IS_ENABLED(sc)) 4078 atw_start(ifp); 4079 4080 splx(s); 4081 return (error); 4082 } 4083 4084 int 4085 atw_media_change(struct ifnet *ifp) 4086 { 4087 int error; 4088 4089 error = ieee80211_media_change(ifp); 4090 if (error == ENETRESET) { 4091 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 4092 (IFF_RUNNING|IFF_UP)) 4093 atw_init(ifp); /* XXX lose error */ 4094 error = 0; 4095 } 4096 return error; 4097 } 4098 4099 void 4100 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 4101 { 4102 struct atw_softc *sc = ifp->if_softc; 4103 4104 if (ATW_IS_ENABLED(sc) == 0) { 4105 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 4106 imr->ifm_status = 0; 4107 return; 4108 } 4109 ieee80211_media_status(ifp, imr); 4110 } 4111