1 /* $OpenBSD: fxpvar.h,v 1.19 2004/09/20 04:27:23 brad Exp $ */ 2 /* $NetBSD: if_fxpvar.h,v 1.1 1997/06/05 02:01:58 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1995, David Greenman 6 * All rights reserved. 7 * 8 * Modifications to support NetBSD: 9 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice unmodified, this list of conditions, and the following 16 * disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Id: if_fxpvar.h,v 1.6 1998/08/02 00:29:15 dg Exp 34 */ 35 36 /* 37 * Misc. definitions for the Intel EtherExpress Pro/100B PCI Fast 38 * Ethernet driver 39 */ 40 41 /* 42 * Number of transmit control blocks. This determines the number 43 * of transmit buffers that can be chained in the CB list. 44 * This must be a power of two. 45 */ 46 #define FXP_NTXCB 128 47 48 /* 49 * Minimum and maximum number of receive frame area buffers. 50 */ 51 #define FXP_NRFABUFS_MIN 4 52 #define FXP_NRFABUFS_MAX 64 /* These are large so choose wisely. */ 53 54 /* 55 * Default maximum time, in microseconds, that an interrupt may be delayed 56 * in an attempt to coalesce interrupts. This is only effective if the Intel 57 * microcode is loaded. 58 */ 59 #ifndef FXP_INT_DELAY 60 #define FXP_INT_DELAY 64 61 #endif 62 63 /* 64 * Default number of packets that will be bundled, before an interrupt is 65 * generated. This is only effective if the Intel microcode is loaded. 66 * This is not present in all microcode revisions. 67 */ 68 #ifndef FXP_BUNDLE_MAX 69 #define FXP_BUNDLE_MAX 16 70 #endif 71 72 /* 73 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 74 * for functional grouping. 75 */ 76 77 struct fxp_txsw { 78 struct fxp_txsw *tx_next; 79 struct mbuf *tx_mbuf; 80 bus_dmamap_t tx_map; 81 bus_addr_t tx_off; 82 struct fxp_cb_tx *tx_cb; 83 }; 84 85 struct fxp_ctrl { 86 struct fxp_cb_tx tx_cb[FXP_NTXCB]; 87 struct fxp_stats stats; 88 union { 89 struct fxp_cb_mcs mcs; 90 struct fxp_cb_ias ias; 91 struct fxp_cb_config cfg; 92 struct fxp_cb_ucode code; 93 } u; 94 }; 95 96 struct fxp_softc { 97 struct device sc_dev; /* generic device structures */ 98 void *sc_ih; /* interrupt handler cookie */ 99 bus_space_tag_t sc_st; /* bus space tag */ 100 bus_space_handle_t sc_sh; /* bus space handle */ 101 bus_dma_tag_t sc_dmat; /* bus dma tag */ 102 struct arpcom sc_arpcom; /* per-interface network data */ 103 struct mii_data sc_mii; /* MII media information */ 104 struct mbuf *rfa_headm; /* first mbuf in receive frame area */ 105 struct mbuf *rfa_tailm; /* last mbuf in receive frame area */ 106 int sc_flags; /* misc. flags */ 107 #define FXPF_DISABLE_STANDBY 0x20 /* currently need to work-around */ 108 #define FXPF_UCODE 0x40 /* ucode is loaded */ 109 struct timeout stats_update_to; /* Pointer to timeout structure */ 110 int rx_idle_secs; /* # of seconds RX has been idle */ 111 struct fxp_cb_tx *cbl_base; /* base of TxCB list */ 112 int phy_primary_addr; /* address of primary PHY */ 113 int phy_primary_device; /* device type of primary PHY */ 114 int phy_10Mbps_only; /* PHY is 10Mbps-only device */ 115 int eeprom_size; /* size of serial EEPROM */ 116 int not_82557; /* yes if we are 82558/82559 */ 117 int rx_bufs; /* how many rx buffers allocated? */ 118 void *sc_sdhook; /* shutdownhook */ 119 void *sc_powerhook; /* powerhook */ 120 struct fxp_txsw txs[FXP_NTXCB]; 121 struct fxp_txsw *sc_cbt_cons, *sc_cbt_prod, *sc_cbt_prev; 122 int sc_cbt_cnt; 123 bus_dmamap_t tx_cb_map; 124 bus_dma_segment_t sc_cb_seg; 125 int sc_cb_nseg; 126 struct fxp_ctrl *sc_ctrl; 127 bus_dmamap_t sc_rxmaps[FXP_NRFABUFS_MAX]; 128 int sc_rxfree; 129 u_int32_t sc_revision; /* chip revision */ 130 u_int16_t sc_int_delay; /* interrupt delay value for ucode */ 131 u_int16_t sc_bundle_max; /* max # frames per interrupt (ucode) */ 132 }; 133 134 /* Macros to ease CSR access. */ 135 #define CSR_READ_1(sc, reg) \ 136 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 137 #define CSR_READ_2(sc, reg) \ 138 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 139 #define CSR_READ_4(sc, reg) \ 140 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 141 #define CSR_WRITE_1(sc, reg, val) \ 142 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 143 #define CSR_WRITE_2(sc, reg, val) \ 144 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 145 #define CSR_WRITE_4(sc, reg, val) \ 146 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 147 148 extern int fxp_intr(void *); 149 extern int fxp_attach_common(struct fxp_softc *, const char *); 150 extern int fxp_detach(struct fxp_softc *); 151 152 #define FXP_RXMAP_GET(sc) ((sc)->sc_rxmaps[(sc)->sc_rxfree++]) 153 #define FXP_RXMAP_PUT(sc,map) ((sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map)) 154 155 #define FXP_TXCB_SYNC(sc, txs, p) \ 156 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, (txs)->tx_off, \ 157 sizeof(struct fxp_cb_tx), (p)) 158 159 #define FXP_MCS_SYNC(sc, p) \ 160 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \ 161 offsetof(struct fxp_ctrl, u.mcs), sizeof(struct fxp_cb_mcs), (p)) 162 163 #define FXP_IAS_SYNC(sc, p) \ 164 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \ 165 offsetof(struct fxp_ctrl, u.ias), sizeof(struct fxp_cb_ias), (p)) 166 167 #define FXP_CFG_SYNC(sc, p) \ 168 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \ 169 offsetof(struct fxp_ctrl, u.cfg), sizeof(struct fxp_cb_config), (p)) 170 171 #define FXP_UCODE_SYNC(sc, p) \ 172 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \ 173 offsetof(struct fxp_ctrl, u.code), sizeof(struct fxp_cb_ucode), (p)) 174 175 #define FXP_STATS_SYNC(sc, p) \ 176 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \ 177 offsetof(struct fxp_ctrl, stats), sizeof(struct fxp_stats), (p)) 178 179 #define FXP_MBUF_SYNC(sc, m, p) \ 180 bus_dmamap_sync((sc)->sc_dmat, (m), 0, (m)->dm_mapsize, (p)) 181