1 /* $OpenBSD: lsi64854.c,v 1.9 2008/06/26 05:42:15 ray Exp $ */ 2 /* $NetBSD: lsi64854.c,v 1.18 2001/06/04 20:56:51 mrg Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/errno.h> 38 #include <sys/device.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <machine/bus.h> 43 #include <machine/autoconf.h> 44 #include <machine/cpu.h> 45 46 #include <scsi/scsi_all.h> 47 #include <scsi/scsiconf.h> 48 49 #include <dev/ic/lsi64854reg.h> 50 #include <dev/ic/lsi64854var.h> 51 52 #include <dev/ic/ncr53c9xreg.h> 53 #include <dev/ic/ncr53c9xvar.h> 54 55 void lsi64854_reset(struct lsi64854_softc *); 56 int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *, 57 int, size_t *); 58 int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *, 59 int, size_t *); 60 int lsi64854_scsi_intr(void *); 61 int lsi64854_pp_intr(void *); 62 63 #ifdef DEBUG 64 #define LDB_SCSI 1 65 #define LDB_ENET 2 66 #define LDB_PP 4 67 #define LDB_ANY 0xff 68 int lsi64854debug = 0; 69 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 70 #else 71 #define DPRINTF(a,x) 72 #endif 73 74 #define MAX_DMA_SZ (16*1024*1024) 75 76 /* 77 * Finish attaching this DMA device. 78 * Front-end must fill in these fields: 79 * sc_bustag 80 * sc_dmatag 81 * sc_regs 82 * sc_burst 83 * sc_channel (one of SCSI, ENET, PP) 84 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 85 */ 86 int 87 lsi64854_attach(sc) 88 struct lsi64854_softc *sc; 89 { 90 u_int32_t csr; 91 int rc; 92 93 /* Indirect functions */ 94 switch (sc->sc_channel) { 95 case L64854_CHANNEL_SCSI: 96 sc->intr = lsi64854_scsi_intr; 97 sc->setup = lsi64854_setup; 98 break; 99 case L64854_CHANNEL_ENET: 100 sc->intr = lsi64854_enet_intr; 101 sc->setup = lsi64854_setup; 102 break; 103 case L64854_CHANNEL_PP: 104 sc->intr = lsi64854_pp_intr; 105 sc->setup = lsi64854_setup_pp; 106 break; 107 default: 108 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 109 } 110 sc->reset = lsi64854_reset; 111 112 /* Allocate a dmamap */ 113 if ((rc = bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 114 0, BUS_DMA_WAITOK, &sc->sc_dmamap)) != 0) { 115 printf(": dma map create failed\n"); 116 return (rc); 117 } 118 119 printf(": dma rev "); 120 csr = L64854_GCSR(sc); 121 sc->sc_rev = csr & L64854_DEVID; 122 switch (sc->sc_rev) { 123 case DMAREV_0: 124 printf("0"); 125 break; 126 case DMAREV_ESC: 127 printf("esc"); 128 break; 129 case DMAREV_1: 130 printf("1"); 131 break; 132 case DMAREV_PLUS: 133 printf("1+"); 134 break; 135 case DMAREV_2: 136 printf("2"); 137 break; 138 case DMAREV_HME: 139 printf("fas"); 140 break; 141 default: 142 printf("unknown (0x%x)", sc->sc_rev); 143 } 144 145 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 146 printf("\n"); 147 148 return (0); 149 } 150 151 /* 152 * DMAWAIT waits while condition is true 153 */ 154 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 155 int count = 500000; \ 156 while ((COND) && --count > 0) DELAY(1); \ 157 if (count == 0) { \ 158 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 159 (u_long)L64854_GCSR(SC)); \ 160 if (DONTPANIC) \ 161 printf(MSG); \ 162 else \ 163 panic(MSG); \ 164 } \ 165 } while (0) 166 167 #define DMA_DRAIN(sc, dontpanic) do { \ 168 u_int32_t csr; \ 169 /* \ 170 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 171 * and "drain" bits while it is still thinking about a \ 172 * request. \ 173 * other revs: D_ESC_R_PEND bit reads as 0 \ 174 */ \ 175 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 176 if (sc->sc_rev != DMAREV_HME) { \ 177 /* \ 178 * Select drain bit based on revision \ 179 * also clears errors and D_TC flag \ 180 */ \ 181 csr = L64854_GCSR(sc); \ 182 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 183 csr |= D_ESC_DRAIN; \ 184 else \ 185 csr |= L64854_INVALIDATE; \ 186 \ 187 L64854_SCSR(sc,csr); \ 188 } \ 189 /* \ 190 * Wait for draining to finish \ 191 * rev0 & rev1 call this PACKCNT \ 192 */ \ 193 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 194 } while(0) 195 196 #define DMA_FLUSH(sc, dontpanic) do { \ 197 u_int32_t csr; \ 198 /* \ 199 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 200 * and "drain" bits while it is still thinking about a \ 201 * request. \ 202 * other revs: D_ESC_R_PEND bit reads as 0 \ 203 */ \ 204 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 205 csr = L64854_GCSR(sc); \ 206 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 207 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 208 L64854_SCSR(sc,csr); \ 209 } while(0) 210 211 void 212 lsi64854_reset(sc) 213 struct lsi64854_softc *sc; 214 { 215 u_int32_t csr; 216 217 DMA_FLUSH(sc, 1); 218 csr = L64854_GCSR(sc); 219 220 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 221 222 /* 223 * XXX is sync needed? 224 */ 225 if (sc->sc_dmamap->dm_nsegs > 0) 226 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 227 228 if (sc->sc_rev == DMAREV_HME) 229 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 230 231 232 csr |= L64854_RESET; /* reset DMA */ 233 L64854_SCSR(sc, csr); 234 DELAY(200); /* > 10 Sbus clocks(?) */ 235 236 /*DMAWAIT1(sc); why was this here? */ 237 csr = L64854_GCSR(sc); 238 csr &= ~L64854_RESET; /* de-assert reset line */ 239 L64854_SCSR(sc, csr); 240 DELAY(5); /* allow a few ticks to settle */ 241 242 csr = L64854_GCSR(sc); 243 csr |= L64854_INT_EN; /* enable interrupts */ 244 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 245 if (sc->sc_rev == DMAREV_HME) 246 csr |= D_TWO_CYCLE; 247 else 248 csr |= D_FASTER; 249 } 250 251 /* Set burst */ 252 switch (sc->sc_rev) { 253 case DMAREV_HME: 254 case DMAREV_2: 255 csr &= ~L64854_BURST_SIZE; 256 if (sc->sc_burst == 32) { 257 csr |= L64854_BURST_32; 258 } else if (sc->sc_burst == 16) { 259 csr |= L64854_BURST_16; 260 } else { 261 csr |= L64854_BURST_0; 262 } 263 break; 264 case DMAREV_ESC: 265 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 266 if (sc->sc_burst == 32) { 267 csr &= ~D_ESC_BURST; 268 } else 269 csr |= D_ESC_BURST; 270 break; 271 default: 272 break; 273 } 274 L64854_SCSR(sc, csr); 275 276 if (sc->sc_rev == DMAREV_HME) { 277 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 278 sc->sc_dmactl = csr; 279 } 280 sc->sc_active = 0; 281 282 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 283 } 284 285 286 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 287 /* 288 * setup a dma transfer 289 */ 290 int 291 lsi64854_setup(sc, addr, len, datain, dmasize) 292 struct lsi64854_softc *sc; 293 caddr_t *addr; 294 size_t *len; 295 int datain; 296 size_t *dmasize; /* IN-OUT */ 297 { 298 u_int32_t csr; 299 300 DMA_FLUSH(sc, 0); 301 302 #if 0 303 DMACSR(sc) &= ~D_INT_EN; 304 #endif 305 sc->sc_dmaaddr = addr; 306 sc->sc_dmalen = len; 307 308 /* 309 * the rules say we cannot transfer more than the limit 310 * of this DMA chip (64k for old and 16Mb for new), 311 * and we cannot cross a 16Mb boundary. 312 */ 313 *dmasize = sc->sc_dmasize = 314 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 315 316 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 317 318 /* 319 * XXX what length? 320 */ 321 if (sc->sc_rev == DMAREV_HME) { 322 323 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 324 L64854_SCSR(sc, sc->sc_dmactl); 325 326 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 327 } 328 329 /* Program the DMA address */ 330 if (sc->sc_dmasize) { 331 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 332 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 333 *sc->sc_dmaaddr, sc->sc_dmasize, 334 NULL /* kernel address */, 335 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 336 panic("%s: cannot allocate DVMA address", 337 sc->sc_dev.dv_xname); 338 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 339 datain 340 ? BUS_DMASYNC_PREREAD 341 : BUS_DMASYNC_PREWRITE); 342 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 343 sc->sc_dmamap->dm_segs[0].ds_addr); 344 } 345 346 if (sc->sc_rev == DMAREV_ESC) { 347 /* DMA ESC chip bug work-around */ 348 long bcnt = sc->sc_dmasize; 349 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 350 if ((eaddr & PGOFSET) != 0) 351 bcnt = roundup(bcnt, PAGE_SIZE); 352 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 353 bcnt); 354 } 355 356 /* Setup DMA control register */ 357 csr = L64854_GCSR(sc); 358 359 if (datain) 360 csr |= L64854_WRITE; 361 else 362 csr &= ~L64854_WRITE; 363 csr |= L64854_INT_EN; 364 365 if (sc->sc_rev == DMAREV_HME) { 366 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 367 } 368 369 L64854_SCSR(sc, csr); 370 371 return (0); 372 } 373 374 /* 375 * Pseudo (chained) interrupt from the esp driver to kick the 376 * current running DMA transfer. Called from ncr53c9x_intr() 377 * for now. 378 * 379 * return 1 if it was a DMA continue. 380 */ 381 int 382 lsi64854_scsi_intr(arg) 383 void *arg; 384 { 385 struct lsi64854_softc *sc = arg; 386 struct ncr53c9x_softc *nsc = sc->sc_client; 387 char bits[64]; 388 int trans, resid; 389 u_int32_t csr; 390 391 csr = L64854_GCSR(sc); 392 393 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname, 394 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 395 csr, DDMACSR_BITS)); 396 397 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 398 snprintf(bits, sizeof(bits), "%b", csr, DDMACSR_BITS); 399 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits); 400 csr &= ~D_EN_DMA; /* Stop DMA */ 401 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 402 csr |= D_INVALIDATE|D_SLAVE_ERR; 403 L64854_SCSR(sc, csr); 404 return (-1); 405 } 406 407 /* This is an "assertion" :) */ 408 if (sc->sc_active == 0) 409 panic("dmaintr: DMA wasn't active"); 410 411 DMA_DRAIN(sc, 0); 412 413 /* DMA has stopped */ 414 csr &= ~D_EN_DMA; 415 L64854_SCSR(sc, csr); 416 sc->sc_active = 0; 417 418 if (sc->sc_dmasize == 0) { 419 /* A "Transfer Pad" operation completed */ 420 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 421 NCR_READ_REG(nsc, NCR_TCL) | 422 (NCR_READ_REG(nsc, NCR_TCM) << 8), 423 NCR_READ_REG(nsc, NCR_TCL), 424 NCR_READ_REG(nsc, NCR_TCM))); 425 return 0; 426 } 427 428 resid = 0; 429 /* 430 * If a transfer onto the SCSI bus gets interrupted by the device 431 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 432 * as residual since the NCR53C9X counter registers get decremented 433 * as bytes are clocked into the FIFO. 434 */ 435 if (!(csr & D_WRITE) && 436 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 437 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 438 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 439 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 440 resid <<= 1; 441 } 442 443 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 444 /* 445 * `Terminal count' is off, so read the residue 446 * out of the NCR53C9X counter registers. 447 */ 448 resid += (NCR_READ_REG(nsc, NCR_TCL) | 449 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 450 ((nsc->sc_cfg2 & NCRCFG2_FE) 451 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 452 : 0)); 453 454 if (resid == 0 && sc->sc_dmasize == 65536 && 455 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 456 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 457 resid = 65536; 458 } 459 460 trans = sc->sc_dmasize - resid; 461 if (trans < 0) { /* transferred < 0 ? */ 462 #if 0 463 /* 464 * This situation can happen in perfectly normal operation 465 * if the ESP is reselected while using DMA to select 466 * another target. As such, don't print the warning. 467 */ 468 printf("%s: xfer (%d) > req (%d)\n", 469 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 470 #endif 471 trans = sc->sc_dmasize; 472 } 473 474 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 475 NCR_READ_REG(nsc, NCR_TCL), 476 NCR_READ_REG(nsc, NCR_TCM), 477 (nsc->sc_cfg2 & NCRCFG2_FE) 478 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 479 trans, resid)); 480 481 if (sc->sc_dmamap->dm_nsegs > 0) { 482 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 483 (csr & D_WRITE) != 0 484 ? BUS_DMASYNC_POSTREAD 485 : BUS_DMASYNC_POSTWRITE); 486 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 487 } 488 489 *sc->sc_dmalen -= trans; 490 *sc->sc_dmaaddr += trans; 491 492 #if 0 /* this is not normal operation just yet */ 493 if (*sc->sc_dmalen == 0 || 494 nsc->sc_phase != nsc->sc_prevphase) 495 return 0; 496 497 /* and again */ 498 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 499 return 1; 500 #endif 501 return 0; 502 } 503 504 /* 505 * Pseudo (chained) interrupt to le driver to handle DMA errors. 506 */ 507 int 508 lsi64854_enet_intr(arg) 509 void *arg; 510 { 511 struct lsi64854_softc *sc = arg; 512 char bits[64]; 513 u_int32_t csr; 514 static int dodrain = 0; 515 int rv; 516 517 csr = L64854_GCSR(sc); 518 519 /* If the DMA logic shows an interrupt, claim it */ 520 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 521 522 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 523 snprintf(bits, sizeof(bits), "%b", csr, EDMACSR_BITS); 524 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits); 525 csr &= ~L64854_EN_DMA; /* Stop DMA */ 526 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 527 csr |= E_INVALIDATE|E_SLAVE_ERR; 528 L64854_SCSR(sc, csr); 529 DMA_RESET(sc); 530 dodrain = 1; 531 return (1); 532 } 533 534 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 535 int i = 10; 536 csr |= E_DRAIN; 537 L64854_SCSR(sc, csr); 538 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 539 delay(1); 540 } 541 542 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 543 } 544 545 /* 546 * setup a dma transfer 547 */ 548 int 549 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 550 struct lsi64854_softc *sc; 551 caddr_t *addr; 552 size_t *len; 553 int datain; 554 size_t *dmasize; /* IN-OUT */ 555 { 556 u_int32_t csr; 557 558 DMA_FLUSH(sc, 0); 559 560 sc->sc_dmaaddr = addr; 561 sc->sc_dmalen = len; 562 563 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 564 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 565 566 /* 567 * the rules say we cannot transfer more than the limit 568 * of this DMA chip (64k for old and 16Mb for new), 569 * and we cannot cross a 16Mb boundary. 570 */ 571 *dmasize = sc->sc_dmasize = 572 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 573 574 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 575 576 /* Program the DMA address */ 577 if (sc->sc_dmasize) { 578 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 579 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 580 *sc->sc_dmaaddr, sc->sc_dmasize, 581 NULL /* kernel address */, 582 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 583 panic("%s: pp cannot allocate DVMA address", 584 sc->sc_dev.dv_xname); 585 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 586 datain 587 ? BUS_DMASYNC_PREREAD 588 : BUS_DMASYNC_PREWRITE); 589 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 590 sc->sc_dmamap->dm_segs[0].ds_addr); 591 592 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 593 sc->sc_dmasize); 594 } 595 596 /* Setup DMA control register */ 597 csr = L64854_GCSR(sc); 598 csr &= ~L64854_BURST_SIZE; 599 if (sc->sc_burst == 32) { 600 csr |= L64854_BURST_32; 601 } else if (sc->sc_burst == 16) { 602 csr |= L64854_BURST_16; 603 } else { 604 csr |= L64854_BURST_0; 605 } 606 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 607 #if 0 608 /* This bit is read-only in PP csr register */ 609 if (datain) 610 csr |= P_WRITE; 611 else 612 csr &= ~P_WRITE; 613 #endif 614 L64854_SCSR(sc, csr); 615 616 return (0); 617 } 618 /* 619 * Parallel port DMA interrupt. 620 */ 621 int 622 lsi64854_pp_intr(arg) 623 void *arg; 624 { 625 struct lsi64854_softc *sc = arg; 626 int ret, trans, resid = 0; 627 u_int32_t csr; 628 629 csr = L64854_GCSR(sc); 630 631 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname, 632 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 633 csr, PDMACSR_BITS)); 634 635 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 636 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 637 L64854_REG_CNT); 638 printf("%s: pp error: resid %d csr=%b\n", sc->sc_dev.dv_xname, 639 resid, csr, PDMACSR_BITS); 640 csr &= ~P_EN_DMA; /* Stop DMA */ 641 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 642 csr |= P_INVALIDATE|P_SLAVE_ERR; 643 L64854_SCSR(sc, csr); 644 return (1); 645 } 646 647 ret = (csr & P_INT_PEND) != 0; 648 649 if (sc->sc_active != 0) { 650 DMA_DRAIN(sc, 0); 651 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 652 L64854_REG_CNT); 653 } 654 655 /* DMA has stopped */ 656 csr &= ~D_EN_DMA; 657 L64854_SCSR(sc, csr); 658 sc->sc_active = 0; 659 660 trans = sc->sc_dmasize - resid; 661 if (trans < 0) { /* transferred < 0 ? */ 662 trans = sc->sc_dmasize; 663 } 664 *sc->sc_dmalen -= trans; 665 *sc->sc_dmaaddr += trans; 666 667 if (sc->sc_dmamap->dm_nsegs > 0) { 668 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 669 (csr & D_WRITE) != 0 670 ? BUS_DMASYNC_POSTREAD 671 : BUS_DMASYNC_POSTWRITE); 672 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 673 } 674 675 return (ret != 0); 676 } 677