1 /* $OpenBSD: lsi64854.c,v 1.10 2014/07/08 17:19:25 deraadt Exp $ */ 2 /* $NetBSD: lsi64854.c,v 1.18 2001/06/04 20:56:51 mrg Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/errno.h> 38 #include <sys/device.h> 39 40 #include <machine/bus.h> 41 #include <machine/autoconf.h> 42 #include <machine/cpu.h> 43 44 #include <scsi/scsi_all.h> 45 #include <scsi/scsiconf.h> 46 47 #include <dev/ic/lsi64854reg.h> 48 #include <dev/ic/lsi64854var.h> 49 50 #include <dev/ic/ncr53c9xreg.h> 51 #include <dev/ic/ncr53c9xvar.h> 52 53 void lsi64854_reset(struct lsi64854_softc *); 54 int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *, 55 int, size_t *); 56 int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *, 57 int, size_t *); 58 int lsi64854_scsi_intr(void *); 59 int lsi64854_pp_intr(void *); 60 61 #ifdef DEBUG 62 #define LDB_SCSI 1 63 #define LDB_ENET 2 64 #define LDB_PP 4 65 #define LDB_ANY 0xff 66 int lsi64854debug = 0; 67 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 68 #else 69 #define DPRINTF(a,x) 70 #endif 71 72 #define MAX_DMA_SZ (16*1024*1024) 73 74 /* 75 * Finish attaching this DMA device. 76 * Front-end must fill in these fields: 77 * sc_bustag 78 * sc_dmatag 79 * sc_regs 80 * sc_burst 81 * sc_channel (one of SCSI, ENET, PP) 82 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 83 */ 84 int 85 lsi64854_attach(sc) 86 struct lsi64854_softc *sc; 87 { 88 u_int32_t csr; 89 int rc; 90 91 /* Indirect functions */ 92 switch (sc->sc_channel) { 93 case L64854_CHANNEL_SCSI: 94 sc->intr = lsi64854_scsi_intr; 95 sc->setup = lsi64854_setup; 96 break; 97 case L64854_CHANNEL_ENET: 98 sc->intr = lsi64854_enet_intr; 99 sc->setup = lsi64854_setup; 100 break; 101 case L64854_CHANNEL_PP: 102 sc->intr = lsi64854_pp_intr; 103 sc->setup = lsi64854_setup_pp; 104 break; 105 default: 106 printf("%s: unknown channel\n", sc->sc_dev.dv_xname); 107 } 108 sc->reset = lsi64854_reset; 109 110 /* Allocate a dmamap */ 111 if ((rc = bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ, 112 0, BUS_DMA_WAITOK, &sc->sc_dmamap)) != 0) { 113 printf(": dma map create failed\n"); 114 return (rc); 115 } 116 117 printf(": dma rev "); 118 csr = L64854_GCSR(sc); 119 sc->sc_rev = csr & L64854_DEVID; 120 switch (sc->sc_rev) { 121 case DMAREV_0: 122 printf("0"); 123 break; 124 case DMAREV_ESC: 125 printf("esc"); 126 break; 127 case DMAREV_1: 128 printf("1"); 129 break; 130 case DMAREV_PLUS: 131 printf("1+"); 132 break; 133 case DMAREV_2: 134 printf("2"); 135 break; 136 case DMAREV_HME: 137 printf("fas"); 138 break; 139 default: 140 printf("unknown (0x%x)", sc->sc_rev); 141 } 142 143 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 144 printf("\n"); 145 146 return (0); 147 } 148 149 /* 150 * DMAWAIT waits while condition is true 151 */ 152 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 153 int count = 500000; \ 154 while ((COND) && --count > 0) DELAY(1); \ 155 if (count == 0) { \ 156 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 157 (u_long)L64854_GCSR(SC)); \ 158 if (DONTPANIC) \ 159 printf(MSG); \ 160 else \ 161 panic(MSG); \ 162 } \ 163 } while (0) 164 165 #define DMA_DRAIN(sc, dontpanic) do { \ 166 u_int32_t csr; \ 167 /* \ 168 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 169 * and "drain" bits while it is still thinking about a \ 170 * request. \ 171 * other revs: D_ESC_R_PEND bit reads as 0 \ 172 */ \ 173 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 174 if (sc->sc_rev != DMAREV_HME) { \ 175 /* \ 176 * Select drain bit based on revision \ 177 * also clears errors and D_TC flag \ 178 */ \ 179 csr = L64854_GCSR(sc); \ 180 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 181 csr |= D_ESC_DRAIN; \ 182 else \ 183 csr |= L64854_INVALIDATE; \ 184 \ 185 L64854_SCSR(sc,csr); \ 186 } \ 187 /* \ 188 * Wait for draining to finish \ 189 * rev0 & rev1 call this PACKCNT \ 190 */ \ 191 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 192 } while(0) 193 194 #define DMA_FLUSH(sc, dontpanic) do { \ 195 u_int32_t csr; \ 196 /* \ 197 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 198 * and "drain" bits while it is still thinking about a \ 199 * request. \ 200 * other revs: D_ESC_R_PEND bit reads as 0 \ 201 */ \ 202 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 203 csr = L64854_GCSR(sc); \ 204 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 205 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 206 L64854_SCSR(sc,csr); \ 207 } while(0) 208 209 void 210 lsi64854_reset(sc) 211 struct lsi64854_softc *sc; 212 { 213 u_int32_t csr; 214 215 DMA_FLUSH(sc, 1); 216 csr = L64854_GCSR(sc); 217 218 DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); 219 220 /* 221 * XXX is sync needed? 222 */ 223 if (sc->sc_dmamap->dm_nsegs > 0) 224 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 225 226 if (sc->sc_rev == DMAREV_HME) 227 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 228 229 230 csr |= L64854_RESET; /* reset DMA */ 231 L64854_SCSR(sc, csr); 232 DELAY(200); /* > 10 Sbus clocks(?) */ 233 234 /*DMAWAIT1(sc); why was this here? */ 235 csr = L64854_GCSR(sc); 236 csr &= ~L64854_RESET; /* de-assert reset line */ 237 L64854_SCSR(sc, csr); 238 DELAY(5); /* allow a few ticks to settle */ 239 240 csr = L64854_GCSR(sc); 241 csr |= L64854_INT_EN; /* enable interrupts */ 242 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 243 if (sc->sc_rev == DMAREV_HME) 244 csr |= D_TWO_CYCLE; 245 else 246 csr |= D_FASTER; 247 } 248 249 /* Set burst */ 250 switch (sc->sc_rev) { 251 case DMAREV_HME: 252 case DMAREV_2: 253 csr &= ~L64854_BURST_SIZE; 254 if (sc->sc_burst == 32) { 255 csr |= L64854_BURST_32; 256 } else if (sc->sc_burst == 16) { 257 csr |= L64854_BURST_16; 258 } else { 259 csr |= L64854_BURST_0; 260 } 261 break; 262 case DMAREV_ESC: 263 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 264 if (sc->sc_burst == 32) { 265 csr &= ~D_ESC_BURST; 266 } else 267 csr |= D_ESC_BURST; 268 break; 269 default: 270 break; 271 } 272 L64854_SCSR(sc, csr); 273 274 if (sc->sc_rev == DMAREV_HME) { 275 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 0); 276 sc->sc_dmactl = csr; 277 } 278 sc->sc_active = 0; 279 280 DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); 281 } 282 283 284 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 285 /* 286 * setup a dma transfer 287 */ 288 int 289 lsi64854_setup(sc, addr, len, datain, dmasize) 290 struct lsi64854_softc *sc; 291 caddr_t *addr; 292 size_t *len; 293 int datain; 294 size_t *dmasize; /* IN-OUT */ 295 { 296 u_int32_t csr; 297 298 DMA_FLUSH(sc, 0); 299 300 #if 0 301 DMACSR(sc) &= ~D_INT_EN; 302 #endif 303 sc->sc_dmaaddr = addr; 304 sc->sc_dmalen = len; 305 306 /* 307 * the rules say we cannot transfer more than the limit 308 * of this DMA chip (64k for old and 16Mb for new), 309 * and we cannot cross a 16Mb boundary. 310 */ 311 *dmasize = sc->sc_dmasize = 312 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 313 314 DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); 315 316 /* 317 * XXX what length? 318 */ 319 if (sc->sc_rev == DMAREV_HME) { 320 321 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 322 L64854_SCSR(sc, sc->sc_dmactl); 323 324 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, *dmasize); 325 } 326 327 /* Program the DMA address */ 328 if (sc->sc_dmasize) { 329 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 330 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 331 *sc->sc_dmaaddr, sc->sc_dmasize, 332 NULL /* kernel address */, 333 BUS_DMA_NOWAIT | BUS_DMA_STREAMING)) 334 panic("%s: cannot allocate DVMA address", 335 sc->sc_dev.dv_xname); 336 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 337 datain 338 ? BUS_DMASYNC_PREREAD 339 : BUS_DMASYNC_PREWRITE); 340 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 341 sc->sc_dmamap->dm_segs[0].ds_addr); 342 } 343 344 if (sc->sc_rev == DMAREV_ESC) { 345 /* DMA ESC chip bug work-around */ 346 long bcnt = sc->sc_dmasize; 347 long eaddr = bcnt + (long)*sc->sc_dmaaddr; 348 if ((eaddr & PGOFSET) != 0) 349 bcnt = roundup(bcnt, PAGE_SIZE); 350 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 351 bcnt); 352 } 353 354 /* Setup DMA control register */ 355 csr = L64854_GCSR(sc); 356 357 if (datain) 358 csr |= L64854_WRITE; 359 else 360 csr &= ~L64854_WRITE; 361 csr |= L64854_INT_EN; 362 363 if (sc->sc_rev == DMAREV_HME) { 364 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 365 } 366 367 L64854_SCSR(sc, csr); 368 369 return (0); 370 } 371 372 /* 373 * Pseudo (chained) interrupt from the esp driver to kick the 374 * current running DMA transfer. Called from ncr53c9x_intr() 375 * for now. 376 * 377 * return 1 if it was a DMA continue. 378 */ 379 int 380 lsi64854_scsi_intr(arg) 381 void *arg; 382 { 383 struct lsi64854_softc *sc = arg; 384 struct ncr53c9x_softc *nsc = sc->sc_client; 385 char bits[64]; 386 int trans, resid; 387 u_int32_t csr; 388 389 csr = L64854_GCSR(sc); 390 391 DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname, 392 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 393 csr, DDMACSR_BITS)); 394 395 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 396 snprintf(bits, sizeof(bits), "%b", csr, DDMACSR_BITS); 397 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits); 398 csr &= ~D_EN_DMA; /* Stop DMA */ 399 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 400 csr |= D_INVALIDATE|D_SLAVE_ERR; 401 L64854_SCSR(sc, csr); 402 return (-1); 403 } 404 405 /* This is an "assertion" :) */ 406 if (sc->sc_active == 0) 407 panic("dmaintr: DMA wasn't active"); 408 409 DMA_DRAIN(sc, 0); 410 411 /* DMA has stopped */ 412 csr &= ~D_EN_DMA; 413 L64854_SCSR(sc, csr); 414 sc->sc_active = 0; 415 416 if (sc->sc_dmasize == 0) { 417 /* A "Transfer Pad" operation completed */ 418 DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 419 NCR_READ_REG(nsc, NCR_TCL) | 420 (NCR_READ_REG(nsc, NCR_TCM) << 8), 421 NCR_READ_REG(nsc, NCR_TCL), 422 NCR_READ_REG(nsc, NCR_TCM))); 423 return 0; 424 } 425 426 resid = 0; 427 /* 428 * If a transfer onto the SCSI bus gets interrupted by the device 429 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 430 * as residual since the NCR53C9X counter registers get decremented 431 * as bytes are clocked into the FIFO. 432 */ 433 if (!(csr & D_WRITE) && 434 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 435 DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); 436 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 437 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 438 resid <<= 1; 439 } 440 441 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 442 /* 443 * `Terminal count' is off, so read the residue 444 * out of the NCR53C9X counter registers. 445 */ 446 resid += (NCR_READ_REG(nsc, NCR_TCL) | 447 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 448 ((nsc->sc_cfg2 & NCRCFG2_FE) 449 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) 450 : 0)); 451 452 if (resid == 0 && sc->sc_dmasize == 65536 && 453 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 454 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 455 resid = 65536; 456 } 457 458 trans = sc->sc_dmasize - resid; 459 if (trans < 0) { /* transferred < 0 ? */ 460 #if 0 461 /* 462 * This situation can happen in perfectly normal operation 463 * if the ESP is reselected while using DMA to select 464 * another target. As such, don't print the warning. 465 */ 466 printf("%s: xfer (%d) > req (%d)\n", 467 sc->sc_dev.dv_xname, trans, sc->sc_dmasize); 468 #endif 469 trans = sc->sc_dmasize; 470 } 471 472 DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 473 NCR_READ_REG(nsc, NCR_TCL), 474 NCR_READ_REG(nsc, NCR_TCM), 475 (nsc->sc_cfg2 & NCRCFG2_FE) 476 ? NCR_READ_REG(nsc, NCR_TCH) : 0, 477 trans, resid)); 478 479 if (sc->sc_dmamap->dm_nsegs > 0) { 480 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 481 (csr & D_WRITE) != 0 482 ? BUS_DMASYNC_POSTREAD 483 : BUS_DMASYNC_POSTWRITE); 484 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 485 } 486 487 *sc->sc_dmalen -= trans; 488 *sc->sc_dmaaddr += trans; 489 490 #if 0 /* this is not normal operation just yet */ 491 if (*sc->sc_dmalen == 0 || 492 nsc->sc_phase != nsc->sc_prevphase) 493 return 0; 494 495 /* and again */ 496 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 497 return 1; 498 #endif 499 return 0; 500 } 501 502 /* 503 * Pseudo (chained) interrupt to le driver to handle DMA errors. 504 */ 505 int 506 lsi64854_enet_intr(arg) 507 void *arg; 508 { 509 struct lsi64854_softc *sc = arg; 510 char bits[64]; 511 u_int32_t csr; 512 static int dodrain = 0; 513 int rv; 514 515 csr = L64854_GCSR(sc); 516 517 /* If the DMA logic shows an interrupt, claim it */ 518 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 519 520 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 521 snprintf(bits, sizeof(bits), "%b", csr, EDMACSR_BITS); 522 printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname, bits); 523 csr &= ~L64854_EN_DMA; /* Stop DMA */ 524 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 525 csr |= E_INVALIDATE|E_SLAVE_ERR; 526 L64854_SCSR(sc, csr); 527 DMA_RESET(sc); 528 dodrain = 1; 529 return (1); 530 } 531 532 if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ 533 int i = 10; 534 csr |= E_DRAIN; 535 L64854_SCSR(sc, csr); 536 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) 537 delay(1); 538 } 539 540 return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); 541 } 542 543 /* 544 * setup a dma transfer 545 */ 546 int 547 lsi64854_setup_pp(sc, addr, len, datain, dmasize) 548 struct lsi64854_softc *sc; 549 caddr_t *addr; 550 size_t *len; 551 int datain; 552 size_t *dmasize; /* IN-OUT */ 553 { 554 u_int32_t csr; 555 556 DMA_FLUSH(sc, 0); 557 558 sc->sc_dmaaddr = addr; 559 sc->sc_dmalen = len; 560 561 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->sc_dev.dv_xname, 562 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 563 564 /* 565 * the rules say we cannot transfer more than the limit 566 * of this DMA chip (64k for old and 16Mb for new), 567 * and we cannot cross a 16Mb boundary. 568 */ 569 *dmasize = sc->sc_dmasize = 570 min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 571 572 DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); 573 574 /* Program the DMA address */ 575 if (sc->sc_dmasize) { 576 sc->sc_dvmaaddr = *sc->sc_dmaaddr; 577 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, 578 *sc->sc_dmaaddr, sc->sc_dmasize, 579 NULL /* kernel address */, 580 BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/)) 581 panic("%s: pp cannot allocate DVMA address", 582 sc->sc_dev.dv_xname); 583 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 584 datain 585 ? BUS_DMASYNC_PREREAD 586 : BUS_DMASYNC_PREWRITE); 587 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR, 588 sc->sc_dmamap->dm_segs[0].ds_addr); 589 590 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT, 591 sc->sc_dmasize); 592 } 593 594 /* Setup DMA control register */ 595 csr = L64854_GCSR(sc); 596 csr &= ~L64854_BURST_SIZE; 597 if (sc->sc_burst == 32) { 598 csr |= L64854_BURST_32; 599 } else if (sc->sc_burst == 16) { 600 csr |= L64854_BURST_16; 601 } else { 602 csr |= L64854_BURST_0; 603 } 604 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 605 #if 0 606 /* This bit is read-only in PP csr register */ 607 if (datain) 608 csr |= P_WRITE; 609 else 610 csr &= ~P_WRITE; 611 #endif 612 L64854_SCSR(sc, csr); 613 614 return (0); 615 } 616 /* 617 * Parallel port DMA interrupt. 618 */ 619 int 620 lsi64854_pp_intr(arg) 621 void *arg; 622 { 623 struct lsi64854_softc *sc = arg; 624 int ret, trans, resid = 0; 625 u_int32_t csr; 626 627 csr = L64854_GCSR(sc); 628 629 DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->sc_dev.dv_xname, 630 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR), 631 csr, PDMACSR_BITS)); 632 633 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 634 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 635 L64854_REG_CNT); 636 printf("%s: pp error: resid %d csr=%b\n", sc->sc_dev.dv_xname, 637 resid, csr, PDMACSR_BITS); 638 csr &= ~P_EN_DMA; /* Stop DMA */ 639 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 640 csr |= P_INVALIDATE|P_SLAVE_ERR; 641 L64854_SCSR(sc, csr); 642 return (1); 643 } 644 645 ret = (csr & P_INT_PEND) != 0; 646 647 if (sc->sc_active != 0) { 648 DMA_DRAIN(sc, 0); 649 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs, 650 L64854_REG_CNT); 651 } 652 653 /* DMA has stopped */ 654 csr &= ~D_EN_DMA; 655 L64854_SCSR(sc, csr); 656 sc->sc_active = 0; 657 658 trans = sc->sc_dmasize - resid; 659 if (trans < 0) { /* transferred < 0 ? */ 660 trans = sc->sc_dmasize; 661 } 662 *sc->sc_dmalen -= trans; 663 *sc->sc_dmaaddr += trans; 664 665 if (sc->sc_dmamap->dm_nsegs > 0) { 666 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize, 667 (csr & D_WRITE) != 0 668 ? BUS_DMASYNC_POSTREAD 669 : BUS_DMASYNC_POSTWRITE); 670 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap); 671 } 672 673 return (ret != 0); 674 } 675