1 /* $OpenBSD: mfireg.h,v 1.29 2011/04/08 19:23:46 marco Exp $ */ 2 /* 3 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /* management interface constants */ 19 #define MFI_MGMT_VD 0x01 20 #define MFI_MGMT_SD 0x02 21 22 /* generic constants */ 23 #define MFI_FRAME_SIZE 64 24 #define MFI_SENSE_SIZE 128 25 #define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 26 #define MFI_OSTS_PPC_INTR_VALID 0x80000000 27 #define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 28 #define MFI_INVALID_CTX 0xffffffff 29 #define MFI_ENABLE_INTR 0x01 30 #define MFI_MAXFER MAXPHYS /* XXX bogus */ 31 32 /* register offsets */ 33 #define MFI_IMSG0 0x10 /* inbound msg 0 */ 34 #define MFI_IMSG1 0x14 /* inbound msg 1 */ 35 #define MFI_OMSG0 0x18 /* outbound msg 0 */ 36 #define MFI_OMSG1 0x1c /* outbound msg 1 */ 37 #define MFI_IDB 0x20 /* inbound doorbell */ 38 #define MFI_ISTS 0x24 /* inbound intr stat */ 39 #define MFI_IMSK 0x28 /* inbound intr mask */ 40 #define MFI_ODB 0x2c /* outbound doorbell */ 41 #define MFI_OSTS 0x30 /* outbound intr stat */ 42 #define MFI_OMSK 0x34 /* outbound inter mask */ 43 #define MFI_IQP 0x40 /* inbound queue port */ 44 #define MFI_OQP 0x44 /* outbound queue port */ 45 #define MFI_ODC 0xa0 /* outbound doorbell clr */ 46 #define MFI_OSP 0xb0 /* outbound scratch pad */ 47 48 /* * firmware states */ 49 #define MFI_STATE_MASK 0xf0000000 50 #define MFI_STATE_UNDEFINED 0x00000000 51 #define MFI_STATE_BB_INIT 0x10000000 52 #define MFI_STATE_FW_INIT 0x40000000 53 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 54 #define MFI_STATE_FW_INIT_2 0x70000000 55 #define MFI_STATE_DEVICE_SCAN 0x80000000 56 #define MFI_STATE_FLUSH_CACHE 0xa0000000 57 #define MFI_STATE_READY 0xb0000000 58 #define MFI_STATE_OPERATIONAL 0xc0000000 59 #define MFI_STATE_FAULT 0xf0000000 60 #define MFI_STATE_MAXSGL_MASK 0x00ff0000 61 #define MFI_STATE_MAXCMD_MASK 0x0000ffff 62 63 /* command reset register */ 64 #define MFI_INIT_ABORT 0x00000000 65 #define MFI_INIT_READY 0x00000002 66 #define MFI_INIT_MFIMODE 0x00000004 67 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 68 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE 69 70 /* mfi Frame flags */ 71 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 72 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 73 #define MFI_FRAME_SGL32 0x0000 74 #define MFI_FRAME_SGL64 0x0002 75 #define MFI_FRAME_SENSE32 0x0000 76 #define MFI_FRAME_SENSE64 0x0004 77 #define MFI_FRAME_DIR_NONE 0x0000 78 #define MFI_FRAME_DIR_WRITE 0x0008 79 #define MFI_FRAME_DIR_READ 0x0010 80 #define MFI_FRAME_DIR_BOTH 0x0018 81 82 /* mfi command opcodes */ 83 #define MFI_CMD_INIT 0x00 84 #define MFI_CMD_LD_READ 0x01 85 #define MFI_CMD_LD_WRITE 0x02 86 #define MFI_CMD_LD_SCSI_IO 0x03 87 #define MFI_CMD_PD_SCSI_IO 0x04 88 #define MFI_CMD_DCMD 0x05 89 #define MFI_CMD_ABORT 0x06 90 #define MFI_CMD_SMP 0x07 91 #define MFI_CMD_STP 0x08 92 93 /* direct commands */ 94 #define MR_DCMD_CTRL_GET_INFO 0x01010000 95 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 96 #define MR_FLUSH_CTRL_CACHE 0x01 97 #define MR_FLUSH_DISK_CACHE 0x02 98 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 99 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 100 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 101 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 102 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 103 #define MR_DCMD_PD_GET_LIST 0x02010000 104 #define MR_DCMD_PD_GET_INFO 0x02020000 105 #define MD_DCMD_PD_SET_STATE 0x02030100 106 #define MD_DCMD_PD_REBUILD 0x02040100 107 #define MR_DCMD_PD_BLINK 0x02070100 108 #define MR_DCMD_PD_UNBLINK 0x02070200 109 #define MR_DCMD_PD_GET_ALLOWED_OPS_LIST 0x020a0100 110 #define MR_DCMD_LD_GET_LIST 0x03010000 111 #define MR_DCMD_LD_GET_INFO 0x03020000 112 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 113 #define MD_DCMD_CONF_GET 0x04010000 114 #define MR_DCMD_CLUSTER 0x08000000 115 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 116 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 117 118 #define MR_DCMD_SPEAKER_GET 0x01030100 119 #define MR_DCMD_SPEAKER_ENABLE 0x01030200 120 #define MR_DCMD_SPEAKER_DISABLE 0x01030300 121 #define MR_DCMD_SPEAKER_SILENCE 0x01030400 122 #define MR_DCMD_SPEAKER_TEST 0x01030500 123 124 /* mailbox bytes in direct command */ 125 #define MFI_MBOX_SIZE 12 126 127 /* mfi completion codes */ 128 typedef enum { 129 MFI_STAT_OK = 0x00, 130 MFI_STAT_INVALID_CMD = 0x01, 131 MFI_STAT_INVALID_DCMD = 0x02, 132 MFI_STAT_INVALID_PARAMETER = 0x03, 133 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 134 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 135 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 136 MFI_STAT_APP_IN_USE = 0x07, 137 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 138 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 139 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 140 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 141 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 142 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 143 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 144 MFI_STAT_FLASH_BUSY = 0x0f, 145 MFI_STAT_FLASH_ERROR = 0x10, 146 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 147 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 148 MFI_STAT_FLASH_NOT_OPEN = 0x13, 149 MFI_STAT_FLASH_NOT_STARTED = 0x14, 150 MFI_STAT_FLUSH_FAILED = 0x15, 151 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 152 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 153 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 154 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 155 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 156 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 157 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 158 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 159 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 160 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 161 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 162 MFI_STAT_MFC_HW_ERROR = 0x21, 163 MFI_STAT_NO_HW_PRESENT = 0x22, 164 MFI_STAT_NOT_FOUND = 0x23, 165 MFI_STAT_NOT_IN_ENCL = 0x24, 166 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 167 MFI_STAT_PD_TYPE_WRONG = 0x26, 168 MFI_STAT_PR_DISABLED = 0x27, 169 MFI_STAT_ROW_INDEX_INVALID = 0x28, 170 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 171 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 172 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 173 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 174 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 175 MFI_STAT_SCSI_IO_FAILED = 0x2e, 176 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 177 MFI_STAT_SHUTDOWN_FAILED = 0x30, 178 MFI_STAT_TIME_NOT_SET = 0x31, 179 MFI_STAT_WRONG_STATE = 0x32, 180 MFI_STAT_LD_OFFLINE = 0x33, 181 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 182 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 183 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 184 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 185 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 186 MFI_STAT_INVALID_STATUS = 0xff 187 } mfi_status_t; 188 189 typedef enum { 190 MFI_EVT_CLASS_DEBUG = -2, 191 MFI_EVT_CLASS_PROGRESS = -1, 192 MFI_EVT_CLASS_INFO = 0, 193 MFI_EVT_CLASS_WARNING = 1, 194 MFI_EVT_CLASS_CRITICAL = 2, 195 MFI_EVT_CLASS_FATAL = 3, 196 MFI_EVT_CLASS_DEAD = 4 197 } mfi_evt_class_t; 198 199 typedef enum { 200 MFI_EVT_LOCALE_LD = 0x0001, 201 MFI_EVT_LOCALE_PD = 0x0002, 202 MFI_EVT_LOCALE_ENCL = 0x0004, 203 MFI_EVT_LOCALE_BBU = 0x0008, 204 MFI_EVT_LOCALE_SAS = 0x0010, 205 MFI_EVT_LOCALE_CTRL = 0x0020, 206 MFI_EVT_LOCALE_CONFIG = 0x0040, 207 MFI_EVT_LOCALE_CLUSTER = 0x0080, 208 MFI_EVT_LOCALE_ALL = 0xffff 209 } mfi_evt_locale_t; 210 211 typedef enum { 212 MR_EVT_ARGS_NONE = 0x00, 213 MR_EVT_ARGS_CDB_SENSE, 214 MR_EVT_ARGS_LD, 215 MR_EVT_ARGS_LD_COUNT, 216 MR_EVT_ARGS_LD_LBA, 217 MR_EVT_ARGS_LD_OWNER, 218 MR_EVT_ARGS_LD_LBA_PD_LBA, 219 MR_EVT_ARGS_LD_PROG, 220 MR_EVT_ARGS_LD_STATE, 221 MR_EVT_ARGS_LD_STRIP, 222 MR_EVT_ARGS_PD, 223 MR_EVT_ARGS_PD_ERR, 224 MR_EVT_ARGS_PD_LBA, 225 MR_EVT_ARGS_PD_LBA_LD, 226 MR_EVT_ARGS_PD_PROG, 227 MR_EVT_ARGS_PD_STATE, 228 MR_EVT_ARGS_PCI, 229 MR_EVT_ARGS_RATE, 230 MR_EVT_ARGS_STR, 231 MR_EVT_ARGS_TIME, 232 MR_EVT_ARGS_ECC 233 } mfi_evt_args; 234 235 /* driver definitions */ 236 #define MFI_MAX_PD_CHANNELS 2 237 #define MFI_MAX_PD_ARRAY 32 238 #define MFI_MAX_LD_CHANNELS 2 239 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 240 #define MFI_MAX_CHANNEL_DEVS 128 241 #define MFI_DEFAULT_ID -1 242 #define MFI_MAX_LUN 8 243 #define MFI_MAX_LD 64 244 #define MFI_MAX_SPAN 8 245 #define MFI_MAX_ARRAY_DEDICATED 16 246 #define MFI_MAX_PHYSDISK 256 247 248 /* sense buffer */ 249 struct mfi_sense { 250 uint8_t mse_data[MFI_SENSE_SIZE]; 251 } __packed; 252 253 /* scatter gather elements */ 254 struct mfi_sg32 { 255 uint32_t addr; 256 uint32_t len; 257 } __packed; 258 259 struct mfi_sg64 { 260 uint64_t addr; 261 uint32_t len; 262 } __packed; 263 264 union mfi_sgl { 265 struct mfi_sg32 sg32[1]; 266 struct mfi_sg64 sg64[1]; 267 } __packed; 268 269 /* message frame */ 270 struct mfi_frame_header { 271 uint8_t mfh_cmd; 272 uint8_t mfh_sense_len; 273 uint8_t mfh_cmd_status; 274 uint8_t mfh_scsi_status; 275 uint8_t mfh_target_id; 276 uint8_t mfh_lun_id; 277 uint8_t mfh_cdb_len; 278 uint8_t mfh_sg_count; 279 uint32_t mfh_context; 280 uint32_t mfh_pad0; 281 uint16_t mfh_flags; 282 uint16_t mfh_timeout; 283 uint32_t mfh_data_len; 284 } __packed; 285 286 union mfi_sgl_frame { 287 struct mfi_sg32 sge32[8]; 288 struct mfi_sg64 sge64[5]; 289 290 } __packed; 291 292 struct mfi_init_frame { 293 struct mfi_frame_header mif_header; 294 uint32_t mif_qinfo_new_addr_lo; 295 uint32_t mif_qinfo_new_addr_hi; 296 uint32_t mif_qinfo_old_addr_lo; 297 uint32_t mif_qinfo_old_addr_hi; 298 uint32_t mif_reserved[6]; 299 } __packed; 300 301 /* queue init structure */ 302 struct mfi_init_qinfo { 303 uint32_t miq_flags; 304 uint32_t miq_rq_entries; 305 uint32_t miq_rq_addr_lo; 306 uint32_t miq_rq_addr_hi; 307 uint32_t miq_pi_addr_lo; 308 uint32_t miq_pi_addr_hi; 309 uint32_t miq_ci_addr_lo; 310 uint32_t miq_ci_addr_hi; 311 } __packed; 312 313 #define MFI_IO_FRAME_SIZE 40 314 struct mfi_io_frame { 315 struct mfi_frame_header mif_header; 316 uint32_t mif_sense_addr_lo; 317 uint32_t mif_sense_addr_hi; 318 uint32_t mif_lba_lo; 319 uint32_t mif_lba_hi; 320 union mfi_sgl mif_sgl; 321 } __packed; 322 323 #define MFI_PASS_FRAME_SIZE 48 324 struct mfi_pass_frame { 325 struct mfi_frame_header mpf_header; 326 uint32_t mpf_sense_addr_lo; 327 uint32_t mpf_sense_addr_hi; 328 uint8_t mpf_cdb[16]; 329 union mfi_sgl mpf_sgl; 330 } __packed; 331 332 #define MFI_DCMD_FRAME_SIZE 40 333 struct mfi_dcmd_frame { 334 struct mfi_frame_header mdf_header; 335 uint32_t mdf_opcode; 336 uint8_t mdf_mbox[MFI_MBOX_SIZE]; 337 union mfi_sgl mdf_sgl; 338 } __packed; 339 340 struct mfi_abort_frame { 341 struct mfi_frame_header maf_header; 342 uint32_t maf_abort_context; 343 uint32_t maf_pad; 344 uint32_t maf_abort_mfi_addr_lo; 345 uint32_t maf_abort_mfi_addr_hi; 346 uint32_t maf_reserved[6]; 347 } __packed; 348 349 struct mfi_smp_frame { 350 struct mfi_frame_header msf_header; 351 uint64_t msf_sas_addr; 352 union { 353 struct mfi_sg32 sg32[2]; 354 struct mfi_sg64 sg64[2]; 355 } msf_sgl; 356 } __packed; 357 358 struct mfi_stp_frame { 359 struct mfi_frame_header msf_header; 360 uint16_t msf_fis[10]; 361 uint32_t msf_stp_flags; 362 union { 363 struct mfi_sg32 sg32[2]; 364 struct mfi_sg64 sg64[2]; 365 } msf_sgl; 366 } __packed; 367 368 union mfi_frame { 369 struct mfi_frame_header mfr_header; 370 struct mfi_init_frame mfr_init; 371 struct mfi_io_frame mfr_io; 372 struct mfi_pass_frame mfr_pass; 373 struct mfi_dcmd_frame mfr_dcmd; 374 struct mfi_abort_frame mfr_abort; 375 struct mfi_smp_frame mfr_smp; 376 struct mfi_stp_frame mfr_stp; 377 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 378 }; 379 380 union mfi_evt_class_locale { 381 struct { 382 uint16_t locale; 383 uint8_t reserved; 384 int8_t class; 385 } __packed mec_members; 386 387 uint32_t mec_word; 388 } __packed; 389 390 struct mfi_evt_log_info { 391 uint32_t mel_newest_seq_num; 392 uint32_t mel_oldest_seq_num; 393 uint32_t mel_clear_seq_num; 394 uint32_t mel_shutdown_seq_num; 395 uint32_t mel_boot_seq_num; 396 } __packed; 397 398 struct mfi_progress { 399 uint16_t mp_progress; 400 uint16_t mp_elapsed_seconds; 401 } __packed; 402 403 struct mfi_evtarg_ld { 404 uint16_t mel_target_id; 405 uint8_t mel_ld_index; 406 uint8_t mel_reserved; 407 } __packed; 408 409 struct mfi_evtarg_pd { 410 uint16_t mep_device_id; 411 uint8_t mep_encl_index; 412 uint8_t mep_slot_number; 413 } __packed; 414 415 struct mfi_evt_detail { 416 uint32_t med_seq_num; 417 uint32_t med_time_stamp; 418 uint32_t med_code; 419 union mfi_evt_class_locale med_cl; 420 uint8_t med_arg_type; 421 uint8_t med_reserved1[15]; 422 423 union { 424 struct { 425 struct mfi_evtarg_pd pd; 426 uint8_t cdb_length; 427 uint8_t sense_length; 428 uint8_t reserved[2]; 429 uint8_t cdb[16]; 430 uint8_t sense[64]; 431 } __packed cdb_sense; 432 433 struct mfi_evtarg_ld ld; 434 435 struct { 436 struct mfi_evtarg_ld ld; 437 uint64_t count; 438 } __packed ld_count; 439 440 struct { 441 uint64_t lba; 442 struct mfi_evtarg_ld ld; 443 } __packed ld_lba; 444 445 struct { 446 struct mfi_evtarg_ld ld; 447 uint32_t prev_owner; 448 uint32_t new_owner; 449 } __packed ld_owner; 450 451 struct { 452 uint64_t ld_lba; 453 uint64_t pd_lba; 454 struct mfi_evtarg_ld ld; 455 struct mfi_evtarg_pd pd; 456 } __packed ld_lba_pd_lba; 457 458 struct { 459 struct mfi_evtarg_ld ld; 460 struct mfi_progress prog; 461 } __packed ld_prog; 462 463 struct { 464 struct mfi_evtarg_ld ld; 465 uint32_t prev_state; 466 uint32_t new_state; 467 } __packed ld_state; 468 469 struct { 470 uint64_t strip; 471 struct mfi_evtarg_ld ld; 472 } __packed ld_strip; 473 474 struct mfi_evtarg_pd pd; 475 476 struct { 477 struct mfi_evtarg_pd pd; 478 uint32_t err; 479 } __packed pd_err; 480 481 struct { 482 uint64_t lba; 483 struct mfi_evtarg_pd pd; 484 } __packed pd_lba; 485 486 struct { 487 uint64_t lba; 488 struct mfi_evtarg_pd pd; 489 struct mfi_evtarg_ld ld; 490 } __packed pd_lba_ld; 491 492 struct { 493 struct mfi_evtarg_pd pd; 494 struct mfi_progress prog; 495 } __packed pd_prog; 496 497 struct { 498 struct mfi_evtarg_pd pd; 499 uint32_t prev_state; 500 uint32_t new_state; 501 } __packed pd_state; 502 503 struct { 504 uint16_t vendor_id; 505 uint16_t device_id; 506 uint16_t subvendor_id; 507 uint16_t subdevice_id; 508 } __packed pci; 509 510 uint32_t rate; 511 char str[96]; 512 513 struct { 514 uint32_t rtc; 515 uint32_t elapsed_seconds; 516 } __packed time; 517 518 struct { 519 uint32_t ecar; 520 uint32_t elog; 521 char str[64]; 522 } __packed ecc; 523 524 uint8_t b[96]; 525 uint16_t s[48]; 526 uint32_t w[24]; 527 uint64_t d[12]; 528 } args; 529 530 char med_description[128]; 531 } __packed; 532 533 /* controller properties from mfi_ctrl_info */ 534 struct mfi_ctrl_props { 535 uint16_t mcp_seq_num; 536 uint16_t mcp_pred_fail_poll_interval; 537 uint16_t mcp_intr_throttle_cnt; 538 uint16_t mcp_intr_throttle_timeout; 539 uint8_t mcp_rebuild_rate; 540 uint8_t mcp_patrol_read_rate; 541 uint8_t mcp_bgi_rate; 542 uint8_t mcp_cc_rate; 543 uint8_t mcp_recon_rate; 544 uint8_t mcp_cache_flush_interval; 545 uint8_t mcp_spinup_drv_cnt; 546 uint8_t mcp_spinup_delay; 547 uint8_t mcp_cluster_enable; 548 uint8_t mcp_coercion_mode; 549 uint8_t mcp_alarm_enable; 550 uint8_t mcp_disable_auto_rebuild; 551 uint8_t mcp_disable_battery_warn; 552 uint8_t mcp_ecc_bucket_size; 553 uint16_t mcp_ecc_bucket_leak_rate; 554 uint8_t mcp_restore_hotspare_on_insertion; 555 uint8_t mcp_expose_encl_devices; 556 uint8_t mcp_reserved[38]; 557 } __packed; 558 559 /* pci info */ 560 struct mfi_info_pci { 561 uint16_t mip_vendor; 562 uint16_t mip_device; 563 uint16_t mip_subvendor; 564 uint16_t mip_subdevice; 565 uint8_t mip_reserved[24]; 566 } __packed; 567 568 /* host interface infor */ 569 struct mfi_info_host { 570 uint8_t mih_type; 571 #define MFI_INFO_HOST_PCIX 0x01 572 #define MFI_INFO_HOST_PCIE 0x02 573 #define MFI_INFO_HOST_ISCSI 0x04 574 #define MFI_INFO_HOST_SAS3G 0x08 575 uint8_t mih_reserved[6]; 576 uint8_t mih_port_count; 577 uint64_t mih_port_addr[8]; 578 } __packed; 579 580 /* device interface info */ 581 struct mfi_info_device { 582 uint8_t mid_type; 583 #define MFI_INFO_DEV_SPI 0x01 584 #define MFI_INFO_DEV_SAS3G 0x02 585 #define MFI_INFO_DEV_SATA1 0x04 586 #define MFI_INFO_DEV_SATA3G 0x08 587 uint8_t mid_reserved[6]; 588 uint8_t mid_port_count; 589 uint64_t mid_port_addr[8]; 590 } __packed; 591 592 /* firmware component info */ 593 struct mfi_info_component { 594 char mic_name[8]; 595 char mic_version[32]; 596 char mic_build_date[16]; 597 char mic_build_time[16]; 598 } __packed; 599 600 /* controller info from MFI_DCMD_CTRL_GETINFO. */ 601 struct mfi_ctrl_info { 602 struct mfi_info_pci mci_pci; 603 struct mfi_info_host mci_host; 604 struct mfi_info_device mci_device; 605 606 /* Firmware components that are present and active. */ 607 uint32_t mci_image_check_word; 608 uint32_t mci_image_component_count; 609 struct mfi_info_component mci_image_component[8]; 610 611 /* Firmware components that have been flashed but are inactive */ 612 uint32_t mci_pending_image_component_count; 613 struct mfi_info_component mci_pending_image_component[8]; 614 615 uint8_t mci_max_arms; 616 uint8_t mci_max_spans; 617 uint8_t mci_max_arrays; 618 uint8_t mci_max_lds; 619 char mci_product_name[80]; 620 char mci_serial_number[32]; 621 uint32_t mci_hw_present; 622 #define MFI_INFO_HW_BBU 0x01 623 #define MFI_INFO_HW_ALARM 0x02 624 #define MFI_INFO_HW_NVRAM 0x04 625 #define MFI_INFO_HW_UART 0x08 626 uint32_t mci_current_fw_time; 627 uint16_t mci_max_cmds; 628 uint16_t mci_max_sg_elements; 629 uint32_t mci_max_request_size; 630 uint16_t mci_lds_present; 631 uint16_t mci_lds_degraded; 632 uint16_t mci_lds_offline; 633 uint16_t mci_pd_present; 634 uint16_t mci_pd_disks_present; 635 uint16_t mci_pd_disks_pred_failure; 636 uint16_t mci_pd_disks_failed; 637 uint16_t mci_nvram_size; 638 uint16_t mci_memory_size; 639 uint16_t mci_flash_size; 640 uint16_t mci_ram_correctable_errors; 641 uint16_t mci_ram_uncorrectable_errors; 642 uint8_t mci_cluster_allowed; 643 uint8_t mci_cluster_active; 644 uint16_t mci_max_strips_per_io; 645 646 uint32_t mci_raid_levels; 647 #define MFI_INFO_RAID_0 0x01 648 #define MFI_INFO_RAID_1 0x02 649 #define MFI_INFO_RAID_5 0x04 650 #define MFI_INFO_RAID_1E 0x08 651 #define MFI_INFO_RAID_6 0x10 652 653 uint32_t mci_adapter_ops; 654 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 655 #define MFI_INFO_AOPS_CC_RATE 0x0002 656 #define MFI_INFO_AOPS_BGI_RATE 0x0004 657 #define MFI_INFO_AOPS_RECON_RATE 0x0008 658 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 659 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 660 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 661 #define MFI_INFO_AOPS_BBU 0x0080 662 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 663 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 664 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 665 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 666 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 667 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 668 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 669 670 uint32_t mci_ld_ops; 671 #define MFI_INFO_LDOPS_READ_POLICY 0x01 672 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 673 #define MFI_INFO_LDOPS_IO_POLICY 0x04 674 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 675 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 676 677 struct { 678 uint8_t min; 679 uint8_t max; 680 uint8_t reserved[2]; 681 } __packed mci_stripe_sz_ops; 682 683 uint32_t mci_pd_ops; 684 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 685 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 686 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 687 688 uint32_t mci_pd_mix_support; 689 #define MFI_INFO_PDMIX_SAS 0x01 690 #define MFI_INFO_PDMIX_SATA 0x02 691 #define MFI_INFO_PDMIX_ENCL 0x04 692 #define MFI_INFO_PDMIX_LD 0x08 693 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 694 695 uint8_t mci_ecc_bucket_count; 696 uint8_t mci_reserved2[11]; 697 struct mfi_ctrl_props mci_properties; 698 char mci_package_version[0x60]; 699 uint8_t mci_pad[0x800 - 0x6a0]; 700 } __packed; 701 702 /* logical disk info from MR_DCMD_LD_GET_LIST */ 703 struct mfi_ld { 704 uint8_t mld_target; 705 uint8_t mld_res; 706 uint16_t mld_seq; 707 } __packed; 708 709 struct mfi_ld_list { 710 uint32_t mll_no_ld; 711 uint32_t mll_res; 712 struct { 713 struct mfi_ld mll_ld; 714 uint8_t mll_state; 715 #define MFI_LD_OFFLINE 0x00 716 #define MFI_LD_PART_DEGRADED 0x01 717 #define MFI_LD_DEGRADED 0x02 718 #define MFI_LD_ONLINE 0x03 719 uint8_t mll_res2; 720 uint8_t mll_res3; 721 uint8_t mll_res4; 722 u_quad_t mll_size; 723 } mll_list[MFI_MAX_LD]; 724 } __packed; 725 726 /* logicl disk details from MR_DCMD_LD_GET_INFO */ 727 struct mfi_ld_prop { 728 struct mfi_ld mlp_ld; 729 char mlp_name[16]; 730 uint8_t mlp_cache_policy; 731 uint8_t mlp_acces_policy; 732 uint8_t mlp_diskcache_policy; 733 uint8_t mlp_cur_cache_policy; 734 uint8_t mlp_disable_bgi; 735 uint8_t mlp_res[7]; 736 } __packed; 737 738 struct mfi_ld_parm { 739 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 740 #define MFI_DDF_PRL_RAID0 0x00 741 #define MFI_DDF_PRL_RAID1 0x01 742 #define MFI_DDF_PRL_RAID3 0x03 743 #define MFI_DDF_PRL_RAID4 0x04 744 #define MFI_DDF_PRL_RAID5 0x05 745 #define MFI_DDF_PRL_RAID1E 0x11 746 #define MFI_DDF_PRL_JBOD 0x0f 747 #define MFI_DDF_PRL_CONCAT 0x1f 748 #define MFI_DDF_PRL_RAID5E 0x15 749 #define MFI_DDF_PRL_RAID5EE 0x25 750 #define MFI_DDF_PRL_RAID6 0x16 751 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 752 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 753 #define MFI_DDF_SRL_STRIPED 0x00 754 #define MFI_DDF_SRL_MIRRORED 0x01 755 #define MFI_DDF_SRL_CONCAT 0x02 756 #define MFI_DDF_SRL_SPANNED 0x03 757 uint8_t mpa_stripe_size; 758 uint8_t mpa_no_drv_per_span; 759 uint8_t mpa_span_depth; 760 uint8_t mpa_state; 761 uint8_t mpa_init_state; 762 uint8_t mpa_res[24]; 763 } __packed; 764 765 struct mfi_ld_span { 766 u_quad_t mls_start_block; 767 u_quad_t mls_no_blocks; 768 uint16_t mls_index; 769 uint8_t mls_res[6]; 770 } __packed; 771 772 struct mfi_ld_cfg { 773 struct mfi_ld_prop mlc_prop; 774 struct mfi_ld_parm mlc_parm; 775 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 776 } __packed; 777 778 struct mfi_ld_progress { 779 uint32_t mlp_in_prog; 780 #define MFI_LD_PROG_CC 0x01 781 #define MFI_LD_PROG_BGI 0x02 782 #define MFI_LD_PROG_FGI 0x04 783 #define MFI_LD_PROG_RECONSTRUCT 0x08 784 struct mfi_progress mlp_cc; 785 struct mfi_progress mlp_bgi; 786 struct mfi_progress mlp_fgi; 787 struct mfi_progress mlp_reconstruct; 788 struct mfi_progress mlp_res[4]; 789 } __packed; 790 791 struct mfi_ld_details { 792 struct mfi_ld_cfg mld_cfg; 793 u_quad_t mld_size; 794 struct mfi_ld_progress mld_progress; 795 uint16_t mld_clust_own_id; 796 uint8_t mld_res1; 797 uint8_t mld_res2; 798 uint8_t mld_inq_page83[64]; 799 uint8_t mld_res[16]; 800 } __packed; 801 802 /* physical disk info from MR_DCMD_PD_GET_LIST */ 803 struct mfi_pd_address { 804 uint16_t mpa_pd_id; 805 uint16_t mpa_enc_id; 806 uint8_t mpa_enc_index; 807 uint8_t mpa_enc_slot; 808 uint8_t mpa_scsi_type; 809 uint8_t mpa_port; 810 u_quad_t mpa_sas_address[2]; 811 } __packed; 812 813 struct mfi_pd_list { 814 uint32_t mpl_size; 815 uint32_t mpl_no_pd; 816 struct mfi_pd_address mpl_address[1]; 817 } __packed; 818 #define MFI_PD_LIST_SIZE (MFI_MAX_PHYSDISK * sizeof(struct mfi_pd_address) + 8) 819 820 struct mfi_pd { 821 uint16_t mfp_id; 822 uint16_t mfp_seq; 823 } __packed; 824 825 struct mfi_pd_progress { 826 uint32_t mfp_in_prog; 827 #define MFI_PD_PROG_RBLD 0x01 828 #define MFI_PD_PROG_PR 0x02 829 #define MFI_PD_PROG_CLEAR 0x04 830 struct mfi_progress mfp_rebuild; 831 struct mfi_progress mfp_patrol_read; 832 struct mfi_progress mfp_clear; 833 struct mfi_progress mfp_res[4]; 834 } __packed; 835 836 struct mfi_pd_details { 837 struct mfi_pd mpd_pd; 838 uint8_t mpd_inq_data[96]; 839 uint8_t mpd_inq_page83[64]; 840 uint8_t mpd_no_support; 841 uint8_t mpd_scsi_type; 842 uint8_t mpd_port; 843 uint8_t mpd_speed; 844 uint32_t mpd_mediaerr_cnt; 845 uint32_t mpd_othererr_cnt; 846 uint32_t mpd_predfail_cnt; 847 uint32_t mpd_last_pred_event; 848 uint16_t mpd_fw_state; 849 uint8_t mpd_rdy_for_remove; 850 uint8_t mpd_link_speed; 851 uint32_t mpd_ddf_state; 852 #define MFI_DDF_GUID_FORCED 0x01 853 #define MFI_DDF_PART_OF_VD 0x02 854 #define MFI_DDF_GLOB_HOTSPARE 0x04 855 #define MFI_DDF_HOTSPARE 0x08 856 #define MFI_DDF_FOREIGN 0x10 857 #define MFI_DDF_TYPE_MASK 0xf000 858 #define MFI_DDF_TYPE_UNKNOWN 0x0000 859 #define MFI_DDF_TYPE_PAR_SCSI 0x1000 860 #define MFI_DDF_TYPE_SAS 0x2000 861 #define MFI_DDF_TYPE_SATA 0x3000 862 #define MFI_DDF_TYPE_FC 0x4000 863 struct { 864 uint8_t mpp_cnt; 865 uint8_t mpp_severed; 866 uint8_t mpp_connector_idx[2]; 867 uint8_t mpp_res[4]; 868 u_quad_t mpp_sas_addr[2]; 869 uint8_t mpp_res2[16]; 870 } __packed mpd_path; 871 u_quad_t mpd_size; 872 u_quad_t mpd_no_coerce_size; 873 u_quad_t mpd_coerce_size; 874 uint16_t mpd_enc_id; 875 uint8_t mpd_enc_idx; 876 uint8_t mpd_enc_slot; 877 struct mfi_pd_progress mpd_progress; 878 uint8_t mpd_bblock_full; 879 uint8_t mpd_unusable; 880 uint8_t mpd_inq_page83_ext[64]; 881 uint8_t mpd_power_state; /* XXX */ 882 uint8_t mpd_enc_pos; 883 uint32_t mpd_allowed_ops; 884 #define MFI_PD_A_ONLINE (1<<0) 885 #define MFI_PD_A_OFFLINE (1<<1) 886 #define MFI_PD_A_FAILED (1<<2) 887 #define MFI_PD_A_BAD (1<<3) 888 #define MFI_PD_A_UNCONFIG (1<<4) 889 #define MFI_PD_A_HOTSPARE (1<<5) 890 #define MFI_PD_A_REMOVEHOTSPARE (1<<6) 891 #define MFI_PD_A_REPLACEMISSING (1<<7) 892 #define MFI_PD_A_MARKMISSING (1<<8) 893 #define MFI_PD_A_STARTREBUILD (1<<9) 894 #define MFI_PD_A_STOPREBUILD (1<<10) 895 #define MFI_PD_A_BLINK (1<<11) 896 #define MFI_PD_A_CLEAR (1<<12) 897 #define MFI_PD_A_FOREIGNIMPORNOTALLOWED (1<<13) 898 #define MFI_PD_A_STARTCOPYBACK (1<<14) 899 #define MFI_PD_A_STOPCOPYBACK (1<<15) 900 #define MFI_PD_A_FWDOWNLOADDNOTALLOWED (1<<16) 901 #define MFI_PD_A_REPROVISION (1<<17) 902 uint16_t mpd_copyback_partner_id; 903 uint16_t mpd_enc_partner_devid; 904 uint16_t mpd_security; 905 #define MFI_PD_FDE_CAPABLE (1<<0) 906 #define MFI_PD_FDE_ENABLED (1<<1) 907 #define MFI_PD_FDE_SECURED (1<<2) 908 #define MFI_PD_FDE_LOCKED (1<<3) 909 #define MFI_PD_FDE_FOREIGNLOCK (1<<4) 910 uint8_t mpd_media; 911 uint8_t mpd_res[141]; /* size is 512 */ 912 } __packed; 913 914 struct mfi_pd_allowedops_list { 915 uint32_t mpo_no_entries; 916 uint32_t mpo_res; 917 uint32_t mpo_allowedops_list[MFI_MAX_PHYSDISK]; 918 } __packed; 919 920 /* array configuration from MD_DCMD_CONF_GET */ 921 struct mfi_array { 922 u_quad_t mar_smallest_pd; 923 uint8_t mar_no_disk; 924 uint8_t mar_res1; 925 uint16_t mar_array_ref; 926 uint8_t mar_res2[20]; 927 struct { 928 struct mfi_pd mar_pd; 929 uint16_t mar_pd_state; 930 #define MFI_PD_UNCONFIG_GOOD 0x00 931 #define MFI_PD_UNCONFIG_BAD 0x01 932 #define MFI_PD_HOTSPARE 0x02 933 #define MFI_PD_OFFLINE 0x10 934 #define MFI_PD_FAILED 0x11 935 #define MFI_PD_REBUILD 0x14 936 #define MFI_PD_ONLINE 0x18 937 uint8_t mar_enc_pd; 938 uint8_t mar_enc_slot; 939 } pd[MFI_MAX_PD_ARRAY]; 940 } __packed; 941 942 struct mfi_hotspare { 943 struct mfi_pd mhs_pd; 944 uint8_t mhs_type; 945 #define MFI_PD_HS_DEDICATED 0x01 946 #define MFI_PD_HS_REVERTIBLE 0x02 947 #define MFI_PD_HS_ENC_AFFINITY 0x04 948 uint8_t mhs_res[2]; 949 uint8_t mhs_array_max; 950 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 951 } __packed; 952 953 struct mfi_conf { 954 uint32_t mfc_size; 955 uint16_t mfc_no_array; 956 uint16_t mfc_array_size; 957 uint16_t mfc_no_ld; 958 uint16_t mfc_ld_size; 959 uint16_t mfc_no_hs; 960 uint16_t mfc_hs_size; 961 uint8_t mfc_res[16]; 962 /* 963 * XXX this is a ridiculous hack and does not reflect reality 964 * Structures are actually indexed and therefore need pointer 965 * math to reach. We need the size of this structure first so 966 * call it with the size of this structure and then use the returned 967 * values to allocate memory and do the transfer of the whole structure 968 * then calculate pointers to each of these structures. 969 */ 970 struct mfi_array mfc_array[1]; 971 struct mfi_ld_cfg mfc_ld[1]; 972 struct mfi_hotspare mfc_hs[1]; 973 } __packed; 974