1 /* $OpenBSD: nvmereg.h,v 1.4 2014/04/16 00:26:59 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define NVME_CAP 0x0000 /* Controller Capabilities */ 20 #define NVME_CAP_MPSMAX(_r) (12 + (((_r) >> 52) & 0xf)) /* shift */ 21 #define NVME_CAP_MPSMIN(_r) (12 + (((_r) >> 48) & 0xf)) /* shift */ 22 #define NVME_CAP_CSS(_r) (((_r) >> 37) & 0x7f) 23 #define NVME_CAP_CSS_NVM (1 << 0) 24 #define NVME_CAP_NSSRS(_r) ISSET((_r), (1ULL << 36)) 25 #define NVME_CAP_DSTRD(_r) (1 << (2 + (((_r) >> 32) & 0xf))) /* bytes */ 26 #define NVME_CAP_TO(_r) (500 * (((_r) >> 24) & 0xff)) /* ms */ 27 #define NVME_CAP_AMS(_r) (((_r) >> 17) & 0x3) 28 #define NVME_CAP_AMS_WRR (1 << 0) 29 #define NVME_CAP_AMS_VENDOR (1 << 1) 30 #define NVME_CAP_CQR(_r) ISSET((_r), (1 << 16)) 31 #define NVME_CAP_MQES(_r) ((_r) & 0xffff) 32 #define NVME_CAP_LO 0x0000 33 #define NVME_CAP_HI 0x0004 34 #define NVME_VS 0x0008 /* Version */ 35 #define NVME_VS_MJR(_r) (((_r) >> 16) & 0xffff) 36 #define NVME_VS_MNR(_r) ((_r) & 0xffff) 37 #define NVME_INTMS 0x000c /* Interrupt Mask Set */ 38 #define NVME_INTMC 0x0010 /* Interrupt Mask Clear */ 39 #define NVME_CC 0x0014 /* Controller Configuration */ 40 #define NVME_CC_IOCQES(_v) (((_v) & 0xf) << 20) 41 #define NVME_CC_IOCQES_MASK NVME_CC_IOCQES(0xf) 42 #define NVME_CC_IOCQES_R(_v) (((_v) >> 20) & 0xf) 43 #define NVME_CC_IOSQES(_v) (((_v) & 0xf) << 16) 44 #define NVME_CC_IOSQES_MASK NVME_CC_IOSQES(0xf) 45 #define NVME_CC_IOSQES_R(_v) (((_v) >> 16) & 0xf) 46 #define NVME_CC_SHN(_v) (((_v) & 0x3) << 14) 47 #define NVME_CC_SHN_MASK NVME_CC_SHN(0x3) 48 #define NVME_CC_SHN_R(_v) (((_v) >> 15) & 0x3) 49 #define NVME_CC_SHN_NONE 0 50 #define NVME_CC_SHN_NORMAL 1 51 #define NVME_CC_SHN_ABRUPT 2 52 #define NVME_CC_AMS(_v) (((_v) & 0x7) << 11) 53 #define NVME_CC_AMS_MASK NVME_CC_AMS(0x7) 54 #define NVME_CC_AMS_R(_v) (((_v) >> 11) & 0xf) 55 #define NVME_CC_AMS_RR 0 /* round-robin */ 56 #define NVME_CC_AMS_WRR_U 1 /* weighted round-robin w/ urgent */ 57 #define NVME_CC_AMS_VENDOR 7 /* vendor */ 58 #define NVME_CC_MPS(_v) ((((_v) - 12) & 0xf) << 7) 59 #define NVME_CC_MPS_MASK (0xf << 7) 60 #define NVME_CC_MPS_R(_v) (12 + (((_v) >> 7) & 0xf)) 61 #define NVME_CC_CSS(_v) (((_v) & 0x7) << 4) 62 #define NVME_CC_CSS_MASK NVME_CC_CSS(0x7) 63 #define NVME_CC_CSS_R(_v) (((_v) >> 4) & 0x7) 64 #define NVME_CC_CSS_NVM 0 65 #define NVME_CC_EN (1 << 0) 66 #define NVME_CSTS 0x001c /* Controller Status */ 67 #define NVME_CSTS_CFS (1 << 1) 68 #define NVME_CSTS_RDY (1 << 0) 69 #define NVME_NSSR 0x0020 /* NVM Subsystem Reset (Optional) */ 70 #define NVME_AQA 0x0024 /* Admin Queue Attributes */ 71 /* Admin Completion Queue Size */ 72 #define NVME_AQA_ACQS(_v) (((_v) - 1) << 16) 73 /* Admin Submission Queue Size */ 74 #define NVME_AQA_ASQS(_v) (((_v) - 1) << 0) 75 #define NVME_ASQ 0x0028 /* Admin Submission Queue Base Address */ 76 #define NVME_ACQ 0x0030 /* Admin Completion Queue Base Address */ 77 78 #define NVME_ADMIN_Q 0 79 /* Submission Queue Tail Doorbell */ 80 #define NVME_SQTDBL(_q, _s) (0x1000 + (2 * (_q) + 0) * (_s)) 81 /* Completion Queue Head Doorbell */ 82 #define NVME_CQHDBL(_q, _s) (0x1000 + (2 * (_q) + 1) * (_s)) 83 84 struct nvme_sge { 85 u_int8_t id; 86 u_int8_t _reserved[15]; 87 } __packed __aligned(8); 88 89 struct nvme_sge_data { 90 u_int8_t id; 91 u_int8_t _reserved[3]; 92 93 u_int32_t length; 94 95 u_int64_t address; 96 } __packed __aligned(8); 97 98 struct nvme_sge_bit_bucket { 99 u_int8_t id; 100 u_int8_t _reserved[3]; 101 102 u_int32_t length; 103 104 u_int64_t address; 105 } __packed __aligned(8); 106 107 struct nvme_sqe { 108 u_int8_t opcode; 109 u_int8_t flags; 110 u_int16_t cid; 111 112 u_int32_t nsid; 113 114 u_int8_t _reserved[8]; 115 116 u_int64_t mptr; 117 118 union { 119 u_int64_t prp[2]; 120 struct nvme_sge sge; 121 } __packed entry; 122 123 u_int32_t cdw10; 124 u_int32_t cdw11; 125 u_int32_t cdw12; 126 u_int32_t cdw13; 127 u_int32_t cdw14; 128 u_int32_t cdw15; 129 } __packed __aligned(8); 130 131 struct nvme_cqe { 132 u_int32_t cdw0; 133 134 u_int32_t _reserved; 135 136 u_int16_t sqhd; /* SQ Head Pointer */ 137 u_int16_t sqid; /* SQ Identifier */ 138 139 u_int16_t cid; /* Command Identifier */ 140 u_int16_t flags; 141 #define NVME_CQE_DNR (1 << 15) 142 #define NVME_CQE_M (1 << 14) 143 #define NVME_CQE_SCT(_f) ((_f) & (0x07 << 8)) 144 #define NVME_CQE_SCT_GENERIC (0x00 << 8) 145 #define NVME_CQE_SCT_COMMAND (0x01 << 8) 146 #define NVME_CQE_SCT_MEDIAERR (0x02 << 8) 147 #define NVME_CQE_SCT_VENDOR (0x07 << 8) 148 #define NVME_CQE_SC(_f) ((_f) & (0x7f << 1)) 149 #define NVME_CQE_SC_SUCCESS (0x00 << 1) 150 #define NVME_CQE_SC_INVALID_OPCODE (0x01 << 1) 151 #define NVME_CQE_SC_INVALID_FIELD (0x02 << 1) 152 #define NVME_CQE_SC_CID_CONFLICT (0x03 << 1) 153 #define NVME_CQE_SC_DATA_XFER_ERR (0x04 << 1) 154 #define NVME_CQE_SC_ABRT_BY_NO_PWR (0x05 << 1) 155 #define NVME_CQE_SC_INTERNAL_DEV_ERR (0x06 << 1) 156 #define NVME_CQE_SC_CMD_ABRT_REQD (0x07 << 1) 157 #define NVME_CQE_SC_CMD_ABDR_SQ_DEL (0x08 << 1) 158 #define NVME_CQE_SC_CMD_ABDR_FUSE_ERR (0x09 << 1) 159 #define NVME_CQE_SC_CMD_ABDR_FUSE_MISS (0x0a << 1) 160 #define NVME_CQE_SC_INVALID_NS (0x0b << 1) 161 #define NVME_CQE_SC_CMD_SEQ_ERR (0x0c << 1) 162 #define NVME_CQE_SC_INVALID_LAST_SGL (0x0d << 1) 163 #define NVME_CQE_SC_INVALID_NUM_SGL (0x0e << 1) 164 #define NVME_CQE_SC_DATA_SGL_LEN (0x0f << 1) 165 #define NVME_CQE_SC_MDATA_SGL_LEN (0x10 << 1) 166 #define NVME_CQE_SC_SGL_TYPE_INVALID (0x11 << 1) 167 #define NVME_CQE_SC_LBA_RANGE (0x80 << 1) 168 #define NVME_CQE_SC_CAP_EXCEEDED (0x81 << 1) 169 #define NVME_CQE_NS_NOT_RDY (0x82 << 1) 170 #define NVME_CQE_RSV_CONFLICT (0x83 << 1) 171 #define NVME_CQE_PHASE (1 << 0) 172 } __packed __aligned(8); 173 174 #define NVM_ADMIN_DEL_IOSQ 0x00 /* Delete I/O Submission Queue */ 175 #define NVM_ADMIN_ADD_IOSQ 0x01 /* Create I/O Submission Queue */ 176 #define NVM_ADMIN_GET_LOG_PG 0x02 /* Get Log Page */ 177 #define NVM_ADMIN_DEL_IOCQ 0x04 /* Delete I/O Completion Queue */ 178 #define NVM_ADMIN_ADD_IOCQ 0x05 /* Create I/O Completion Queue */ 179 #define NVM_ADMIN_IDENTIFY 0x06 /* Identify */ 180 #define NVM_ADMIN_ABORT 0x08 /* Abort */ 181 #define NVM_ADMIN_SET_FEATURES 0x09 /* Set Features */ 182 #define NVM_ADMIN_GET_FEATURES 0x0a /* Get Features */ 183 #define NVM_ADMIN_ASYNC_EV_REQ 0x0c /* Asynchronous Event Request */ 184 #define NVM_ADMIN_FW_ACTIVATE 0x10 /* Firmware Activate */ 185 #define NVM_ADMIN_FW_DOWNLOAD 0x11 /* Firmware Image Download */ 186 187 /* Power State Descriptor Data */ 188 struct nvm_identify_psd { 189 u_int16_t mp; /* Max Power */ 190 u_int16_t flags; 191 192 u_int32_t enlat; /* Entry Latency */ 193 194 u_int32_t exlat; /* Exit Latency */ 195 196 u_int8_t rrt; /* Relative Read Throughput */ 197 u_int8_t rrl; /* Relative Read Latency */ 198 u_int8_t rwt; /* Relative Write Throughput */ 199 u_int8_t rwl; /* Relative Write Latency */ 200 201 u_int8_t _reserved[16]; 202 } __packed __aligned(8); 203 204 struct nvm_identify_controller { 205 /* Controller Capabilities and Features */ 206 207 u_int16_t vid; /* PCI Vendor ID */ 208 u_int16_t ssvid; /* PCI Subsystem Vendor ID */ 209 210 u_int8_t sn[20]; /* Serial Number */ 211 u_int8_t mn[40]; /* Model Number */ 212 u_int8_t fr[8]; /* Firmware Revision */ 213 214 u_int8_t rab; /* Recommended Arbitration Burst */ 215 u_int8_t ieee[3]; /* IEEE OUI Identifier */ 216 217 u_int8_t cmic; /* Controller Multi-Path I/O and 218 Namespace Sharing Capabilities */ 219 u_int8_t mdts; /* Maximum Data Transfer Size */ 220 u_int16_t cntlid; /* Controller ID */ 221 222 u_int8_t _reserved1[176]; 223 224 /* Admin Command Set Attributes & Optional Controller Capabilities */ 225 226 u_int16_t oacs; /* Optional Admin Command Support */ 227 u_int8_t acl; /* Abort Command Limit */ 228 u_int8_t aerl; /* Asynchronous Event Request Limit */ 229 230 u_int8_t frmw; /* Firmware Updates */ 231 u_int8_t lpa; /* Log Page Attributes */ 232 u_int8_t elpe; /* Error Log Page Entries */ 233 u_int8_t npss; /* Number of Power States Support */ 234 235 u_int8_t avscc; /* Admin Vendor Specific Command 236 Configuration */ 237 u_int8_t apsta; /* Autonomous Power State Transition 238 Attributes */ 239 240 u_int8_t _reserved2[246]; 241 242 /* NVM Command Set Attributes */ 243 244 u_int8_t sqes; /* Submission Queue Entry Size */ 245 u_int8_t cqes; /* Completion Queue Entry Size */ 246 u_int8_t _reserved3[2]; 247 248 u_int32_t nn; /* Number of Namespaces */ 249 250 u_int16_t oncs; /* Optional NVM Command Support */ 251 u_int16_t fuses; /* Fused Operation Support */ 252 253 u_int8_t fna; /* Format NVM Attributes */ 254 u_int8_t vwc; /* Volatile Write Cache */ 255 u_int16_t awun; /* Atomic Write Unit Normal */ 256 257 u_int16_t awupf; /* Atomic Write Unit Power Fail */ 258 u_int8_t nvscc; /* NVM Vendor Specific Command */ 259 u_int8_t _reserved4[1]; 260 261 u_int16_t acwu; /* Atomic Compare & Write Unit */ 262 u_int8_t _reserved5[2]; 263 264 u_int32_t sgls; /* SGL Support */ 265 266 u_int8_t _reserved6[164]; 267 268 /* I/O Command Set Attributes */ 269 270 u_int8_t _reserved7[1344]; 271 272 /* Power State Descriptors */ 273 274 struct nvm_identify_psd psd[32]; /* Power State Descriptors */ 275 276 /* Vendor Specific */ 277 278 u_int8_t _reserved8[1024]; 279 } __packed __aligned(8); 280