1 /* $OpenBSD: qlareg.h,v 1.8 2016/05/10 11:16:18 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* firmware loading */ 20 #define QLA_2100_CODE_ORG 0x1000 21 #define QLA_2200_CODE_ORG 0x1000 22 #define QLA_2300_CODE_ORG 0x0800 23 24 /* firmware attributes */ 25 #define QLA_FW_ATTR_EXPANDED_LUN 0x0002 26 #define QLA_FW_ATTR_FABRIC 0x0004 27 #define QLA_FW_ATTR_2K_LOGINS 0x0100 28 29 /* interrupt types */ 30 #define QLA_INT_TYPE_MBOX 1 31 #define QLA_INT_TYPE_ASYNC 2 32 #define QLA_INT_TYPE_IO 3 33 #define QLA_INT_TYPE_OTHER 4 34 35 /* 23xx interrupt status codes */ 36 #define QLA_23XX_INT_ROM_MBOX 0x01 37 #define QLA_23XX_INT_ROM_MBOX_FAIL 0x02 38 #define QLA_23XX_INT_MBOX 0x10 39 #define QLA_23XX_INT_MBOX_FAIL 0x11 40 #define QLA_23XX_INT_ASYNC 0x12 41 #define QLA_23XX_INT_RSPQ 0x13 42 #define QLA_23XX_INT_FP16 0x15 43 #define QLA_23XX_INT_FP_SCSI 0x16 44 #define QLA_23XX_INT_FP_CTIO 0x17 45 46 /* ISP registers */ 47 #define QLA_FLASH_BIOS_ADDR 0x00 48 #define QLA_FLASH_BIOS_DATA 0x02 49 #define QLA_CTRL_STATUS 0x06 50 #define QLA_INT_CTRL 0x08 51 #define QLA_INT_STATUS 0x0A 52 #define QLA_SEMA 0x0C 53 #define QLA_NVRAM 0x0E 54 #define QLA_REQ_IN 0x10 55 #define QLA_REQ_OUT 0x12 56 #define QLA_RESP_IN 0x14 57 #define QLA_RESP_OUT 0x16 58 #define QLA_RISC_STATUS_LOW 0x18 59 #define QLA_RISC_STATUS_HIGH 0x1A 60 #define QLA_HOST_CMD_CTRL 0xC0 61 #define QLA_GPIO_DATA 0xCC 62 #define QLA_GPIO_ENABLE 0xCE 63 64 #define QLA_FPM_DIAG 0x96 65 66 67 /* mailbox base moves around between generations */ 68 #define QLA_MBOX_BASE_23XX 0x40 69 #define QLA_MBOX_BASE_2100 0x10 70 #define QLA_MBOX_BASE_2200 0x10 71 72 /* QLA_CTRL_STATUS */ 73 #define QLA_CTRL_RESET 0x0001 74 #define QLA_CTRL_RISC_REGS 0x0000 75 #define QLA_CTRL_FB_REGS 0x0010 76 #define QLA_CTRL_FPM0_REGS 0x0020 77 #define QLA_CTRL_FPM1_REGS 0x0030 78 79 /* QLA_INT_STATUS */ 80 #define QLA_INT_REQ 0x8000 81 #define QLA_RISC_INT_REQ 0x0008 82 83 /* QLA_SEMA */ 84 #define QLA_SEMA_STATUS 0x0002 85 #define QLA_SEMA_LOCK 0x0001 86 87 /* QLA_NVRAM */ 88 #define QLA_NVRAM_DATA_IN 0x0008 89 #define QLA_NVRAM_DATA_OUT 0x0004 90 #define QLA_NVRAM_CHIP_SEL 0x0002 91 #define QLA_NVRAM_CLOCK 0x0001 92 #define QLA_NVRAM_CMD_READ 6 93 94 95 /* QLA_RISC_STATUS LOW/HIGH */ 96 #define QLA_INT_INFO_SHIFT 16 97 #define QLA_RISC_HOST_INT_REQ 0x8000 98 #define QLA_RISC_PAUSED 0x0100 99 #define QLA_INT_STATUS_MASK 0x00FF 100 101 /* QLA_HOST_CMD_CTRL write */ 102 #define QLA_HOST_CMD_SHIFT 12 103 #define QLA_HOST_CMD_NOP 0x0 104 #define QLA_HOST_CMD_RESET 0x1 105 #define QLA_HOST_CMD_PAUSE 0x2 106 #define QLA_HOST_CMD_RELEASE 0x3 107 #define QLA_HOST_CMD_MASK_PARITY 0x4 108 #define QLA_HOST_CMD_SET_HOST_INT 0x5 109 #define QLA_HOST_CMD_CLR_HOST_INT 0x6 110 #define QLA_HOST_CMD_CLR_RISC_INT 0x7 111 #define QLA_HOST_CMD_ENABLE_PARITY 0xA 112 #define QLA_HOST_CMD_PARITY_ERROR 0xE 113 114 /* QLA_HOST_CMD_CTRL read */ 115 #define QLA_HOST_STATUS_HOST_INT 0x0080 116 #define QLA_HOST_STATUS_RISC_RESET 0x0040 117 #define QLA_HOST_STATUS_RISC_PAUSE 0x0020 118 #define QLA_HOST_STATUS_RISC_EXT 0x0010 119 120 /* QLA_FPM_DIAG */ 121 #define QLA_FPM_RESET 0x0100 122 123 /* QLA_MBOX_BASE (reg 0) read */ 124 #define QLA_MBOX_HAS_STATUS 0x4000 125 #define QLA_MBOX_COMPLETE 0x4000 126 #define QLA_MBOX_INVALID 0x4001 127 #define QLA_MBOX_INTF_ERROR 0x4002 128 #define QLA_MBOX_TEST_FAILED 0x4003 129 #define QLA_MBOX_CMD_ERROR 0x4005 130 #define QLA_MBOX_CMD_PARAM 0x4006 131 #define QLA_MBOX_PORT_USED 0x4007 132 #define QLA_MBOX_LOOP_USED 0x4008 133 #define QLA_MBOX_ALL_IDS_USED 0x4009 134 #define QLA_MBOX_NOT_LOGGED_IN 0x400A 135 #define QLA_MBOX_LINK_DOWN 0x400B 136 #define QLA_ASYNC_SYSTEM_ERROR 0x8002 137 #define QLA_ASYNC_REQ_XFER_ERROR 0x8003 138 #define QLA_ASYNC_RSP_XFER_ERROR 0x8004 139 #define QLA_ASYNC_LIP_OCCURRED 0x8010 140 #define QLA_ASYNC_LOOP_UP 0x8011 141 #define QLA_ASYNC_LOOP_DOWN 0x8012 142 #define QLA_ASYNC_LIP_RESET 0x8013 143 #define QLA_ASYNC_PORT_DB_CHANGE 0x8014 144 #define QLA_ASYNC_CHANGE_NOTIFY 0x8015 145 #define QLA_ASYNC_LIP_F8 0x8016 146 #define QLA_ASYNC_LOOP_INIT_ERROR 0x8017 147 #define QLA_ASYNC_LOGIN_REJECT 0x8018 148 #define QLA_ASYNC_SCSI_CMD_COMPLETE 0x8020 149 #define QLA_ASYNC_CTIO_COMPLETE 0x8021 150 #define QLA_ASYNC_POINT_TO_POINT 0x8030 151 #define QLA_ASYNC_ZIO_RESP_UPDATE 0x8040 152 #define QLA_ASYNC_RND_ERROR 0x8048 153 #define QLA_ASYNC_QUEUE_FULL 0x8049 154 155 156 /* QLA_MBOX_BASE (reg 0) write */ 157 #define QLA_MBOX_NOP 0x0000 158 #define QLA_MBOX_LOAD_RAM 0x0001 159 #define QLA_MBOX_EXEC_FIRMWARE 0x0002 160 #define QLA_MBOX_WRITE_RAM_WORD 0x0004 161 #define QLA_MBOX_REGISTER_TEST 0x0006 162 #define QLA_MBOX_VERIFY_CSUM 0x0007 163 #define QLA_MBOX_ABOUT_FIRMWARE 0x0008 164 #define QLA_MBOX_LOAD_RAM_EXT 0x000B 165 #define QLA_MBOX_CSUM_FIRMWARE 0x000E 166 #define QLA_MBOX_INIT_REQ_QUEUE 0x0010 167 #define QLA_MBOX_INIT_RSP_QUEUE 0x0011 168 #define QLA_MBOX_STOP_FIRMWARE 0x0014 169 #define QLA_MBOX_ABORT_IOCB 0x0015 170 #define QLA_MBOX_ABORT_DEVICE 0x0016 171 #define QLA_MBOX_ABORT_TARGET 0x0017 172 #define QLA_MBOX_RESET 0x0018 173 #define QLA_MBOX_ABORT_QUEUE 0x001C 174 #define QLA_MBOX_GET_QUEUE_STATUS 0x001D 175 #define QLA_MBOX_GET_FIRMWARE_STATUS 0x001F 176 #define QLA_MBOX_GET_LOOP_ID 0x0020 177 #define QLA_MBOX_SET_FIRMWARE_OPTIONS 0x0038 178 #define QLA_MBOX_ENH_GET_PORT_DB 0x0047 179 #define QLA_MBOX_PLOGO 0x0056 180 #define QLA_MBOX_INIT_FIRMWARE 0x0060 181 #define QLA_MBOX_GET_INIT_CB 0x0061 182 #define QLA_MBOX_LIP 0x0062 183 #define QLA_MBOX_GET_FC_AL_POS 0x0063 184 #define QLA_MBOX_GET_PORT_DB 0x0064 185 #define QLA_MBOX_TARGET_RESET 0x0066 186 #define QLA_MBOX_GET_FIRMWARE_STATE 0x0069 187 #define QLA_MBOX_GET_PORT_NAME 0x006A 188 #define QLA_MBOX_GET_LINK_STATUS 0x006B 189 #define QLA_MBOX_LIP_RESET 0x006C 190 #define QLA_MBOX_SEND_SNS 0x006E 191 #define QLA_MBOX_FABRIC_PLOGI 0x006F 192 #define QLA_MBOX_SEND_CHANGE_REQ 0x0070 193 #define QLA_MBOX_FABRIC_PLOGO 0x0071 194 #define QLA_MBOX_LOOP_PLOGI 0x0074 195 #define QLA_MBOX_GET_PORT_NAME_LIST 0x0075 196 #define QLA_MBOX_LUN_RESET 0x007E 197 198 199 /* nvram layout */ 200 struct qla_nvram { 201 u_int8_t id[4]; 202 u_int8_t nvram_version; 203 u_int8_t reserved_0; 204 205 u_int8_t parameter_block_version; 206 u_int8_t reserved_1; 207 208 u_int16_t fw_options; 209 210 u_int16_t frame_payload_size; 211 u_int16_t max_iocb_allocation; 212 u_int16_t execution_throttle; 213 u_int8_t retry_count; 214 u_int8_t retry_delay; 215 u_int64_t port_name; 216 u_int16_t hard_address; 217 u_int8_t inquiry_data; 218 u_int8_t login_timeout; 219 u_int64_t node_name; 220 221 u_int16_t add_fw_options; 222 223 u_int8_t response_accumulation_timer; 224 u_int8_t interrupt_delay_timer; 225 226 u_int16_t special_options; 227 228 u_int8_t reserved_2[22]; 229 230 u_int8_t seriallink_options[4]; 231 232 u_int8_t host_p[2]; 233 234 u_int64_t boot_node_name; 235 u_int8_t boot_lun_number; 236 u_int8_t reset_delay; 237 u_int8_t port_down_retry_count; 238 u_int8_t boot_id_number; 239 u_int16_t max_luns_per_target; 240 u_int64_t fcode_boot_port_name; 241 u_int64_t alternate_port_name; 242 u_int64_t alternate_node_name; 243 244 u_int8_t efi_parameters; 245 246 u_int8_t link_down_timeout; 247 248 u_int8_t adapter_id[16]; 249 250 u_int64_t alt1_boot_node_name; 251 u_int16_t alt1_boot_lun_number; 252 u_int64_t alt2_boot_node_name; 253 u_int16_t alt2_boot_lun_number; 254 u_int64_t alt3_boot_node_name; 255 u_int16_t alt3_boot_lun_number; 256 u_int64_t alt4_boot_node_name; 257 u_int16_t alt4_boot_lun_number; 258 u_int64_t alt5_boot_node_name; 259 u_int16_t alt5_boot_lun_number; 260 u_int64_t alt6_boot_node_name; 261 u_int16_t alt6_boot_lun_number; 262 u_int64_t alt7_boot_node_name; 263 u_int16_t alt7_boot_lun_number; 264 265 u_int8_t reserved_3[2]; 266 267 u_int8_t model_number[16]; 268 269 u_int8_t oem_specific[16]; 270 271 u_int8_t adapter_features[2]; 272 273 u_int8_t reserved_4[16]; 274 275 u_int16_t subsystem_vendor_id_2200; 276 u_int16_t subsystem_device_id_2200; 277 278 u_int8_t reserved_5; 279 u_int8_t checksum; 280 } __packed; 281 282 /* init firmware control block */ 283 #define QLA_ICB_VERSION 1 284 285 #define QLA_ICB_FW_HARD_ADDR 0x0001 286 #define QLA_ICB_FW_FAIRNESS 0x0002 287 #define QLA_ICB_FW_FULL_DUPLEX 0x0004 288 #define QLA_ICB_FW_FAST_POST 0x0008 289 #define QLA_ICB_FW_TARGET_MODE 0x0010 290 #define QLA_ICB_FW_DISABLE_INITIATOR 0x0020 291 #define QLA_ICB_FW_ENABLE_ADISC 0x0040 292 #define QLA_ICB_FW_ENABLE_TGT_DEV 0x0080 293 #define QLA_ICB_FW_ENABLE_PDB_CHANGED 0x0100 294 #define QLA_ICB_FW_DISABLE_INIT_LIP 0x0200 295 #define QLA_ICB_FW_DESC_LOOP_ID 0x0400 296 #define QLA_ICB_FW_PREV_LOOP_ID 0x0800 297 #define QLA_ICB_FW_RESERVED 0x1000 298 #define QLA_ICB_FW_LOGIN_AFTER_LIP 0x2000 299 #define QLA_ICB_FW_NAME_OPTION 0x4000 300 #define QLA_ICB_FW_EXTENDED_INIT_CB 0x8000 301 302 #define QLA_ICB_XFW_ZIO_DISABLED 0x0000 303 #define QLA_ICB_XFW_ZIO_MODE_5 0x0005 304 #define QLA_ICB_XFW_ZIO_MODE_6 0x0006 305 306 #define QLA_ICB_XFW_LOOP_PTP 0x0020 307 #define QLA_ICB_XFW_PTP_ONLY 0x0010 308 #define QLA_ICB_XFW_LOOP_ONLY 0x0000 309 310 #define QLA_ICB_XFW_HARD_ADDR_ONLY 0x0080 311 #define QLA_ICB_XFW_ENABLE_CLASS_2 0x0100 312 #define QLA_ICB_XFW_ENABLE_ACK0 0x0200 313 #define QLA_ICB_XFW_ENABLE_FC_TAPE 0x1000 314 #define QLA_ICB_XFW_ENABLE_FC_CONFIRM 0x2000 315 #define QLA_ICB_XFW_ENABLE_TGT_QUEUE 0x4000 316 #define QLA_ICB_XFW_NO_IMPLICIT_LOGOUT 0x8000 317 318 #define QLA_ICB_ZFW_ENABLE_XFR_RDY 0x0001 319 #define QLA_ICB_ZFW_SOFT_ID_ONLY 0x0002 320 #define QLA_ICB_ZFW_FCP_RSP_12_0 0x0010 321 #define QLA_ICB_ZFW_FCP_RSP_24_0 0x0020 322 #define QLA_ICB_ZFW_FCP_RSP_32_BYTES 0x0030 323 #define QLA_ICB_ZFW_ENABLE_OOO 0x0040 324 #define QLA_ICB_ZFW_NO_AUTO_PLOGI 0x0080 325 #define QLA_ICB_ZFW_50_OHMS 0x2000 326 #define QLA_ICB_ZFW_1GBPS 0x0000 327 #define QLA_ICB_ZFW_2GBPS 0x4000 328 #define QLA_ICB_ZFW_AUTONEG 0x8000 329 330 331 struct qla_init_cb { 332 u_int8_t icb_version; 333 u_int8_t icb_reserved; 334 u_int16_t icb_fw_options; 335 u_int16_t icb_max_frame_len; 336 u_int16_t icb_max_alloc; 337 u_int16_t icb_exec_throttle; 338 u_int8_t icb_retry_count; 339 u_int8_t icb_retry_delay; 340 u_int64_t icb_portname; 341 u_int16_t icb_hardaddr; 342 u_int8_t icb_inquiry_data; 343 u_int8_t icb_login_timeout; 344 u_int64_t icb_nodename; 345 u_int16_t icb_req_out; 346 u_int16_t icb_resp_in; 347 u_int16_t icb_req_queue_len; 348 u_int16_t icb_resp_queue_len; 349 u_int64_t icb_req_queue_addr; 350 u_int64_t icb_resp_queue_addr; 351 u_int16_t icb_lun_enables; 352 u_int8_t icb_cmd_count; 353 u_int8_t icb_notify_count; 354 u_int16_t icb_lun_timeout; 355 u_int16_t icb_reserved2; 356 u_int16_t icb_xfwoptions; 357 u_int8_t icb_reserved3; 358 u_int8_t icb_int_delaytimer; 359 u_int16_t icb_zfwoptions; 360 u_int16_t icb_reserved4[13]; 361 } __packed; 362 363 #define QLA_FW_OPTION1_ASYNC_LIP_F8 0x0001 364 #define QLA_FW_OPTION1_ASYNC_LIP_RESET 0x0002 365 #define QLA_FW_OPTION1_SYNC_LOSS_LIP 0x0010 366 #define QLA_FW_OPTION1_ASYNC_LIP_ERROR 0x0080 367 #define QLA_FW_OPTION1_ASYNC_LOGIN_RJT 0x0800 368 369 #define QLA_FW_OPTION3_EMERG_IOCB 0x0001 370 #define QLA_FW_OPTION3_ASYNC_RND_ERROR 0x0002 371 372 /* topology types returned from QLA_MBOX_GET_LOOP_ID */ 373 #define QLA_TOPO_NL_PORT 0 374 #define QLA_TOPO_FL_PORT 1 375 #define QLA_TOPO_N_PORT 2 376 #define QLA_TOPO_F_PORT 3 377 #define QLA_TOPO_N_PORT_NO_TARGET 4 378 379 380 struct qla_get_port_db { 381 u_int8_t options; 382 u_int8_t control; 383 u_int8_t master_state; 384 u_int8_t slave_state; 385 u_int32_t adisc_hard_addr; 386 u_int16_t port_id[2]; 387 u_int64_t node_name; 388 u_int64_t port_name; 389 u_int16_t exec_throttle; 390 u_int16_t exec_count; 391 u_int8_t retry_count; 392 u_int8_t reserved; 393 u_int16_t resource_alloc; 394 u_int16_t current_alloc; 395 u_int16_t queue_head; 396 u_int16_t queue_tail; 397 u_int16_t xmit_exec_list_next; 398 u_int16_t xmit_exec_list_prev; 399 u_int16_t common_features; 400 u_int16_t total_concurrent_seq; 401 u_int16_t rel_offset; 402 u_int16_t recip_control_flags; 403 u_int16_t recv_data_size; 404 u_int16_t concurrent_seq; 405 u_int16_t open_seq; 406 u_int8_t reserved2[8]; 407 u_int16_t retry_timer; 408 u_int16_t next_seq_id; 409 u_int16_t frame_count; 410 u_int16_t prli_payload_len; 411 u_int16_t prli_svc_word0; 412 u_int16_t prli_svc_word3; 413 u_int16_t loop_id; 414 u_int16_t ext_lun_list_ptr; 415 u_int16_t ext_lun_stop_ptr; 416 } __packed; 417 418 struct qla_port_name_list { 419 u_int64_t port_name; 420 u_int16_t loop_id; 421 } __packed; 422 423 #define QLA_SVC3_TARGET_ROLE 0x0010 424 425 /* fabric name server commands */ 426 #define QLA_SNS_GA_NXT 0x0100 427 #define QLA_SNS_GID_FT 0x0171 428 #define QLA_SNS_RFT_ID 0x0217 429 430 #define QLA_FC4_SCSI 8 431 432 #define QLA_LS_REJECT 0x8001 433 #define QLA_LS_ACCEPT 0x8002 434 435 struct qla_sns_req_hdr { 436 u_int16_t resp_len; 437 u_int16_t reserved; 438 u_int64_t resp_addr; 439 u_int16_t subcmd_len; 440 u_int16_t reserved2; 441 } __packed; 442 443 struct qla_sns_ga_nxt { 444 struct qla_sns_req_hdr header; 445 u_int16_t subcmd; 446 u_int16_t max_word; 447 u_int32_t reserved3; 448 u_int32_t port_id; 449 } __packed; 450 451 struct qla_sns_ga_nxt_resp { 452 struct qla_sns_req_hdr header; 453 u_int32_t port_type_id; 454 u_int64_t port_name; 455 u_int8_t sym_port_name_len; 456 u_int8_t sym_port_name[255]; 457 u_int64_t node_name; 458 u_int8_t sym_node_name_len; 459 u_int8_t sym_node_name[255]; 460 u_int64_t initial_assoc; 461 u_int8_t ip_addr[16]; 462 u_int32_t cos; 463 u_int32_t fc4_types[8]; 464 } __packed; 465 466 struct qla_sns_rft_id { 467 struct qla_sns_req_hdr header; 468 u_int16_t subcmd; 469 u_int16_t max_word; 470 u_int32_t reserved3; 471 u_int32_t port_id; 472 u_int32_t fc4_types[8]; 473 } __packed; 474 475 struct qla_sns_gid_ft { 476 struct qla_sns_req_hdr header; 477 u_int16_t subcmd; 478 u_int16_t max_word; 479 u_int32_t reserved3; 480 u_int32_t fc4_proto; 481 } __packed; 482 483 /* available handle ranges */ 484 #define QLA_2KL_MIN_HANDLE 0x81 485 #define QLA_2KL_MAX_HANDLE 0x7EF 486 #define QLA_2KL_BUSWIDTH 0x800 487 488 #define QLA_MIN_HANDLE 0x81 489 #define QLA_MAX_HANDLE 0xFE 490 #define QLA_BUSWIDTH 0x100 491 492 #define QLA_F_PORT_HANDLE 0x7E 493 #define QLA_FABRIC_CTRL_HANDLE 0x7F 494 #define QLA_SNS_HANDLE 0x80 495 /* where does this go with 2klogin firmware? */ 496 #define QLA_IP_BCAST_HANDLE 0xFF 497 498 499 /* IOCB types */ 500 /*#define QLA_IOCB_CONT_TYPE_1 0x02 */ 501 #define QLA_IOCB_STATUS 0x03 502 #define QLA_IOCB_MARKER 0x04 503 #define QLA_IOCB_STATUS_CONT 0x10 504 #define QLA_IOCB_CMD_TYPE_4 0x15 505 #define QLA_IOCB_CMD_TYPE_3 0x19 506 #define QLA_IOCB_MAILBOX 0x39 507 508 #define QLA_REQ_FLAG_CONT 0x01 509 #define QLA_REQ_FLAG_FULL 0x02 510 #define QLA_REQ_FLAG_BAD_HDR 0x04 511 #define QLA_REQ_FLAG_BAD_PKT 0x08 512 513 #define QLA_RESP_FLAG_INVALID_COUNT 0x10 514 #define QLA_RESP_FLAG_INVALID_ORDER 0x20 515 #define QLA_RESP_FLAG_DMA_ERR 0x40 516 #define QLA_RESP_FLAG_RESERVED 0x80 517 518 #define QLA_IOCB_CMD_HEAD_OF_QUEUE 0x0002 519 #define QLA_IOCB_CMD_ORDERED_QUEUE 0x0004 520 #define QLA_IOCB_CMD_SIMPLE_QUEUE 0x0008 521 #define QLA_IOCB_CMD_NO_DATA 0x0000 522 #define QLA_IOCB_CMD_READ_DATA 0x0020 523 #define QLA_IOCB_CMD_WRITE_DATA 0x0040 524 #define QLA_IOCB_CMD_NO_FAST_POST 0x0080 525 526 #define QLA_IOCB_SEGS_PER_CMD 2 527 #define QLA_IOCB_SEGS_PER_CMD_CONT 5 528 529 #define QLA_IOCB_MARKER_SYNC_ALL 2 530 531 struct qla_iocb_seg { 532 u_int32_t seg_addr_lo; 533 u_int32_t seg_addr_hi; 534 u_int32_t seg_len; 535 } __packed __aligned(4); 536 537 #if 0 538 struct qla_iocb_cont1 { 539 u_int8_t entry_type; /* QLA_IOCB_CONT_TYPE_1 */ 540 u_int8_t entry_count; 541 u_int8_t seqno; 542 u_int8_t flags; 543 544 struct qla_iocb_seg segs[5]; 545 } __packed; 546 #endif 547 548 struct qla_iocb_status { 549 u_int8_t entry_type; /* QLA_IOCB_STATUS */ 550 u_int8_t entry_count; 551 u_int8_t seqno; 552 u_int8_t flags; 553 554 u_int32_t handle; 555 u_int16_t scsi_status; 556 u_int16_t completion; 557 u_int16_t state_flags; 558 u_int16_t status_flags; 559 u_int16_t rsp_len; 560 u_int16_t sense_len; 561 u_int32_t resid; 562 u_int8_t fcp_rsp[8]; 563 u_int8_t sense_data[32]; 564 } __packed; 565 566 /* completion */ 567 #define QLA_IOCB_STATUS_COMPLETE 0x0000 568 #define QLA_IOCB_STATUS_DMA_ERROR 0x0002 569 #define QLA_IOCB_STATUS_RESET 0x0004 570 #define QLA_IOCB_STATUS_ABORTED 0x0005 571 #define QLA_IOCB_STATUS_TIMEOUT 0x0006 572 #define QLA_IOCB_STATUS_DATA_OVERRUN 0x0007 573 #define QLA_IOCB_STATUS_DATA_UNDERRUN 0x0015 574 #define QLA_IOCB_STATUS_QUEUE_FULL 0x001C 575 #define QLA_IOCB_STATUS_PORT_UNAVAIL 0x0028 576 #define QLA_IOCB_STATUS_PORT_LOGGED_OUT 0x0029 577 #define QLA_IOCB_STATUS_PORT_CHANGED 0x002A 578 #define QLA_IOCB_STATUS_PORT_BUSY 0x002B 579 580 #define QLA_SCSI_STATUS_FCP_LEN_VALID 0x0100 581 #define QLA_SCSI_STATUS_SENSE_VALID 0x0200 582 #define QLA_SCSI_STATUS_RESID_OVER 0x0400 583 #define QLA_SCSI_STATUS_RESID_UNDER 0x0800 584 585 586 struct qla_iocb_marker { 587 u_int8_t entry_type; /* QLA_IOCB_MARKER */ 588 u_int8_t entry_count; 589 u_int8_t seqno; 590 u_int8_t flags; 591 592 u_int32_t handle; 593 u_int8_t reserved; 594 u_int8_t target; 595 u_int8_t modifier; 596 u_int8_t vp_index; 597 u_int16_t marker_flags; 598 u_int16_t lun; 599 u_int8_t reserved2[48]; 600 } __packed; 601 602 struct qla_iocb_status_cont { 603 u_int8_t entry_type; /* QLA_IOCB_STATUS_CONT */ 604 u_int8_t entry_count; 605 u_int8_t seqno; 606 u_int8_t flags; 607 608 u_int8_t sense[44]; 609 } __packed; 610 611 struct qla_iocb_req34 { 612 u_int8_t entry_type; /* QLA_IOCB_CMD_TYPE_3 or 4 */ 613 u_int8_t entry_count; 614 u_int8_t seqno; 615 u_int8_t flags; 616 617 u_int32_t req_handle; 618 u_int16_t req_target; 619 u_int16_t req_scclun; 620 u_int16_t req_flags; 621 u_int16_t req_reserved; 622 u_int16_t req_time; 623 u_int16_t req_seg_count; 624 u_int8_t req_cdb[16]; 625 u_int32_t req_totalcnt; 626 union { 627 struct qla_iocb_seg req3_segs[2]; 628 struct { 629 u_int16_t req4_seg_type; 630 u_int32_t req4_seg_base; 631 u_int64_t req4_seg_addr; 632 u_int8_t req4_reserved[10]; 633 } __packed req4; 634 } req_type; 635 } __packed; 636 637