1 /* $OpenBSD: qwxreg.h,v 1.7 2024/02/21 14:40:50 kevlo Exp $ */ 2 3 /* 4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. 5 * Copyright (c) 2018-2021 The Linux Foundation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted (subject to the limitations in the disclaimer 10 * below) provided that the following conditions are met: 11 * 12 * * Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * * Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * * Neither the name of [Owner Organization] nor the names of its 20 * contributors may be used to endorse or promote products derived from 21 * this software without specific prior written permission. 22 * 23 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY 24 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 25 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT 26 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER 28 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * core.h 39 */ 40 41 #define ATH11K_TX_MGMT_NUM_PENDING_MAX 512 42 43 #define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 44 45 /* Pending management packets threshold for dropping probe responses */ 46 #define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 47 48 #define ATH11K_INVALID_HW_MAC_ID 0xFF 49 #define ATH11K_CONNECTION_LOSS_HZ (3 * HZ) 50 51 enum ath11k_hw_rev { 52 ATH11K_HW_IPQ8074, 53 ATH11K_HW_QCA6390_HW20, 54 ATH11K_HW_IPQ6018_HW10, 55 ATH11K_HW_QCN9074_HW10, 56 ATH11K_HW_WCN6855_HW20, 57 ATH11K_HW_WCN6855_HW21, 58 ATH11K_HW_WCN6750_HW10, 59 }; 60 61 enum ath11k_firmware_mode { 62 /* the default mode, standard 802.11 functionality */ 63 ATH11K_FIRMWARE_MODE_NORMAL, 64 65 /* factory tests etc */ 66 ATH11K_FIRMWARE_MODE_FTM, 67 68 /* Cold boot calibration */ 69 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7, 70 }; 71 72 enum ath11k_crypt_mode { 73 /* Only use hardware crypto engine */ 74 ATH11K_CRYPT_MODE_HW, 75 /* Only use software crypto */ 76 ATH11K_CRYPT_MODE_SW, 77 }; 78 79 /* IPQ8074 HW channel counters frequency value in hertz */ 80 #define IPQ8074_CC_FREQ_HERTZ 320000 81 82 #define ATH11K_MIN_5G_FREQ 4150 83 #define ATH11K_MIN_6G_FREQ 5925 84 #define ATH11K_MAX_6G_FREQ 7115 85 #define ATH11K_NUM_CHANS 102 86 #define ATH11K_MAX_5G_CHAN 177 87 88 /* Antenna noise floor */ 89 #define ATH11K_DEFAULT_NOISE_FLOOR -95 90 91 /* 92 * wmi.h 93 */ 94 95 #define PSOC_HOST_MAX_NUM_SS (8) 96 97 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 98 #define MAX_HE_NSS 8 99 #define MAX_HE_MODULATION 8 100 #define MAX_HE_RU 4 101 #define HE_MODULATION_NONE 7 102 #define HE_PET_0_USEC 0 103 #define HE_PET_8_USEC 1 104 #define HE_PET_16_USEC 2 105 106 #define WMI_MAX_CHAINS 8 107 108 #define WMI_MAX_NUM_SS MAX_HE_NSS 109 #define WMI_MAX_NUM_RU MAX_HE_RU 110 111 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 112 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 113 #define WMI_TLV_CMD_UNSUPPORTED 0 114 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 115 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 116 117 struct wmi_cmd_hdr { 118 uint32_t cmd_id; 119 } __packed; 120 121 struct wmi_tlv { 122 uint32_t header; 123 uint8_t value[]; 124 } __packed; 125 126 #define WMI_TLV_LEN GENMASK(15, 0) 127 #define WMI_TLV_TAG GENMASK(31, 16) 128 #define TLV_HDR_SIZE sizeof(uint32_t) /* wmi_tlv.header */ 129 130 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 131 #define WMI_MAX_MEM_REQS 32 132 #define ATH11K_MAX_HW_LISTEN_INTERVAL 5 133 134 #define WLAN_SCAN_MAX_HINT_S_SSID 10 135 #define WLAN_SCAN_MAX_HINT_BSSID 10 136 #define MAX_RNR_BSS 5 137 138 #define WLAN_SCAN_MAX_HINT_S_SSID 10 139 #define WLAN_SCAN_MAX_HINT_BSSID 10 140 #define MAX_RNR_BSS 5 141 142 #define WLAN_SCAN_PARAMS_MAX_SSID 16 143 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 144 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 256 145 146 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 147 148 #define MAX_WMI_UTF_LEN 252 149 #define WMI_BA_MODE_BUFFER_SIZE_256 3 150 151 /* 152 * HW mode config type replicated from FW header 153 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 154 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 155 * one in 2G and another in 5G. 156 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 157 * same band; no tx allowed. 158 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 159 * Support for both PHYs within one band is planned 160 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 161 * but could be extended to other bands in the future. 162 * The separation of the band between the two PHYs needs 163 * to be communicated separately. 164 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 165 * as in WMI_HW_MODE_SBS, and 3rd on the other band 166 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and 167 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 168 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 169 */ 170 enum wmi_host_hw_mode_config_type { 171 WMI_HOST_HW_MODE_SINGLE = 0, 172 WMI_HOST_HW_MODE_DBS = 1, 173 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 174 WMI_HOST_HW_MODE_SBS = 3, 175 WMI_HOST_HW_MODE_DBS_SBS = 4, 176 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 177 178 /* keep last */ 179 WMI_HOST_HW_MODE_MAX 180 }; 181 182 /* HW mode priority values used to detect the preferred HW mode 183 * on the available modes. 184 */ 185 enum wmi_host_hw_mode_priority { 186 WMI_HOST_HW_MODE_DBS_SBS_PRI, 187 WMI_HOST_HW_MODE_DBS_PRI, 188 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 189 WMI_HOST_HW_MODE_SBS_PRI, 190 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 191 WMI_HOST_HW_MODE_SINGLE_PRI, 192 193 /* keep last the lowest priority */ 194 WMI_HOST_HW_MODE_MAX_PRI 195 }; 196 197 enum WMI_HOST_WLAN_BAND { 198 WMI_HOST_WLAN_2G_CAP = 0x1, 199 WMI_HOST_WLAN_5G_CAP = 0x2, 200 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP, 201 }; 202 203 /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. 204 * Used only for HE auto rate mode. 205 */ 206 enum { 207 /* HE LTF related configuration */ 208 WMI_HE_AUTORATE_LTF_1X = BIT(0), 209 WMI_HE_AUTORATE_LTF_2X = BIT(1), 210 WMI_HE_AUTORATE_LTF_4X = BIT(2), 211 212 /* HE GI related configuration */ 213 WMI_AUTORATE_400NS_GI = BIT(8), 214 WMI_AUTORATE_800NS_GI = BIT(9), 215 WMI_AUTORATE_1600NS_GI = BIT(10), 216 WMI_AUTORATE_3200NS_GI = BIT(11), 217 }; 218 219 enum { 220 WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001, 221 WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002, 222 WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004, 223 WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008, 224 WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010, 225 }; 226 227 /* 228 * wmi command groups. 229 */ 230 enum wmi_cmd_group { 231 /* 0 to 2 are reserved */ 232 WMI_GRP_START = 0x3, 233 WMI_GRP_SCAN = WMI_GRP_START, 234 WMI_GRP_PDEV = 0x4, 235 WMI_GRP_VDEV = 0x5, 236 WMI_GRP_PEER = 0x6, 237 WMI_GRP_MGMT = 0x7, 238 WMI_GRP_BA_NEG = 0x8, 239 WMI_GRP_STA_PS = 0x9, 240 WMI_GRP_DFS = 0xa, 241 WMI_GRP_ROAM = 0xb, 242 WMI_GRP_OFL_SCAN = 0xc, 243 WMI_GRP_P2P = 0xd, 244 WMI_GRP_AP_PS = 0xe, 245 WMI_GRP_RATE_CTRL = 0xf, 246 WMI_GRP_PROFILE = 0x10, 247 WMI_GRP_SUSPEND = 0x11, 248 WMI_GRP_BCN_FILTER = 0x12, 249 WMI_GRP_WOW = 0x13, 250 WMI_GRP_RTT = 0x14, 251 WMI_GRP_SPECTRAL = 0x15, 252 WMI_GRP_STATS = 0x16, 253 WMI_GRP_ARP_NS_OFL = 0x17, 254 WMI_GRP_NLO_OFL = 0x18, 255 WMI_GRP_GTK_OFL = 0x19, 256 WMI_GRP_CSA_OFL = 0x1a, 257 WMI_GRP_CHATTER = 0x1b, 258 WMI_GRP_TID_ADDBA = 0x1c, 259 WMI_GRP_MISC = 0x1d, 260 WMI_GRP_GPIO = 0x1e, 261 WMI_GRP_FWTEST = 0x1f, 262 WMI_GRP_TDLS = 0x20, 263 WMI_GRP_RESMGR = 0x21, 264 WMI_GRP_STA_SMPS = 0x22, 265 WMI_GRP_WLAN_HB = 0x23, 266 WMI_GRP_RMC = 0x24, 267 WMI_GRP_MHF_OFL = 0x25, 268 WMI_GRP_LOCATION_SCAN = 0x26, 269 WMI_GRP_OEM = 0x27, 270 WMI_GRP_NAN = 0x28, 271 WMI_GRP_COEX = 0x29, 272 WMI_GRP_OBSS_OFL = 0x2a, 273 WMI_GRP_LPI = 0x2b, 274 WMI_GRP_EXTSCAN = 0x2c, 275 WMI_GRP_DHCP_OFL = 0x2d, 276 WMI_GRP_IPA = 0x2e, 277 WMI_GRP_MDNS_OFL = 0x2f, 278 WMI_GRP_SAP_OFL = 0x30, 279 WMI_GRP_OCB = 0x31, 280 WMI_GRP_SOC = 0x32, 281 WMI_GRP_PKT_FILTER = 0x33, 282 WMI_GRP_MAWC = 0x34, 283 WMI_GRP_PMF_OFFLOAD = 0x35, 284 WMI_GRP_BPF_OFFLOAD = 0x36, 285 WMI_GRP_NAN_DATA = 0x37, 286 WMI_GRP_PROTOTYPE = 0x38, 287 WMI_GRP_MONITOR = 0x39, 288 WMI_GRP_REGULATORY = 0x3a, 289 WMI_GRP_HW_DATA_FILTER = 0x3b, 290 WMI_GRP_WLM = 0x3c, 291 WMI_GRP_11K_OFFLOAD = 0x3d, 292 WMI_GRP_TWT = 0x3e, 293 WMI_GRP_MOTION_DET = 0x3f, 294 WMI_GRP_SPATIAL_REUSE = 0x40, 295 }; 296 297 298 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 299 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 300 301 #define WMI_CMD_UNSUPPORTED 0 302 303 enum wmi_tlv_cmd_id { 304 WMI_INIT_CMDID = 0x1, 305 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 306 WMI_STOP_SCAN_CMDID, 307 WMI_SCAN_CHAN_LIST_CMDID, 308 WMI_SCAN_SCH_PRIO_TBL_CMDID, 309 WMI_SCAN_UPDATE_REQUEST_CMDID, 310 WMI_SCAN_PROB_REQ_OUI_CMDID, 311 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 312 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 313 WMI_PDEV_SET_CHANNEL_CMDID, 314 WMI_PDEV_SET_PARAM_CMDID, 315 WMI_PDEV_PKTLOG_ENABLE_CMDID, 316 WMI_PDEV_PKTLOG_DISABLE_CMDID, 317 WMI_PDEV_SET_WMM_PARAMS_CMDID, 318 WMI_PDEV_SET_HT_CAP_IE_CMDID, 319 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 320 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 321 WMI_PDEV_SET_QUIET_MODE_CMDID, 322 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 323 WMI_PDEV_GET_TPC_CONFIG_CMDID, 324 WMI_PDEV_SET_BASE_MACADDR_CMDID, 325 WMI_PDEV_DUMP_CMDID, 326 WMI_PDEV_SET_LED_CONFIG_CMDID, 327 WMI_PDEV_GET_TEMPERATURE_CMDID, 328 WMI_PDEV_SET_LED_FLASHING_CMDID, 329 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 330 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 331 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 332 WMI_PDEV_SET_CTL_TABLE_CMDID, 333 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 334 WMI_PDEV_FIPS_CMDID, 335 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 336 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 337 WMI_PDEV_GET_NFCAL_POWER_CMDID, 338 WMI_PDEV_GET_TPC_CMDID, 339 WMI_MIB_STATS_ENABLE_CMDID, 340 WMI_PDEV_SET_PCL_CMDID, 341 WMI_PDEV_SET_HW_MODE_CMDID, 342 WMI_PDEV_SET_MAC_CONFIG_CMDID, 343 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 344 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 345 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 346 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 347 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 348 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 349 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 350 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 351 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 352 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 353 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 354 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 355 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 356 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 357 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 358 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 359 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 360 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 361 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 362 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 363 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 364 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 365 WMI_PDEV_PKTLOG_FILTER_CMDID, 366 WMI_PDEV_SET_RAP_CONFIG_CMDID, 367 WMI_PDEV_DSM_FILTER_CMDID, 368 WMI_PDEV_FRAME_INJECT_CMDID, 369 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID, 370 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, 371 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 372 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 373 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 374 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 375 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 376 WMI_PDEV_GET_TPC_STATS_CMDID, 377 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID, 378 WMI_PDEV_GET_DPD_STATUS_CMDID, 379 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID, 380 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID, 381 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 382 WMI_VDEV_DELETE_CMDID, 383 WMI_VDEV_START_REQUEST_CMDID, 384 WMI_VDEV_RESTART_REQUEST_CMDID, 385 WMI_VDEV_UP_CMDID, 386 WMI_VDEV_STOP_CMDID, 387 WMI_VDEV_DOWN_CMDID, 388 WMI_VDEV_SET_PARAM_CMDID, 389 WMI_VDEV_INSTALL_KEY_CMDID, 390 WMI_VDEV_WNM_SLEEPMODE_CMDID, 391 WMI_VDEV_WMM_ADDTS_CMDID, 392 WMI_VDEV_WMM_DELTS_CMDID, 393 WMI_VDEV_SET_WMM_PARAMS_CMDID, 394 WMI_VDEV_SET_GTX_PARAMS_CMDID, 395 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 396 WMI_VDEV_PLMREQ_START_CMDID, 397 WMI_VDEV_PLMREQ_STOP_CMDID, 398 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 399 WMI_VDEV_SET_IE_CMDID, 400 WMI_VDEV_RATEMASK_CMDID, 401 WMI_VDEV_ATF_REQUEST_CMDID, 402 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 403 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 404 WMI_VDEV_SET_QUIET_MODE_CMDID, 405 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 406 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 407 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 408 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 409 WMI_PEER_DELETE_CMDID, 410 WMI_PEER_FLUSH_TIDS_CMDID, 411 WMI_PEER_SET_PARAM_CMDID, 412 WMI_PEER_ASSOC_CMDID, 413 WMI_PEER_ADD_WDS_ENTRY_CMDID, 414 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 415 WMI_PEER_MCAST_GROUP_CMDID, 416 WMI_PEER_INFO_REQ_CMDID, 417 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 418 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 419 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 420 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 421 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 422 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 423 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 424 WMI_PEER_ATF_REQUEST_CMDID, 425 WMI_PEER_BWF_REQUEST_CMDID, 426 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 427 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 428 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 429 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 430 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 431 WMI_PDEV_SEND_BCN_CMDID, 432 WMI_BCN_TMPL_CMDID, 433 WMI_BCN_FILTER_RX_CMDID, 434 WMI_PRB_REQ_FILTER_RX_CMDID, 435 WMI_MGMT_TX_CMDID, 436 WMI_PRB_TMPL_CMDID, 437 WMI_MGMT_TX_SEND_CMDID, 438 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 439 WMI_PDEV_SEND_FD_CMDID, 440 WMI_BCN_OFFLOAD_CTRL_CMDID, 441 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 442 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 443 WMI_FILS_DISCOVERY_TMPL_CMDID, 444 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 445 WMI_ADDBA_SEND_CMDID, 446 WMI_ADDBA_STATUS_CMDID, 447 WMI_DELBA_SEND_CMDID, 448 WMI_ADDBA_SET_RESP_CMDID, 449 WMI_SEND_SINGLEAMSDU_CMDID, 450 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 451 WMI_STA_POWERSAVE_PARAM_CMDID, 452 WMI_STA_MIMO_PS_MODE_CMDID, 453 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 454 WMI_PDEV_DFS_DISABLE_CMDID, 455 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 456 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 457 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 458 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 459 WMI_VDEV_ADFS_CH_CFG_CMDID, 460 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 461 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 462 WMI_ROAM_SCAN_RSSI_THRESHOLD, 463 WMI_ROAM_SCAN_PERIOD, 464 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 465 WMI_ROAM_AP_PROFILE, 466 WMI_ROAM_CHAN_LIST, 467 WMI_ROAM_SCAN_CMD, 468 WMI_ROAM_SYNCH_COMPLETE, 469 WMI_ROAM_SET_RIC_REQUEST_CMDID, 470 WMI_ROAM_INVOKE_CMDID, 471 WMI_ROAM_FILTER_CMDID, 472 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 473 WMI_ROAM_CONFIGURE_MAWC_CMDID, 474 WMI_ROAM_SET_MBO_PARAM_CMDID, 475 WMI_ROAM_PER_CONFIG_CMDID, 476 WMI_ROAM_BTM_CONFIG_CMDID, 477 WMI_ENABLE_FILS_CMDID, 478 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 479 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 480 WMI_OFL_SCAN_PERIOD, 481 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 482 WMI_P2P_DEV_SET_DISCOVERABILITY, 483 WMI_P2P_GO_SET_BEACON_IE, 484 WMI_P2P_GO_SET_PROBE_RESP_IE, 485 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 486 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 487 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 488 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 489 WMI_P2P_SET_OPPPS_PARAM_CMDID, 490 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 491 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 492 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 493 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 494 WMI_AP_PS_EGAP_PARAM_CMDID, 495 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 496 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 497 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 498 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 499 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 500 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 501 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 502 WMI_PDEV_RESUME_CMDID, 503 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 504 WMI_RMV_BCN_FILTER_CMDID, 505 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 506 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 507 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 508 WMI_WOW_ENABLE_CMDID, 509 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 510 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 511 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 512 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 513 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 514 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 515 WMI_EXTWOW_ENABLE_CMDID, 516 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 517 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 518 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 519 WMI_WOW_UDP_SVC_OFLD_CMDID, 520 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 521 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 522 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 523 WMI_RTT_TSF_CMDID, 524 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 525 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 526 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 527 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 528 WMI_REQUEST_STATS_EXT_CMDID, 529 WMI_REQUEST_LINK_STATS_CMDID, 530 WMI_START_LINK_STATS_CMDID, 531 WMI_CLEAR_LINK_STATS_CMDID, 532 WMI_GET_FW_MEM_DUMP_CMDID, 533 WMI_DEBUG_MESG_FLUSH_CMDID, 534 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 535 WMI_REQUEST_WLAN_STATS_CMDID, 536 WMI_REQUEST_RCPI_CMDID, 537 WMI_REQUEST_PEER_STATS_INFO_CMDID, 538 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 539 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 540 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 541 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 542 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 543 WMI_APFIND_CMDID, 544 WMI_PASSPOINT_LIST_CONFIG_CMDID, 545 WMI_NLO_CONFIGURE_MAWC_CMDID, 546 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 547 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 548 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 549 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 550 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 551 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 552 WMI_CHATTER_COALESCING_QUERY_CMDID, 553 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 554 WMI_PEER_TID_DELBA_CMDID, 555 WMI_STA_DTIM_PS_METHOD_CMDID, 556 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 557 WMI_STA_KEEPALIVE_CMDID, 558 WMI_BA_REQ_SSN_CMDID, 559 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 560 WMI_PDEV_UTF_CMDID, 561 WMI_DBGLOG_CFG_CMDID, 562 WMI_PDEV_QVIT_CMDID, 563 WMI_PDEV_FTM_INTG_CMDID, 564 WMI_VDEV_SET_KEEPALIVE_CMDID, 565 WMI_VDEV_GET_KEEPALIVE_CMDID, 566 WMI_FORCE_FW_HANG_CMDID, 567 WMI_SET_MCASTBCAST_FILTER_CMDID, 568 WMI_THERMAL_MGMT_CMDID, 569 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 570 WMI_TPC_CHAINMASK_CONFIG_CMDID, 571 WMI_SET_ANTENNA_DIVERSITY_CMDID, 572 WMI_OCB_SET_SCHED_CMDID, 573 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 574 WMI_LRO_CONFIG_CMDID, 575 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 576 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 577 WMI_VDEV_WISA_CMDID, 578 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 579 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 580 WMI_READ_DATA_FROM_FLASH_CMDID, 581 WMI_THERM_THROT_SET_CONF_CMDID, 582 WMI_RUNTIME_DPD_RECAL_CMDID, 583 WMI_GET_TPC_POWER_CMDID, 584 WMI_IDLE_TRIGGER_MONITOR_CMDID, 585 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 586 WMI_GPIO_OUTPUT_CMDID, 587 WMI_TXBF_CMDID, 588 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 589 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 590 WMI_UNIT_TEST_CMDID, 591 WMI_FWTEST_CMDID, 592 WMI_QBOOST_CFG_CMDID, 593 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 594 WMI_TDLS_PEER_UPDATE_CMDID, 595 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 596 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 597 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 598 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 599 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 600 WMI_STA_SMPS_PARAM_CMDID, 601 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 602 WMI_HB_SET_TCP_PARAMS_CMDID, 603 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 604 WMI_HB_SET_UDP_PARAMS_CMDID, 605 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 606 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 607 WMI_RMC_SET_ACTION_PERIOD_CMDID, 608 WMI_RMC_CONFIG_CMDID, 609 WMI_RMC_SET_MANUAL_LEADER_CMDID, 610 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 611 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 612 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 613 WMI_BATCH_SCAN_DISABLE_CMDID, 614 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 615 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 616 WMI_OEM_REQUEST_CMDID, 617 WMI_LPI_OEM_REQ_CMDID, 618 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 619 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 620 WMI_CHAN_AVOID_UPDATE_CMDID, 621 WMI_COEX_CONFIG_CMDID, 622 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 623 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 624 WMI_SAR_LIMITS_CMDID, 625 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 626 WMI_OBSS_SCAN_DISABLE_CMDID, 627 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 628 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 629 WMI_LPI_START_SCAN_CMDID, 630 WMI_LPI_STOP_SCAN_CMDID, 631 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 632 WMI_EXTSCAN_STOP_CMDID, 633 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 634 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 635 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 636 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 637 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 638 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 639 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 640 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 641 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 642 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 643 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 644 WMI_MDNS_SET_FQDN_CMDID, 645 WMI_MDNS_SET_RESPONSE_CMDID, 646 WMI_MDNS_GET_STATS_CMDID, 647 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 648 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 649 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 650 WMI_OCB_SET_UTC_TIME_CMDID, 651 WMI_OCB_START_TIMING_ADVERT_CMDID, 652 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 653 WMI_OCB_GET_TSF_TIMER_CMDID, 654 WMI_DCC_GET_STATS_CMDID, 655 WMI_DCC_CLEAR_STATS_CMDID, 656 WMI_DCC_UPDATE_NDL_CMDID, 657 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 658 WMI_SOC_SET_HW_MODE_CMDID, 659 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 660 WMI_SOC_SET_ANTENNA_MODE_CMDID, 661 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 662 WMI_PACKET_FILTER_ENABLE_CMDID, 663 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 664 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 665 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 666 WMI_BPF_GET_VDEV_STATS_CMDID, 667 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 668 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 669 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 670 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 671 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 672 WMI_11D_SCAN_START_CMDID, 673 WMI_11D_SCAN_STOP_CMDID, 674 WMI_SET_INIT_COUNTRY_CMDID, 675 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 676 WMI_NDP_INITIATOR_REQ_CMDID, 677 WMI_NDP_RESPONDER_REQ_CMDID, 678 WMI_NDP_END_REQ_CMDID, 679 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 680 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 681 WMI_TWT_DISABLE_CMDID, 682 WMI_TWT_ADD_DIALOG_CMDID, 683 WMI_TWT_DEL_DIALOG_CMDID, 684 WMI_TWT_PAUSE_DIALOG_CMDID, 685 WMI_TWT_RESUME_DIALOG_CMDID, 686 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 687 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 688 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 689 }; 690 691 enum wmi_tlv_event_id { 692 WMI_SERVICE_READY_EVENTID = 0x1, 693 WMI_READY_EVENTID, 694 WMI_SERVICE_AVAILABLE_EVENTID, 695 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 696 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 697 WMI_CHAN_INFO_EVENTID, 698 WMI_PHYERR_EVENTID, 699 WMI_PDEV_DUMP_EVENTID, 700 WMI_TX_PAUSE_EVENTID, 701 WMI_DFS_RADAR_EVENTID, 702 WMI_PDEV_L1SS_TRACK_EVENTID, 703 WMI_PDEV_TEMPERATURE_EVENTID, 704 WMI_SERVICE_READY_EXT_EVENTID, 705 WMI_PDEV_FIPS_EVENTID, 706 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 707 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 708 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 709 WMI_PDEV_TPC_EVENTID, 710 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 711 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 712 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 713 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 714 WMI_PDEV_ANTDIV_STATUS_EVENTID, 715 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 716 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 717 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 718 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 719 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 720 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 721 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 722 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 723 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 724 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 725 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 726 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 727 WMI_PDEV_RAP_INFO_EVENTID, 728 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 729 WMI_SERVICE_READY_EXT2_EVENTID, 730 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 731 WMI_VDEV_STOPPED_EVENTID, 732 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 733 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 734 WMI_VDEV_TSF_REPORT_EVENTID, 735 WMI_VDEV_DELETE_RESP_EVENTID, 736 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 737 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 738 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 739 WMI_PEER_INFO_EVENTID, 740 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 741 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 742 WMI_PEER_STATE_EVENTID, 743 WMI_PEER_ASSOC_CONF_EVENTID, 744 WMI_PEER_DELETE_RESP_EVENTID, 745 WMI_PEER_RATECODE_LIST_EVENTID, 746 WMI_WDS_PEER_EVENTID, 747 WMI_PEER_STA_PS_STATECHG_EVENTID, 748 WMI_PEER_ANTDIV_INFO_EVENTID, 749 WMI_PEER_RESERVED0_EVENTID, 750 WMI_PEER_RESERVED1_EVENTID, 751 WMI_PEER_RESERVED2_EVENTID, 752 WMI_PEER_RESERVED3_EVENTID, 753 WMI_PEER_RESERVED4_EVENTID, 754 WMI_PEER_RESERVED5_EVENTID, 755 WMI_PEER_RESERVED6_EVENTID, 756 WMI_PEER_RESERVED7_EVENTID, 757 WMI_PEER_RESERVED8_EVENTID, 758 WMI_PEER_RESERVED9_EVENTID, 759 WMI_PEER_RESERVED10_EVENTID, 760 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 761 WMI_PEER_TX_PN_RESPONSE_EVENTID, 762 WMI_PEER_CFR_CAPTURE_EVENTID, 763 WMI_PEER_CREATE_CONF_EVENTID, 764 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 765 WMI_HOST_SWBA_EVENTID, 766 WMI_TBTTOFFSET_UPDATE_EVENTID, 767 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 768 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 769 WMI_MGMT_TX_COMPLETION_EVENTID, 770 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 771 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 772 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 773 WMI_HOST_FILS_DISCOVERY_EVENTID, 774 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 775 WMI_TX_ADDBA_COMPLETE_EVENTID, 776 WMI_BA_RSP_SSN_EVENTID, 777 WMI_AGGR_STATE_TRIG_EVENTID, 778 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 779 WMI_PROFILE_MATCH, 780 WMI_ROAM_SYNCH_EVENTID, 781 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 782 WMI_P2P_NOA_EVENTID, 783 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 784 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 785 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 786 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 787 WMI_D0_WOW_DISABLE_ACK_EVENTID, 788 WMI_WOW_INITIAL_WAKEUP_EVENTID, 789 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 790 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 791 WMI_RTT_ERROR_REPORT_EVENTID, 792 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 793 WMI_IFACE_LINK_STATS_EVENTID, 794 WMI_PEER_LINK_STATS_EVENTID, 795 WMI_RADIO_LINK_STATS_EVENTID, 796 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 797 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 798 WMI_INST_RSSI_STATS_EVENTID, 799 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 800 WMI_REPORT_STATS_EVENTID, 801 WMI_UPDATE_RCPI_EVENTID, 802 WMI_PEER_STATS_INFO_EVENTID, 803 WMI_RADIO_CHAN_STATS_EVENTID, 804 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 805 WMI_NLO_SCAN_COMPLETE_EVENTID, 806 WMI_APFIND_EVENTID, 807 WMI_PASSPOINT_MATCH_EVENTID, 808 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 809 WMI_GTK_REKEY_FAIL_EVENTID, 810 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 811 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 812 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 813 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 814 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 815 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 816 WMI_PDEV_UTF_EVENTID, 817 WMI_DEBUG_MESG_EVENTID, 818 WMI_UPDATE_STATS_EVENTID, 819 WMI_DEBUG_PRINT_EVENTID, 820 WMI_DCS_INTERFERENCE_EVENTID, 821 WMI_PDEV_QVIT_EVENTID, 822 WMI_WLAN_PROFILE_DATA_EVENTID, 823 WMI_PDEV_FTM_INTG_EVENTID, 824 WMI_WLAN_FREQ_AVOID_EVENTID, 825 WMI_VDEV_GET_KEEPALIVE_EVENTID, 826 WMI_THERMAL_MGMT_EVENTID, 827 WMI_DIAG_DATA_CONTAINER_EVENTID, 828 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 829 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 830 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 831 WMI_DIAG_EVENTID, 832 WMI_OCB_SET_SCHED_EVENTID, 833 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 834 WMI_RSSI_BREACH_EVENTID, 835 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 836 WMI_PDEV_UTF_SCPC_EVENTID, 837 WMI_READ_DATA_FROM_FLASH_EVENTID, 838 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 839 WMI_PKGID_EVENTID, 840 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 841 WMI_UPLOADH_EVENTID, 842 WMI_CAPTUREH_EVENTID, 843 WMI_RFKILL_STATE_CHANGE_EVENTID, 844 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 845 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 846 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 847 WMI_BATCH_SCAN_RESULT_EVENTID, 848 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 849 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 850 WMI_OEM_ERROR_REPORT_EVENTID, 851 WMI_OEM_RESPONSE_EVENTID, 852 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 853 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 854 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 855 WMI_NAN_STARTED_CLUSTER_EVENTID, 856 WMI_NAN_JOINED_CLUSTER_EVENTID, 857 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 858 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 859 WMI_LPI_STATUS_EVENTID, 860 WMI_LPI_HANDOFF_EVENTID, 861 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 862 WMI_EXTSCAN_OPERATION_EVENTID, 863 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 864 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 865 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 866 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 867 WMI_EXTSCAN_CAPABILITIES_EVENTID, 868 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 869 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 870 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 871 WMI_SAP_OFL_DEL_STA_EVENTID, 872 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 873 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 874 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 875 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 876 WMI_DCC_GET_STATS_RESP_EVENTID, 877 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 878 WMI_DCC_STATS_EVENTID, 879 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 880 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 881 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 882 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 883 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 884 WMI_BPF_VDEV_STATS_INFO_EVENTID, 885 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 886 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 887 WMI_11D_NEW_COUNTRY_EVENTID, 888 WMI_REG_CHAN_LIST_CC_EXT_EVENTID, 889 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 890 WMI_NDP_INITIATOR_RSP_EVENTID, 891 WMI_NDP_RESPONDER_RSP_EVENTID, 892 WMI_NDP_END_RSP_EVENTID, 893 WMI_NDP_INDICATION_EVENTID, 894 WMI_NDP_CONFIRM_EVENTID, 895 WMI_NDP_END_INDICATION_EVENTID, 896 897 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 898 WMI_TWT_DISABLE_EVENTID, 899 WMI_TWT_ADD_DIALOG_EVENTID, 900 WMI_TWT_DEL_DIALOG_EVENTID, 901 WMI_TWT_PAUSE_DIALOG_EVENTID, 902 WMI_TWT_RESUME_DIALOG_EVENTID, 903 }; 904 905 enum wmi_tlv_pdev_param { 906 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 907 WMI_PDEV_PARAM_RX_CHAIN_MASK, 908 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 909 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 910 WMI_PDEV_PARAM_TXPOWER_SCALE, 911 WMI_PDEV_PARAM_BEACON_GEN_MODE, 912 WMI_PDEV_PARAM_BEACON_TX_MODE, 913 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 914 WMI_PDEV_PARAM_PROTECTION_MODE, 915 WMI_PDEV_PARAM_DYNAMIC_BW, 916 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 917 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 918 WMI_PDEV_PARAM_STA_KICKOUT_TH, 919 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 920 WMI_PDEV_PARAM_LTR_ENABLE, 921 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 922 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 923 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 924 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 925 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 926 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 927 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 928 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 929 WMI_PDEV_PARAM_L1SS_ENABLE, 930 WMI_PDEV_PARAM_DSLEEP_ENABLE, 931 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 932 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 933 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 934 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 935 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 936 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 937 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 938 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 939 WMI_PDEV_PARAM_PMF_QOS, 940 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 941 WMI_PDEV_PARAM_DCS, 942 WMI_PDEV_PARAM_ANI_ENABLE, 943 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 944 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 945 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 946 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 947 WMI_PDEV_PARAM_DYNTXCHAIN, 948 WMI_PDEV_PARAM_PROXY_STA, 949 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 950 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 951 WMI_PDEV_PARAM_RFKILL_ENABLE, 952 WMI_PDEV_PARAM_BURST_DUR, 953 WMI_PDEV_PARAM_BURST_ENABLE, 954 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 955 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 956 WMI_PDEV_PARAM_L1SS_TRACK, 957 WMI_PDEV_PARAM_HYST_EN, 958 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 959 WMI_PDEV_PARAM_LED_SYS_STATE, 960 WMI_PDEV_PARAM_LED_ENABLE, 961 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 962 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 963 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 964 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 965 WMI_PDEV_PARAM_CTS_CBW, 966 WMI_PDEV_PARAM_WNTS_CONFIG, 967 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 968 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 969 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 970 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 971 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 972 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 973 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 974 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 975 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 976 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 977 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 978 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 979 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 980 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 981 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 982 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 983 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 984 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 985 WMI_PDEV_PARAM_AGGR_BURST, 986 WMI_PDEV_PARAM_RX_DECAP_MODE, 987 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 988 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 989 WMI_PDEV_PARAM_ANTENNA_GAIN, 990 WMI_PDEV_PARAM_RX_FILTER, 991 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 992 WMI_PDEV_PARAM_PROXY_STA_MODE, 993 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 994 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 995 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 996 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 997 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 998 WMI_PDEV_PARAM_BLOCK_INTERBSS, 999 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 1000 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 1001 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 1002 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 1003 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 1004 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 1005 WMI_PDEV_PARAM_EN_STATS, 1006 WMI_PDEV_PARAM_MU_GROUP_POLICY, 1007 WMI_PDEV_PARAM_NOISE_DETECTION, 1008 WMI_PDEV_PARAM_NOISE_THRESHOLD, 1009 WMI_PDEV_PARAM_DPD_ENABLE, 1010 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 1011 WMI_PDEV_PARAM_ATF_STRICT_SCH, 1012 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 1013 WMI_PDEV_PARAM_ANT_PLZN, 1014 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 1015 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 1016 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 1017 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 1018 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 1019 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 1020 WMI_PDEV_PARAM_CCA_THRESHOLD, 1021 WMI_PDEV_PARAM_RTS_FIXED_RATE, 1022 WMI_PDEV_PARAM_PDEV_RESET, 1023 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 1024 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 1025 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 1026 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 1027 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 1028 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 1029 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 1030 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 1031 WMI_PDEV_PARAM_PROPAGATION_DELAY, 1032 WMI_PDEV_PARAM_ENA_ANT_DIV, 1033 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 1034 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 1035 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 1036 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 1037 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 1038 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 1039 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 1040 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 1041 WMI_PDEV_PARAM_TX_SCH_DELAY, 1042 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 1043 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 1044 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 1045 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 1046 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 1047 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 1048 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 1049 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, 1050 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, 1051 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, 1052 }; 1053 1054 enum wmi_tlv_vdev_param { 1055 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 1056 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 1057 WMI_VDEV_PARAM_BEACON_INTERVAL, 1058 WMI_VDEV_PARAM_LISTEN_INTERVAL, 1059 WMI_VDEV_PARAM_MULTICAST_RATE, 1060 WMI_VDEV_PARAM_MGMT_TX_RATE, 1061 WMI_VDEV_PARAM_SLOT_TIME, 1062 WMI_VDEV_PARAM_PREAMBLE, 1063 WMI_VDEV_PARAM_SWBA_TIME, 1064 WMI_VDEV_STATS_UPDATE_PERIOD, 1065 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 1066 WMI_VDEV_HOST_SWBA_INTERVAL, 1067 WMI_VDEV_PARAM_DTIM_PERIOD, 1068 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 1069 WMI_VDEV_PARAM_WDS, 1070 WMI_VDEV_PARAM_ATIM_WINDOW, 1071 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 1072 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 1073 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 1074 WMI_VDEV_PARAM_FEATURE_WMM, 1075 WMI_VDEV_PARAM_CHWIDTH, 1076 WMI_VDEV_PARAM_CHEXTOFFSET, 1077 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 1078 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 1079 WMI_VDEV_PARAM_MGMT_RATE, 1080 WMI_VDEV_PARAM_PROTECTION_MODE, 1081 WMI_VDEV_PARAM_FIXED_RATE, 1082 WMI_VDEV_PARAM_SGI, 1083 WMI_VDEV_PARAM_LDPC, 1084 WMI_VDEV_PARAM_TX_STBC, 1085 WMI_VDEV_PARAM_RX_STBC, 1086 WMI_VDEV_PARAM_INTRA_BSS_FWD, 1087 WMI_VDEV_PARAM_DEF_KEYID, 1088 WMI_VDEV_PARAM_NSS, 1089 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1090 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1091 WMI_VDEV_PARAM_MCAST_INDICATE, 1092 WMI_VDEV_PARAM_DHCP_INDICATE, 1093 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1094 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1095 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1096 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1097 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1098 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1099 WMI_VDEV_PARAM_TXBF, 1100 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1101 WMI_VDEV_PARAM_DROP_UNENCRY, 1102 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1103 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1104 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1105 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1106 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1107 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1108 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1109 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1110 WMI_VDEV_PARAM_TX_PWRLIMIT, 1111 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1112 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1113 WMI_VDEV_PARAM_ENABLE_RMC, 1114 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1115 WMI_VDEV_PARAM_MAX_RATE, 1116 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1117 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1118 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1119 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1120 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1121 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1122 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1123 WMI_VDEV_PARAM_INACTIVITY_CNT, 1124 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1125 WMI_VDEV_PARAM_DTIM_POLICY, 1126 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1127 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1128 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1129 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1130 WMI_VDEV_PARAM_DISCONNECT_TH, 1131 WMI_VDEV_PARAM_RTSCTS_RATE, 1132 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1133 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1134 WMI_VDEV_PARAM_TXPOWER_SCALE, 1135 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1136 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1137 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1138 WMI_VDEV_PARAM_CABQ_MAXDUR, 1139 WMI_VDEV_PARAM_MFPTEST_SET, 1140 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1141 WMI_VDEV_PARAM_VHT_SGIMASK, 1142 WMI_VDEV_PARAM_VHT80_RATEMASK, 1143 WMI_VDEV_PARAM_PROXY_STA, 1144 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1145 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1146 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1147 WMI_VDEV_PARAM_SENSOR_AP, 1148 WMI_VDEV_PARAM_BEACON_RATE, 1149 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1150 WMI_VDEV_PARAM_STA_KICKOUT, 1151 WMI_VDEV_PARAM_CAPABILITIES, 1152 WMI_VDEV_PARAM_TSF_INCREMENT, 1153 WMI_VDEV_PARAM_AMPDU_PER_AC, 1154 WMI_VDEV_PARAM_RX_FILTER, 1155 WMI_VDEV_PARAM_MGMT_TX_POWER, 1156 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1157 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1158 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1159 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1160 WMI_VDEV_PARAM_HE_DCM, 1161 WMI_VDEV_PARAM_HE_RANGE_EXT, 1162 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1163 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1164 WMI_VDEV_PARAM_HE_LTF = 0x74, 1165 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d, 1166 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1167 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, 1168 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1169 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1170 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1171 WMI_VDEV_PARAM_BSS_COLOR, 1172 WMI_VDEV_PARAM_SET_HEMU_MODE, 1173 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1174 }; 1175 1176 enum wmi_tlv_peer_flags { 1177 WMI_TLV_PEER_AUTH = 0x00000001, 1178 WMI_TLV_PEER_QOS = 0x00000002, 1179 WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004, 1180 WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010, 1181 WMI_TLV_PEER_APSD = 0x00000800, 1182 WMI_TLV_PEER_HT = 0x00001000, 1183 WMI_TLV_PEER_40MHZ = 0x00002000, 1184 WMI_TLV_PEER_STBC = 0x00008000, 1185 WMI_TLV_PEER_LDPC = 0x00010000, 1186 WMI_TLV_PEER_DYN_MIMOPS = 0x00020000, 1187 WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000, 1188 WMI_TLV_PEER_SPATIAL_MUX = 0x00200000, 1189 WMI_TLV_PEER_VHT = 0x02000000, 1190 WMI_TLV_PEER_80MHZ = 0x04000000, 1191 WMI_TLV_PEER_PMF = 0x08000000, 1192 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1193 WMI_PEER_160MHZ = 0x40000000, 1194 WMI_PEER_SAFEMODE_EN = 0x80000000, 1195 1196 }; 1197 1198 /** Enum list of TLV Tags for each parameter structure type. */ 1199 enum wmi_tlv_tag { 1200 WMI_TAG_LAST_RESERVED = 15, 1201 WMI_TAG_FIRST_ARRAY_ENUM, 1202 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1203 WMI_TAG_ARRAY_BYTE, 1204 WMI_TAG_ARRAY_STRUCT, 1205 WMI_TAG_ARRAY_FIXED_STRUCT, 1206 WMI_TAG_LAST_ARRAY_ENUM = 31, 1207 WMI_TAG_SERVICE_READY_EVENT, 1208 WMI_TAG_HAL_REG_CAPABILITIES, 1209 WMI_TAG_WLAN_HOST_MEM_REQ, 1210 WMI_TAG_READY_EVENT, 1211 WMI_TAG_SCAN_EVENT, 1212 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1213 WMI_TAG_CHAN_INFO_EVENT, 1214 WMI_TAG_COMB_PHYERR_RX_HDR, 1215 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1216 WMI_TAG_VDEV_STOPPED_EVENT, 1217 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1218 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1219 WMI_TAG_MGMT_RX_HDR, 1220 WMI_TAG_TBTT_OFFSET_EVENT, 1221 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1222 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1223 WMI_TAG_ROAM_EVENT, 1224 WMI_TAG_WOW_EVENT_INFO, 1225 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1226 WMI_TAG_RTT_EVENT_HEADER, 1227 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1228 WMI_TAG_RTT_MEAS_EVENT, 1229 WMI_TAG_ECHO_EVENT, 1230 WMI_TAG_FTM_INTG_EVENT, 1231 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1232 WMI_TAG_GPIO_INPUT_EVENT, 1233 WMI_TAG_CSA_EVENT, 1234 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1235 WMI_TAG_IGTK_INFO, 1236 WMI_TAG_DCS_INTERFERENCE_EVENT, 1237 WMI_TAG_ATH_DCS_CW_INT, 1238 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1239 WMI_TAG_ATH_DCS_CW_INT, 1240 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1241 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1242 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1243 WMI_TAG_WLAN_PROFILE_CTX_T, 1244 WMI_TAG_WLAN_PROFILE_T, 1245 WMI_TAG_PDEV_QVIT_EVENT, 1246 WMI_TAG_HOST_SWBA_EVENT, 1247 WMI_TAG_TIM_INFO, 1248 WMI_TAG_P2P_NOA_INFO, 1249 WMI_TAG_STATS_EVENT, 1250 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1251 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1252 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1253 WMI_TAG_INIT_CMD, 1254 WMI_TAG_RESOURCE_CONFIG, 1255 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1256 WMI_TAG_START_SCAN_CMD, 1257 WMI_TAG_STOP_SCAN_CMD, 1258 WMI_TAG_SCAN_CHAN_LIST_CMD, 1259 WMI_TAG_CHANNEL, 1260 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1261 WMI_TAG_PDEV_SET_PARAM_CMD, 1262 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1263 WMI_TAG_WMM_PARAMS, 1264 WMI_TAG_PDEV_SET_QUIET_CMD, 1265 WMI_TAG_VDEV_CREATE_CMD, 1266 WMI_TAG_VDEV_DELETE_CMD, 1267 WMI_TAG_VDEV_START_REQUEST_CMD, 1268 WMI_TAG_P2P_NOA_DESCRIPTOR, 1269 WMI_TAG_P2P_GO_SET_BEACON_IE, 1270 WMI_TAG_GTK_OFFLOAD_CMD, 1271 WMI_TAG_VDEV_UP_CMD, 1272 WMI_TAG_VDEV_STOP_CMD, 1273 WMI_TAG_VDEV_DOWN_CMD, 1274 WMI_TAG_VDEV_SET_PARAM_CMD, 1275 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1276 WMI_TAG_PEER_CREATE_CMD, 1277 WMI_TAG_PEER_DELETE_CMD, 1278 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1279 WMI_TAG_PEER_SET_PARAM_CMD, 1280 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1281 WMI_TAG_VHT_RATE_SET, 1282 WMI_TAG_BCN_TMPL_CMD, 1283 WMI_TAG_PRB_TMPL_CMD, 1284 WMI_TAG_BCN_PRB_INFO, 1285 WMI_TAG_PEER_TID_ADDBA_CMD, 1286 WMI_TAG_PEER_TID_DELBA_CMD, 1287 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1288 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1289 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1290 WMI_TAG_ROAM_SCAN_MODE, 1291 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1292 WMI_TAG_ROAM_SCAN_PERIOD, 1293 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1294 WMI_TAG_PDEV_SUSPEND_CMD, 1295 WMI_TAG_PDEV_RESUME_CMD, 1296 WMI_TAG_ADD_BCN_FILTER_CMD, 1297 WMI_TAG_RMV_BCN_FILTER_CMD, 1298 WMI_TAG_WOW_ENABLE_CMD, 1299 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1300 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1301 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1302 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1303 WMI_TAG_ARP_OFFLOAD_TUPLE, 1304 WMI_TAG_NS_OFFLOAD_TUPLE, 1305 WMI_TAG_FTM_INTG_CMD, 1306 WMI_TAG_STA_KEEPALIVE_CMD, 1307 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE, 1308 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1309 WMI_TAG_AP_PS_PEER_CMD, 1310 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1311 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1312 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1313 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1314 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1315 WMI_TAG_WOW_DEL_PATTERN_CMD, 1316 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1317 WMI_TAG_RTT_MEASREQ_HEAD, 1318 WMI_TAG_RTT_MEASREQ_BODY, 1319 WMI_TAG_RTT_TSF_CMD, 1320 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1321 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1322 WMI_TAG_REQUEST_STATS_CMD, 1323 WMI_TAG_NLO_CONFIG_CMD, 1324 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1325 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1326 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1327 WMI_TAG_CHATTER_SET_MODE_CMD, 1328 WMI_TAG_ECHO_CMD, 1329 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1330 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1331 WMI_TAG_FORCE_FW_HANG_CMD, 1332 WMI_TAG_GPIO_CONFIG_CMD, 1333 WMI_TAG_GPIO_OUTPUT_CMD, 1334 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1335 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1336 WMI_TAG_BCN_TX_HDR, 1337 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1338 WMI_TAG_MGMT_TX_HDR, 1339 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1340 WMI_TAG_ADDBA_SEND_CMD, 1341 WMI_TAG_DELBA_SEND_CMD, 1342 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1343 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1344 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1345 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1346 WMI_TAG_PDEV_SET_HT_IE_CMD, 1347 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1348 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1349 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1350 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1351 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1352 WMI_TAG_PEER_MCAST_GROUP_CMD, 1353 WMI_TAG_ROAM_AP_PROFILE, 1354 WMI_TAG_AP_PROFILE, 1355 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1356 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1357 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1358 WMI_TAG_WOW_ADD_PATTERN_CMD, 1359 WMI_TAG_WOW_BITMAP_PATTERN_T, 1360 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1361 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1362 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1363 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1364 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1365 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1366 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1367 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1368 WMI_TAG_TXBF_CMD, 1369 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1370 WMI_TAG_NLO_EVENT, 1371 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1372 WMI_TAG_UPLOAD_H_HDR, 1373 WMI_TAG_CAPTURE_H_EVENT_HDR, 1374 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1375 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1376 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1377 WMI_TAG_VDEV_WMM_DELTS_CMD, 1378 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1379 WMI_TAG_TDLS_SET_STATE_CMD, 1380 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1381 WMI_TAG_TDLS_PEER_EVENT, 1382 WMI_TAG_TDLS_PEER_CAPABILITIES, 1383 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1384 WMI_TAG_ROAM_CHAN_LIST, 1385 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1386 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1387 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1388 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1389 WMI_TAG_BA_REQ_SSN_CMD, 1390 WMI_TAG_BA_RSP_SSN_EVENT, 1391 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1392 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1393 WMI_TAG_P2P_SET_OPPPS_CMD, 1394 WMI_TAG_P2P_SET_NOA_CMD, 1395 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1396 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1397 WMI_TAG_STA_SMPS_PARAM_CMD, 1398 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1399 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1400 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1401 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1402 WMI_TAG_P2P_NOA_EVENT, 1403 WMI_TAG_HB_SET_ENABLE_CMD, 1404 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1405 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1406 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1407 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1408 WMI_TAG_HB_IND_EVENT, 1409 WMI_TAG_TX_PAUSE_EVENT, 1410 WMI_TAG_RFKILL_EVENT, 1411 WMI_TAG_DFS_RADAR_EVENT, 1412 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1413 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1414 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1415 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1416 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1417 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1418 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1419 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1420 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1421 WMI_TAG_VDEV_PLMREQ_START_CMD, 1422 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1423 WMI_TAG_THERMAL_MGMT_CMD, 1424 WMI_TAG_THERMAL_MGMT_EVENT, 1425 WMI_TAG_PEER_INFO_REQ_CMD, 1426 WMI_TAG_PEER_INFO_EVENT, 1427 WMI_TAG_PEER_INFO, 1428 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1429 WMI_TAG_RMC_SET_MODE_CMD, 1430 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1431 WMI_TAG_RMC_CONFIG_CMD, 1432 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1433 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1434 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1435 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1436 WMI_TAG_NAN_CMD_PARAM, 1437 WMI_TAG_NAN_EVENT_HDR, 1438 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1439 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1440 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1441 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1442 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1443 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1444 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1445 WMI_TAG_ROAM_SCAN_CMD, 1446 WMI_TAG_REQ_STATS_EXT_CMD, 1447 WMI_TAG_STATS_EXT_EVENT, 1448 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1449 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1450 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1451 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1452 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1453 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1454 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1455 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1456 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1457 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1458 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1459 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1460 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1461 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1462 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1463 WMI_TAG_START_LINK_STATS_CMD, 1464 WMI_TAG_CLEAR_LINK_STATS_CMD, 1465 WMI_TAG_REQUEST_LINK_STATS_CMD, 1466 WMI_TAG_IFACE_LINK_STATS_EVENT, 1467 WMI_TAG_RADIO_LINK_STATS_EVENT, 1468 WMI_TAG_PEER_STATS_EVENT, 1469 WMI_TAG_CHANNEL_STATS, 1470 WMI_TAG_RADIO_LINK_STATS, 1471 WMI_TAG_RATE_STATS, 1472 WMI_TAG_PEER_LINK_STATS, 1473 WMI_TAG_WMM_AC_STATS, 1474 WMI_TAG_IFACE_LINK_STATS, 1475 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1476 WMI_TAG_LPI_START_SCAN_CMD, 1477 WMI_TAG_LPI_STOP_SCAN_CMD, 1478 WMI_TAG_LPI_RESULT_EVENT, 1479 WMI_TAG_PEER_STATE_EVENT, 1480 WMI_TAG_EXTSCAN_BUCKET_CMD, 1481 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1482 WMI_TAG_EXTSCAN_START_CMD, 1483 WMI_TAG_EXTSCAN_STOP_CMD, 1484 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1485 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1486 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1487 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1488 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1489 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1490 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1491 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1492 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1493 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1494 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1495 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1496 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1497 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1498 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1499 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1500 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1501 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1502 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1503 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1504 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1505 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1506 WMI_TAG_UNIT_TEST_CMD, 1507 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1508 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1509 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1510 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1511 WMI_TAG_ROAM_SYNCH_EVENT, 1512 WMI_TAG_ROAM_SYNCH_COMPLETE, 1513 WMI_TAG_EXTWOW_ENABLE_CMD, 1514 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1515 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1516 WMI_TAG_LPI_STATUS_EVENT, 1517 WMI_TAG_LPI_HANDOFF_EVENT, 1518 WMI_TAG_VDEV_RATE_STATS_EVENT, 1519 WMI_TAG_VDEV_RATE_HT_INFO, 1520 WMI_TAG_RIC_REQUEST, 1521 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1522 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1523 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1524 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1525 WMI_TAG_RIC_TSPEC, 1526 WMI_TAG_TPC_CHAINMASK_CONFIG, 1527 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1528 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1529 WMI_TAG_KEY_MATERIAL, 1530 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1531 WMI_TAG_SET_LED_FLASHING_CMD, 1532 WMI_TAG_MDNS_OFFLOAD_CMD, 1533 WMI_TAG_MDNS_SET_FQDN_CMD, 1534 WMI_TAG_MDNS_SET_RESP_CMD, 1535 WMI_TAG_MDNS_GET_STATS_CMD, 1536 WMI_TAG_MDNS_STATS_EVENT, 1537 WMI_TAG_ROAM_INVOKE_CMD, 1538 WMI_TAG_PDEV_RESUME_EVENT, 1539 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1540 WMI_TAG_SAP_OFL_ENABLE_CMD, 1541 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1542 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1543 WMI_TAG_APFIND_CMD_PARAM, 1544 WMI_TAG_APFIND_EVENT_HDR, 1545 WMI_TAG_OCB_SET_SCHED_CMD, 1546 WMI_TAG_OCB_SET_SCHED_EVENT, 1547 WMI_TAG_OCB_SET_CONFIG_CMD, 1548 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1549 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1550 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1551 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1552 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1553 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1554 WMI_TAG_DCC_GET_STATS_CMD, 1555 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1556 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1557 WMI_TAG_DCC_CLEAR_STATS_CMD, 1558 WMI_TAG_DCC_UPDATE_NDL_CMD, 1559 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1560 WMI_TAG_DCC_STATS_EVENT, 1561 WMI_TAG_OCB_CHANNEL, 1562 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1563 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1564 WMI_TAG_DCC_NDL_CHAN, 1565 WMI_TAG_QOS_PARAMETER, 1566 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1567 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1568 WMI_TAG_ROAM_FILTER, 1569 WMI_TAG_PASSPOINT_CONFIG_CMD, 1570 WMI_TAG_PASSPOINT_EVENT_HDR, 1571 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1572 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1573 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1574 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1575 WMI_TAG_GET_FW_MEM_DUMP, 1576 WMI_TAG_UPDATE_FW_MEM_DUMP, 1577 WMI_TAG_FW_MEM_DUMP_PARAMS, 1578 WMI_TAG_DEBUG_MESG_FLUSH, 1579 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1580 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1581 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1582 WMI_TAG_VDEV_SET_IE_CMD, 1583 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1584 WMI_TAG_RSSI_BREACH_EVENT, 1585 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1586 WMI_TAG_SOC_SET_PCL_CMD, 1587 WMI_TAG_SOC_SET_HW_MODE_CMD, 1588 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1589 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1590 WMI_TAG_VDEV_TXRX_STREAMS, 1591 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1592 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1593 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1594 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1595 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1596 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1597 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1598 WMI_TAG_PACKET_FILTER_CONFIG, 1599 WMI_TAG_PACKET_FILTER_ENABLE, 1600 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1601 WMI_TAG_MGMT_TX_SEND_CMD, 1602 WMI_TAG_MGMT_TX_COMPL_EVENT, 1603 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1604 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1605 WMI_TAG_LRO_INFO_CMD, 1606 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1607 WMI_TAG_SERVICE_READY_EXT_EVENT, 1608 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1609 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1610 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1611 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1612 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1613 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1614 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1615 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1616 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1617 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1618 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1619 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1620 WMI_TAG_SCPC_EVENT, 1621 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1622 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1623 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1624 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1625 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1626 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1627 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1628 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1629 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1630 WMI_TAG_PEER_DELETE_RESP_EVENT, 1631 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1632 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1633 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1634 WMI_TAG_VDEV_CONFIG_RATEMASK, 1635 WMI_TAG_PDEV_FIPS_CMD, 1636 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1637 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1638 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1639 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1640 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1641 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1642 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1643 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1644 WMI_TAG_FWTEST_SET_PARAM_CMD, 1645 WMI_TAG_PEER_ATF_REQUEST, 1646 WMI_TAG_VDEV_ATF_REQUEST, 1647 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1648 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1649 WMI_TAG_INST_RSSI_STATS_RESP, 1650 WMI_TAG_MED_UTIL_REPORT_EVENT, 1651 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1652 WMI_TAG_WDS_ADDR_EVENT, 1653 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1654 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1655 WMI_TAG_PDEV_TPC_EVENT, 1656 WMI_TAG_ANI_OFDM_EVENT, 1657 WMI_TAG_ANI_CCK_EVENT, 1658 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1659 WMI_TAG_PDEV_FIPS_EVENT, 1660 WMI_TAG_ATF_PEER_INFO, 1661 WMI_TAG_PDEV_GET_TPC_CMD, 1662 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1663 WMI_TAG_QBOOST_CFG_CMD, 1664 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1665 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1666 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1667 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1668 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1669 WMI_TAG_PEER_MCS_RATE_INFO, 1670 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1671 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1672 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1673 WMI_TAG_MU_REPORT_TOTAL_MU, 1674 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1675 WMI_TAG_ROAM_SET_MBO, 1676 WMI_TAG_MIB_STATS_ENABLE_CMD, 1677 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1678 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1679 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1680 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1681 WMI_TAG_NDI_GET_CAP_REQ, 1682 WMI_TAG_NDP_INITIATOR_REQ, 1683 WMI_TAG_NDP_RESPONDER_REQ, 1684 WMI_TAG_NDP_END_REQ, 1685 WMI_TAG_NDI_CAP_RSP_EVENT, 1686 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1687 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1688 WMI_TAG_NDP_END_RSP_EVENT, 1689 WMI_TAG_NDP_INDICATION_EVENT, 1690 WMI_TAG_NDP_CONFIRM_EVENT, 1691 WMI_TAG_NDP_END_INDICATION_EVENT, 1692 WMI_TAG_VDEV_SET_QUIET_CMD, 1693 WMI_TAG_PDEV_SET_PCL_CMD, 1694 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1695 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1696 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1697 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1698 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1699 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1700 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1701 WMI_TAG_COEX_CONFIG_CMD, 1702 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1703 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1704 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1705 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1706 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1707 WMI_TAG_MAC_PHY_CAPABILITIES, 1708 WMI_TAG_HW_MODE_CAPABILITIES, 1709 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1710 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1711 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1712 WMI_TAG_VDEV_WISA_CMD, 1713 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1714 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1715 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1716 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1717 WMI_TAG_NDP_END_RSP_PER_NDI, 1718 WMI_TAG_PEER_BWF_REQUEST, 1719 WMI_TAG_BWF_PEER_INFO, 1720 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1721 WMI_TAG_RMC_SET_LEADER_CMD, 1722 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1723 WMI_TAG_PER_CHAIN_RSSI_STATS, 1724 WMI_TAG_RSSI_STATS, 1725 WMI_TAG_P2P_LO_START_CMD, 1726 WMI_TAG_P2P_LO_STOP_CMD, 1727 WMI_TAG_P2P_LO_STOPPED_EVENT, 1728 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1729 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1730 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1731 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1732 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1733 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1734 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1735 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1736 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1737 WMI_TAG_TLV_BUF_LEN_PARAM, 1738 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1739 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1740 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1741 WMI_TAG_PEER_ANTDIV_INFO, 1742 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1743 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1744 WMI_TAG_MNT_FILTER_CMD, 1745 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1746 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1747 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1748 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1749 WMI_TAG_CHAN_CCA_STATS, 1750 WMI_TAG_PEER_SIGNAL_STATS, 1751 WMI_TAG_TX_STATS, 1752 WMI_TAG_PEER_AC_TX_STATS, 1753 WMI_TAG_RX_STATS, 1754 WMI_TAG_PEER_AC_RX_STATS, 1755 WMI_TAG_REPORT_STATS_EVENT, 1756 WMI_TAG_CHAN_CCA_STATS_THRESH, 1757 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1758 WMI_TAG_TX_STATS_THRESH, 1759 WMI_TAG_RX_STATS_THRESH, 1760 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1761 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1762 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1763 WMI_TAG_RX_AGGR_FAILURE_INFO, 1764 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1765 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1766 WMI_TAG_PDEV_BAND_TO_MAC, 1767 WMI_TAG_TBTT_OFFSET_INFO, 1768 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1769 WMI_TAG_SAR_LIMITS_CMD, 1770 WMI_TAG_SAR_LIMIT_CMD_ROW, 1771 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1772 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1773 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1774 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1775 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1776 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1777 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1778 WMI_TAG_VENDOR_OUI, 1779 WMI_TAG_REQUEST_RCPI_CMD, 1780 WMI_TAG_UPDATE_RCPI_EVENT, 1781 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1782 WMI_TAG_PEER_STATS_INFO, 1783 WMI_TAG_PEER_STATS_INFO_EVENT, 1784 WMI_TAG_PKGID_EVENT, 1785 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1786 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1787 WMI_TAG_REGULATORY_RULE_STRUCT, 1788 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1789 WMI_TAG_11D_SCAN_START_CMD, 1790 WMI_TAG_11D_SCAN_STOP_CMD, 1791 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1792 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1793 WMI_TAG_RADIO_CHAN_STATS, 1794 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1795 WMI_TAG_ROAM_PER_CONFIG, 1796 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1797 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1798 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1799 WMI_TAG_HW_DATA_FILTER_CMD, 1800 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1801 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1802 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1803 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1804 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1805 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1806 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1807 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1808 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1809 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1810 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1811 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1812 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1813 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1814 WMI_TAG_IFACE_OFFLOAD_STATS, 1815 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1816 WMI_TAG_RSSI_CTL_EXT, 1817 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1818 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1819 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1820 WMI_TAG_VDEV_TX_POWER_EVENT, 1821 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1822 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1823 WMI_TAG_TX_SEND_PARAMS, 1824 WMI_TAG_HE_RATE_SET, 1825 WMI_TAG_CONGESTION_STATS, 1826 WMI_TAG_SET_INIT_COUNTRY_CMD, 1827 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1828 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1829 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1830 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1831 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1832 WMI_TAG_THERM_THROT_STATS_EVENT, 1833 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1834 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1835 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1836 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1837 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1838 WMI_TAG_OEM_INDIRECT_DATA, 1839 WMI_TAG_OEM_DMA_BUF_RELEASE, 1840 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1841 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1842 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1843 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1844 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1845 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1846 WMI_TAG_UNIT_TEST_EVENT, 1847 WMI_TAG_ROAM_FILS_OFFLOAD, 1848 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1849 WMI_TAG_PMK_CACHE, 1850 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1851 WMI_TAG_ROAM_FILS_SYNCH, 1852 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1853 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1854 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1855 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1856 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1857 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1858 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1859 WMI_TAG_BTM_CONFIG, 1860 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1861 WMI_TAG_WLM_CONFIG_CMD, 1862 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1863 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1864 WMI_TAG_ROAM_CND_SCORING_PARAM, 1865 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1866 WMI_TAG_VENDOR_OUI_EXT, 1867 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1868 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1869 WMI_TAG_ENABLE_FILS_CMD, 1870 WMI_TAG_HOST_SWFDA_EVENT, 1871 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1872 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1873 WMI_TAG_STATS_PERIOD, 1874 WMI_TAG_NDL_SCHEDULE_UPDATE, 1875 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1876 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1877 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1878 WMI_TAG_SAR2_RESULT_EVENT, 1879 WMI_TAG_SAR_CAPABILITIES, 1880 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1881 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1882 WMI_TAG_DMA_RING_CAPABILITIES, 1883 WMI_TAG_DMA_RING_CFG_REQ, 1884 WMI_TAG_DMA_RING_CFG_RSP, 1885 WMI_TAG_DMA_BUF_RELEASE, 1886 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1887 WMI_TAG_SAR_GET_LIMITS_CMD, 1888 WMI_TAG_SAR_GET_LIMITS_EVENT, 1889 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1890 WMI_TAG_OFFLOAD_11K_REPORT, 1891 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1892 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1893 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1894 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1895 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1896 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1897 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1898 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1899 WMI_TAG_PDEV_GET_NFCAL_POWER, 1900 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1901 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1902 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1903 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1904 WMI_TAG_TWT_ENABLE_CMD, 1905 WMI_TAG_TWT_DISABLE_CMD, 1906 WMI_TAG_TWT_ADD_DIALOG_CMD, 1907 WMI_TAG_TWT_DEL_DIALOG_CMD, 1908 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1909 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1910 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1911 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1912 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1913 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1914 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1915 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1916 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1917 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1918 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1919 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1920 WMI_TAG_GET_TPC_POWER_CMD, 1921 WMI_TAG_GET_TPC_POWER_EVENT, 1922 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1923 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1924 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1925 WMI_TAG_MOTION_DET_START_STOP_CMD, 1926 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1927 WMI_TAG_MOTION_DET_EVENT, 1928 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1929 WMI_TAG_NDP_TRANSPORT_IP, 1930 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1931 WMI_TAG_ESP_ESTIMATE_EVENT, 1932 WMI_TAG_NAN_HOST_CONFIG, 1933 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1934 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1935 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1936 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1937 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1938 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1939 WMI_TAG_PEER_EXTD2_STATS, 1940 WMI_TAG_HPCS_PULSE_START_CMD, 1941 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1942 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1943 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1944 WMI_TAG_NAN_EVENT_INFO, 1945 WMI_TAG_NDP_CHANNEL_INFO, 1946 WMI_TAG_NDP_CMD, 1947 WMI_TAG_NDP_EVENT, 1948 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1949 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1950 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 1951 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, 1952 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 1953 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, 1954 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1955 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 1956 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1957 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, 1958 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, 1959 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 1960 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, 1961 WMI_TAG_MAX 1962 }; 1963 1964 enum wmi_tlv_service { 1965 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 1966 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 1967 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 1968 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 1969 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 1970 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 1971 WMI_TLV_SERVICE_AP_UAPSD = 6, 1972 WMI_TLV_SERVICE_AP_DFS = 7, 1973 WMI_TLV_SERVICE_11AC = 8, 1974 WMI_TLV_SERVICE_BLOCKACK = 9, 1975 WMI_TLV_SERVICE_PHYERR = 10, 1976 WMI_TLV_SERVICE_BCN_FILTER = 11, 1977 WMI_TLV_SERVICE_RTT = 12, 1978 WMI_TLV_SERVICE_WOW = 13, 1979 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 1980 WMI_TLV_SERVICE_IRAM_TIDS = 15, 1981 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 1982 WMI_TLV_SERVICE_NLO = 17, 1983 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 1984 WMI_TLV_SERVICE_SCAN_SCH = 19, 1985 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 1986 WMI_TLV_SERVICE_CHATTER = 21, 1987 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 1988 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 1989 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 1990 WMI_TLV_SERVICE_GPIO = 25, 1991 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 1992 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 1993 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 1994 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 1995 WMI_TLV_SERVICE_TX_ENCAP = 30, 1996 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 1997 WMI_TLV_SERVICE_EARLY_RX = 32, 1998 WMI_TLV_SERVICE_STA_SMPS = 33, 1999 WMI_TLV_SERVICE_FWTEST = 34, 2000 WMI_TLV_SERVICE_STA_WMMAC = 35, 2001 WMI_TLV_SERVICE_TDLS = 36, 2002 WMI_TLV_SERVICE_BURST = 37, 2003 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 2004 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 2005 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 2006 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 2007 WMI_TLV_SERVICE_WLAN_HB = 42, 2008 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 2009 WMI_TLV_SERVICE_BATCH_SCAN = 44, 2010 WMI_TLV_SERVICE_QPOWER = 45, 2011 WMI_TLV_SERVICE_PLMREQ = 46, 2012 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 2013 WMI_TLV_SERVICE_RMC = 48, 2014 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 2015 WMI_TLV_SERVICE_COEX_SAR = 50, 2016 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 2017 WMI_TLV_SERVICE_NAN = 52, 2018 WMI_TLV_SERVICE_L1SS_STAT = 53, 2019 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 2020 WMI_TLV_SERVICE_OBSS_SCAN = 55, 2021 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 2022 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 2023 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 2024 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 2025 WMI_TLV_SERVICE_LPASS = 60, 2026 WMI_TLV_SERVICE_EXTSCAN = 61, 2027 WMI_TLV_SERVICE_D0WOW = 62, 2028 WMI_TLV_SERVICE_HSOFFLOAD = 63, 2029 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 2030 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 2031 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 2032 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 2033 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 2034 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 2035 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 2036 WMI_TLV_SERVICE_OCB = 71, 2037 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 2038 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 2039 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 2040 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 2041 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 2042 WMI_TLV_SERVICE_EXT_MSG = 77, 2043 WMI_TLV_SERVICE_MAWC = 78, 2044 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 2045 WMI_TLV_SERVICE_EGAP = 80, 2046 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 2047 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 2048 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 2049 WMI_TLV_SERVICE_ATF = 84, 2050 WMI_TLV_SERVICE_COEX_GPIO = 85, 2051 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 2052 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 2053 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 2054 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 2055 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 2056 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 2057 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 2058 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 2059 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 2060 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 2061 WMI_TLV_SERVICE_NAN_DATA = 96, 2062 WMI_TLV_SERVICE_NAN_RTT = 97, 2063 WMI_TLV_SERVICE_11AX = 98, 2064 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 2065 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 2066 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 2067 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 2068 WMI_TLV_SERVICE_MESH_11S = 103, 2069 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 2070 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 2071 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 2072 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 2073 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 2074 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 2075 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 2076 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 2077 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 2078 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 2079 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 2080 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 2081 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 2082 WMI_TLV_SERVICE_REGULATORY_DB = 117, 2083 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 2084 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 2085 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 2086 WMI_TLV_SERVICE_PKT_ROUTING = 121, 2087 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 2088 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 2089 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 2090 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2091 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2092 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2093 2094 /* The first 128 bits */ 2095 WMI_MAX_SERVICE = 128, 2096 2097 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2098 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2099 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2100 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2101 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2102 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2103 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2104 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2105 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2106 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2107 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2108 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2109 WMI_TLV_SERVICE_THERM_THROT = 140, 2110 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2111 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2112 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2113 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2114 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2115 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2116 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2117 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2118 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2119 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2120 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2121 WMI_TLV_SERVICE_STA_TWT = 152, 2122 WMI_TLV_SERVICE_AP_TWT = 153, 2123 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2124 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2125 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2126 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2127 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2128 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2129 WMI_TLV_SERVICE_MOTION_DET = 160, 2130 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2131 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2132 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2133 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2134 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2135 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2136 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2137 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2138 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2139 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2140 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2141 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2142 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2143 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2144 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2145 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2146 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2147 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2148 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2149 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2150 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2151 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2152 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2153 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2154 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2155 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2156 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2157 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2158 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2159 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2160 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2161 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2162 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2163 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2164 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2165 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2166 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2167 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2168 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2169 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2170 WMI_TLV_SERVICE_PS_TDCC = 201, 2171 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2172 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2173 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2174 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2175 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2176 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2177 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2178 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2179 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2180 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2181 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2182 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2183 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2184 WMI_TLV_SERVICE_EXT2_MSG = 220, 2185 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, 2186 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, 2187 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, 2188 WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, 2189 2190 /* The second 128 bits */ 2191 WMI_MAX_EXT_SERVICE = 256, 2192 WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, 2193 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, 2194 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, 2195 WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, 2196 2197 /* The third 128 bits */ 2198 WMI_MAX_EXT2_SERVICE = 384 2199 }; 2200 2201 enum { 2202 WMI_SMPS_FORCED_MODE_NONE = 0, 2203 WMI_SMPS_FORCED_MODE_DISABLED, 2204 WMI_SMPS_FORCED_MODE_STATIC, 2205 WMI_SMPS_FORCED_MODE_DYNAMIC 2206 }; 2207 2208 #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0 2209 #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1 2210 #define WMI_NUM_SUPPORTED_BAND_MAX 2 2211 2212 #define WMI_PEER_MIMO_PS_STATE 0x1 2213 #define WMI_PEER_AMPDU 0x2 2214 #define WMI_PEER_AUTHORIZE 0x3 2215 #define WMI_PEER_CHWIDTH 0x4 2216 #define WMI_PEER_NSS 0x5 2217 #define WMI_PEER_USE_4ADDR 0x6 2218 #define WMI_PEER_MEMBERSHIP 0x7 2219 #define WMI_PEER_USERPOS 0x8 2220 #define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 2221 #define WMI_PEER_TX_FAIL_CNT_THR 0xA 2222 #define WMI_PEER_SET_HW_RETRY_CTS2S 0xB 2223 #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC 2224 #define WMI_PEER_PHYMODE 0xD 2225 #define WMI_PEER_USE_FIXED_PWR 0xE 2226 #define WMI_PEER_PARAM_FIXED_RATE 0xF 2227 #define WMI_PEER_SET_MU_WHITELIST 0x10 2228 #define WMI_PEER_SET_MAX_TX_RATE 0x11 2229 #define WMI_PEER_SET_MIN_TX_RATE 0x12 2230 #define WMI_PEER_SET_DEFAULT_ROUTING 0x13 2231 2232 /* slot time long */ 2233 #define WMI_VDEV_SLOT_TIME_LONG 0x1 2234 /* slot time short */ 2235 #define WMI_VDEV_SLOT_TIME_SHORT 0x2 2236 /* preablbe long */ 2237 #define WMI_VDEV_PREAMBLE_LONG 0x1 2238 /* preablbe short */ 2239 #define WMI_VDEV_PREAMBLE_SHORT 0x2 2240 2241 enum wmi_peer_smps_state { 2242 WMI_PEER_SMPS_PS_NONE = 0x0, 2243 WMI_PEER_SMPS_STATIC = 0x1, 2244 WMI_PEER_SMPS_DYNAMIC = 0x2 2245 }; 2246 2247 enum wmi_peer_chwidth { 2248 WMI_PEER_CHWIDTH_20MHZ = 0, 2249 WMI_PEER_CHWIDTH_40MHZ = 1, 2250 WMI_PEER_CHWIDTH_80MHZ = 2, 2251 WMI_PEER_CHWIDTH_160MHZ = 3, 2252 }; 2253 2254 enum wmi_beacon_gen_mode { 2255 WMI_BEACON_STAGGERED_MODE = 0, 2256 WMI_BEACON_BURST_MODE = 1 2257 }; 2258 2259 enum wmi_direct_buffer_module { 2260 WMI_DIRECT_BUF_SPECTRAL = 0, 2261 WMI_DIRECT_BUF_CFR = 1, 2262 2263 /* keep it last */ 2264 WMI_DIRECT_BUF_MAX 2265 }; 2266 2267 /* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext 2268 * event 2269 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss 2270 * of 80MHz 2271 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss 2272 * of 80MHz 2273 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz 2274 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max 2275 * nss of 80MHz 2276 */ 2277 2278 enum wmi_nss_ratio { 2279 WMI_NSS_RATIO_1BY2_NSS = 0x0, 2280 WMI_NSS_RATIO_3BY4_NSS = 0x1, 2281 WMI_NSS_RATIO_1_NSS = 0x2, 2282 WMI_NSS_RATIO_2_NSS = 0x3, 2283 }; 2284 2285 enum wmi_dtim_policy { 2286 WMI_DTIM_POLICY_IGNORE = 1, 2287 WMI_DTIM_POLICY_NORMAL = 2, 2288 WMI_DTIM_POLICY_STICK = 3, 2289 WMI_DTIM_POLICY_AUTO = 4, 2290 }; 2291 2292 struct wmi_host_pdev_band_to_mac { 2293 uint32_t pdev_id; 2294 uint32_t start_freq; 2295 uint32_t end_freq; 2296 }; 2297 2298 struct ath11k_ppe_threshold { 2299 uint32_t numss_m1; 2300 uint32_t ru_bit_mask; 2301 uint32_t ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS]; 2302 }; 2303 2304 struct ath11k_service_ext_param { 2305 uint32_t default_conc_scan_config_bits; 2306 uint32_t default_fw_config_bits; 2307 struct ath11k_ppe_threshold ppet; 2308 uint32_t he_cap_info; 2309 uint32_t mpdu_density; 2310 uint32_t max_bssid_rx_filters; 2311 uint32_t num_hw_modes; 2312 uint32_t num_phy; 2313 }; 2314 2315 struct ath11k_hw_mode_caps { 2316 uint32_t hw_mode_id; 2317 uint32_t phy_id_map; 2318 uint32_t hw_mode_config_type; 2319 }; 2320 2321 #define PSOC_HOST_MAX_PHY_SIZE (3) 2322 #define ATH11K_11B_SUPPORT BIT(0) 2323 #define ATH11K_11G_SUPPORT BIT(1) 2324 #define ATH11K_11A_SUPPORT BIT(2) 2325 #define ATH11K_11N_SUPPORT BIT(3) 2326 #define ATH11K_11AC_SUPPORT BIT(4) 2327 #define ATH11K_11AX_SUPPORT BIT(5) 2328 2329 struct ath11k_hal_reg_capabilities_ext { 2330 uint32_t phy_id; 2331 uint32_t eeprom_reg_domain; 2332 uint32_t eeprom_reg_domain_ext; 2333 uint32_t regcap1; 2334 uint32_t regcap2; 2335 uint32_t wireless_modes; 2336 uint32_t low_2ghz_chan; 2337 uint32_t high_2ghz_chan; 2338 uint32_t low_5ghz_chan; 2339 uint32_t high_5ghz_chan; 2340 }; 2341 2342 #define WMI_HOST_MAX_PDEV 3 2343 2344 struct wlan_host_mem_chunk { 2345 uint32_t tlv_header; 2346 uint32_t req_id; 2347 uint32_t ptr; 2348 uint32_t size; 2349 } __packed; 2350 2351 struct wmi_host_mem_chunk { 2352 void *vaddr; 2353 bus_addr_t paddr; 2354 uint32_t len; 2355 uint32_t req_id; 2356 }; 2357 2358 struct wmi_init_cmd_param { 2359 uint32_t tlv_header; 2360 struct target_resource_config *res_cfg; 2361 uint8_t num_mem_chunks; 2362 struct wmi_host_mem_chunk *mem_chunks; 2363 uint32_t hw_mode_id; 2364 uint32_t num_band_to_mac; 2365 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV]; 2366 }; 2367 2368 struct wmi_pdev_band_to_mac { 2369 uint32_t tlv_header; 2370 uint32_t pdev_id; 2371 uint32_t start_freq; 2372 uint32_t end_freq; 2373 } __packed; 2374 2375 struct wmi_pdev_set_hw_mode_cmd_param { 2376 uint32_t tlv_header; 2377 uint32_t pdev_id; 2378 uint32_t hw_mode_index; 2379 uint32_t num_band_to_mac; 2380 } __packed; 2381 2382 struct wmi_ppe_threshold { 2383 uint32_t numss_m1; /** NSS - 1*/ 2384 union { 2385 uint32_t ru_count; 2386 uint32_t ru_mask; 2387 } __packed; 2388 uint32_t ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2389 } __packed; 2390 2391 #define HW_BD_INFO_SIZE 5 2392 2393 struct wmi_abi_version { 2394 uint32_t abi_version_0; 2395 uint32_t abi_version_1; 2396 uint32_t abi_version_ns_0; 2397 uint32_t abi_version_ns_1; 2398 uint32_t abi_version_ns_2; 2399 uint32_t abi_version_ns_3; 2400 } __packed; 2401 2402 struct wmi_init_cmd { 2403 uint32_t tlv_header; 2404 struct wmi_abi_version host_abi_vers; 2405 uint32_t num_host_mem_chunks; 2406 } __packed; 2407 2408 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2409 #define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9) 2410 #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) 2411 2412 #define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4 2413 2414 struct wmi_resource_config { 2415 uint32_t tlv_header; 2416 uint32_t num_vdevs; 2417 uint32_t num_peers; 2418 uint32_t num_offload_peers; 2419 uint32_t num_offload_reorder_buffs; 2420 uint32_t num_peer_keys; 2421 uint32_t num_tids; 2422 uint32_t ast_skid_limit; 2423 uint32_t tx_chain_mask; 2424 uint32_t rx_chain_mask; 2425 uint32_t rx_timeout_pri[4]; 2426 uint32_t rx_decap_mode; 2427 uint32_t scan_max_pending_req; 2428 uint32_t bmiss_offload_max_vdev; 2429 uint32_t roam_offload_max_vdev; 2430 uint32_t roam_offload_max_ap_profiles; 2431 uint32_t num_mcast_groups; 2432 uint32_t num_mcast_table_elems; 2433 uint32_t mcast2ucast_mode; 2434 uint32_t tx_dbg_log_size; 2435 uint32_t num_wds_entries; 2436 uint32_t dma_burst_size; 2437 uint32_t mac_aggr_delim; 2438 uint32_t rx_skip_defrag_timeout_dup_detection_check; 2439 uint32_t vow_config; 2440 uint32_t gtk_offload_max_vdev; 2441 uint32_t num_msdu_desc; 2442 uint32_t max_frag_entries; 2443 uint32_t num_tdls_vdevs; 2444 uint32_t num_tdls_conn_table_entries; 2445 uint32_t beacon_tx_offload_max_vdev; 2446 uint32_t num_multicast_filter_entries; 2447 uint32_t num_wow_filters; 2448 uint32_t num_keep_alive_pattern; 2449 uint32_t keep_alive_pattern_size; 2450 uint32_t max_tdls_concurrent_sleep_sta; 2451 uint32_t max_tdls_concurrent_buffer_sta; 2452 uint32_t wmi_send_separate; 2453 uint32_t num_ocb_vdevs; 2454 uint32_t num_ocb_channels; 2455 uint32_t num_ocb_schedules; 2456 uint32_t flag1; 2457 uint32_t smart_ant_cap; 2458 uint32_t bk_minfree; 2459 uint32_t be_minfree; 2460 uint32_t vi_minfree; 2461 uint32_t vo_minfree; 2462 uint32_t alloc_frag_desc_for_data_pkt; 2463 uint32_t num_ns_ext_tuples_cfg; 2464 uint32_t bpf_instruction_size; 2465 uint32_t max_bssid_rx_filters; 2466 uint32_t use_pdev_id; 2467 uint32_t max_num_dbs_scan_duty_cycle; 2468 uint32_t max_num_group_keys; 2469 uint32_t peer_map_unmap_v2_support; 2470 uint32_t sched_params; 2471 uint32_t twt_ap_pdev_count; 2472 uint32_t twt_ap_sta_count; 2473 #ifdef notyet /* 6 GHz support */ 2474 uint32_t max_nlo_ssids; 2475 uint32_t num_pkt_filters; 2476 uint32_t num_max_sta_vdevs; 2477 uint32_t max_bssid_indicator; 2478 uint32_t ul_resp_config; 2479 uint32_t msdu_flow_override_config0; 2480 uint32_t msdu_flow_override_config1; 2481 uint32_t flags2; 2482 uint32_t host_service_flags; 2483 uint32_t max_rnr_neighbours; 2484 uint32_t ema_max_vap_cnt; 2485 uint32_t ema_max_profile_period; 2486 #endif 2487 } __packed; 2488 2489 struct wmi_service_ready_event { 2490 uint32_t fw_build_vers; 2491 struct wmi_abi_version fw_abi_vers; 2492 uint32_t phy_capability; 2493 uint32_t max_frag_entry; 2494 uint32_t num_rf_chains; 2495 uint32_t ht_cap_info; 2496 uint32_t vht_cap_info; 2497 uint32_t vht_supp_mcs; 2498 uint32_t hw_min_tx_power; 2499 uint32_t hw_max_tx_power; 2500 uint32_t sys_cap_info; 2501 uint32_t min_pkt_size_enable; 2502 uint32_t max_bcn_ie_size; 2503 uint32_t num_mem_reqs; 2504 uint32_t max_num_scan_channels; 2505 uint32_t hw_bd_id; 2506 uint32_t hw_bd_info[HW_BD_INFO_SIZE]; 2507 uint32_t max_supported_macs; 2508 uint32_t wmi_fw_sub_feat_caps; 2509 uint32_t num_dbs_hw_modes; 2510 /* txrx_chainmask 2511 * [7:0] - 2G band tx chain mask 2512 * [15:8] - 2G band rx chain mask 2513 * [23:16] - 5G band tx chain mask 2514 * [31:24] - 5G band rx chain mask 2515 */ 2516 uint32_t txrx_chainmask; 2517 uint32_t default_dbs_hw_mode_index; 2518 uint32_t num_msdu_desc; 2519 } __packed; 2520 2521 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(uint32_t) - 1) / sizeof(uint32_t)) 2522 2523 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x uint32_t = 128 bits */ 2524 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(uint32_t)) 2525 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2526 #define WMI_SERVICE_BITS_IN_SIZE32 4 2527 2528 struct wmi_service_ready_ext_event { 2529 uint32_t default_conc_scan_config_bits; 2530 uint32_t default_fw_config_bits; 2531 struct wmi_ppe_threshold ppet; 2532 uint32_t he_cap_info; 2533 uint32_t mpdu_density; 2534 uint32_t max_bssid_rx_filters; 2535 uint32_t fw_build_vers_ext; 2536 uint32_t max_nlo_ssids; 2537 uint32_t max_bssid_indicator; 2538 uint32_t he_cap_info_ext; 2539 } __packed; 2540 2541 struct wmi_soc_mac_phy_hw_mode_caps { 2542 uint32_t num_hw_modes; 2543 uint32_t num_chainmask_tables; 2544 } __packed; 2545 2546 struct wmi_hw_mode_capabilities { 2547 uint32_t tlv_header; 2548 uint32_t hw_mode_id; 2549 uint32_t phy_id_map; 2550 uint32_t hw_mode_config_type; 2551 } __packed; 2552 2553 #define WMI_MAX_HECAP_PHY_SIZE (3) 2554 #define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0) 2555 #define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \ 2556 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val) 2557 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) 2558 #define WMI_NSS_RATIO_INFO_GET(_val) \ 2559 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val) 2560 2561 struct wmi_mac_phy_capabilities { 2562 uint32_t hw_mode_id; 2563 uint32_t pdev_id; 2564 uint32_t phy_id; 2565 uint32_t supported_flags; 2566 uint32_t supported_bands; 2567 uint32_t ampdu_density; 2568 uint32_t max_bw_supported_2g; 2569 uint32_t ht_cap_info_2g; 2570 uint32_t vht_cap_info_2g; 2571 uint32_t vht_supp_mcs_2g; 2572 uint32_t he_cap_info_2g; 2573 uint32_t he_supp_mcs_2g; 2574 uint32_t tx_chain_mask_2g; 2575 uint32_t rx_chain_mask_2g; 2576 uint32_t max_bw_supported_5g; 2577 uint32_t ht_cap_info_5g; 2578 uint32_t vht_cap_info_5g; 2579 uint32_t vht_supp_mcs_5g; 2580 uint32_t he_cap_info_5g; 2581 uint32_t he_supp_mcs_5g; 2582 uint32_t tx_chain_mask_5g; 2583 uint32_t rx_chain_mask_5g; 2584 uint32_t he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2585 uint32_t he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2586 struct wmi_ppe_threshold he_ppet2g; 2587 struct wmi_ppe_threshold he_ppet5g; 2588 uint32_t chainmask_table_id; 2589 uint32_t lmac_id; 2590 uint32_t he_cap_info_2g_ext; 2591 uint32_t he_cap_info_5g_ext; 2592 uint32_t he_cap_info_internal; 2593 uint32_t wireless_modes; 2594 uint32_t low_2ghz_chan_freq; 2595 uint32_t high_2ghz_chan_freq; 2596 uint32_t low_5ghz_chan_freq; 2597 uint32_t high_5ghz_chan_freq; 2598 uint32_t nss_ratio; 2599 } __packed; 2600 2601 struct wmi_hal_reg_capabilities_ext { 2602 uint32_t tlv_header; 2603 uint32_t phy_id; 2604 uint32_t eeprom_reg_domain; 2605 uint32_t eeprom_reg_domain_ext; 2606 uint32_t regcap1; 2607 uint32_t regcap2; 2608 uint32_t wireless_modes; 2609 uint32_t low_2ghz_chan; 2610 uint32_t high_2ghz_chan; 2611 uint32_t low_5ghz_chan; 2612 uint32_t high_5ghz_chan; 2613 } __packed; 2614 2615 struct wmi_soc_hal_reg_capabilities { 2616 uint32_t num_phy; 2617 } __packed; 2618 2619 /* 2 word representation of MAC addr */ 2620 struct wmi_mac_addr { 2621 union { 2622 uint8_t addr[6]; 2623 struct { 2624 uint32_t word0; 2625 uint32_t word1; 2626 } __packed; 2627 } __packed; 2628 } __packed; 2629 2630 struct wmi_dma_ring_capabilities { 2631 uint32_t tlv_header; 2632 uint32_t pdev_id; 2633 uint32_t module_id; 2634 uint32_t min_elem; 2635 uint32_t min_buf_sz; 2636 uint32_t min_buf_align; 2637 } __packed; 2638 2639 struct wmi_ready_event_min { 2640 struct wmi_abi_version fw_abi_vers; 2641 struct wmi_mac_addr mac_addr; 2642 uint32_t status; 2643 uint32_t num_dscp_table; 2644 uint32_t num_extra_mac_addr; 2645 uint32_t num_total_peers; 2646 uint32_t num_extra_peers; 2647 } __packed; 2648 2649 struct wmi_ready_event { 2650 struct wmi_ready_event_min ready_event_min; 2651 uint32_t max_ast_index; 2652 uint32_t pktlog_defs_checksum; 2653 } __packed; 2654 2655 struct wmi_service_available_event { 2656 uint32_t wmi_service_segment_offset; 2657 uint32_t wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2658 } __packed; 2659 2660 struct vdev_create_params { 2661 uint8_t if_id; 2662 uint32_t type; 2663 uint32_t subtype; 2664 struct { 2665 uint8_t tx; 2666 uint8_t rx; 2667 } chains[2]; 2668 uint32_t pdev_id; 2669 uint32_t mbssid_flags; 2670 uint32_t mbssid_tx_vdev_id; 2671 }; 2672 2673 struct wmi_vdev_create_cmd { 2674 uint32_t tlv_header; 2675 uint32_t vdev_id; 2676 uint32_t vdev_type; 2677 uint32_t vdev_subtype; 2678 struct wmi_mac_addr vdev_macaddr; 2679 uint32_t num_cfg_txrx_streams; 2680 uint32_t pdev_id; 2681 uint32_t mbssid_flags; 2682 uint32_t mbssid_tx_vdev_id; 2683 } __packed; 2684 2685 struct wmi_vdev_txrx_streams { 2686 uint32_t tlv_header; 2687 uint32_t band; 2688 uint32_t supported_tx_streams; 2689 uint32_t supported_rx_streams; 2690 } __packed; 2691 2692 struct wmi_vdev_delete_cmd { 2693 uint32_t tlv_header; 2694 uint32_t vdev_id; 2695 } __packed; 2696 2697 struct wmi_vdev_up_cmd { 2698 uint32_t tlv_header; 2699 uint32_t vdev_id; 2700 uint32_t vdev_assoc_id; 2701 struct wmi_mac_addr vdev_bssid; 2702 struct wmi_mac_addr tx_vdev_bssid; 2703 uint32_t nontx_profile_idx; 2704 uint32_t nontx_profile_cnt; 2705 } __packed; 2706 2707 struct wmi_vdev_stop_cmd { 2708 uint32_t tlv_header; 2709 uint32_t vdev_id; 2710 } __packed; 2711 2712 struct wmi_vdev_down_cmd { 2713 uint32_t tlv_header; 2714 uint32_t vdev_id; 2715 } __packed; 2716 2717 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 2718 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 2719 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 2720 #define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4) 2721 2722 struct wmi_ssid { 2723 uint32_t ssid_len; 2724 uint32_t ssid[8]; 2725 } __packed; 2726 2727 #define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ) 2728 2729 struct wmi_vdev_start_request_cmd { 2730 uint32_t tlv_header; 2731 uint32_t vdev_id; 2732 uint32_t requestor_id; 2733 uint32_t beacon_interval; 2734 uint32_t dtim_period; 2735 uint32_t flags; 2736 struct wmi_ssid ssid; 2737 uint32_t bcn_tx_rate; 2738 uint32_t bcn_txpower; 2739 uint32_t num_noa_descriptors; 2740 uint32_t disable_hw_ack; 2741 uint32_t preferred_tx_streams; 2742 uint32_t preferred_rx_streams; 2743 uint32_t he_ops; 2744 uint32_t cac_duration_ms; 2745 uint32_t regdomain; 2746 uint32_t min_data_rate; 2747 uint32_t mbssid_flags; 2748 uint32_t mbssid_tx_vdev_id; 2749 } __packed; 2750 2751 #define MGMT_TX_DL_FRM_LEN 64 2752 #define WMI_MAC_MAX_SSID_LENGTH 32 2753 struct mac_ssid { 2754 uint8_t length; 2755 uint8_t mac_ssid[WMI_MAC_MAX_SSID_LENGTH]; 2756 } __packed; 2757 2758 struct wmi_p2p_noa_descriptor { 2759 uint32_t type_count; 2760 uint32_t duration; 2761 uint32_t interval; 2762 uint32_t start_time; 2763 }; 2764 2765 struct channel_param { 2766 uint8_t chan_id; 2767 uint8_t pwr; 2768 uint32_t mhz; 2769 uint32_t half_rate:1, 2770 quarter_rate:1, 2771 dfs_set:1, 2772 dfs_set_cfreq2:1, 2773 is_chan_passive:1, 2774 allow_ht:1, 2775 allow_vht:1, 2776 allow_he:1, 2777 set_agile:1, 2778 psc_channel:1; 2779 uint32_t phy_mode; 2780 uint32_t cfreq1; 2781 uint32_t cfreq2; 2782 char maxpower; 2783 char minpower; 2784 char maxregpower; 2785 uint8_t antennamax; 2786 uint8_t reg_class_id; 2787 } __packed; 2788 2789 enum wmi_phy_mode { 2790 MODE_11A = 0, 2791 MODE_11G = 1, /* 11b/g Mode */ 2792 MODE_11B = 2, /* 11b Mode */ 2793 MODE_11GONLY = 3, /* 11g only Mode */ 2794 MODE_11NA_HT20 = 4, 2795 MODE_11NG_HT20 = 5, 2796 MODE_11NA_HT40 = 6, 2797 MODE_11NG_HT40 = 7, 2798 MODE_11AC_VHT20 = 8, 2799 MODE_11AC_VHT40 = 9, 2800 MODE_11AC_VHT80 = 10, 2801 MODE_11AC_VHT20_2G = 11, 2802 MODE_11AC_VHT40_2G = 12, 2803 MODE_11AC_VHT80_2G = 13, 2804 MODE_11AC_VHT80_80 = 14, 2805 MODE_11AC_VHT160 = 15, 2806 MODE_11AX_HE20 = 16, 2807 MODE_11AX_HE40 = 17, 2808 MODE_11AX_HE80 = 18, 2809 MODE_11AX_HE80_80 = 19, 2810 MODE_11AX_HE160 = 20, 2811 MODE_11AX_HE20_2G = 21, 2812 MODE_11AX_HE40_2G = 22, 2813 MODE_11AX_HE80_2G = 23, 2814 MODE_UNKNOWN = 24, 2815 MODE_MAX = 24 2816 }; 2817 2818 static inline const char *qwx_wmi_phymode_str(enum wmi_phy_mode mode) 2819 { 2820 switch (mode) { 2821 case MODE_11A: 2822 return "11a"; 2823 case MODE_11G: 2824 return "11g"; 2825 case MODE_11B: 2826 return "11b"; 2827 case MODE_11GONLY: 2828 return "11gonly"; 2829 case MODE_11NA_HT20: 2830 return "11na-ht20"; 2831 case MODE_11NG_HT20: 2832 return "11ng-ht20"; 2833 case MODE_11NA_HT40: 2834 return "11na-ht40"; 2835 case MODE_11NG_HT40: 2836 return "11ng-ht40"; 2837 case MODE_11AC_VHT20: 2838 return "11ac-vht20"; 2839 case MODE_11AC_VHT40: 2840 return "11ac-vht40"; 2841 case MODE_11AC_VHT80: 2842 return "11ac-vht80"; 2843 case MODE_11AC_VHT160: 2844 return "11ac-vht160"; 2845 case MODE_11AC_VHT80_80: 2846 return "11ac-vht80+80"; 2847 case MODE_11AC_VHT20_2G: 2848 return "11ac-vht20-2g"; 2849 case MODE_11AC_VHT40_2G: 2850 return "11ac-vht40-2g"; 2851 case MODE_11AC_VHT80_2G: 2852 return "11ac-vht80-2g"; 2853 case MODE_11AX_HE20: 2854 return "11ax-he20"; 2855 case MODE_11AX_HE40: 2856 return "11ax-he40"; 2857 case MODE_11AX_HE80: 2858 return "11ax-he80"; 2859 case MODE_11AX_HE80_80: 2860 return "11ax-he80+80"; 2861 case MODE_11AX_HE160: 2862 return "11ax-he160"; 2863 case MODE_11AX_HE20_2G: 2864 return "11ax-he20-2g"; 2865 case MODE_11AX_HE40_2G: 2866 return "11ax-he40-2g"; 2867 case MODE_11AX_HE80_2G: 2868 return "11ax-he80-2g"; 2869 case MODE_UNKNOWN: 2870 /* skip */ 2871 break; 2872 2873 /* no default handler to allow compiler to check that the 2874 * enum is fully handled 2875 */ 2876 } 2877 2878 return "<unknown>"; 2879 } 2880 2881 struct wmi_channel_arg { 2882 uint32_t freq; 2883 uint32_t band_center_freq1; 2884 uint32_t band_center_freq2; 2885 bool passive; 2886 bool allow_ibss; 2887 bool allow_ht; 2888 bool allow_vht; 2889 bool ht40plus; 2890 bool chan_radar; 2891 bool freq2_radar; 2892 bool allow_he; 2893 uint32_t min_power; 2894 uint32_t max_power; 2895 uint32_t max_reg_power; 2896 uint32_t max_antenna_gain; 2897 enum wmi_phy_mode mode; 2898 }; 2899 2900 struct wmi_vdev_start_req_arg { 2901 uint32_t vdev_id; 2902 struct wmi_channel_arg channel; 2903 uint32_t bcn_intval; 2904 uint32_t dtim_period; 2905 uint8_t *ssid; 2906 uint32_t ssid_len; 2907 uint32_t bcn_tx_rate; 2908 uint32_t bcn_tx_power; 2909 bool disable_hw_ack; 2910 bool hidden_ssid; 2911 bool pmf_enabled; 2912 uint32_t he_ops; 2913 uint32_t cac_duration_ms; 2914 uint32_t regdomain; 2915 uint32_t pref_rx_streams; 2916 uint32_t pref_tx_streams; 2917 uint32_t num_noa_descriptors; 2918 uint32_t min_data_rate; 2919 uint32_t mbssid_flags; 2920 uint32_t mbssid_tx_vdev_id; 2921 }; 2922 2923 struct peer_create_params { 2924 uint8_t *peer_addr; 2925 uint32_t peer_type; 2926 uint32_t vdev_id; 2927 }; 2928 2929 struct peer_delete_params { 2930 uint8_t vdev_id; 2931 }; 2932 2933 struct peer_flush_params { 2934 uint32_t peer_tid_bitmap; 2935 uint8_t vdev_id; 2936 }; 2937 2938 struct pdev_set_regdomain_params { 2939 uint16_t current_rd_in_use; 2940 uint16_t current_rd_2g; 2941 uint16_t current_rd_5g; 2942 uint32_t ctl_2g; 2943 uint32_t ctl_5g; 2944 uint8_t dfs_domain; 2945 uint32_t pdev_id; 2946 }; 2947 2948 struct rx_reorder_queue_remove_params { 2949 uint8_t *peer_macaddr; 2950 uint16_t vdev_id; 2951 uint32_t peer_tid_bitmap; 2952 }; 2953 2954 #define WMI_HOST_PDEV_ID_SOC 0xFF 2955 #define WMI_HOST_PDEV_ID_0 0 2956 #define WMI_HOST_PDEV_ID_1 1 2957 #define WMI_HOST_PDEV_ID_2 2 2958 2959 #define WMI_PDEV_ID_SOC 0 2960 #define WMI_PDEV_ID_1ST 1 2961 #define WMI_PDEV_ID_2ND 2 2962 #define WMI_PDEV_ID_3RD 3 2963 2964 /* Freq units in MHz */ 2965 #define REG_RULE_START_FREQ 0x0000ffff 2966 #define REG_RULE_END_FREQ 0xffff0000 2967 #define REG_RULE_FLAGS 0x0000ffff 2968 #define REG_RULE_MAX_BW 0x0000ffff 2969 #define REG_RULE_REG_PWR 0x00ff0000 2970 #define REG_RULE_ANT_GAIN 0xff000000 2971 #define REG_RULE_PSD_INFO BIT(0) 2972 #define REG_RULE_PSD_EIRP 0xff0000 2973 2974 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 2975 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 2976 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 2977 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 2978 2979 #define HE_PHYCAP_BYTE_0 0 2980 #define HE_PHYCAP_BYTE_1 1 2981 #define HE_PHYCAP_BYTE_2 2 2982 #define HE_PHYCAP_BYTE_3 3 2983 #define HE_PHYCAP_BYTE_4 4 2984 2985 #define HECAP_PHY_SU_BFER BIT(7) 2986 #define HECAP_PHY_SU_BFEE BIT(0) 2987 #define HECAP_PHY_MU_BFER BIT(1) 2988 #define HECAP_PHY_UL_MUMIMO BIT(6) 2989 #define HECAP_PHY_UL_MUOFDMA BIT(7) 2990 2991 #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ 2992 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3]) 2993 2994 #define HECAP_PHY_SUBFME_GET(hecap_phy) \ 2995 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4]) 2996 2997 #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ 2998 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4]) 2999 3000 #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ 3001 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2]) 3002 3003 #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ 3004 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2]) 3005 3006 #define HE_MODE_SU_TX_BFEE BIT(0) 3007 #define HE_MODE_SU_TX_BFER BIT(1) 3008 #define HE_MODE_MU_TX_BFEE BIT(2) 3009 #define HE_MODE_MU_TX_BFER BIT(3) 3010 #define HE_MODE_DL_OFDMA BIT(4) 3011 #define HE_MODE_UL_OFDMA BIT(5) 3012 #define HE_MODE_UL_MUMIMO BIT(6) 3013 3014 #define HE_DL_MUOFDMA_ENABLE 1 3015 #define HE_UL_MUOFDMA_ENABLE 1 3016 #define HE_DL_MUMIMO_ENABLE 1 3017 #define HE_UL_MUMIMO_ENABLE 1 3018 #define HE_MU_BFEE_ENABLE 1 3019 #define HE_SU_BFEE_ENABLE 1 3020 #define HE_MU_BFER_ENABLE 1 3021 #define HE_SU_BFER_ENABLE 1 3022 3023 #define HE_VHT_SOUNDING_MODE_ENABLE 1 3024 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 3025 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 3026 3027 /* HE or VHT Sounding */ 3028 #define HE_VHT_SOUNDING_MODE BIT(0) 3029 /* SU or MU Sounding */ 3030 #define HE_SU_MU_SOUNDING_MODE BIT(2) 3031 /* Trig or Non-Trig Sounding */ 3032 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 3033 3034 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 3035 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 3036 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 3037 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 3038 3039 struct pdev_params { 3040 uint32_t param_id; 3041 uint32_t param_value; 3042 }; 3043 3044 enum wmi_peer_type { 3045 WMI_PEER_TYPE_DEFAULT = 0, 3046 WMI_PEER_TYPE_BSS = 1, 3047 WMI_PEER_TYPE_TDLS = 2, 3048 }; 3049 3050 struct wmi_peer_create_cmd { 3051 uint32_t tlv_header; 3052 uint32_t vdev_id; 3053 struct wmi_mac_addr peer_macaddr; 3054 uint32_t peer_type; 3055 } __packed; 3056 3057 struct wmi_peer_delete_cmd { 3058 uint32_t tlv_header; 3059 uint32_t vdev_id; 3060 struct wmi_mac_addr peer_macaddr; 3061 } __packed; 3062 3063 struct wmi_peer_reorder_queue_setup_cmd { 3064 uint32_t tlv_header; 3065 uint32_t vdev_id; 3066 struct wmi_mac_addr peer_macaddr; 3067 uint32_t tid; 3068 uint32_t queue_ptr_lo; 3069 uint32_t queue_ptr_hi; 3070 uint32_t queue_no; 3071 uint32_t ba_window_size_valid; 3072 uint32_t ba_window_size; 3073 } __packed; 3074 3075 struct wmi_peer_reorder_queue_remove_cmd { 3076 uint32_t tlv_header; 3077 uint32_t vdev_id; 3078 struct wmi_mac_addr peer_macaddr; 3079 uint32_t tid_mask; 3080 } __packed; 3081 3082 struct gpio_config_params { 3083 uint32_t gpio_num; 3084 uint32_t input; 3085 uint32_t pull_type; 3086 uint32_t intr_mode; 3087 }; 3088 3089 enum wmi_gpio_type { 3090 WMI_GPIO_PULL_NONE, 3091 WMI_GPIO_PULL_UP, 3092 WMI_GPIO_PULL_DOWN 3093 }; 3094 3095 enum wmi_gpio_intr_type { 3096 WMI_GPIO_INTTYPE_DISABLE, 3097 WMI_GPIO_INTTYPE_RISING_EDGE, 3098 WMI_GPIO_INTTYPE_FALLING_EDGE, 3099 WMI_GPIO_INTTYPE_BOTH_EDGE, 3100 WMI_GPIO_INTTYPE_LEVEL_LOW, 3101 WMI_GPIO_INTTYPE_LEVEL_HIGH 3102 }; 3103 3104 enum wmi_bss_chan_info_req_type { 3105 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 3106 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 3107 }; 3108 3109 struct wmi_gpio_config_cmd_param { 3110 uint32_t tlv_header; 3111 uint32_t gpio_num; 3112 uint32_t input; 3113 uint32_t pull_type; 3114 uint32_t intr_mode; 3115 }; 3116 3117 struct gpio_output_params { 3118 uint32_t gpio_num; 3119 uint32_t set; 3120 }; 3121 3122 struct wmi_gpio_output_cmd_param { 3123 uint32_t tlv_header; 3124 uint32_t gpio_num; 3125 uint32_t set; 3126 }; 3127 3128 struct set_fwtest_params { 3129 uint32_t arg; 3130 uint32_t value; 3131 }; 3132 3133 struct wmi_fwtest_set_param_cmd_param { 3134 uint32_t tlv_header; 3135 uint32_t param_id; 3136 uint32_t param_value; 3137 }; 3138 3139 struct wmi_pdev_set_param_cmd { 3140 uint32_t tlv_header; 3141 uint32_t pdev_id; 3142 uint32_t param_id; 3143 uint32_t param_value; 3144 } __packed; 3145 3146 struct wmi_pdev_set_ps_mode_cmd { 3147 uint32_t tlv_header; 3148 uint32_t vdev_id; 3149 uint32_t sta_ps_mode; 3150 } __packed; 3151 3152 struct wmi_pdev_suspend_cmd { 3153 uint32_t tlv_header; 3154 uint32_t pdev_id; 3155 uint32_t suspend_opt; 3156 } __packed; 3157 3158 struct wmi_pdev_resume_cmd { 3159 uint32_t tlv_header; 3160 uint32_t pdev_id; 3161 } __packed; 3162 3163 struct wmi_pdev_bss_chan_info_req_cmd { 3164 uint32_t tlv_header; 3165 /* ref wmi_bss_chan_info_req_type */ 3166 uint32_t req_type; 3167 uint32_t pdev_id; 3168 } __packed; 3169 3170 struct wmi_ap_ps_peer_cmd { 3171 uint32_t tlv_header; 3172 uint32_t vdev_id; 3173 struct wmi_mac_addr peer_macaddr; 3174 uint32_t param; 3175 uint32_t value; 3176 } __packed; 3177 3178 struct wmi_sta_powersave_param_cmd { 3179 uint32_t tlv_header; 3180 uint32_t vdev_id; 3181 uint32_t param; 3182 uint32_t value; 3183 } __packed; 3184 3185 struct wmi_pdev_set_regdomain_cmd { 3186 uint32_t tlv_header; 3187 uint32_t pdev_id; 3188 uint32_t reg_domain; 3189 uint32_t reg_domain_2g; 3190 uint32_t reg_domain_5g; 3191 uint32_t conformance_test_limit_2g; 3192 uint32_t conformance_test_limit_5g; 3193 uint32_t dfs_domain; 3194 } __packed; 3195 3196 struct wmi_peer_set_param_cmd { 3197 uint32_t tlv_header; 3198 uint32_t vdev_id; 3199 struct wmi_mac_addr peer_macaddr; 3200 uint32_t param_id; 3201 uint32_t param_value; 3202 } __packed; 3203 3204 struct wmi_peer_flush_tids_cmd { 3205 uint32_t tlv_header; 3206 uint32_t vdev_id; 3207 struct wmi_mac_addr peer_macaddr; 3208 uint32_t peer_tid_bitmap; 3209 } __packed; 3210 3211 struct wmi_dfs_phyerr_offload_cmd { 3212 uint32_t tlv_header; 3213 uint32_t pdev_id; 3214 } __packed; 3215 3216 struct wmi_bcn_offload_ctrl_cmd { 3217 uint32_t tlv_header; 3218 uint32_t vdev_id; 3219 uint32_t bcn_ctrl_op; 3220 } __packed; 3221 3222 enum scan_dwelltime_adaptive_mode { 3223 SCAN_DWELL_MODE_DEFAULT = 0, 3224 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3225 SCAN_DWELL_MODE_MODERATE = 2, 3226 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3227 SCAN_DWELL_MODE_STATIC = 4 3228 }; 3229 3230 #define WLAN_SSID_MAX_LEN 32 3231 3232 struct element_info { 3233 uint32_t len; 3234 uint8_t *ptr; 3235 }; 3236 3237 struct wlan_ssid { 3238 uint8_t length; 3239 uint8_t ssid[WLAN_SSID_MAX_LEN]; 3240 }; 3241 3242 #define WMI_IE_BITMAP_SIZE 8 3243 3244 /* prefix used by scan requestor ids on the host */ 3245 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3246 3247 /* prefix used by scan request ids generated on the host */ 3248 /* host cycles through the lower 12 bits to generate ids */ 3249 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3250 3251 /* Values lower than this may be refused by some firmware revisions with a scan 3252 * completion with a timedout reason. 3253 */ 3254 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3255 3256 /* Scan priority numbers must be sequential, starting with 0 */ 3257 enum wmi_scan_priority { 3258 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3259 WMI_SCAN_PRIORITY_LOW, 3260 WMI_SCAN_PRIORITY_MEDIUM, 3261 WMI_SCAN_PRIORITY_HIGH, 3262 WMI_SCAN_PRIORITY_VERY_HIGH, 3263 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3264 }; 3265 3266 enum wmi_scan_event_type { 3267 WMI_SCAN_EVENT_STARTED = BIT(0), 3268 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3269 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3270 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3271 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3272 /* possibly by high-prio scan */ 3273 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3274 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3275 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3276 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3277 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3278 WMI_SCAN_EVENT_RESUMED = BIT(10), 3279 WMI_SCAN_EVENT_MAX = BIT(15), 3280 }; 3281 3282 enum wmi_scan_completion_reason { 3283 WMI_SCAN_REASON_COMPLETED, 3284 WMI_SCAN_REASON_CANCELLED, 3285 WMI_SCAN_REASON_PREEMPTED, 3286 WMI_SCAN_REASON_TIMEDOUT, 3287 WMI_SCAN_REASON_INTERNAL_FAILURE, 3288 WMI_SCAN_REASON_MAX, 3289 }; 3290 3291 struct wmi_start_scan_cmd { 3292 uint32_t tlv_header; 3293 uint32_t scan_id; 3294 uint32_t scan_req_id; 3295 uint32_t vdev_id; 3296 uint32_t scan_priority; 3297 uint32_t notify_scan_events; 3298 uint32_t dwell_time_active; 3299 uint32_t dwell_time_passive; 3300 uint32_t min_rest_time; 3301 uint32_t max_rest_time; 3302 uint32_t repeat_probe_time; 3303 uint32_t probe_spacing_time; 3304 uint32_t idle_time; 3305 uint32_t max_scan_time; 3306 uint32_t probe_delay; 3307 uint32_t scan_ctrl_flags; 3308 uint32_t burst_duration; 3309 uint32_t num_chan; 3310 uint32_t num_bssid; 3311 uint32_t num_ssids; 3312 uint32_t ie_len; 3313 uint32_t n_probes; 3314 struct wmi_mac_addr mac_addr; 3315 struct wmi_mac_addr mac_mask; 3316 uint32_t ie_bitmap[WMI_IE_BITMAP_SIZE]; 3317 uint32_t num_vendor_oui; 3318 uint32_t scan_ctrl_flags_ext; 3319 uint32_t dwell_time_active_2g; 3320 uint32_t dwell_time_active_6g; 3321 uint32_t dwell_time_passive_6g; 3322 uint32_t scan_start_offset; 3323 } __packed; 3324 3325 #define WMI_SCAN_FLAG_PASSIVE 0x1 3326 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3327 #define WMI_SCAN_ADD_CCK_RATES 0x4 3328 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3329 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3330 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3331 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3332 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3333 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3334 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3335 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3336 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3337 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3338 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3339 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3340 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3341 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3342 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3343 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3344 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3345 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3346 3347 #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 3348 #define WMI_SCAN_DWELL_MODE_SHIFT 21 3349 #define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800 3350 3351 #define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0) 3352 #define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20) 3353 3354 enum { 3355 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3356 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3357 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3358 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3359 WMI_SCAN_DWELL_MODE_STATIC = 4, 3360 }; 3361 3362 #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \ 3363 ((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \ 3364 WMI_SCAN_DWELL_MODE_MASK)) 3365 3366 struct hint_short_ssid { 3367 uint32_t freq_flags; 3368 uint32_t short_ssid; 3369 }; 3370 3371 struct hint_bssid { 3372 uint32_t freq_flags; 3373 struct wmi_mac_addr bssid; 3374 }; 3375 3376 struct scan_req_params { 3377 uint32_t scan_id; 3378 uint32_t scan_req_id; 3379 uint32_t vdev_id; 3380 uint32_t pdev_id; 3381 enum wmi_scan_priority scan_priority; 3382 union { 3383 struct { 3384 uint32_t scan_ev_started:1, 3385 scan_ev_completed:1, 3386 scan_ev_bss_chan:1, 3387 scan_ev_foreign_chan:1, 3388 scan_ev_dequeued:1, 3389 scan_ev_preempted:1, 3390 scan_ev_start_failed:1, 3391 scan_ev_restarted:1, 3392 scan_ev_foreign_chn_exit:1, 3393 scan_ev_invalid:1, 3394 scan_ev_gpio_timeout:1, 3395 scan_ev_suspended:1, 3396 scan_ev_resumed:1; 3397 }; 3398 uint32_t scan_events; 3399 }; 3400 uint32_t scan_ctrl_flags_ext; 3401 uint32_t dwell_time_active; 3402 uint32_t dwell_time_active_2g; 3403 uint32_t dwell_time_passive; 3404 uint32_t dwell_time_active_6g; 3405 uint32_t dwell_time_passive_6g; 3406 uint32_t min_rest_time; 3407 uint32_t max_rest_time; 3408 uint32_t repeat_probe_time; 3409 uint32_t probe_spacing_time; 3410 uint32_t idle_time; 3411 uint32_t max_scan_time; 3412 uint32_t probe_delay; 3413 union { 3414 struct { 3415 uint32_t scan_f_passive:1, 3416 scan_f_bcast_probe:1, 3417 scan_f_cck_rates:1, 3418 scan_f_ofdm_rates:1, 3419 scan_f_chan_stat_evnt:1, 3420 scan_f_filter_prb_req:1, 3421 scan_f_bypass_dfs_chn:1, 3422 scan_f_continue_on_err:1, 3423 scan_f_offchan_mgmt_tx:1, 3424 scan_f_offchan_data_tx:1, 3425 scan_f_promisc_mode:1, 3426 scan_f_capture_phy_err:1, 3427 scan_f_strict_passive_pch:1, 3428 scan_f_half_rate:1, 3429 scan_f_quarter_rate:1, 3430 scan_f_force_active_dfs_chn:1, 3431 scan_f_add_tpc_ie_in_probe:1, 3432 scan_f_add_ds_ie_in_probe:1, 3433 scan_f_add_spoofed_mac_in_probe:1, 3434 scan_f_add_rand_seq_in_probe:1, 3435 scan_f_en_ie_whitelist_in_probe:1, 3436 scan_f_forced:1, 3437 scan_f_2ghz:1, 3438 scan_f_5ghz:1, 3439 scan_f_80mhz:1; 3440 }; 3441 uint32_t scan_flags; 3442 }; 3443 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3444 uint32_t burst_duration; 3445 uint32_t num_chan; 3446 uint32_t num_bssid; 3447 uint32_t num_ssids; 3448 uint32_t n_probes; 3449 uint32_t *chan_list; 3450 uint32_t notify_scan_events; 3451 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID]; 3452 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID]; 3453 struct element_info extraie; 3454 struct element_info htcap; 3455 struct element_info vhtcap; 3456 uint32_t num_hint_s_ssid; 3457 uint32_t num_hint_bssid; 3458 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3459 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3460 struct wmi_mac_addr mac_addr; 3461 struct wmi_mac_addr mac_mask; 3462 }; 3463 3464 struct wmi_ssid_arg { 3465 int len; 3466 const uint8_t *ssid; 3467 }; 3468 3469 struct wmi_bssid_arg { 3470 const uint8_t *bssid; 3471 }; 3472 3473 struct wmi_start_scan_arg { 3474 uint32_t scan_id; 3475 uint32_t scan_req_id; 3476 uint32_t vdev_id; 3477 uint32_t scan_priority; 3478 uint32_t notify_scan_events; 3479 uint32_t dwell_time_active; 3480 uint32_t dwell_time_passive; 3481 uint32_t min_rest_time; 3482 uint32_t max_rest_time; 3483 uint32_t repeat_probe_time; 3484 uint32_t probe_spacing_time; 3485 uint32_t idle_time; 3486 uint32_t max_scan_time; 3487 uint32_t probe_delay; 3488 uint32_t scan_ctrl_flags; 3489 3490 uint32_t ie_len; 3491 uint32_t n_channels; 3492 uint32_t n_ssids; 3493 uint32_t n_bssids; 3494 3495 uint8_t ie[WLAN_SCAN_PARAMS_MAX_IE_LEN]; 3496 uint32_t channels[64]; 3497 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID]; 3498 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID]; 3499 }; 3500 3501 #define WMI_SCAN_STOP_ONE 0x00000000 3502 #define WMI_SCN_STOP_VAP_ALL 0x01000000 3503 #define WMI_SCAN_STOP_ALL 0x04000000 3504 3505 /* Prefix 0xA000 indicates that the scan request 3506 * is trigger by HOST 3507 */ 3508 #define ATH11K_SCAN_ID 0xA000 3509 3510 enum scan_cancel_req_type { 3511 WLAN_SCAN_CANCEL_SINGLE = 1, 3512 WLAN_SCAN_CANCEL_VDEV_ALL, 3513 WLAN_SCAN_CANCEL_PDEV_ALL, 3514 }; 3515 3516 struct scan_cancel_param { 3517 uint32_t requester; 3518 uint32_t scan_id; 3519 enum scan_cancel_req_type req_type; 3520 uint32_t vdev_id; 3521 uint32_t pdev_id; 3522 }; 3523 3524 struct wmi_bcn_send_from_host_cmd { 3525 uint32_t tlv_header; 3526 uint32_t vdev_id; 3527 uint32_t data_len; 3528 union { 3529 uint32_t frag_ptr; 3530 uint32_t frag_ptr_lo; 3531 }; 3532 uint32_t frame_ctrl; 3533 uint32_t dtim_flag; 3534 uint32_t bcn_antenna; 3535 uint32_t frag_ptr_hi; 3536 }; 3537 3538 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3539 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3540 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3541 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3542 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3543 #define WMI_CHAN_INFO_DFS BIT(10) 3544 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3545 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3546 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3547 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3548 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3549 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3550 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3551 #define WMI_CHAN_INFO_PSC BIT(18) 3552 3553 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3554 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3555 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3556 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3557 3558 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3559 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3560 3561 struct wmi_channel { 3562 uint32_t tlv_header; 3563 uint32_t mhz; 3564 uint32_t band_center_freq1; 3565 uint32_t band_center_freq2; 3566 uint32_t info; 3567 uint32_t reg_info_1; 3568 uint32_t reg_info_2; 3569 } __packed; 3570 3571 struct wmi_mgmt_params { 3572 void *tx_frame; 3573 uint16_t frm_len; 3574 uint8_t vdev_id; 3575 uint16_t chanfreq; 3576 void *pdata; 3577 uint16_t desc_id; 3578 uint8_t *macaddr; 3579 }; 3580 3581 enum wmi_sta_ps_mode { 3582 WMI_STA_PS_MODE_DISABLED = 0, 3583 WMI_STA_PS_MODE_ENABLED = 1, 3584 }; 3585 3586 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3587 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3588 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3589 3590 #define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1 3591 #define ATH11K_WMI_FW_HANG_DELAY 0 3592 3593 /* type, 0:unused 1: ASSERT 2: not respond detect command 3594 * delay_time_ms, the simulate will delay time 3595 */ 3596 3597 struct wmi_force_fw_hang_cmd { 3598 uint32_t tlv_header; 3599 uint32_t type; 3600 uint32_t delay_time_ms; 3601 }; 3602 3603 struct wmi_vdev_set_param_cmd { 3604 uint32_t tlv_header; 3605 uint32_t vdev_id; 3606 uint32_t param_id; 3607 uint32_t param_value; 3608 } __packed; 3609 3610 enum wmi_stats_id { 3611 WMI_REQUEST_PEER_STAT = BIT(0), 3612 WMI_REQUEST_AP_STAT = BIT(1), 3613 WMI_REQUEST_PDEV_STAT = BIT(2), 3614 WMI_REQUEST_VDEV_STAT = BIT(3), 3615 WMI_REQUEST_BCNFLT_STAT = BIT(4), 3616 WMI_REQUEST_VDEV_RATE_STAT = BIT(5), 3617 WMI_REQUEST_INST_STAT = BIT(6), 3618 WMI_REQUEST_MIB_STAT = BIT(7), 3619 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 3620 WMI_REQUEST_CONGESTION_STAT = BIT(9), 3621 WMI_REQUEST_PEER_EXTD_STAT = BIT(10), 3622 WMI_REQUEST_BCN_STAT = BIT(11), 3623 WMI_REQUEST_BCN_STAT_RESET = BIT(12), 3624 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13), 3625 }; 3626 3627 struct wmi_request_stats_cmd { 3628 uint32_t tlv_header; 3629 enum wmi_stats_id stats_id; 3630 uint32_t vdev_id; 3631 struct wmi_mac_addr peer_macaddr; 3632 uint32_t pdev_id; 3633 } __packed; 3634 3635 struct wmi_get_pdev_temperature_cmd { 3636 uint32_t tlv_header; 3637 uint32_t param; 3638 uint32_t pdev_id; 3639 } __packed; 3640 3641 struct wmi_ftm_seg_hdr { 3642 uint32_t len; 3643 uint32_t msgref; 3644 uint32_t segmentinfo; 3645 uint32_t pdev_id; 3646 } __packed; 3647 3648 struct wmi_ftm_cmd { 3649 uint32_t tlv_header; 3650 struct wmi_ftm_seg_hdr seg_hdr; 3651 uint8_t data[]; 3652 } __packed; 3653 3654 struct wmi_ftm_event_msg { 3655 struct wmi_ftm_seg_hdr seg_hdr; 3656 uint8_t data[]; 3657 } __packed; 3658 3659 #define WMI_BEACON_TX_BUFFER_SIZE 512 3660 3661 #define WMI_EMA_TMPL_IDX_SHIFT 8 3662 #define WMI_EMA_FIRST_TMPL_SHIFT 16 3663 #define WMI_EMA_LAST_TMPL_SHIFT 24 3664 3665 struct wmi_bcn_tmpl_cmd { 3666 uint32_t tlv_header; 3667 uint32_t vdev_id; 3668 uint32_t tim_ie_offset; 3669 uint32_t buf_len; 3670 uint32_t csa_switch_count_offset; 3671 uint32_t ext_csa_switch_count_offset; 3672 uint32_t csa_event_bitmap; 3673 uint32_t mbssid_ie_offset; 3674 uint32_t esp_ie_offset; 3675 uint32_t csc_switch_count_offset; 3676 uint32_t csc_event_bitmap; 3677 uint32_t mu_edca_ie_offset; 3678 uint32_t feature_enable_bitmap; 3679 uint32_t ema_params; 3680 } __packed; 3681 3682 struct wmi_key_seq_counter { 3683 uint32_t key_seq_counter_l; 3684 uint32_t key_seq_counter_h; 3685 } __packed; 3686 3687 struct wmi_vdev_install_key_cmd { 3688 uint32_t tlv_header; 3689 uint32_t vdev_id; 3690 struct wmi_mac_addr peer_macaddr; 3691 uint32_t key_idx; 3692 uint32_t key_flags; 3693 uint32_t key_cipher; 3694 struct wmi_key_seq_counter key_rsc_counter; 3695 struct wmi_key_seq_counter key_global_rsc_counter; 3696 struct wmi_key_seq_counter key_tsc_counter; 3697 uint8_t wpi_key_rsc_counter[16]; 3698 uint8_t wpi_key_tsc_counter[16]; 3699 uint32_t key_len; 3700 uint32_t key_txmic_len; 3701 uint32_t key_rxmic_len; 3702 uint32_t is_group_key_id_valid; 3703 uint32_t group_key_id; 3704 3705 /* Followed by key_data containing key followed by 3706 * tx mic and then rx mic 3707 */ 3708 } __packed; 3709 3710 struct wmi_vdev_install_key_arg { 3711 uint32_t vdev_id; 3712 const uint8_t *macaddr; 3713 uint32_t key_idx; 3714 uint32_t key_flags; 3715 uint32_t key_cipher; 3716 uint32_t key_len; 3717 uint32_t key_txmic_len; 3718 uint32_t key_rxmic_len; 3719 uint64_t key_rsc_counter; 3720 const void *key_data; 3721 }; 3722 3723 #define WMI_MAX_SUPPORTED_RATES 128 3724 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3725 #define WMI_HOST_MAX_HE_RATE_SET 3 3726 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3727 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3728 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 3729 3730 struct wmi_rate_set_arg { 3731 uint32_t num_rates; 3732 uint8_t rates[WMI_MAX_SUPPORTED_RATES]; 3733 }; 3734 3735 struct peer_assoc_params { 3736 struct wmi_mac_addr peer_macaddr; 3737 uint32_t vdev_id; 3738 uint32_t peer_new_assoc; 3739 uint32_t peer_associd; 3740 uint32_t peer_flags; 3741 uint32_t peer_caps; 3742 uint32_t peer_listen_intval; 3743 uint32_t peer_ht_caps; 3744 uint32_t peer_max_mpdu; 3745 uint32_t peer_mpdu_density; 3746 uint32_t peer_rate_caps; 3747 uint32_t peer_nss; 3748 uint32_t peer_vht_caps; 3749 uint32_t peer_phymode; 3750 uint32_t peer_ht_info[2]; 3751 struct wmi_rate_set_arg peer_legacy_rates; 3752 struct wmi_rate_set_arg peer_ht_rates; 3753 uint32_t rx_max_rate; 3754 uint32_t rx_mcs_set; 3755 uint32_t tx_max_rate; 3756 uint32_t tx_mcs_set; 3757 uint8_t vht_capable; 3758 uint8_t min_data_rate; 3759 uint32_t tx_max_mcs_nss; 3760 uint32_t peer_bw_rxnss_override; 3761 bool is_pmf_enabled; 3762 bool is_wme_set; 3763 bool qos_flag; 3764 bool apsd_flag; 3765 bool ht_flag; 3766 bool bw_40; 3767 bool bw_80; 3768 bool bw_160; 3769 bool stbc_flag; 3770 bool ldpc_flag; 3771 bool static_mimops_flag; 3772 bool dynamic_mimops_flag; 3773 bool spatial_mux_flag; 3774 bool vht_flag; 3775 bool vht_ng_flag; 3776 bool need_ptk_4_way; 3777 bool need_gtk_2_way; 3778 bool auth_flag; 3779 bool safe_mode_enabled; 3780 bool amsdu_disable; 3781 /* Use common structure */ 3782 uint8_t peer_mac[IEEE80211_ADDR_LEN]; 3783 3784 bool he_flag; 3785 uint32_t peer_he_cap_macinfo[2]; 3786 uint32_t peer_he_cap_macinfo_internal; 3787 uint32_t peer_he_caps_6ghz; 3788 uint32_t peer_he_ops; 3789 uint32_t peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3790 uint32_t peer_he_mcs_count; 3791 uint32_t peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3792 uint32_t peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3793 bool twt_responder; 3794 bool twt_requester; 3795 bool is_assoc; 3796 struct ath11k_ppe_threshold peer_ppet; 3797 }; 3798 3799 struct wmi_peer_assoc_complete_cmd { 3800 uint32_t tlv_header; 3801 struct wmi_mac_addr peer_macaddr; 3802 uint32_t vdev_id; 3803 uint32_t peer_new_assoc; 3804 uint32_t peer_associd; 3805 uint32_t peer_flags; 3806 uint32_t peer_caps; 3807 uint32_t peer_listen_intval; 3808 uint32_t peer_ht_caps; 3809 uint32_t peer_max_mpdu; 3810 uint32_t peer_mpdu_density; 3811 uint32_t peer_rate_caps; 3812 uint32_t peer_nss; 3813 uint32_t peer_vht_caps; 3814 uint32_t peer_phymode; 3815 uint32_t peer_ht_info[2]; 3816 uint32_t num_peer_legacy_rates; 3817 uint32_t num_peer_ht_rates; 3818 uint32_t peer_bw_rxnss_override; 3819 struct wmi_ppe_threshold peer_ppet; 3820 uint32_t peer_he_cap_info; 3821 uint32_t peer_he_ops; 3822 uint32_t peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 3823 uint32_t peer_he_mcs; 3824 uint32_t peer_he_cap_info_ext; 3825 uint32_t peer_he_cap_info_internal; 3826 uint32_t min_data_rate; 3827 uint32_t peer_he_caps_6ghz; 3828 } __packed; 3829 3830 struct wmi_stop_scan_cmd { 3831 uint32_t tlv_header; 3832 uint32_t requestor; 3833 uint32_t scan_id; 3834 uint32_t req_type; 3835 uint32_t vdev_id; 3836 uint32_t pdev_id; 3837 }; 3838 3839 struct scan_chan_list_params { 3840 uint32_t pdev_id; 3841 uint16_t nallchans; 3842 struct channel_param ch_param[]; 3843 }; 3844 3845 struct wmi_scan_chan_list_cmd { 3846 uint32_t tlv_header; 3847 uint32_t num_scan_chans; 3848 uint32_t flags; 3849 uint32_t pdev_id; 3850 } __packed; 3851 3852 struct wmi_scan_prob_req_oui_cmd { 3853 uint32_t tlv_header; 3854 uint32_t prob_req_oui; 3855 } __packed; 3856 3857 #define WMI_MGMT_SEND_DOWNLD_LEN 64 3858 3859 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 3860 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 3861 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 3862 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 3863 3864 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 3865 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 3866 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 3867 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 3868 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 3869 3870 struct wmi_mgmt_send_cmd { 3871 uint32_t tlv_header; 3872 uint32_t vdev_id; 3873 uint32_t desc_id; 3874 uint32_t chanfreq; 3875 uint32_t paddr_lo; 3876 uint32_t paddr_hi; 3877 uint32_t frame_len; 3878 uint32_t buf_len; 3879 uint32_t tx_params_valid; 3880 3881 /* 3882 * Followed by struct wmi_tlv and buf_len bytes of frame data with 3883 * buf_len <= WMI_MGMT_SEND_DOWNLD_LEN, which may be exceeded by 3884 * frame_len. The full frame is mapped at paddr_lo/hi. 3885 * Presumably the idea is that small frames can skip the extra DMA 3886 * transfer of frame data after the command has been transferred. 3887 */ 3888 } __packed; 3889 3890 struct wmi_sta_powersave_mode_cmd { 3891 uint32_t tlv_header; 3892 uint32_t vdev_id; 3893 uint32_t sta_ps_mode; 3894 }; 3895 3896 struct wmi_sta_smps_force_mode_cmd { 3897 uint32_t tlv_header; 3898 uint32_t vdev_id; 3899 uint32_t forced_mode; 3900 }; 3901 3902 struct wmi_sta_smps_param_cmd { 3903 uint32_t tlv_header; 3904 uint32_t vdev_id; 3905 uint32_t param; 3906 uint32_t value; 3907 }; 3908 3909 struct wmi_bcn_prb_info { 3910 uint32_t tlv_header; 3911 uint32_t caps; 3912 uint32_t erp; 3913 } __packed; 3914 3915 enum { 3916 WMI_PDEV_SUSPEND, 3917 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 3918 }; 3919 3920 struct green_ap_ps_params { 3921 uint32_t value; 3922 }; 3923 3924 struct wmi_pdev_green_ap_ps_enable_cmd_param { 3925 uint32_t tlv_header; 3926 uint32_t pdev_id; 3927 uint32_t enable; 3928 }; 3929 3930 struct ap_ps_params { 3931 uint32_t vdev_id; 3932 uint32_t param; 3933 uint32_t value; 3934 }; 3935 3936 struct vdev_set_params { 3937 uint32_t if_id; 3938 uint32_t param_id; 3939 uint32_t param_value; 3940 }; 3941 3942 struct stats_request_params { 3943 uint32_t stats_id; 3944 uint32_t vdev_id; 3945 uint32_t pdev_id; 3946 }; 3947 3948 struct wmi_set_current_country_params { 3949 uint8_t alpha2[3]; 3950 }; 3951 3952 struct wmi_set_current_country_cmd { 3953 uint32_t tlv_header; 3954 uint32_t pdev_id; 3955 uint32_t new_alpha2; 3956 } __packed; 3957 3958 enum set_init_cc_type { 3959 WMI_COUNTRY_INFO_TYPE_ALPHA, 3960 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 3961 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 3962 }; 3963 3964 enum set_init_cc_flags { 3965 INVALID_CC, 3966 CC_IS_SET, 3967 REGDMN_IS_SET, 3968 ALPHA_IS_SET, 3969 }; 3970 3971 struct wmi_init_country_params { 3972 union { 3973 uint16_t country_code; 3974 uint16_t regdom_id; 3975 uint8_t alpha2[3]; 3976 } cc_info; 3977 enum set_init_cc_flags flags; 3978 }; 3979 3980 struct wmi_init_country_cmd { 3981 uint32_t tlv_header; 3982 uint32_t pdev_id; 3983 uint32_t init_cc_type; 3984 union { 3985 uint32_t country_code; 3986 uint32_t regdom_id; 3987 uint32_t alpha2; 3988 } cc_info; 3989 } __packed; 3990 3991 struct wmi_11d_scan_start_params { 3992 uint32_t vdev_id; 3993 uint32_t scan_period_msec; 3994 uint32_t start_interval_msec; 3995 }; 3996 3997 struct wmi_11d_scan_start_cmd { 3998 uint32_t tlv_header; 3999 uint32_t vdev_id; 4000 uint32_t scan_period_msec; 4001 uint32_t start_interval_msec; 4002 } __packed; 4003 4004 struct wmi_11d_scan_stop_cmd { 4005 uint32_t tlv_header; 4006 uint32_t vdev_id; 4007 } __packed; 4008 4009 struct wmi_11d_new_cc_ev { 4010 uint32_t new_alpha2; 4011 } __packed; 4012 4013 #define THERMAL_LEVELS 1 4014 struct tt_level_config { 4015 uint32_t tmplwm; 4016 uint32_t tmphwm; 4017 uint32_t dcoffpercent; 4018 uint32_t priority; 4019 }; 4020 4021 struct thermal_mitigation_params { 4022 uint32_t pdev_id; 4023 uint32_t enable; 4024 uint32_t dc; 4025 uint32_t dc_per_event; 4026 struct tt_level_config levelconf[THERMAL_LEVELS]; 4027 }; 4028 4029 struct wmi_therm_throt_config_request_cmd { 4030 uint32_t tlv_header; 4031 uint32_t pdev_id; 4032 uint32_t enable; 4033 uint32_t dc; 4034 uint32_t dc_per_event; 4035 uint32_t therm_throt_levels; 4036 } __packed; 4037 4038 struct wmi_therm_throt_level_config_info { 4039 uint32_t tlv_header; 4040 uint32_t temp_lwm; 4041 uint32_t temp_hwm; 4042 uint32_t dc_off_percent; 4043 uint32_t prio; 4044 } __packed; 4045 4046 struct wmi_delba_send_cmd { 4047 uint32_t tlv_header; 4048 uint32_t vdev_id; 4049 struct wmi_mac_addr peer_macaddr; 4050 uint32_t tid; 4051 uint32_t initiator; 4052 uint32_t reasoncode; 4053 } __packed; 4054 4055 struct wmi_addba_setresponse_cmd { 4056 uint32_t tlv_header; 4057 uint32_t vdev_id; 4058 struct wmi_mac_addr peer_macaddr; 4059 uint32_t tid; 4060 uint32_t statuscode; 4061 } __packed; 4062 4063 struct wmi_addba_send_cmd { 4064 uint32_t tlv_header; 4065 uint32_t vdev_id; 4066 struct wmi_mac_addr peer_macaddr; 4067 uint32_t tid; 4068 uint32_t buffersize; 4069 } __packed; 4070 4071 struct wmi_addba_clear_resp_cmd { 4072 uint32_t tlv_header; 4073 uint32_t vdev_id; 4074 struct wmi_mac_addr peer_macaddr; 4075 } __packed; 4076 4077 struct wmi_pdev_pktlog_filter_info { 4078 uint32_t tlv_header; 4079 struct wmi_mac_addr peer_macaddr; 4080 } __packed; 4081 4082 struct wmi_pdev_pktlog_filter_cmd { 4083 uint32_t tlv_header; 4084 uint32_t pdev_id; 4085 uint32_t enable; 4086 uint32_t filter_type; 4087 uint32_t num_mac; 4088 } __packed; 4089 4090 enum ath11k_wmi_pktlog_enable { 4091 ATH11K_WMI_PKTLOG_ENABLE_AUTO = 0, 4092 ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1, 4093 }; 4094 4095 struct wmi_pktlog_enable_cmd { 4096 uint32_t tlv_header; 4097 uint32_t pdev_id; 4098 uint32_t evlist; /* WMI_PKTLOG_EVENT */ 4099 uint32_t enable; 4100 } __packed; 4101 4102 struct wmi_pktlog_disable_cmd { 4103 uint32_t tlv_header; 4104 uint32_t pdev_id; 4105 } __packed; 4106 4107 #define DFS_PHYERR_UNIT_TEST_CMD 0 4108 #define DFS_UNIT_TEST_MODULE 0x2b 4109 #define DFS_UNIT_TEST_TOKEN 0xAA 4110 4111 enum dfs_test_args_idx { 4112 DFS_TEST_CMDID = 0, 4113 DFS_TEST_PDEV_ID, 4114 DFS_TEST_RADAR_PARAM, 4115 DFS_MAX_TEST_ARGS, 4116 }; 4117 4118 struct wmi_dfs_unit_test_arg { 4119 uint32_t cmd_id; 4120 uint32_t pdev_id; 4121 uint32_t radar_param; 4122 }; 4123 4124 struct wmi_unit_test_cmd { 4125 uint32_t tlv_header; 4126 uint32_t vdev_id; 4127 uint32_t module_id; 4128 uint32_t num_args; 4129 uint32_t diag_token; 4130 /* Followed by test args*/ 4131 } __packed; 4132 4133 #define MAX_SUPPORTED_RATES 128 4134 4135 #define WMI_PEER_AUTH 0x00000001 4136 #define WMI_PEER_QOS 0x00000002 4137 #define WMI_PEER_NEED_PTK_4_WAY 0x00000004 4138 #define WMI_PEER_NEED_GTK_2_WAY 0x00000010 4139 #define WMI_PEER_HE 0x00000400 4140 #define WMI_PEER_APSD 0x00000800 4141 #define WMI_PEER_HT 0x00001000 4142 #define WMI_PEER_40MHZ 0x00002000 4143 #define WMI_PEER_STBC 0x00008000 4144 #define WMI_PEER_LDPC 0x00010000 4145 #define WMI_PEER_DYN_MIMOPS 0x00020000 4146 #define WMI_PEER_STATIC_MIMOPS 0x00040000 4147 #define WMI_PEER_SPATIAL_MUX 0x00200000 4148 #define WMI_PEER_TWT_REQ 0x00400000 4149 #define WMI_PEER_TWT_RESP 0x00800000 4150 #define WMI_PEER_VHT 0x02000000 4151 #define WMI_PEER_80MHZ 0x04000000 4152 #define WMI_PEER_PMF 0x08000000 4153 /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. 4154 * Need to be cleaned up 4155 */ 4156 #define WMI_PEER_IS_P2P_CAPABLE 0x20000000 4157 #define WMI_PEER_160MHZ 0x40000000 4158 #define WMI_PEER_SAFEMODE_EN 0x80000000 4159 4160 struct beacon_tmpl_params { 4161 uint8_t vdev_id; 4162 uint32_t tim_ie_offset; 4163 uint32_t tmpl_len; 4164 uint32_t tmpl_len_aligned; 4165 uint32_t csa_switch_count_offset; 4166 uint32_t ext_csa_switch_count_offset; 4167 uint8_t *frm; 4168 }; 4169 4170 struct wmi_rate_set { 4171 uint32_t num_rates; 4172 uint32_t rates[(MAX_SUPPORTED_RATES / 4) + 1]; 4173 }; 4174 4175 struct wmi_vht_rate_set { 4176 uint32_t tlv_header; 4177 uint32_t rx_max_rate; 4178 uint32_t rx_mcs_set; 4179 uint32_t tx_max_rate; 4180 uint32_t tx_mcs_set; 4181 uint32_t tx_max_mcs_nss; 4182 } __packed; 4183 4184 struct wmi_he_rate_set { 4185 uint32_t tlv_header; 4186 4187 /* MCS at which the peer can receive */ 4188 uint32_t rx_mcs_set; 4189 4190 /* MCS at which the peer can transmit */ 4191 uint32_t tx_mcs_set; 4192 } __packed; 4193 4194 #define MAX_REG_RULES 10 4195 #define REG_ALPHA2_LEN 2 4196 #define MAX_6GHZ_REG_RULES 5 4197 4198 enum wmi_start_event_param { 4199 WMI_VDEV_START_RESP_EVENT = 0, 4200 WMI_VDEV_RESTART_RESP_EVENT, 4201 }; 4202 4203 struct wmi_vdev_start_resp_event { 4204 uint32_t vdev_id; 4205 uint32_t requestor_id; 4206 enum wmi_start_event_param resp_type; 4207 uint32_t status; 4208 uint32_t chain_mask; 4209 uint32_t smps_mode; 4210 union { 4211 uint32_t mac_id; 4212 uint32_t pdev_id; 4213 }; 4214 uint32_t cfgd_tx_streams; 4215 uint32_t cfgd_rx_streams; 4216 } __packed; 4217 4218 /* VDEV start response status codes */ 4219 enum wmi_vdev_start_resp_status_code { 4220 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4221 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4222 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4223 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4224 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4225 }; 4226 4227 /* Regaulatory Rule Flags Passed by FW */ 4228 #define REGULATORY_CHAN_DISABLED BIT(0) 4229 #define REGULATORY_CHAN_NO_IR BIT(1) 4230 #define REGULATORY_CHAN_RADAR BIT(3) 4231 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4232 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4233 4234 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4235 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4236 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4237 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4238 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4239 4240 enum wmi_reg_chan_list_cmd_type { 4241 WMI_REG_CHAN_LIST_CC_ID = 0, 4242 WMI_REG_CHAN_LIST_CC_EXT_ID = 1, 4243 }; 4244 4245 enum wmi_reg_cc_setting_code { 4246 WMI_REG_SET_CC_STATUS_PASS = 0, 4247 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4248 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4249 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4250 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4251 WMI_REG_SET_CC_STATUS_FAIL = 5, 4252 4253 /* add new setting code above, update in 4254 * @enum cc_setting_code as well. 4255 * Also handle it in ath11k_wmi_cc_setting_code_to_reg() 4256 */ 4257 }; 4258 4259 enum cc_setting_code { 4260 REG_SET_CC_STATUS_PASS = 0, 4261 REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4262 REG_INIT_ALPHA2_NOT_FOUND = 2, 4263 REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4264 REG_SET_CC_STATUS_NO_MEMORY = 4, 4265 REG_SET_CC_STATUS_FAIL = 5, 4266 4267 /* add new setting code above, update in 4268 * @enum wmi_reg_cc_setting_code as well. 4269 * Also handle it in ath11k_cc_status_to_str() 4270 */ 4271 }; 4272 4273 static inline enum cc_setting_code 4274 qwx_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code) 4275 { 4276 switch (status_code) { 4277 case WMI_REG_SET_CC_STATUS_PASS: 4278 return REG_SET_CC_STATUS_PASS; 4279 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND: 4280 return REG_CURRENT_ALPHA2_NOT_FOUND; 4281 case WMI_REG_INIT_ALPHA2_NOT_FOUND: 4282 return REG_INIT_ALPHA2_NOT_FOUND; 4283 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED: 4284 return REG_SET_CC_CHANGE_NOT_ALLOWED; 4285 case WMI_REG_SET_CC_STATUS_NO_MEMORY: 4286 return REG_SET_CC_STATUS_NO_MEMORY; 4287 case WMI_REG_SET_CC_STATUS_FAIL: 4288 return REG_SET_CC_STATUS_FAIL; 4289 } 4290 4291 return REG_SET_CC_STATUS_FAIL; 4292 } 4293 4294 static inline const char * 4295 qwx_cc_status_to_str(enum cc_setting_code code) 4296 { 4297 switch (code) { 4298 case REG_SET_CC_STATUS_PASS: 4299 return "REG_SET_CC_STATUS_PASS"; 4300 case REG_CURRENT_ALPHA2_NOT_FOUND: 4301 return "REG_CURRENT_ALPHA2_NOT_FOUND"; 4302 case REG_INIT_ALPHA2_NOT_FOUND: 4303 return "REG_INIT_ALPHA2_NOT_FOUND"; 4304 case REG_SET_CC_CHANGE_NOT_ALLOWED: 4305 return "REG_SET_CC_CHANGE_NOT_ALLOWED"; 4306 case REG_SET_CC_STATUS_NO_MEMORY: 4307 return "REG_SET_CC_STATUS_NO_MEMORY"; 4308 case REG_SET_CC_STATUS_FAIL: 4309 return "REG_SET_CC_STATUS_FAIL"; 4310 } 4311 4312 return "Unknown CC status"; 4313 } 4314 4315 enum wmi_reg_6ghz_ap_type { 4316 WMI_REG_INDOOR_AP = 0, 4317 WMI_REG_STANDARD_POWER_AP = 1, 4318 WMI_REG_VERY_LOW_POWER_AP = 2, 4319 4320 /* add AP type above, handle in ath11k_6ghz_ap_type_to_str() 4321 */ 4322 WMI_REG_CURRENT_MAX_AP_TYPE, 4323 WMI_REG_MAX_AP_TYPE = 7, 4324 }; 4325 4326 static inline const char * 4327 qwx_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type) 4328 { 4329 switch (type) { 4330 case WMI_REG_INDOOR_AP: 4331 return "INDOOR AP"; 4332 case WMI_REG_STANDARD_POWER_AP: 4333 return "STANDARD POWER AP"; 4334 case WMI_REG_VERY_LOW_POWER_AP: 4335 return "VERY LOW POWER AP"; 4336 case WMI_REG_CURRENT_MAX_AP_TYPE: 4337 return "CURRENT_MAX_AP_TYPE"; 4338 case WMI_REG_MAX_AP_TYPE: 4339 return "MAX_AP_TYPE"; 4340 } 4341 4342 return "unknown 6 GHz AP type"; 4343 } 4344 4345 enum wmi_reg_6ghz_client_type { 4346 WMI_REG_DEFAULT_CLIENT = 0, 4347 WMI_REG_SUBORDINATE_CLIENT = 1, 4348 WMI_REG_MAX_CLIENT_TYPE = 2, 4349 4350 /* add client type above, handle it in 4351 * ath11k_6ghz_client_type_to_str() 4352 */ 4353 }; 4354 4355 static inline const char * 4356 qwx_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type) 4357 { 4358 switch (type) { 4359 case WMI_REG_DEFAULT_CLIENT: 4360 return "DEFAULT CLIENT"; 4361 case WMI_REG_SUBORDINATE_CLIENT: 4362 return "SUBORDINATE CLIENT"; 4363 case WMI_REG_MAX_CLIENT_TYPE: 4364 return "MAX_CLIENT_TYPE"; 4365 } 4366 4367 return "unknown 6 GHz client type"; 4368 } 4369 4370 enum reg_subdomains_6ghz { 4371 EMPTY_6GHZ = 0x0, 4372 FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01, 4373 FCC1_CLIENT_SP_6GHZ = 0x02, 4374 FCC1_AP_LPI_6GHZ = 0x03, 4375 FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ, 4376 FCC1_AP_SP_6GHZ = 0x04, 4377 ETSI1_LPI_6GHZ = 0x10, 4378 ETSI1_VLP_6GHZ = 0x11, 4379 ETSI2_LPI_6GHZ = 0x12, 4380 ETSI2_VLP_6GHZ = 0x13, 4381 APL1_LPI_6GHZ = 0x20, 4382 APL1_VLP_6GHZ = 0x21, 4383 4384 /* add sub-domain above, handle it in 4385 * ath11k_sub_reg_6ghz_to_str() 4386 */ 4387 }; 4388 4389 static inline const char * 4390 qwx_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id) 4391 { 4392 switch (sub_id) { 4393 case EMPTY_6GHZ: 4394 return "N/A"; 4395 case FCC1_CLIENT_LPI_REGULAR_6GHZ: 4396 return "FCC1_CLIENT_LPI_REGULAR_6GHZ"; 4397 case FCC1_CLIENT_SP_6GHZ: 4398 return "FCC1_CLIENT_SP_6GHZ"; 4399 case FCC1_AP_LPI_6GHZ: 4400 return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE"; 4401 case FCC1_AP_SP_6GHZ: 4402 return "FCC1_AP_SP_6GHZ"; 4403 case ETSI1_LPI_6GHZ: 4404 return "ETSI1_LPI_6GHZ"; 4405 case ETSI1_VLP_6GHZ: 4406 return "ETSI1_VLP_6GHZ"; 4407 case ETSI2_LPI_6GHZ: 4408 return "ETSI2_LPI_6GHZ"; 4409 case ETSI2_VLP_6GHZ: 4410 return "ETSI2_VLP_6GHZ"; 4411 case APL1_LPI_6GHZ: 4412 return "APL1_LPI_6GHZ"; 4413 case APL1_VLP_6GHZ: 4414 return "APL1_VLP_6GHZ"; 4415 } 4416 4417 return "unknown sub reg id"; 4418 } 4419 4420 enum reg_super_domain_6ghz { 4421 FCC1_6GHZ = 0x01, 4422 ETSI1_6GHZ = 0x02, 4423 ETSI2_6GHZ = 0x03, 4424 APL1_6GHZ = 0x04, 4425 FCC1_6GHZ_CL = 0x05, 4426 4427 /* add super domain above, handle it in 4428 * ath11k_super_reg_6ghz_to_str() 4429 */ 4430 }; 4431 4432 static inline const char * 4433 qwx_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id) 4434 { 4435 switch (domain_id) { 4436 case FCC1_6GHZ: 4437 return "FCC1_6GHZ"; 4438 case ETSI1_6GHZ: 4439 return "ETSI1_6GHZ"; 4440 case ETSI2_6GHZ: 4441 return "ETSI2_6GHZ"; 4442 case APL1_6GHZ: 4443 return "APL1_6GHZ"; 4444 case FCC1_6GHZ_CL: 4445 return "FCC1_6GHZ_CL"; 4446 } 4447 4448 return "unknown domain id"; 4449 } 4450 4451 struct cur_reg_rule { 4452 uint16_t start_freq; 4453 uint16_t end_freq; 4454 uint16_t max_bw; 4455 uint8_t reg_power; 4456 uint8_t ant_gain; 4457 uint16_t flags; 4458 bool psd_flag; 4459 int8_t psd_eirp; 4460 }; 4461 4462 struct cur_regulatory_info { 4463 enum cc_setting_code status_code; 4464 uint8_t num_phy; 4465 uint8_t phy_id; 4466 uint16_t reg_dmn_pair; 4467 uint16_t ctry_code; 4468 uint8_t alpha2[REG_ALPHA2_LEN + 1]; 4469 uint32_t dfs_region; 4470 uint32_t phybitmap; 4471 uint32_t min_bw_2ghz; 4472 uint32_t max_bw_2ghz; 4473 uint32_t min_bw_5ghz; 4474 uint32_t max_bw_5ghz; 4475 uint32_t num_2ghz_reg_rules; 4476 uint32_t num_5ghz_reg_rules; 4477 struct cur_reg_rule *reg_rules_2ghz_ptr; 4478 struct cur_reg_rule *reg_rules_5ghz_ptr; 4479 bool is_ext_reg_event; 4480 enum wmi_reg_6ghz_client_type client_type; 4481 bool rnr_tpe_usable; 4482 bool unspecified_ap_usable; 4483 uint8_t domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4484 uint8_t domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4485 uint32_t domain_code_6ghz_super_id; 4486 uint32_t min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4487 uint32_t max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4488 uint32_t min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4489 uint32_t max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4490 uint32_t num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4491 uint32_t num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4492 struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE]; 4493 struct cur_reg_rule *reg_rules_6ghz_client_ptr 4494 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4495 }; 4496 4497 struct wmi_reg_chan_list_cc_event { 4498 uint32_t status_code; 4499 uint32_t phy_id; 4500 uint32_t alpha2; 4501 uint32_t num_phy; 4502 uint32_t country_id; 4503 uint32_t domain_code; 4504 uint32_t dfs_region; 4505 uint32_t phybitmap; 4506 uint32_t min_bw_2ghz; 4507 uint32_t max_bw_2ghz; 4508 uint32_t min_bw_5ghz; 4509 uint32_t max_bw_5ghz; 4510 uint32_t num_2ghz_reg_rules; 4511 uint32_t num_5ghz_reg_rules; 4512 } __packed; 4513 4514 struct wmi_regulatory_rule_struct { 4515 uint32_t tlv_header; 4516 uint32_t freq_info; 4517 uint32_t bw_pwr_info; 4518 uint32_t flag_info; 4519 }; 4520 4521 #define WMI_REG_CLIENT_MAX 4 4522 4523 struct wmi_reg_chan_list_cc_ext_event { 4524 uint32_t status_code; 4525 uint32_t phy_id; 4526 uint32_t alpha2; 4527 uint32_t num_phy; 4528 uint32_t country_id; 4529 uint32_t domain_code; 4530 uint32_t dfs_region; 4531 uint32_t phybitmap; 4532 uint32_t min_bw_2ghz; 4533 uint32_t max_bw_2ghz; 4534 uint32_t min_bw_5ghz; 4535 uint32_t max_bw_5ghz; 4536 uint32_t num_2ghz_reg_rules; 4537 uint32_t num_5ghz_reg_rules; 4538 uint32_t client_type; 4539 uint32_t rnr_tpe_usable; 4540 uint32_t unspecified_ap_usable; 4541 uint32_t domain_code_6ghz_ap_lpi; 4542 uint32_t domain_code_6ghz_ap_sp; 4543 uint32_t domain_code_6ghz_ap_vlp; 4544 uint32_t domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4545 uint32_t domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4546 uint32_t domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4547 uint32_t domain_code_6ghz_super_id; 4548 uint32_t min_bw_6ghz_ap_sp; 4549 uint32_t max_bw_6ghz_ap_sp; 4550 uint32_t min_bw_6ghz_ap_lpi; 4551 uint32_t max_bw_6ghz_ap_lpi; 4552 uint32_t min_bw_6ghz_ap_vlp; 4553 uint32_t max_bw_6ghz_ap_vlp; 4554 uint32_t min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4555 uint32_t max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4556 uint32_t min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4557 uint32_t max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4558 uint32_t min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4559 uint32_t max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4560 uint32_t num_6ghz_reg_rules_ap_sp; 4561 uint32_t num_6ghz_reg_rules_ap_lpi; 4562 uint32_t num_6ghz_reg_rules_ap_vlp; 4563 uint32_t num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; 4564 uint32_t num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; 4565 uint32_t num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; 4566 } __packed; 4567 4568 struct wmi_regulatory_ext_rule { 4569 uint32_t tlv_header; 4570 uint32_t freq_info; 4571 uint32_t bw_pwr_info; 4572 uint32_t flag_info; 4573 uint32_t psd_power_info; 4574 } __packed; 4575 4576 struct wmi_vdev_delete_resp_event { 4577 uint32_t vdev_id; 4578 } __packed; 4579 4580 struct wmi_peer_delete_resp_event { 4581 uint32_t vdev_id; 4582 struct wmi_mac_addr peer_macaddr; 4583 } __packed; 4584 4585 struct wmi_bcn_tx_status_event { 4586 uint32_t vdev_id; 4587 uint32_t tx_status; 4588 } __packed; 4589 4590 struct wmi_vdev_stopped_event { 4591 uint32_t vdev_id; 4592 } __packed; 4593 4594 struct wmi_pdev_bss_chan_info_event { 4595 uint32_t freq; /* Units in MHz */ 4596 uint32_t noise_floor; /* units are dBm */ 4597 /* rx clear - how often the channel was unused */ 4598 uint32_t rx_clear_count_low; 4599 uint32_t rx_clear_count_high; 4600 /* cycle count - elapsed time during measured period, in clock ticks */ 4601 uint32_t cycle_count_low; 4602 uint32_t cycle_count_high; 4603 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4604 uint32_t tx_cycle_count_low; 4605 uint32_t tx_cycle_count_high; 4606 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4607 uint32_t rx_cycle_count_low; 4608 uint32_t rx_cycle_count_high; 4609 /*rx_cycle cnt for my bss in 64bits format */ 4610 uint32_t rx_bss_cycle_count_low; 4611 uint32_t rx_bss_cycle_count_high; 4612 uint32_t pdev_id; 4613 } __packed; 4614 4615 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4616 4617 struct wmi_vdev_install_key_compl_event { 4618 uint32_t vdev_id; 4619 struct wmi_mac_addr peer_macaddr; 4620 uint32_t key_idx; 4621 uint32_t key_flags; 4622 uint32_t status; 4623 } __packed; 4624 4625 struct wmi_vdev_install_key_complete_arg { 4626 uint32_t vdev_id; 4627 const uint8_t *macaddr; 4628 uint32_t key_idx; 4629 uint32_t key_flags; 4630 uint32_t status; 4631 }; 4632 4633 struct wmi_peer_assoc_conf_event { 4634 uint32_t vdev_id; 4635 struct wmi_mac_addr peer_macaddr; 4636 } __packed; 4637 4638 struct wmi_peer_assoc_conf_arg { 4639 uint32_t vdev_id; 4640 const uint8_t *macaddr; 4641 }; 4642 4643 struct wmi_fils_discovery_event { 4644 uint32_t vdev_id; 4645 uint32_t fils_tt; 4646 uint32_t tbtt; 4647 } __packed; 4648 4649 struct wmi_probe_resp_tx_status_event { 4650 uint32_t vdev_id; 4651 uint32_t tx_status; 4652 } __packed; 4653 4654 /* 4655 * PDEV statistics 4656 */ 4657 struct wmi_pdev_stats_base { 4658 int32_t chan_nf; 4659 uint32_t tx_frame_count; /* Cycles spent transmitting frames */ 4660 uint32_t rx_frame_count; /* Cycles spent receiving frames */ 4661 uint32_t rx_clear_count; /* Total channel busy time, evidently */ 4662 uint32_t cycle_count; /* Total on-channel time */ 4663 uint32_t phy_err_count; 4664 uint32_t chan_tx_pwr; 4665 } __packed; 4666 4667 struct wmi_pdev_stats_extra { 4668 uint32_t ack_rx_bad; 4669 uint32_t rts_bad; 4670 uint32_t rts_good; 4671 uint32_t fcs_bad; 4672 uint32_t no_beacons; 4673 uint32_t mib_int_count; 4674 } __packed; 4675 4676 struct wmi_pdev_stats_tx { 4677 /* Num HTT cookies queued to dispatch list */ 4678 int32_t comp_queued; 4679 4680 /* Num HTT cookies dispatched */ 4681 int32_t comp_delivered; 4682 4683 /* Num MSDU queued to WAL */ 4684 int32_t msdu_enqued; 4685 4686 /* Num MPDU queue to WAL */ 4687 int32_t mpdu_enqued; 4688 4689 /* Num MSDUs dropped by WMM limit */ 4690 int32_t wmm_drop; 4691 4692 /* Num Local frames queued */ 4693 int32_t local_enqued; 4694 4695 /* Num Local frames done */ 4696 int32_t local_freed; 4697 4698 /* Num queued to HW */ 4699 int32_t hw_queued; 4700 4701 /* Num PPDU reaped from HW */ 4702 int32_t hw_reaped; 4703 4704 /* Num underruns */ 4705 int32_t underrun; 4706 4707 /* Num hw paused */ 4708 uint32_t hw_paused; 4709 4710 /* Num PPDUs cleaned up in TX abort */ 4711 int32_t tx_abort; 4712 4713 /* Num MPDUs requeued by SW */ 4714 int32_t mpdus_requeued; 4715 4716 /* excessive retries */ 4717 uint32_t tx_ko; 4718 4719 uint32_t tx_xretry; 4720 4721 /* data hw rate code */ 4722 uint32_t data_rc; 4723 4724 /* Scheduler self triggers */ 4725 uint32_t self_triggers; 4726 4727 /* frames dropped due to excessive sw retries */ 4728 uint32_t sw_retry_failure; 4729 4730 /* illegal rate phy errors */ 4731 uint32_t illgl_rate_phy_err; 4732 4733 /* wal pdev continuous xretry */ 4734 uint32_t pdev_cont_xretry; 4735 4736 /* wal pdev tx timeouts */ 4737 uint32_t pdev_tx_timeout; 4738 4739 /* wal pdev resets */ 4740 uint32_t pdev_resets; 4741 4742 /* frames dropped due to non-availability of stateless TIDs */ 4743 uint32_t stateless_tid_alloc_failure; 4744 4745 /* PhY/BB underrun */ 4746 uint32_t phy_underrun; 4747 4748 /* MPDU is more than txop limit */ 4749 uint32_t txop_ovf; 4750 4751 /* Num sequences posted */ 4752 uint32_t seq_posted; 4753 4754 /* Num sequences failed in queueing */ 4755 uint32_t seq_failed_queueing; 4756 4757 /* Num sequences completed */ 4758 uint32_t seq_completed; 4759 4760 /* Num sequences restarted */ 4761 uint32_t seq_restarted; 4762 4763 /* Num of MU sequences posted */ 4764 uint32_t mu_seq_posted; 4765 4766 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 4767 * (Reset,channel change) 4768 */ 4769 int32_t mpdus_sw_flush; 4770 4771 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 4772 int32_t mpdus_hw_filter; 4773 4774 /* Num MPDUs truncated by PDG (TXOP, TBTT, 4775 * PPDU_duration based on rate, dyn_bw) 4776 */ 4777 int32_t mpdus_truncated; 4778 4779 /* Num MPDUs that was tried but didn't receive ACK or BA */ 4780 int32_t mpdus_ack_failed; 4781 4782 /* Num MPDUs that was dropped du to expiry. */ 4783 int32_t mpdus_expired; 4784 } __packed; 4785 4786 struct wmi_pdev_stats_rx { 4787 /* Cnts any change in ring routing mid-ppdu */ 4788 int32_t mid_ppdu_route_change; 4789 4790 /* Total number of statuses processed */ 4791 int32_t status_rcvd; 4792 4793 /* Extra frags on rings 0-3 */ 4794 int32_t r0_frags; 4795 int32_t r1_frags; 4796 int32_t r2_frags; 4797 int32_t r3_frags; 4798 4799 /* MSDUs / MPDUs delivered to HTT */ 4800 int32_t htt_msdus; 4801 int32_t htt_mpdus; 4802 4803 /* MSDUs / MPDUs delivered to local stack */ 4804 int32_t loc_msdus; 4805 int32_t loc_mpdus; 4806 4807 /* AMSDUs that have more MSDUs than the status ring size */ 4808 int32_t oversize_amsdu; 4809 4810 /* Number of PHY errors */ 4811 int32_t phy_errs; 4812 4813 /* Number of PHY errors drops */ 4814 int32_t phy_err_drop; 4815 4816 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 4817 int32_t mpdu_errs; 4818 4819 /* Num overflow errors */ 4820 int32_t rx_ovfl_errs; 4821 } __packed; 4822 4823 struct wmi_pdev_stats { 4824 struct wmi_pdev_stats_base base; 4825 struct wmi_pdev_stats_tx tx; 4826 struct wmi_pdev_stats_rx rx; 4827 } __packed; 4828 4829 #define WLAN_MAX_AC 4 4830 #define MAX_TX_RATE_VALUES 10 4831 #define MAX_TX_RATE_VALUES 10 4832 4833 struct wmi_vdev_stats { 4834 uint32_t vdev_id; 4835 uint32_t beacon_snr; 4836 uint32_t data_snr; 4837 uint32_t num_tx_frames[WLAN_MAX_AC]; 4838 uint32_t num_rx_frames; 4839 uint32_t num_tx_frames_retries[WLAN_MAX_AC]; 4840 uint32_t num_tx_frames_failures[WLAN_MAX_AC]; 4841 uint32_t num_rts_fail; 4842 uint32_t num_rts_success; 4843 uint32_t num_rx_err; 4844 uint32_t num_rx_discard; 4845 uint32_t num_tx_not_acked; 4846 uint32_t tx_rate_history[MAX_TX_RATE_VALUES]; 4847 uint32_t beacon_rssi_history[MAX_TX_RATE_VALUES]; 4848 } __packed; 4849 4850 struct wmi_bcn_stats { 4851 uint32_t vdev_id; 4852 uint32_t tx_bcn_succ_cnt; 4853 uint32_t tx_bcn_outage_cnt; 4854 } __packed; 4855 4856 struct wmi_stats_event { 4857 uint32_t stats_id; 4858 uint32_t num_pdev_stats; 4859 uint32_t num_vdev_stats; 4860 uint32_t num_peer_stats; 4861 uint32_t num_bcnflt_stats; 4862 uint32_t num_chan_stats; 4863 uint32_t num_mib_stats; 4864 uint32_t pdev_id; 4865 uint32_t num_bcn_stats; 4866 uint32_t num_peer_extd_stats; 4867 uint32_t num_peer_extd2_stats; 4868 } __packed; 4869 4870 struct wmi_rssi_stats { 4871 uint32_t vdev_id; 4872 uint32_t rssi_avg_beacon[WMI_MAX_CHAINS]; 4873 uint32_t rssi_avg_data[WMI_MAX_CHAINS]; 4874 struct wmi_mac_addr peer_macaddr; 4875 } __packed; 4876 4877 struct wmi_per_chain_rssi_stats { 4878 uint32_t num_per_chain_rssi_stats; 4879 } __packed; 4880 4881 struct wmi_pdev_ctl_failsafe_chk_event { 4882 uint32_t pdev_id; 4883 uint32_t ctl_failsafe_status; 4884 } __packed; 4885 4886 struct wmi_pdev_csa_switch_ev { 4887 uint32_t pdev_id; 4888 uint32_t current_switch_count; 4889 uint32_t num_vdevs; 4890 } __packed; 4891 4892 struct wmi_pdev_radar_ev { 4893 uint32_t pdev_id; 4894 uint32_t detection_mode; 4895 uint32_t chan_freq; 4896 uint32_t chan_width; 4897 uint32_t detector_id; 4898 uint32_t segment_id; 4899 uint32_t timestamp; 4900 uint32_t is_chirp; 4901 int32_t freq_offset; 4902 int32_t sidx; 4903 } __packed; 4904 4905 struct wmi_pdev_temperature_event { 4906 /* temperature value in Celsius degree */ 4907 int32_t temp; 4908 uint32_t pdev_id; 4909 } __packed; 4910 4911 #define WMI_RX_STATUS_OK 0x00 4912 #define WMI_RX_STATUS_ERR_CRC 0x01 4913 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4914 #define WMI_RX_STATUS_ERR_MIC 0x10 4915 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4916 4917 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4918 4919 struct mgmt_rx_event_params { 4920 uint32_t chan_freq; 4921 uint32_t channel; 4922 uint32_t snr; 4923 uint8_t rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4924 uint32_t rate; 4925 enum wmi_phy_mode phy_mode; 4926 uint32_t buf_len; 4927 int status; 4928 uint32_t flags; 4929 int rssi; 4930 uint32_t tsf_delta; 4931 uint8_t pdev_id; 4932 }; 4933 4934 #define ATH_MAX_ANTENNA 4 4935 4936 struct wmi_mgmt_rx_hdr { 4937 uint32_t channel; 4938 uint32_t snr; 4939 uint32_t rate; 4940 uint32_t phy_mode; 4941 uint32_t buf_len; 4942 uint32_t status; 4943 uint32_t rssi_ctl[ATH_MAX_ANTENNA]; 4944 uint32_t flags; 4945 int rssi; 4946 uint32_t tsf_delta; 4947 uint32_t rx_tsf_l32; 4948 uint32_t rx_tsf_u32; 4949 uint32_t pdev_id; 4950 uint32_t chan_freq; 4951 } __packed; 4952 4953 #define MAX_ANTENNA_EIGHT 8 4954 4955 struct wmi_rssi_ctl_ext { 4956 uint32_t tlv_header; 4957 uint32_t rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA]; 4958 }; 4959 4960 struct wmi_mgmt_tx_compl_event { 4961 uint32_t desc_id; 4962 uint32_t status; 4963 uint32_t pdev_id; 4964 uint32_t ppdu_id; 4965 uint32_t ack_rssi; 4966 } __packed; 4967 4968 struct wmi_scan_event { 4969 uint32_t event_type; /* %WMI_SCAN_EVENT_ */ 4970 uint32_t reason; /* %WMI_SCAN_REASON_ */ 4971 uint32_t channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 4972 uint32_t scan_req_id; 4973 uint32_t scan_id; 4974 uint32_t vdev_id; 4975 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 4976 * In case of AP it is TSF of the AP vdev 4977 * In case of STA connected state, this is the TSF of the AP 4978 * In case of STA not connected, it will be the free running HW timer 4979 */ 4980 uint32_t tsf_timestamp; 4981 } __packed; 4982 4983 struct wmi_peer_sta_kickout_arg { 4984 const uint8_t *mac_addr; 4985 }; 4986 4987 struct wmi_peer_sta_kickout_event { 4988 struct wmi_mac_addr peer_macaddr; 4989 } __packed; 4990 4991 enum wmi_roam_reason { 4992 WMI_ROAM_REASON_BETTER_AP = 1, 4993 WMI_ROAM_REASON_BEACON_MISS = 2, 4994 WMI_ROAM_REASON_LOW_RSSI = 3, 4995 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 4996 WMI_ROAM_REASON_HO_FAILED = 5, 4997 4998 /* keep last */ 4999 WMI_ROAM_REASON_MAX, 5000 }; 5001 5002 struct wmi_roam_event { 5003 uint32_t vdev_id; 5004 uint32_t reason; 5005 uint32_t rssi; 5006 } __packed; 5007 5008 #define WMI_CHAN_INFO_START_RESP 0 5009 #define WMI_CHAN_INFO_END_RESP 1 5010 5011 struct wmi_chan_info_event { 5012 uint32_t err_code; 5013 uint32_t freq; 5014 uint32_t cmd_flags; 5015 uint32_t noise_floor; 5016 uint32_t rx_clear_count; 5017 uint32_t cycle_count; 5018 uint32_t chan_tx_pwr_range; 5019 uint32_t chan_tx_pwr_tp; 5020 uint32_t rx_frame_count; 5021 uint32_t my_bss_rx_cycle_count; 5022 uint32_t rx_11b_mode_data_duration; 5023 uint32_t tx_frame_cnt; 5024 uint32_t mac_clk_mhz; 5025 uint32_t vdev_id; 5026 } __packed; 5027 5028 struct ath11k_targ_cap { 5029 uint32_t phy_capability; 5030 uint32_t max_frag_entry; 5031 uint32_t num_rf_chains; 5032 uint32_t ht_cap_info; 5033 uint32_t vht_cap_info; 5034 uint32_t vht_supp_mcs; 5035 uint32_t hw_min_tx_power; 5036 uint32_t hw_max_tx_power; 5037 uint32_t sys_cap_info; 5038 uint32_t min_pkt_size_enable; 5039 uint32_t max_bcn_ie_size; 5040 uint32_t max_num_scan_channels; 5041 uint32_t max_supported_macs; 5042 uint32_t wmi_fw_sub_feat_caps; 5043 uint32_t txrx_chainmask; 5044 uint32_t default_dbs_hw_mode_index; 5045 uint32_t num_msdu_desc; 5046 }; 5047 5048 enum wmi_vdev_type { 5049 WMI_VDEV_TYPE_AP = 1, 5050 WMI_VDEV_TYPE_STA = 2, 5051 WMI_VDEV_TYPE_IBSS = 3, 5052 WMI_VDEV_TYPE_MONITOR = 4, 5053 }; 5054 5055 enum wmi_vdev_subtype { 5056 WMI_VDEV_SUBTYPE_NONE, 5057 WMI_VDEV_SUBTYPE_P2P_DEVICE, 5058 WMI_VDEV_SUBTYPE_P2P_CLIENT, 5059 WMI_VDEV_SUBTYPE_P2P_GO, 5060 WMI_VDEV_SUBTYPE_PROXY_STA, 5061 WMI_VDEV_SUBTYPE_MESH_NON_11S, 5062 WMI_VDEV_SUBTYPE_MESH_11S, 5063 }; 5064 5065 enum wmi_sta_powersave_param { 5066 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 5067 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 5068 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 5069 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 5070 WMI_STA_PS_PARAM_UAPSD = 4, 5071 }; 5072 5073 #define WMI_UAPSD_AC_TYPE_DELI 0 5074 #define WMI_UAPSD_AC_TYPE_TRIG 1 5075 5076 #define WMI_UAPSD_AC_BIT_MASK(ac, type) \ 5077 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \ 5078 (1 << (ac << 1)) : (1 << ((ac << 1) + 1))) 5079 5080 enum wmi_sta_ps_param_uapsd { 5081 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5082 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5083 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5084 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5085 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5086 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5087 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5088 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5089 }; 5090 5091 #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX 5092 5093 struct wmi_sta_uapsd_auto_trig_param { 5094 uint32_t wmm_ac; 5095 uint32_t user_priority; 5096 uint32_t service_interval; 5097 uint32_t suspend_interval; 5098 uint32_t delay_interval; 5099 }; 5100 5101 struct wmi_sta_uapsd_auto_trig_cmd_fixed_param { 5102 uint32_t vdev_id; 5103 struct wmi_mac_addr peer_macaddr; 5104 uint32_t num_ac; 5105 }; 5106 5107 struct wmi_sta_uapsd_auto_trig_arg { 5108 uint32_t wmm_ac; 5109 uint32_t user_priority; 5110 uint32_t service_interval; 5111 uint32_t suspend_interval; 5112 uint32_t delay_interval; 5113 }; 5114 5115 enum wmi_sta_ps_param_tx_wake_threshold { 5116 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 5117 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 5118 5119 /* Values greater than one indicate that many TX attempts per beacon 5120 * interval before the STA will wake up 5121 */ 5122 }; 5123 5124 /* The maximum number of PS-Poll frames the FW will send in response to 5125 * traffic advertised in TIM before waking up (by sending a null frame with PS 5126 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 5127 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 5128 * parameter is used when the RX wake policy is 5129 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 5130 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 5131 */ 5132 enum wmi_sta_ps_param_pspoll_count { 5133 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 5134 /* Values greater than 0 indicate the maximum number of PS-Poll frames 5135 * FW will send before waking up. 5136 */ 5137 }; 5138 5139 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 5140 enum wmi_ap_ps_param_uapsd { 5141 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5142 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5143 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5144 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5145 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5146 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5147 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5148 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5149 }; 5150 5151 /* U-APSD maximum service period of peer station */ 5152 enum wmi_ap_ps_peer_param_max_sp { 5153 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 5154 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 5155 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 5156 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 5157 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 5158 }; 5159 5160 enum wmi_ap_ps_peer_param { 5161 /** Set uapsd configuration for a given peer. 5162 * 5163 * This include the delivery and trigger enabled state for each AC. 5164 * The host MLME needs to set this based on AP capability and stations 5165 * request Set in the association request received from the station. 5166 * 5167 * Lower 8 bits of the value specify the UAPSD configuration. 5168 * 5169 * (see enum wmi_ap_ps_param_uapsd) 5170 * The default value is 0. 5171 */ 5172 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 5173 5174 /** 5175 * Set the service period for a UAPSD capable station 5176 * 5177 * The service period from wme ie in the (re)assoc request frame. 5178 * 5179 * (see enum wmi_ap_ps_peer_param_max_sp) 5180 */ 5181 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 5182 5183 /** Time in seconds for aging out buffered frames 5184 * for STA in power save 5185 */ 5186 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 5187 5188 /** Specify frame types that are considered SIFS 5189 * RESP trigger frame 5190 */ 5191 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 5192 5193 /** Specifies the trigger state of TID. 5194 * Valid only for UAPSD frame type 5195 */ 5196 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 5197 5198 /* Specifies the WNM sleep state of a STA */ 5199 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 5200 }; 5201 5202 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 5203 5204 #define WMI_MAX_KEY_INDEX 3 5205 #define WMI_MAX_KEY_LEN 32 5206 5207 #define WMI_KEY_PAIRWISE 0x00 5208 #define WMI_KEY_GROUP 0x01 5209 5210 #define WMI_CIPHER_NONE 0x0 /* clear key */ 5211 #define WMI_CIPHER_WEP 0x1 5212 #define WMI_CIPHER_TKIP 0x2 5213 #define WMI_CIPHER_AES_OCB 0x3 5214 #define WMI_CIPHER_AES_CCM 0x4 5215 #define WMI_CIPHER_WAPI 0x5 5216 #define WMI_CIPHER_CKIP 0x6 5217 #define WMI_CIPHER_AES_CMAC 0x7 5218 #define WMI_CIPHER_ANY 0x8 5219 #define WMI_CIPHER_AES_GCM 0x9 5220 #define WMI_CIPHER_AES_GMAC 0xa 5221 5222 /* Value to disable fixed rate setting */ 5223 #define WMI_FIXED_RATE_NONE (0xffff) 5224 5225 #define ATH11K_RC_VERSION_OFFSET 28 5226 #define ATH11K_RC_PREAMBLE_OFFSET 8 5227 #define ATH11K_RC_NSS_OFFSET 5 5228 5229 #define ATH11K_HW_RATE_CODE(rate, nss, preamble) \ 5230 ((1 << ATH11K_RC_VERSION_OFFSET) | \ 5231 ((nss) << ATH11K_RC_NSS_OFFSET) | \ 5232 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) | \ 5233 (rate)) 5234 5235 /* Preamble types to be used with VDEV fixed rate configuration */ 5236 enum wmi_rate_preamble { 5237 WMI_RATE_PREAMBLE_OFDM, 5238 WMI_RATE_PREAMBLE_CCK, 5239 WMI_RATE_PREAMBLE_HT, 5240 WMI_RATE_PREAMBLE_VHT, 5241 WMI_RATE_PREAMBLE_HE, 5242 }; 5243 5244 /** 5245 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 5246 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 5247 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 5248 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 5249 */ 5250 enum wmi_rtscts_prot_mode { 5251 WMI_RTS_CTS_DISABLED = 0, 5252 WMI_USE_RTS_CTS = 1, 5253 WMI_USE_CTS2SELF = 2, 5254 }; 5255 5256 /** 5257 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 5258 * protection mode. 5259 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 5260 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 5261 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 5262 * but if there's a sw retry, both the rate 5263 * series will use RTS-CTS. 5264 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 5265 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 5266 */ 5267 enum wmi_rtscts_profile { 5268 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 5269 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 5270 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 5271 WMI_RTSCTS_ERP = 3, 5272 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 5273 }; 5274 5275 struct ath11k_hal_reg_cap { 5276 uint32_t eeprom_rd; 5277 uint32_t eeprom_rd_ext; 5278 uint32_t regcap1; 5279 uint32_t regcap2; 5280 uint32_t wireless_modes; 5281 uint32_t low_2ghz_chan; 5282 uint32_t high_2ghz_chan; 5283 uint32_t low_5ghz_chan; 5284 uint32_t high_5ghz_chan; 5285 }; 5286 5287 struct ath11k_mem_chunk { 5288 void *vaddr; 5289 bus_addr_t paddr; 5290 uint32_t len; 5291 uint32_t req_id; 5292 }; 5293 5294 enum wmi_sta_ps_param_rx_wake_policy { 5295 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 5296 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 5297 }; 5298 5299 /* Do not change existing values! Used by ath11k_frame_mode parameter 5300 * module parameter. 5301 */ 5302 enum ath11k_hw_txrx_mode { 5303 ATH11K_HW_TXRX_RAW = 0, 5304 ATH11K_HW_TXRX_NATIVE_WIFI = 1, 5305 ATH11K_HW_TXRX_ETHERNET = 2, 5306 }; 5307 5308 struct wmi_wmm_params { 5309 uint32_t tlv_header; 5310 uint32_t cwmin; 5311 uint32_t cwmax; 5312 uint32_t aifs; 5313 uint32_t txoplimit; 5314 uint32_t acm; 5315 uint32_t no_ack; 5316 } __packed; 5317 5318 struct wmi_wmm_params_arg { 5319 uint8_t acm; 5320 uint8_t aifs; 5321 uint16_t cwmin; 5322 uint16_t cwmax; 5323 uint16_t txop; 5324 uint8_t no_ack; 5325 }; 5326 5327 struct wmi_vdev_set_wmm_params_cmd { 5328 uint32_t tlv_header; 5329 uint32_t vdev_id; 5330 struct wmi_wmm_params wmm_params[4]; 5331 uint32_t wmm_param_type; 5332 } __packed; 5333 5334 struct wmi_wmm_params_all_arg { 5335 struct wmi_wmm_params_arg ac_be; 5336 struct wmi_wmm_params_arg ac_bk; 5337 struct wmi_wmm_params_arg ac_vi; 5338 struct wmi_wmm_params_arg ac_vo; 5339 }; 5340 5341 #define ATH11K_TWT_DEF_STA_CONG_TIMER_MS 5000 5342 #define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE 10 5343 #define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP 50 5344 #define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 5345 #define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 5346 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 5347 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 5348 #define ATH11K_TWT_DEF_MIN_NO_STA_SETUP 10 5349 #define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 5350 #define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 5351 #define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS 2 5352 #define ATH11K_TWT_DEF_MAX_NO_STA_TWT 500 5353 #define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL 10000 5354 #define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 5355 #define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 5356 5357 struct wmi_twt_enable_params { 5358 uint32_t sta_cong_timer_ms; 5359 uint32_t mbss_support; 5360 uint32_t default_slot_size; 5361 uint32_t congestion_thresh_setup; 5362 uint32_t congestion_thresh_teardown; 5363 uint32_t congestion_thresh_critical; 5364 uint32_t interference_thresh_teardown; 5365 uint32_t interference_thresh_setup; 5366 uint32_t min_no_sta_setup; 5367 uint32_t min_no_sta_teardown; 5368 uint32_t no_of_bcast_mcast_slots; 5369 uint32_t min_no_twt_slots; 5370 uint32_t max_no_sta_twt; 5371 uint32_t mode_check_interval; 5372 uint32_t add_sta_slot_interval; 5373 uint32_t remove_sta_slot_interval; 5374 }; 5375 5376 struct wmi_twt_enable_params_cmd { 5377 uint32_t tlv_header; 5378 uint32_t pdev_id; 5379 uint32_t sta_cong_timer_ms; 5380 uint32_t mbss_support; 5381 uint32_t default_slot_size; 5382 uint32_t congestion_thresh_setup; 5383 uint32_t congestion_thresh_teardown; 5384 uint32_t congestion_thresh_critical; 5385 uint32_t interference_thresh_teardown; 5386 uint32_t interference_thresh_setup; 5387 uint32_t min_no_sta_setup; 5388 uint32_t min_no_sta_teardown; 5389 uint32_t no_of_bcast_mcast_slots; 5390 uint32_t min_no_twt_slots; 5391 uint32_t max_no_sta_twt; 5392 uint32_t mode_check_interval; 5393 uint32_t add_sta_slot_interval; 5394 uint32_t remove_sta_slot_interval; 5395 } __packed; 5396 5397 struct wmi_twt_disable_params_cmd { 5398 uint32_t tlv_header; 5399 uint32_t pdev_id; 5400 } __packed; 5401 5402 enum WMI_HOST_TWT_COMMAND { 5403 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0, 5404 WMI_HOST_TWT_COMMAND_SUGGEST_TWT, 5405 WMI_HOST_TWT_COMMAND_DEMAND_TWT, 5406 WMI_HOST_TWT_COMMAND_TWT_GROUPING, 5407 WMI_HOST_TWT_COMMAND_ACCEPT_TWT, 5408 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT, 5409 WMI_HOST_TWT_COMMAND_DICTATE_TWT, 5410 WMI_HOST_TWT_COMMAND_REJECT_TWT, 5411 }; 5412 5413 #define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8) 5414 #define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9) 5415 #define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10) 5416 #define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11) 5417 5418 struct wmi_twt_add_dialog_params_cmd { 5419 uint32_t tlv_header; 5420 uint32_t vdev_id; 5421 struct wmi_mac_addr peer_macaddr; 5422 uint32_t dialog_id; 5423 uint32_t wake_intvl_us; 5424 uint32_t wake_intvl_mantis; 5425 uint32_t wake_dura_us; 5426 uint32_t sp_offset_us; 5427 uint32_t flags; 5428 } __packed; 5429 5430 struct wmi_twt_add_dialog_params { 5431 uint32_t vdev_id; 5432 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5433 uint32_t dialog_id; 5434 uint32_t wake_intvl_us; 5435 uint32_t wake_intvl_mantis; 5436 uint32_t wake_dura_us; 5437 uint32_t sp_offset_us; 5438 uint8_t twt_cmd; 5439 uint8_t flag_bcast; 5440 uint8_t flag_trigger; 5441 uint8_t flag_flow_type; 5442 uint8_t flag_protection; 5443 } __packed; 5444 5445 enum wmi_twt_add_dialog_status { 5446 WMI_ADD_TWT_STATUS_OK, 5447 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED, 5448 WMI_ADD_TWT_STATUS_USED_DIALOG_ID, 5449 WMI_ADD_TWT_STATUS_INVALID_PARAM, 5450 WMI_ADD_TWT_STATUS_NOT_READY, 5451 WMI_ADD_TWT_STATUS_NO_RESOURCE, 5452 WMI_ADD_TWT_STATUS_NO_ACK, 5453 WMI_ADD_TWT_STATUS_NO_RESPONSE, 5454 WMI_ADD_TWT_STATUS_DENIED, 5455 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR, 5456 }; 5457 5458 struct wmi_twt_add_dialog_event { 5459 uint32_t vdev_id; 5460 struct wmi_mac_addr peer_macaddr; 5461 uint32_t dialog_id; 5462 uint32_t status; 5463 } __packed; 5464 5465 struct wmi_twt_del_dialog_params { 5466 uint32_t vdev_id; 5467 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5468 uint32_t dialog_id; 5469 } __packed; 5470 5471 struct wmi_twt_del_dialog_params_cmd { 5472 uint32_t tlv_header; 5473 uint32_t vdev_id; 5474 struct wmi_mac_addr peer_macaddr; 5475 uint32_t dialog_id; 5476 } __packed; 5477 5478 struct wmi_twt_pause_dialog_params { 5479 uint32_t vdev_id; 5480 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5481 uint32_t dialog_id; 5482 } __packed; 5483 5484 struct wmi_twt_pause_dialog_params_cmd { 5485 uint32_t tlv_header; 5486 uint32_t vdev_id; 5487 struct wmi_mac_addr peer_macaddr; 5488 uint32_t dialog_id; 5489 } __packed; 5490 5491 struct wmi_twt_resume_dialog_params { 5492 uint32_t vdev_id; 5493 uint8_t peer_macaddr[IEEE80211_ADDR_LEN]; 5494 uint32_t dialog_id; 5495 uint32_t sp_offset_us; 5496 uint32_t next_twt_size; 5497 } __packed; 5498 5499 struct wmi_twt_resume_dialog_params_cmd { 5500 uint32_t tlv_header; 5501 uint32_t vdev_id; 5502 struct wmi_mac_addr peer_macaddr; 5503 uint32_t dialog_id; 5504 uint32_t sp_offset_us; 5505 uint32_t next_twt_size; 5506 } __packed; 5507 5508 struct wmi_obss_spatial_reuse_params_cmd { 5509 uint32_t tlv_header; 5510 uint32_t pdev_id; 5511 uint32_t enable; 5512 int32_t obss_min; 5513 int32_t obss_max; 5514 uint32_t vdev_id; 5515 } __packed; 5516 5517 struct wmi_pdev_obss_pd_bitmap_cmd { 5518 uint32_t tlv_header; 5519 uint32_t pdev_id; 5520 uint32_t bitmap[2]; 5521 } __packed; 5522 5523 #define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 5524 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 5525 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION 1 5526 5527 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000 5528 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000 5529 5530 enum wmi_bss_color_collision { 5531 WMI_BSS_COLOR_COLLISION_DISABLE = 0, 5532 WMI_BSS_COLOR_COLLISION_DETECTION, 5533 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, 5534 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, 5535 }; 5536 5537 struct wmi_obss_color_collision_cfg_params_cmd { 5538 uint32_t tlv_header; 5539 uint32_t vdev_id; 5540 uint32_t flags; 5541 uint32_t evt_type; 5542 uint32_t current_bss_color; 5543 uint32_t detection_period_ms; 5544 uint32_t scan_period_ms; 5545 uint32_t free_slot_expiry_time_ms; 5546 } __packed; 5547 5548 struct wmi_bss_color_change_enable_params_cmd { 5549 uint32_t tlv_header; 5550 uint32_t vdev_id; 5551 uint32_t enable; 5552 } __packed; 5553 5554 struct wmi_obss_color_collision_event { 5555 uint32_t vdev_id; 5556 uint32_t evt_type; 5557 uint64_t obss_color_bitmap; 5558 } __packed; 5559 5560 #define ATH11K_IPV4_TH_SEED_SIZE 5 5561 #define ATH11K_IPV6_TH_SEED_SIZE 11 5562 5563 struct ath11k_wmi_pdev_lro_config_cmd { 5564 uint32_t tlv_header; 5565 uint32_t lro_enable; 5566 uint32_t res; 5567 uint32_t th_4[ATH11K_IPV4_TH_SEED_SIZE]; 5568 uint32_t th_6[ATH11K_IPV6_TH_SEED_SIZE]; 5569 uint32_t pdev_id; 5570 } __packed; 5571 5572 #define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT 0 5573 #define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT 224 5574 #define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 5575 #define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 5576 #define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 5577 #define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 5578 #define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 5579 #define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 5580 #define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 5581 #define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 5582 #define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 5583 #define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 5584 #define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 5585 #define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 5586 #define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 5587 #define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 5588 #define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 5589 #define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 5590 5591 struct ath11k_wmi_vdev_spectral_conf_param { 5592 uint32_t vdev_id; 5593 uint32_t scan_count; 5594 uint32_t scan_period; 5595 uint32_t scan_priority; 5596 uint32_t scan_fft_size; 5597 uint32_t scan_gc_ena; 5598 uint32_t scan_restart_ena; 5599 uint32_t scan_noise_floor_ref; 5600 uint32_t scan_init_delay; 5601 uint32_t scan_nb_tone_thr; 5602 uint32_t scan_str_bin_thr; 5603 uint32_t scan_wb_rpt_mode; 5604 uint32_t scan_rssi_rpt_mode; 5605 uint32_t scan_rssi_thr; 5606 uint32_t scan_pwr_format; 5607 uint32_t scan_rpt_mode; 5608 uint32_t scan_bin_scale; 5609 uint32_t scan_dbm_adj; 5610 uint32_t scan_chn_mask; 5611 } __packed; 5612 5613 struct ath11k_wmi_vdev_spectral_conf_cmd { 5614 uint32_t tlv_header; 5615 struct ath11k_wmi_vdev_spectral_conf_param param; 5616 } __packed; 5617 5618 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 5619 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 5620 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 5621 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 5622 5623 struct ath11k_wmi_vdev_spectral_enable_cmd { 5624 uint32_t tlv_header; 5625 uint32_t vdev_id; 5626 uint32_t trigger_cmd; 5627 uint32_t enable_cmd; 5628 } __packed; 5629 5630 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd { 5631 uint32_t tlv_header; 5632 uint32_t pdev_id; 5633 uint32_t module_id; /* see enum wmi_direct_buffer_module */ 5634 uint32_t base_paddr_lo; 5635 uint32_t base_paddr_hi; 5636 uint32_t head_idx_paddr_lo; 5637 uint32_t head_idx_paddr_hi; 5638 uint32_t tail_idx_paddr_lo; 5639 uint32_t tail_idx_paddr_hi; 5640 uint32_t num_elems; /* Number of elems in the ring */ 5641 uint32_t buf_size; /* size of allocated buffer in bytes */ 5642 5643 /* Number of wmi_dma_buf_release_entry packed together */ 5644 uint32_t num_resp_per_event; 5645 5646 /* Target should timeout and send whatever resp 5647 * it has if this time expires, units in milliseconds 5648 */ 5649 uint32_t event_timeout_ms; 5650 } __packed; 5651 5652 struct ath11k_wmi_dma_buf_release_fixed_param { 5653 uint32_t pdev_id; 5654 uint32_t module_id; 5655 uint32_t num_buf_release_entry; 5656 uint32_t num_meta_data_entry; 5657 } __packed; 5658 5659 struct wmi_dma_buf_release_entry { 5660 uint32_t tlv_header; 5661 uint32_t paddr_lo; 5662 5663 /* Bits 11:0: address of data 5664 * Bits 31:12: host context data 5665 */ 5666 uint32_t paddr_hi; 5667 } __packed; 5668 5669 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5670 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5671 5672 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5673 5674 struct wmi_dma_buf_release_meta_data { 5675 uint32_t tlv_header; 5676 int32_t noise_floor[WMI_MAX_CHAINS]; 5677 uint32_t reset_delay; 5678 uint32_t freq1; 5679 uint32_t freq2; 5680 uint32_t ch_width; 5681 } __packed; 5682 5683 enum wmi_fils_discovery_cmd_type { 5684 WMI_FILS_DISCOVERY_CMD, 5685 WMI_UNSOL_BCAST_PROBE_RESP, 5686 }; 5687 5688 struct wmi_fils_discovery_cmd { 5689 uint32_t tlv_header; 5690 uint32_t vdev_id; 5691 uint32_t interval; 5692 uint32_t config; /* enum wmi_fils_discovery_cmd_type */ 5693 } __packed; 5694 5695 struct wmi_fils_discovery_tmpl_cmd { 5696 uint32_t tlv_header; 5697 uint32_t vdev_id; 5698 uint32_t buf_len; 5699 } __packed; 5700 5701 struct wmi_probe_tmpl_cmd { 5702 uint32_t tlv_header; 5703 uint32_t vdev_id; 5704 uint32_t buf_len; 5705 } __packed; 5706 5707 struct target_resource_config { 5708 uint32_t num_vdevs; 5709 uint32_t num_peers; 5710 uint32_t num_active_peers; 5711 uint32_t num_offload_peers; 5712 uint32_t num_offload_reorder_buffs; 5713 uint32_t num_peer_keys; 5714 uint32_t num_tids; 5715 uint32_t ast_skid_limit; 5716 uint32_t tx_chain_mask; 5717 uint32_t rx_chain_mask; 5718 uint32_t rx_timeout_pri[4]; 5719 uint32_t rx_decap_mode; 5720 uint32_t scan_max_pending_req; 5721 uint32_t bmiss_offload_max_vdev; 5722 uint32_t roam_offload_max_vdev; 5723 uint32_t roam_offload_max_ap_profiles; 5724 uint32_t num_mcast_groups; 5725 uint32_t num_mcast_table_elems; 5726 uint32_t mcast2ucast_mode; 5727 uint32_t tx_dbg_log_size; 5728 uint32_t num_wds_entries; 5729 uint32_t dma_burst_size; 5730 uint32_t mac_aggr_delim; 5731 uint32_t rx_skip_defrag_timeout_dup_detection_check; 5732 uint32_t vow_config; 5733 uint32_t gtk_offload_max_vdev; 5734 uint32_t num_msdu_desc; 5735 uint32_t max_frag_entries; 5736 uint32_t max_peer_ext_stats; 5737 uint32_t smart_ant_cap; 5738 uint32_t bk_minfree; 5739 uint32_t be_minfree; 5740 uint32_t vi_minfree; 5741 uint32_t vo_minfree; 5742 uint32_t rx_batchmode; 5743 uint32_t tt_support; 5744 uint32_t flag1; 5745 uint32_t iphdr_pad_config; 5746 uint32_t qwrap_config:16, 5747 alloc_frag_desc_for_data_pkt:16; 5748 uint32_t num_tdls_vdevs; 5749 uint32_t num_tdls_conn_table_entries; 5750 uint32_t beacon_tx_offload_max_vdev; 5751 uint32_t num_multicast_filter_entries; 5752 uint32_t num_wow_filters; 5753 uint32_t num_keep_alive_pattern; 5754 uint32_t keep_alive_pattern_size; 5755 uint32_t max_tdls_concurrent_sleep_sta; 5756 uint32_t max_tdls_concurrent_buffer_sta; 5757 uint32_t wmi_send_separate; 5758 uint32_t num_ocb_vdevs; 5759 uint32_t num_ocb_channels; 5760 uint32_t num_ocb_schedules; 5761 uint32_t num_ns_ext_tuples_cfg; 5762 uint32_t bpf_instruction_size; 5763 uint32_t max_bssid_rx_filters; 5764 uint32_t use_pdev_id; 5765 uint32_t peer_map_unmap_v2_support; 5766 uint32_t sched_params; 5767 uint32_t twt_ap_pdev_count; 5768 uint32_t twt_ap_sta_count; 5769 uint8_t is_reg_cc_ext_event_supported; 5770 uint32_t ema_max_vap_cnt; 5771 uint32_t ema_max_profile_period; 5772 }; 5773 5774 enum wmi_debug_log_param { 5775 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1, 5776 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE, 5777 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE, 5778 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP, 5779 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP, 5780 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP, 5781 }; 5782 5783 struct wmi_debug_log_config_cmd_fixed_param { 5784 uint32_t tlv_header; 5785 uint32_t dbg_log_param; 5786 uint32_t value; 5787 } __packed; 5788 5789 #define WMI_MAX_MEM_REQS 32 5790 5791 #define MAX_RADIOS 3 5792 5793 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5794 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5795 5796 enum ath11k_wmi_peer_ps_state { 5797 WMI_PEER_PS_STATE_OFF, 5798 WMI_PEER_PS_STATE_ON, 5799 WMI_PEER_PS_STATE_DISABLED, 5800 }; 5801 5802 enum wmi_peer_ps_supported_bitmap { 5803 /* Used to indicate that power save state change is valid */ 5804 WMI_PEER_PS_VALID = 0x1, 5805 WMI_PEER_PS_STATE_TIMESTAMP = 0x2, 5806 }; 5807 5808 struct wmi_peer_sta_ps_state_chg_event { 5809 struct wmi_mac_addr peer_macaddr; 5810 uint32_t peer_ps_state; 5811 uint32_t ps_supported_bitmap; 5812 uint32_t peer_ps_valid; 5813 uint32_t peer_ps_timestamp; 5814 } __packed; 5815 5816 /* Definition of HW data filtering */ 5817 enum hw_data_filter_type { 5818 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5819 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5820 }; 5821 5822 struct wmi_hw_data_filter_cmd { 5823 uint32_t tlv_header; 5824 uint32_t vdev_id; 5825 uint32_t enable; 5826 uint32_t hw_filter_bitmap; 5827 } __packed; 5828 5829 /* WOW structures */ 5830 enum wmi_wow_wakeup_event { 5831 WOW_BMISS_EVENT = 0, 5832 WOW_BETTER_AP_EVENT, 5833 WOW_DEAUTH_RECVD_EVENT, 5834 WOW_MAGIC_PKT_RECVD_EVENT, 5835 WOW_GTK_ERR_EVENT, 5836 WOW_FOURWAY_HSHAKE_EVENT, 5837 WOW_EAPOL_RECVD_EVENT, 5838 WOW_NLO_DETECTED_EVENT, 5839 WOW_DISASSOC_RECVD_EVENT, 5840 WOW_PATTERN_MATCH_EVENT, 5841 WOW_CSA_IE_EVENT, 5842 WOW_PROBE_REQ_WPS_IE_EVENT, 5843 WOW_AUTH_REQ_EVENT, 5844 WOW_ASSOC_REQ_EVENT, 5845 WOW_HTT_EVENT, 5846 WOW_RA_MATCH_EVENT, 5847 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5848 WOW_IOAC_MAGIC_EVENT, 5849 WOW_IOAC_SHORT_EVENT, 5850 WOW_IOAC_EXTEND_EVENT, 5851 WOW_IOAC_TIMER_EVENT, 5852 WOW_DFS_PHYERR_RADAR_EVENT, 5853 WOW_BEACON_EVENT, 5854 WOW_CLIENT_KICKOUT_EVENT, 5855 WOW_EVENT_MAX, 5856 }; 5857 5858 enum wmi_wow_interface_cfg { 5859 WOW_IFACE_PAUSE_ENABLED, 5860 WOW_IFACE_PAUSE_DISABLED 5861 }; 5862 5863 #define C2S(x) case x: return #x 5864 5865 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5866 { 5867 switch (ev) { 5868 C2S(WOW_BMISS_EVENT); 5869 C2S(WOW_BETTER_AP_EVENT); 5870 C2S(WOW_DEAUTH_RECVD_EVENT); 5871 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5872 C2S(WOW_GTK_ERR_EVENT); 5873 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5874 C2S(WOW_EAPOL_RECVD_EVENT); 5875 C2S(WOW_NLO_DETECTED_EVENT); 5876 C2S(WOW_DISASSOC_RECVD_EVENT); 5877 C2S(WOW_PATTERN_MATCH_EVENT); 5878 C2S(WOW_CSA_IE_EVENT); 5879 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5880 C2S(WOW_AUTH_REQ_EVENT); 5881 C2S(WOW_ASSOC_REQ_EVENT); 5882 C2S(WOW_HTT_EVENT); 5883 C2S(WOW_RA_MATCH_EVENT); 5884 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5885 C2S(WOW_IOAC_MAGIC_EVENT); 5886 C2S(WOW_IOAC_SHORT_EVENT); 5887 C2S(WOW_IOAC_EXTEND_EVENT); 5888 C2S(WOW_IOAC_TIMER_EVENT); 5889 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5890 C2S(WOW_BEACON_EVENT); 5891 C2S(WOW_CLIENT_KICKOUT_EVENT); 5892 C2S(WOW_EVENT_MAX); 5893 default: 5894 return NULL; 5895 } 5896 } 5897 5898 enum wmi_wow_wake_reason { 5899 WOW_REASON_UNSPECIFIED = -1, 5900 WOW_REASON_NLOD = 0, 5901 WOW_REASON_AP_ASSOC_LOST, 5902 WOW_REASON_LOW_RSSI, 5903 WOW_REASON_DEAUTH_RECVD, 5904 WOW_REASON_DISASSOC_RECVD, 5905 WOW_REASON_GTK_HS_ERR, 5906 WOW_REASON_EAP_REQ, 5907 WOW_REASON_FOURWAY_HS_RECV, 5908 WOW_REASON_TIMER_INTR_RECV, 5909 WOW_REASON_PATTERN_MATCH_FOUND, 5910 WOW_REASON_RECV_MAGIC_PATTERN, 5911 WOW_REASON_P2P_DISC, 5912 WOW_REASON_WLAN_HB, 5913 WOW_REASON_CSA_EVENT, 5914 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5915 WOW_REASON_AUTH_REQ_RECV, 5916 WOW_REASON_ASSOC_REQ_RECV, 5917 WOW_REASON_HTT_EVENT, 5918 WOW_REASON_RA_MATCH, 5919 WOW_REASON_HOST_AUTO_SHUTDOWN, 5920 WOW_REASON_IOAC_MAGIC_EVENT, 5921 WOW_REASON_IOAC_SHORT_EVENT, 5922 WOW_REASON_IOAC_EXTEND_EVENT, 5923 WOW_REASON_IOAC_TIMER_EVENT, 5924 WOW_REASON_ROAM_HO, 5925 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5926 WOW_REASON_BEACON_RECV, 5927 WOW_REASON_CLIENT_KICKOUT_EVENT, 5928 WOW_REASON_PAGE_FAULT = 0x3a, 5929 WOW_REASON_DEBUG_TEST = 0xFF, 5930 }; 5931 5932 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5933 { 5934 switch (reason) { 5935 C2S(WOW_REASON_UNSPECIFIED); 5936 C2S(WOW_REASON_NLOD); 5937 C2S(WOW_REASON_AP_ASSOC_LOST); 5938 C2S(WOW_REASON_LOW_RSSI); 5939 C2S(WOW_REASON_DEAUTH_RECVD); 5940 C2S(WOW_REASON_DISASSOC_RECVD); 5941 C2S(WOW_REASON_GTK_HS_ERR); 5942 C2S(WOW_REASON_EAP_REQ); 5943 C2S(WOW_REASON_FOURWAY_HS_RECV); 5944 C2S(WOW_REASON_TIMER_INTR_RECV); 5945 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 5946 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 5947 C2S(WOW_REASON_P2P_DISC); 5948 C2S(WOW_REASON_WLAN_HB); 5949 C2S(WOW_REASON_CSA_EVENT); 5950 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 5951 C2S(WOW_REASON_AUTH_REQ_RECV); 5952 C2S(WOW_REASON_ASSOC_REQ_RECV); 5953 C2S(WOW_REASON_HTT_EVENT); 5954 C2S(WOW_REASON_RA_MATCH); 5955 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 5956 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 5957 C2S(WOW_REASON_IOAC_SHORT_EVENT); 5958 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 5959 C2S(WOW_REASON_IOAC_TIMER_EVENT); 5960 C2S(WOW_REASON_ROAM_HO); 5961 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 5962 C2S(WOW_REASON_BEACON_RECV); 5963 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 5964 C2S(WOW_REASON_PAGE_FAULT); 5965 C2S(WOW_REASON_DEBUG_TEST); 5966 default: 5967 return NULL; 5968 } 5969 } 5970 5971 #undef C2S 5972 5973 struct wmi_wow_ev_arg { 5974 uint32_t vdev_id; 5975 uint32_t flag; 5976 enum wmi_wow_wake_reason wake_reason; 5977 uint32_t data_len; 5978 }; 5979 5980 enum wmi_tlv_pattern_type { 5981 WOW_PATTERN_MIN = 0, 5982 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 5983 WOW_IPV4_SYNC_PATTERN, 5984 WOW_IPV6_SYNC_PATTERN, 5985 WOW_WILD_CARD_PATTERN, 5986 WOW_TIMER_PATTERN, 5987 WOW_MAGIC_PATTERN, 5988 WOW_IPV6_RA_PATTERN, 5989 WOW_IOAC_PKT_PATTERN, 5990 WOW_IOAC_TMR_PATTERN, 5991 WOW_PATTERN_MAX 5992 }; 5993 5994 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 5995 #define WOW_DEFAULT_BITMASK_SIZE 148 5996 5997 #define WOW_MIN_PATTERN_SIZE 1 5998 #define WOW_MAX_PATTERN_SIZE 148 5999 #define WOW_MAX_PKT_OFFSET 128 6000 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 6001 sizeof(struct rfc1042_hdr)) 6002 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 6003 offsetof(struct ieee80211_hdr_3addr, addr1)) 6004 6005 struct wmi_wow_add_del_event_cmd { 6006 uint32_t tlv_header; 6007 uint32_t vdev_id; 6008 uint32_t is_add; 6009 uint32_t event_bitmap; 6010 } __packed; 6011 6012 struct wmi_wow_enable_cmd { 6013 uint32_t tlv_header; 6014 uint32_t enable; 6015 uint32_t pause_iface_config; 6016 uint32_t flags; 6017 } __packed; 6018 6019 struct wmi_wow_host_wakeup_ind { 6020 uint32_t tlv_header; 6021 uint32_t reserved; 6022 } __packed; 6023 6024 struct wmi_tlv_wow_event_info { 6025 uint32_t vdev_id; 6026 uint32_t flag; 6027 uint32_t wake_reason; 6028 uint32_t data_len; 6029 } __packed; 6030 6031 struct wmi_wow_bitmap_pattern { 6032 uint32_t tlv_header; 6033 uint8_t patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 6034 uint8_t bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 6035 uint32_t pattern_offset; 6036 uint32_t pattern_len; 6037 uint32_t bitmask_len; 6038 uint32_t pattern_id; 6039 } __packed; 6040 6041 struct wmi_wow_add_pattern_cmd { 6042 uint32_t tlv_header; 6043 uint32_t vdev_id; 6044 uint32_t pattern_id; 6045 uint32_t pattern_type; 6046 } __packed; 6047 6048 struct wmi_wow_del_pattern_cmd { 6049 uint32_t tlv_header; 6050 uint32_t vdev_id; 6051 uint32_t pattern_id; 6052 uint32_t pattern_type; 6053 } __packed; 6054 6055 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 6056 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 6057 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 6058 #define WMI_PNO_MAX_NETW_CHANNELS 26 6059 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 6060 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 6061 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 6062 6063 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 6064 #define WMI_PNO_MAX_PB_REQ_SIZE 450 6065 6066 #define WMI_PNO_24G_DEFAULT_CH 1 6067 #define WMI_PNO_5G_DEFAULT_CH 36 6068 6069 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 6070 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 6071 6072 /* SSID broadcast type */ 6073 enum wmi_ssid_bcast_type { 6074 BCAST_UNKNOWN = 0, 6075 BCAST_NORMAL = 1, 6076 BCAST_HIDDEN = 2, 6077 }; 6078 6079 #define WMI_NLO_MAX_SSIDS 16 6080 #define WMI_NLO_MAX_CHAN 48 6081 6082 #define WMI_NLO_CONFIG_STOP BIT(0) 6083 #define WMI_NLO_CONFIG_START BIT(1) 6084 #define WMI_NLO_CONFIG_RESET BIT(2) 6085 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 6086 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 6087 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 6088 6089 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 6090 * Only one of them can be enabled at a given time 6091 */ 6092 #define WMI_NLO_CONFIG_ENLO BIT(7) 6093 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 6094 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 6095 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 6096 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 6097 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 6098 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 6099 6100 struct wmi_nlo_ssid_param { 6101 uint32_t valid; 6102 struct wmi_ssid ssid; 6103 } __packed; 6104 6105 struct wmi_nlo_enc_param { 6106 uint32_t valid; 6107 uint32_t enc_type; 6108 } __packed; 6109 6110 struct wmi_nlo_auth_param { 6111 uint32_t valid; 6112 uint32_t auth_type; 6113 } __packed; 6114 6115 struct wmi_nlo_bcast_nw_param { 6116 uint32_t valid; 6117 uint32_t bcast_nw_type; 6118 } __packed; 6119 6120 struct wmi_nlo_rssi_param { 6121 uint32_t valid; 6122 int32_t rssi; 6123 } __packed; 6124 6125 struct nlo_configured_parameters { 6126 /* TLV tag and len;*/ 6127 uint32_t tlv_header; 6128 struct wmi_nlo_ssid_param ssid; 6129 struct wmi_nlo_enc_param enc_type; 6130 struct wmi_nlo_auth_param auth_type; 6131 struct wmi_nlo_rssi_param rssi_cond; 6132 6133 /* indicates if the SSID is hidden or not */ 6134 struct wmi_nlo_bcast_nw_param bcast_nw_type; 6135 } __packed; 6136 6137 struct wmi_network_type { 6138 struct wmi_ssid ssid; 6139 uint32_t authentication; 6140 uint32_t encryption; 6141 uint32_t bcast_nw_type; 6142 uint8_t channel_count; 6143 uint16_t channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 6144 int32_t rssi_threshold; 6145 }; 6146 6147 struct wmi_pno_scan_req { 6148 uint8_t enable; 6149 uint8_t vdev_id; 6150 uint8_t uc_networks_count; 6151 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 6152 uint32_t fast_scan_period; 6153 uint32_t slow_scan_period; 6154 uint8_t fast_scan_max_cycles; 6155 6156 bool do_passive_scan; 6157 6158 uint32_t delay_start_time; 6159 uint32_t active_min_time; 6160 uint32_t active_max_time; 6161 uint32_t passive_min_time; 6162 uint32_t passive_max_time; 6163 6164 /* mac address randomization attributes */ 6165 uint32_t enable_pno_scan_randomization; 6166 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 6167 uint8_t mac_addr_mask[IEEE80211_ADDR_LEN]; 6168 }; 6169 6170 struct wmi_wow_nlo_config_cmd { 6171 uint32_t tlv_header; 6172 uint32_t flags; 6173 uint32_t vdev_id; 6174 uint32_t fast_scan_max_cycles; 6175 uint32_t active_dwell_time; 6176 uint32_t passive_dwell_time; 6177 uint32_t probe_bundle_size; 6178 6179 /* ART = IRT */ 6180 uint32_t rest_time; 6181 6182 /* Max value that can be reached after SBM */ 6183 uint32_t max_rest_time; 6184 6185 /* SBM */ 6186 uint32_t scan_backoff_multiplier; 6187 6188 /* SCBM */ 6189 uint32_t fast_scan_period; 6190 6191 /* specific to windows */ 6192 uint32_t slow_scan_period; 6193 6194 uint32_t no_of_ssids; 6195 6196 uint32_t num_of_channels; 6197 6198 /* NLO scan start delay time in milliseconds */ 6199 uint32_t delay_start_time; 6200 6201 /* MAC Address to use in Probe Req as SA */ 6202 struct wmi_mac_addr mac_addr; 6203 6204 /* Mask on which MAC has to be randomized */ 6205 struct wmi_mac_addr mac_mask; 6206 6207 /* IE bitmap to use in Probe Req */ 6208 uint32_t ie_bitmap[8]; 6209 6210 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 6211 uint32_t num_vendor_oui; 6212 6213 /* Number of connected NLO band preferences */ 6214 uint32_t num_cnlo_band_pref; 6215 6216 /* The TLVs will follow. 6217 * nlo_configured_parameters nlo_list[]; 6218 * uint32_t channel_list[num_of_channels]; 6219 */ 6220 } __packed; 6221 6222 #define WMI_MAX_NS_OFFLOADS 2 6223 #define WMI_MAX_ARP_OFFLOADS 2 6224 6225 #define WMI_ARPOL_FLAGS_VALID BIT(0) 6226 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 6227 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 6228 6229 struct wmi_arp_offload_tuple { 6230 uint32_t tlv_header; 6231 uint32_t flags; 6232 uint8_t target_ipaddr[4]; 6233 uint8_t remote_ipaddr[4]; 6234 struct wmi_mac_addr target_mac; 6235 } __packed; 6236 6237 #define WMI_NSOL_FLAGS_VALID BIT(0) 6238 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 6239 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 6240 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 6241 6242 #define WMI_NSOL_MAX_TARGET_IPS 2 6243 6244 struct wmi_ns_offload_tuple { 6245 uint32_t tlv_header; 6246 uint32_t flags; 6247 uint8_t target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 6248 uint8_t solicitation_ipaddr[16]; 6249 uint8_t remote_ipaddr[16]; 6250 struct wmi_mac_addr target_mac; 6251 } __packed; 6252 6253 struct wmi_set_arp_ns_offload_cmd { 6254 uint32_t tlv_header; 6255 uint32_t flags; 6256 uint32_t vdev_id; 6257 uint32_t num_ns_ext_tuples; 6258 /* The TLVs follow: 6259 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS]; 6260 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS]; 6261 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples]; 6262 */ 6263 } __packed; 6264 6265 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 6266 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 6267 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 6268 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 6269 6270 #define GTK_OFFLOAD_KEK_BYTES 16 6271 #define GTK_OFFLOAD_KCK_BYTES 16 6272 #define GTK_REPLAY_COUNTER_BYTES 8 6273 #define WMI_MAX_KEY_LEN 32 6274 #define IGTK_PN_SIZE 6 6275 6276 struct wmi_replayc_cnt { 6277 union { 6278 uint8_t counter[GTK_REPLAY_COUNTER_BYTES]; 6279 struct { 6280 uint32_t word0; 6281 uint32_t word1; 6282 } __packed; 6283 } __packed; 6284 } __packed; 6285 6286 struct wmi_gtk_offload_status_event { 6287 uint32_t vdev_id; 6288 uint32_t flags; 6289 uint32_t refresh_cnt; 6290 struct wmi_replayc_cnt replay_ctr; 6291 uint8_t igtk_key_index; 6292 uint8_t igtk_key_length; 6293 uint8_t igtk_key_rsc[IGTK_PN_SIZE]; 6294 uint8_t igtk_key[WMI_MAX_KEY_LEN]; 6295 uint8_t gtk_key_index; 6296 uint8_t gtk_key_length; 6297 uint8_t gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 6298 uint8_t gtk_key[WMI_MAX_KEY_LEN]; 6299 } __packed; 6300 6301 struct wmi_gtk_rekey_offload_cmd { 6302 uint32_t tlv_header; 6303 uint32_t vdev_id; 6304 uint32_t flags; 6305 uint8_t kek[GTK_OFFLOAD_KEK_BYTES]; 6306 uint8_t kck[GTK_OFFLOAD_KCK_BYTES]; 6307 uint8_t replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 6308 } __packed; 6309 6310 #define BIOS_SAR_TABLE_LEN (22) 6311 #define BIOS_SAR_RSVD1_LEN (6) 6312 #define BIOS_SAR_RSVD2_LEN (18) 6313 6314 struct wmi_pdev_set_sar_table_cmd { 6315 uint32_t tlv_header; 6316 uint32_t pdev_id; 6317 uint32_t sar_len; 6318 uint32_t rsvd_len; 6319 } __packed; 6320 6321 struct wmi_pdev_set_geo_table_cmd { 6322 uint32_t tlv_header; 6323 uint32_t pdev_id; 6324 uint32_t rsvd_len; 6325 } __packed; 6326 6327 struct wmi_sta_keepalive_cmd { 6328 uint32_t tlv_header; 6329 uint32_t vdev_id; 6330 uint32_t enabled; 6331 6332 /* WMI_STA_KEEPALIVE_METHOD_ */ 6333 uint32_t method; 6334 6335 /* in seconds */ 6336 uint32_t interval; 6337 6338 /* following this structure is the TLV for struct 6339 * wmi_sta_keepalive_arp_resp 6340 */ 6341 } __packed; 6342 6343 struct wmi_sta_keepalive_arp_resp { 6344 uint32_t tlv_header; 6345 uint32_t src_ip4_addr; 6346 uint32_t dest_ip4_addr; 6347 struct wmi_mac_addr dest_mac_addr; 6348 } __packed; 6349 6350 struct wmi_sta_keepalive_arg { 6351 uint32_t vdev_id; 6352 uint32_t enabled; 6353 uint32_t method; 6354 uint32_t interval; 6355 uint32_t src_ip4_addr; 6356 uint32_t dest_ip4_addr; 6357 const uint8_t dest_mac_addr[IEEE80211_ADDR_LEN]; 6358 }; 6359 6360 enum wmi_sta_keepalive_method { 6361 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 6362 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 6363 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 6364 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 6365 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 6366 }; 6367 6368 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 6369 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 6370 6371 6372 /* 6373 * qrtr.h 6374 */ 6375 6376 #define QRTR_PROTO_VER_1 1 6377 #define QRTR_PROTO_VER_2 3 /* (sic!) */ 6378 6379 struct qrtr_hdr_v1 { 6380 uint32_t version; 6381 uint32_t type; 6382 uint32_t src_node_id; 6383 uint32_t src_port_id; 6384 uint32_t confirm_rx; 6385 uint32_t size; 6386 uint32_t dst_node_id; 6387 uint32_t dst_port_id; 6388 } __packed; 6389 6390 struct qrtr_hdr_v2 { 6391 uint8_t version; 6392 uint8_t type; 6393 uint8_t flags; 6394 uint8_t optlen; 6395 uint32_t size; 6396 uint16_t src_node_id; 6397 uint16_t src_port_id; 6398 uint16_t dst_node_id; 6399 uint16_t dst_port_id; 6400 }; 6401 6402 struct qrtr_ctrl_pkt { 6403 uint32_t cmd; 6404 6405 union { 6406 struct { 6407 uint32_t service; 6408 uint32_t instance; 6409 uint32_t node; 6410 uint32_t port; 6411 } server; 6412 struct { 6413 uint32_t node; 6414 uint32_t port; 6415 } client; 6416 }; 6417 } __packed; 6418 6419 #define QRTR_TYPE_DATA 1 6420 #define QRTR_TYPE_HELLO 2 6421 #define QRTR_TYPE_BYE 3 6422 #define QRTR_TYPE_NEW_SERVER 4 6423 #define QRTR_TYPE_DEL_SERVER 5 6424 #define QRTR_TYPE_DEL_CLIENT 6 6425 #define QRTR_TYPE_RESUME_TX 7 6426 #define QRTR_TYPE_EXIT 8 6427 #define QRTR_TYPE_PING 9 6428 #define QRTR_TYPE_NEW_LOOKUP 10 6429 #define QRTR_TYPE_DEL_LOOKUP 11 6430 6431 #define QRTR_FLAGS_CONFIRM_RX (1 << 0) 6432 6433 #define QRTR_NODE_BCAST 0xffffffffU 6434 #define QRTR_PORT_CTRL 0xfffffffeU 6435 6436 /* 6437 * qmi.h 6438 */ 6439 6440 #define QMI_REQUEST 0 6441 #define QMI_RESPONSE 2 6442 #define QMI_INDICATION 4 6443 6444 struct qmi_header { 6445 uint8_t type; 6446 uint16_t txn_id; 6447 uint16_t msg_id; 6448 uint16_t msg_len; 6449 } __packed; 6450 6451 #define QMI_COMMON_TLV_TYPE 0 6452 6453 enum qmi_elem_type { 6454 QMI_EOTI, 6455 QMI_OPT_FLAG, 6456 QMI_DATA_LEN, 6457 QMI_UNSIGNED_1_BYTE, 6458 QMI_UNSIGNED_2_BYTE, 6459 QMI_UNSIGNED_4_BYTE, 6460 QMI_UNSIGNED_8_BYTE, 6461 QMI_SIGNED_2_BYTE_ENUM, 6462 QMI_SIGNED_4_BYTE_ENUM, 6463 QMI_STRUCT, 6464 QMI_STRING, 6465 QMI_NUM_DATA_TYPES 6466 }; 6467 6468 enum qmi_array_type { 6469 NO_ARRAY, 6470 STATIC_ARRAY, 6471 VAR_LEN_ARRAY, 6472 }; 6473 6474 struct qmi_elem_info { 6475 enum qmi_elem_type data_type; 6476 uint32_t elem_len; 6477 uint32_t elem_size; 6478 enum qmi_array_type array_type; 6479 uint8_t tlv_type; 6480 uint32_t offset; 6481 const struct qmi_elem_info *ei_array; 6482 }; 6483 6484 #define QMI_RESULT_SUCCESS_V01 0 6485 #define QMI_RESULT_FAILURE_V01 1 6486 6487 #define QMI_ERR_NONE_V01 0 6488 #define QMI_ERR_MALFORMED_MSG_V01 1 6489 #define QMI_ERR_NO_MEMORY_V01 2 6490 #define QMI_ERR_INTERNAL_V01 3 6491 #define QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 5 6492 #define QMI_ERR_INVALID_ID_V01 41 6493 #define QMI_ERR_ENCODING_V01 58 6494 #define QMI_ERR_DISABLED_V01 69 6495 #define QMI_ERR_INCOMPATIBLE_STATE_V01 90 6496 #define QMI_ERR_NOT_SUPPORTED_V01 94 6497 6498 struct qmi_response_type_v01 { 6499 uint16_t result; 6500 uint16_t error; 6501 }; 6502 6503 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 6504 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 6505 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 6506 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 6507 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 6508 6509 struct qmi_wlanfw_ind_register_req_msg_v01 { 6510 uint8_t fw_ready_enable_valid; 6511 uint8_t fw_ready_enable; 6512 uint8_t initiate_cal_download_enable_valid; 6513 uint8_t initiate_cal_download_enable; 6514 uint8_t initiate_cal_update_enable_valid; 6515 uint8_t initiate_cal_update_enable; 6516 uint8_t msa_ready_enable_valid; 6517 uint8_t msa_ready_enable; 6518 uint8_t pin_connect_result_enable_valid; 6519 uint8_t pin_connect_result_enable; 6520 uint8_t client_id_valid; 6521 uint32_t client_id; 6522 uint8_t request_mem_enable_valid; 6523 uint8_t request_mem_enable; 6524 uint8_t fw_mem_ready_enable_valid; 6525 uint8_t fw_mem_ready_enable; 6526 uint8_t fw_init_done_enable_valid; 6527 uint8_t fw_init_done_enable; 6528 uint8_t rejuvenate_enable_valid; 6529 uint32_t rejuvenate_enable; 6530 uint8_t xo_cal_enable_valid; 6531 uint8_t xo_cal_enable; 6532 uint8_t cal_done_enable_valid; 6533 uint8_t cal_done_enable; 6534 }; 6535 6536 struct qmi_wlanfw_ind_register_resp_msg_v01 { 6537 struct qmi_response_type_v01 resp; 6538 uint8_t fw_status_valid; 6539 uint64_t fw_status; 6540 }; 6541 6542 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 6543 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 6544 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 6545 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 6546 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 6547 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 6548 #define HOST_DDR_REGION_TYPE 0x1 6549 #define BDF_MEM_REGION_TYPE 0x2 6550 #define M3_DUMP_REGION_TYPE 0x3 6551 #define CALDB_MEM_REGION_TYPE 0x4 6552 6553 struct qmi_wlanfw_host_cap_req_msg_v01 { 6554 uint8_t num_clients_valid; 6555 uint32_t num_clients; 6556 uint8_t wake_msi_valid; 6557 uint32_t wake_msi; 6558 uint8_t gpios_valid; 6559 uint32_t gpios_len; 6560 uint32_t gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 6561 uint8_t nm_modem_valid; 6562 uint8_t nm_modem; 6563 uint8_t bdf_support_valid; 6564 uint8_t bdf_support; 6565 uint8_t bdf_cache_support_valid; 6566 uint8_t bdf_cache_support; 6567 uint8_t m3_support_valid; 6568 uint8_t m3_support; 6569 uint8_t m3_cache_support_valid; 6570 uint8_t m3_cache_support; 6571 uint8_t cal_filesys_support_valid; 6572 uint8_t cal_filesys_support; 6573 uint8_t cal_cache_support_valid; 6574 uint8_t cal_cache_support; 6575 uint8_t cal_done_valid; 6576 uint8_t cal_done; 6577 uint8_t mem_bucket_valid; 6578 uint32_t mem_bucket; 6579 uint8_t mem_cfg_mode_valid; 6580 uint8_t mem_cfg_mode; 6581 }; 6582 6583 struct qmi_wlanfw_host_cap_resp_msg_v01 { 6584 struct qmi_response_type_v01 resp; 6585 }; 6586 6587 #define ATH11K_HOST_VERSION_STRING "WIN" 6588 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 6589 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 6590 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 6591 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 6592 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 6593 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 6594 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 6595 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 6596 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 6597 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 6598 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03 6599 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 6600 6601 #define ATH11K_QMI_RESP_LEN_MAX 8192 6602 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 6603 #define ATH11K_QMI_CALDB_SIZE 0x480000 6604 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 6605 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 5 6606 6607 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 6608 #define QMI_WLFW_RESPOND_MEM_RESP_V01 0x0036 6609 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 6610 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x003E 6611 #define QMI_WLFW_FW_READY_IND_V01 0x0021 6612 #define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 6613 6614 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 6615 #define ATH11K_FIRMWARE_MODE_OFF 4 6616 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) 6617 6618 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 6619 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 6620 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 6621 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 6622 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 6623 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 6624 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 6625 6626 struct qmi_wlanfw_mem_cfg_s_v01 { 6627 uint64_t offset; 6628 uint32_t size; 6629 uint8_t secure_flag; 6630 }; 6631 6632 enum qmi_wlanfw_mem_type_enum_v01 { 6633 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 6634 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 6635 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 6636 QMI_WLANFW_MEM_BDF_V01 = 2, 6637 QMI_WLANFW_MEM_M3_V01 = 3, 6638 QMI_WLANFW_MEM_CAL_V01 = 4, 6639 QMI_WLANFW_MEM_DPD_V01 = 5, 6640 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 6641 }; 6642 6643 struct qmi_wlanfw_mem_seg_s_v01 { 6644 uint32_t size; 6645 enum qmi_wlanfw_mem_type_enum_v01 type; 6646 uint32_t mem_cfg_len; 6647 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 6648 }; 6649 6650 struct qmi_wlanfw_request_mem_ind_msg_v01 { 6651 uint32_t mem_seg_len; 6652 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 6653 }; 6654 6655 struct qmi_wlanfw_mem_seg_resp_s_v01 { 6656 uint64_t addr; 6657 uint32_t size; 6658 enum qmi_wlanfw_mem_type_enum_v01 type; 6659 uint8_t restore; 6660 }; 6661 6662 struct qmi_wlanfw_respond_mem_req_msg_v01 { 6663 uint32_t mem_seg_len; 6664 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 6665 }; 6666 6667 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 6668 struct qmi_response_type_v01 resp; 6669 }; 6670 6671 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 6672 char placeholder; 6673 }; 6674 6675 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 6676 char placeholder; 6677 }; 6678 6679 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 6680 char placeholder; 6681 }; 6682 6683 struct qmi_wlfw_fw_init_done_ind_msg_v01 { 6684 char placeholder; 6685 }; 6686 6687 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 6688 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 6689 #define QMI_WLANFW_CAP_REQ_V01 0x0024 6690 #define QMI_WLANFW_CAP_RESP_V01 0x0024 6691 #define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C 6692 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 6693 6694 enum qmi_wlanfw_pipedir_enum_v01 { 6695 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 6696 QMI_WLFW_PIPEDIR_IN_V01 = 1, 6697 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 6698 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 6699 }; 6700 6701 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 6702 uint32_t pipe_num; 6703 uint32_t pipe_dir; 6704 uint32_t nentries; 6705 uint32_t nbytes_max; 6706 uint32_t flags; 6707 }; 6708 6709 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 6710 uint32_t service_id; 6711 uint32_t pipe_dir; 6712 uint32_t pipe_num; 6713 }; 6714 6715 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 6716 uint16_t id; 6717 uint16_t offset; 6718 }; 6719 6720 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 6721 uint32_t addr; 6722 }; 6723 6724 struct qmi_wlanfw_memory_region_info_s_v01 { 6725 uint64_t region_addr; 6726 uint32_t size; 6727 uint8_t secure_flag; 6728 }; 6729 6730 struct qmi_wlanfw_rf_chip_info_s_v01 { 6731 uint32_t chip_id; 6732 uint32_t chip_family; 6733 }; 6734 6735 struct qmi_wlanfw_rf_board_info_s_v01 { 6736 uint32_t board_id; 6737 }; 6738 6739 struct qmi_wlanfw_soc_info_s_v01 { 6740 uint32_t soc_id; 6741 }; 6742 6743 struct qmi_wlanfw_fw_version_info_s_v01 { 6744 uint32_t fw_version; 6745 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 6746 }; 6747 6748 enum qmi_wlanfw_cal_temp_id_enum_v01 { 6749 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 6750 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 6751 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 6752 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 6753 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 6754 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 6755 }; 6756 6757 struct qmi_wlanfw_cap_resp_msg_v01 { 6758 struct qmi_response_type_v01 resp; 6759 uint8_t chip_info_valid; 6760 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 6761 uint8_t board_info_valid; 6762 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 6763 uint8_t soc_info_valid; 6764 struct qmi_wlanfw_soc_info_s_v01 soc_info; 6765 uint8_t fw_version_info_valid; 6766 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 6767 uint8_t fw_build_id_valid; 6768 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 6769 uint8_t num_macs_valid; 6770 uint8_t num_macs; 6771 uint8_t voltage_mv_valid; 6772 uint32_t voltage_mv; 6773 uint8_t time_freq_hz_valid; 6774 uint32_t time_freq_hz; 6775 uint8_t otp_version_valid; 6776 uint32_t otp_version; 6777 uint8_t eeprom_read_timeout_valid; 6778 uint32_t eeprom_read_timeout; 6779 }; 6780 6781 struct qmi_wlanfw_cap_req_msg_v01 { 6782 char placeholder; 6783 }; 6784 6785 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 6786 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 6787 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 6788 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 6789 /* TODO: Need to check with MCL and FW team that data can be pointer and 6790 * can be last element in structure 6791 */ 6792 struct qmi_wlanfw_bdf_download_req_msg_v01 { 6793 uint8_t valid; 6794 uint8_t file_id_valid; 6795 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 6796 uint8_t total_size_valid; 6797 uint32_t total_size; 6798 uint8_t seg_id_valid; 6799 uint32_t seg_id; 6800 uint8_t data_valid; 6801 uint32_t data_len; 6802 uint8_t data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 6803 uint8_t end_valid; 6804 uint8_t end; 6805 uint8_t bdf_type_valid; 6806 uint8_t bdf_type; 6807 }; 6808 6809 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 6810 struct qmi_response_type_v01 resp; 6811 }; 6812 6813 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 6814 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 6815 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003c 6816 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003c 6817 6818 struct qmi_wlanfw_m3_info_req_msg_v01 { 6819 uint64_t addr; 6820 uint32_t size; 6821 }; 6822 6823 struct qmi_wlanfw_m3_info_resp_msg_v01 { 6824 struct qmi_response_type_v01 resp; 6825 }; 6826 6827 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 6828 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 6829 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 6830 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 6831 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 4 6832 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 6833 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 6834 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 6835 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 6836 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002f 6837 #define QMI_WLANFW_WLAN_INI_RESP_V01 0x002f 6838 #define QMI_WLANFW_MAX_STR_LEN_V01 16 6839 #define QMI_WLANFW_MAX_NUM_CE_V01 12 6840 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 6841 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 6842 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 6843 6844 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 6845 uint32_t mode; 6846 uint8_t hw_debug_valid; 6847 uint8_t hw_debug; 6848 }; 6849 6850 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 6851 struct qmi_response_type_v01 resp; 6852 }; 6853 6854 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 6855 uint8_t host_version_valid; 6856 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 6857 uint8_t tgt_cfg_valid; 6858 uint32_t tgt_cfg_len; 6859 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 6860 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 6861 uint8_t svc_cfg_valid; 6862 uint32_t svc_cfg_len; 6863 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 6864 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 6865 uint8_t shadow_reg_valid; 6866 uint32_t shadow_reg_len; 6867 struct qmi_wlanfw_shadow_reg_cfg_s_v01 6868 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 6869 uint8_t shadow_reg_v2_valid; 6870 uint32_t shadow_reg_v2_len; 6871 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 6872 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 6873 }; 6874 6875 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 6876 struct qmi_response_type_v01 resp; 6877 }; 6878 6879 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 6880 /* Must be set to true if enablefwlog is being passed */ 6881 uint8_t enablefwlog_valid; 6882 uint8_t enablefwlog; 6883 }; 6884 6885 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 6886 struct qmi_response_type_v01 resp; 6887 }; 6888 6889 enum ath11k_qmi_file_type { 6890 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 6891 ATH11K_QMI_FILE_TYPE_CALDATA = 2, 6892 ATH11K_QMI_FILE_TYPE_EEPROM, 6893 ATH11K_QMI_MAX_FILE_TYPE, 6894 }; 6895 6896 enum ath11k_qmi_bdf_type { 6897 ATH11K_QMI_BDF_TYPE_BIN = 0, 6898 ATH11K_QMI_BDF_TYPE_ELF = 1, 6899 ATH11K_QMI_BDF_TYPE_REGDB = 4, 6900 }; 6901 6902 #define HAL_LINK_DESC_SIZE (32 << 2) 6903 #define HAL_LINK_DESC_ALIGN 128 6904 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 6905 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 6906 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 6907 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 6908 #define HAL_MAX_AVAIL_BLK_RES 3 6909 6910 #define HAL_RING_BASE_ALIGN 8 6911 6912 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 6913 /* TODO: Check with hw team on the supported scatter buf size */ 6914 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 6915 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 6916 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 6917 6918 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 6919 #define HAL_DSCP_TID_TBL_SIZE 24 6920 6921 /* calculate the register address from bar0 of shadow register x */ 6922 #define HAL_SHADOW_BASE_ADDR(sc) \ 6923 (sc->hw_params.regs->hal_shadow_base_addr) 6924 #define HAL_SHADOW_NUM_REGS 36 6925 #define HAL_HP_OFFSET_IN_REG_START 1 6926 #define HAL_OFFSET_FROM_HP_TO_TP 4 6927 6928 #define HAL_SHADOW_REG(sc, x) (HAL_SHADOW_BASE_ADDR(sc) + (4 * (x))) 6929 6930 enum hal_srng_ring_id { 6931 HAL_SRNG_RING_ID_REO2SW1 = 0, 6932 HAL_SRNG_RING_ID_REO2SW2, 6933 HAL_SRNG_RING_ID_REO2SW3, 6934 HAL_SRNG_RING_ID_REO2SW4, 6935 HAL_SRNG_RING_ID_REO2TCL, 6936 HAL_SRNG_RING_ID_SW2REO, 6937 6938 HAL_SRNG_RING_ID_REO_CMD = 8, 6939 HAL_SRNG_RING_ID_REO_STATUS, 6940 6941 HAL_SRNG_RING_ID_SW2TCL1 = 16, 6942 HAL_SRNG_RING_ID_SW2TCL2, 6943 HAL_SRNG_RING_ID_SW2TCL3, 6944 HAL_SRNG_RING_ID_SW2TCL4, 6945 6946 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 6947 HAL_SRNG_RING_ID_TCL_STATUS, 6948 6949 HAL_SRNG_RING_ID_CE0_SRC = 32, 6950 HAL_SRNG_RING_ID_CE1_SRC, 6951 HAL_SRNG_RING_ID_CE2_SRC, 6952 HAL_SRNG_RING_ID_CE3_SRC, 6953 HAL_SRNG_RING_ID_CE4_SRC, 6954 HAL_SRNG_RING_ID_CE5_SRC, 6955 HAL_SRNG_RING_ID_CE6_SRC, 6956 HAL_SRNG_RING_ID_CE7_SRC, 6957 HAL_SRNG_RING_ID_CE8_SRC, 6958 HAL_SRNG_RING_ID_CE9_SRC, 6959 HAL_SRNG_RING_ID_CE10_SRC, 6960 HAL_SRNG_RING_ID_CE11_SRC, 6961 6962 HAL_SRNG_RING_ID_CE0_DST = 56, 6963 HAL_SRNG_RING_ID_CE1_DST, 6964 HAL_SRNG_RING_ID_CE2_DST, 6965 HAL_SRNG_RING_ID_CE3_DST, 6966 HAL_SRNG_RING_ID_CE4_DST, 6967 HAL_SRNG_RING_ID_CE5_DST, 6968 HAL_SRNG_RING_ID_CE6_DST, 6969 HAL_SRNG_RING_ID_CE7_DST, 6970 HAL_SRNG_RING_ID_CE8_DST, 6971 HAL_SRNG_RING_ID_CE9_DST, 6972 HAL_SRNG_RING_ID_CE10_DST, 6973 HAL_SRNG_RING_ID_CE11_DST, 6974 6975 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 6976 HAL_SRNG_RING_ID_CE1_DST_STATUS, 6977 HAL_SRNG_RING_ID_CE2_DST_STATUS, 6978 HAL_SRNG_RING_ID_CE3_DST_STATUS, 6979 HAL_SRNG_RING_ID_CE4_DST_STATUS, 6980 HAL_SRNG_RING_ID_CE5_DST_STATUS, 6981 HAL_SRNG_RING_ID_CE6_DST_STATUS, 6982 HAL_SRNG_RING_ID_CE7_DST_STATUS, 6983 HAL_SRNG_RING_ID_CE8_DST_STATUS, 6984 HAL_SRNG_RING_ID_CE9_DST_STATUS, 6985 HAL_SRNG_RING_ID_CE10_DST_STATUS, 6986 HAL_SRNG_RING_ID_CE11_DST_STATUS, 6987 6988 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 6989 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 6990 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 6991 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 6992 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 6993 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 6994 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 6995 6996 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 6997 HAL_SRNG_RING_ID_LMAC1_ID_START, 6998 6999 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 7000 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 7001 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 7002 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 7003 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 7004 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 7005 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 7006 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 7007 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 7008 7009 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 7010 }; 7011 7012 /* SRNG registers are split into two groups R0 and R2 */ 7013 #define HAL_SRNG_REG_GRP_R0 0 7014 #define HAL_SRNG_REG_GRP_R2 1 7015 #define HAL_SRNG_NUM_REG_GRP 2 7016 7017 #define HAL_SRNG_NUM_LMACS 3 7018 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 7019 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 7020 HAL_SRNG_RING_ID_LMAC1_ID_START) 7021 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 7022 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 7023 HAL_SRNG_NUM_LMAC_RINGS) 7024 7025 #define HAL_RX_MAX_BA_WINDOW 256 7026 7027 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 7028 7029 /** 7030 * enum hal_reo_cmd_type: Enum for REO command type 7031 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 7032 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 7033 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 7034 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 7035 * earlier with a 'REO_FLUSH_CACHE' command 7036 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 7037 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 7038 */ 7039 enum hal_reo_cmd_type { 7040 HAL_REO_CMD_GET_QUEUE_STATS = 0, 7041 HAL_REO_CMD_FLUSH_QUEUE = 1, 7042 HAL_REO_CMD_FLUSH_CACHE = 2, 7043 HAL_REO_CMD_UNBLOCK_CACHE = 3, 7044 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 7045 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 7046 }; 7047 7048 /** 7049 * enum hal_reo_cmd_status: Enum for execution status of REO command 7050 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 7051 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 7052 * or cache was blocked 7053 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 7054 * invalid queue desc 7055 * @HAL_REO_CMD_RESOURCE_BLOCKED: 7056 * @HAL_REO_CMD_DRAIN: 7057 */ 7058 enum hal_reo_cmd_status { 7059 HAL_REO_CMD_SUCCESS = 0, 7060 HAL_REO_CMD_BLOCKED = 1, 7061 HAL_REO_CMD_FAILED = 2, 7062 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 7063 HAL_REO_CMD_DRAIN = 0xff, 7064 }; 7065 7066 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 7067 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 7068 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 7069 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 7070 7071 /* Interrupt mitigation - timer threshold in us */ 7072 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 7073 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 7074 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 7075 7076 /* WCSS Relative address */ 7077 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 7078 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 7079 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 7080 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc) \ 7081 (sc->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg) 7082 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(sc) \ 7083 (sc->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg) 7084 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(sc) \ 7085 (sc->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg) 7086 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(sc) \ 7087 (sc->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg) 7088 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 7089 7090 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 7091 #define HAL_WLAON_REG_BASE 0x01f80000 7092 7093 /* SW2TCL(x) R0 ring configuration address */ 7094 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 7095 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 7096 #define HAL_TCL1_RING_BASE_LSB(sc) \ 7097 (sc->hw_params.regs->hal_tcl1_ring_base_lsb) 7098 #define HAL_TCL1_RING_BASE_MSB(sc) \ 7099 (sc->hw_params.regs->hal_tcl1_ring_base_msb) 7100 #define HAL_TCL1_RING_ID(sc) \ 7101 (sc->hw_params.regs->hal_tcl1_ring_id) 7102 #define HAL_TCL1_RING_MISC(sc) \ 7103 (sc->hw_params.regs->hal_tcl1_ring_misc) 7104 #define HAL_TCL1_RING_TP_ADDR_LSB(sc) \ 7105 (sc->hw_params.regs->hal_tcl1_ring_tp_addr_lsb) 7106 #define HAL_TCL1_RING_TP_ADDR_MSB(sc) \ 7107 (sc->hw_params.regs->hal_tcl1_ring_tp_addr_msb) 7108 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) \ 7109 (sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0) 7110 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) \ 7111 (sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1) 7112 #define HAL_TCL1_RING_MSI1_BASE_LSB(sc) \ 7113 (sc->hw_params.regs->hal_tcl1_ring_msi1_base_lsb) 7114 #define HAL_TCL1_RING_MSI1_BASE_MSB(sc) \ 7115 (sc->hw_params.regs->hal_tcl1_ring_msi1_base_msb) 7116 #define HAL_TCL1_RING_MSI1_DATA(sc) \ 7117 (sc->hw_params.regs->hal_tcl1_ring_msi1_data) 7118 #define HAL_TCL2_RING_BASE_LSB(sc) \ 7119 (sc->hw_params.regs->hal_tcl2_ring_base_lsb) 7120 #define HAL_TCL_RING_BASE_LSB(sc) \ 7121 (sc->hw_params.regs->hal_tcl_ring_base_lsb) 7122 7123 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(sc) \ 7124 (HAL_TCL1_RING_MSI1_BASE_LSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7125 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(sc) \ 7126 (HAL_TCL1_RING_MSI1_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7127 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(sc) \ 7128 (HAL_TCL1_RING_MSI1_DATA(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7129 #define HAL_TCL1_RING_BASE_MSB_OFFSET(sc) \ 7130 (HAL_TCL1_RING_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7131 #define HAL_TCL1_RING_ID_OFFSET(sc) \ 7132 (HAL_TCL1_RING_ID(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7133 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(sc) \ 7134 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7135 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(sc) \ 7136 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) - \ 7137 HAL_TCL1_RING_BASE_LSB(sc)) 7138 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(sc) \ 7139 (HAL_TCL1_RING_TP_ADDR_LSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7140 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(sc) \ 7141 (HAL_TCL1_RING_TP_ADDR_MSB(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7142 #define HAL_TCL1_RING_MISC_OFFSET(sc) \ 7143 (HAL_TCL1_RING_MISC(sc) - HAL_TCL1_RING_BASE_LSB(sc)) 7144 7145 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 7146 #define HAL_TCL1_RING_HP 0x00002000 7147 #define HAL_TCL1_RING_TP 0x00002004 7148 #define HAL_TCL2_RING_HP 0x00002008 7149 #define HAL_TCL_RING_HP 0x00002018 7150 7151 #define HAL_TCL1_RING_TP_OFFSET \ 7152 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 7153 7154 /* TCL STATUS ring address */ 7155 #define HAL_TCL_STATUS_RING_BASE_LSB(sc) \ 7156 (sc->hw_params.regs->hal_tcl_status_ring_base_lsb) 7157 #define HAL_TCL_STATUS_RING_HP 0x00002030 7158 7159 /* REO2SW(x) R0 ring configuration address */ 7160 #define HAL_REO1_GEN_ENABLE 0x00000000 7161 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 7162 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 7163 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 7164 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 7165 #define HAL_REO1_MISC_CTL(sc) \ 7166 (sc->hw_params.regs->hal_reo1_misc_ctl) 7167 #define HAL_REO1_RING_BASE_LSB(sc) \ 7168 (sc->hw_params.regs->hal_reo1_ring_base_lsb) 7169 #define HAL_REO1_RING_BASE_MSB(sc) \ 7170 (sc->hw_params.regs->hal_reo1_ring_base_msb) 7171 #define HAL_REO1_RING_ID(sc) \ 7172 (sc->hw_params.regs->hal_reo1_ring_id) 7173 #define HAL_REO1_RING_MISC(sc) \ 7174 (sc->hw_params.regs->hal_reo1_ring_misc) 7175 #define HAL_REO1_RING_HP_ADDR_LSB(sc) \ 7176 (sc->hw_params.regs->hal_reo1_ring_hp_addr_lsb) 7177 #define HAL_REO1_RING_HP_ADDR_MSB(sc) \ 7178 (sc->hw_params.regs->hal_reo1_ring_hp_addr_msb) 7179 #define HAL_REO1_RING_PRODUCER_INT_SETUP(sc) \ 7180 (sc->hw_params.regs->hal_reo1_ring_producer_int_setup) 7181 #define HAL_REO1_RING_MSI1_BASE_LSB(sc) \ 7182 (sc->hw_params.regs->hal_reo1_ring_msi1_base_lsb) 7183 #define HAL_REO1_RING_MSI1_BASE_MSB(sc) \ 7184 (sc->hw_params.regs->hal_reo1_ring_msi1_base_msb) 7185 #define HAL_REO1_RING_MSI1_DATA(sc) \ 7186 (sc->hw_params.regs->hal_reo1_ring_msi1_data) 7187 #define HAL_REO2_RING_BASE_LSB(sc) \ 7188 (sc->hw_params.regs->hal_reo2_ring_base_lsb) 7189 #define HAL_REO1_AGING_THRESH_IX_0(sc) \ 7190 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_0) 7191 #define HAL_REO1_AGING_THRESH_IX_1(sc) \ 7192 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_1) 7193 #define HAL_REO1_AGING_THRESH_IX_2(sc) \ 7194 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_2) 7195 #define HAL_REO1_AGING_THRESH_IX_3(sc) \ 7196 (sc->hw_params.regs->hal_reo1_aging_thresh_ix_3) 7197 7198 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(sc) \ 7199 (HAL_REO1_RING_MSI1_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7200 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(sc) \ 7201 (HAL_REO1_RING_MSI1_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7202 #define HAL_REO1_RING_MSI1_DATA_OFFSET(sc) \ 7203 (HAL_REO1_RING_MSI1_DATA(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7204 #define HAL_REO1_RING_BASE_MSB_OFFSET(sc) \ 7205 (HAL_REO1_RING_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7206 #define HAL_REO1_RING_ID_OFFSET(sc) (HAL_REO1_RING_ID(sc) - \ 7207 HAL_REO1_RING_BASE_LSB(sc)) 7208 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(sc) \ 7209 (HAL_REO1_RING_PRODUCER_INT_SETUP(sc) - \ 7210 HAL_REO1_RING_BASE_LSB(sc)) 7211 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(sc) \ 7212 (HAL_REO1_RING_HP_ADDR_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7213 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(sc) \ 7214 (HAL_REO1_RING_HP_ADDR_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7215 #define HAL_REO1_RING_MISC_OFFSET(sc) \ 7216 (HAL_REO1_RING_MISC(sc) - HAL_REO1_RING_BASE_LSB(sc)) 7217 7218 /* REO2SW(x) R2 ring pointers (head/tail) address */ 7219 #define HAL_REO1_RING_HP(sc) \ 7220 (sc->hw_params.regs->hal_reo1_ring_hp) 7221 #define HAL_REO1_RING_TP(sc) \ 7222 (sc->hw_params.regs->hal_reo1_ring_tp) 7223 #define HAL_REO2_RING_HP(sc) \ 7224 (sc->hw_params.regs->hal_reo2_ring_hp) 7225 7226 #define HAL_REO1_RING_TP_OFFSET(sc) \ 7227 (HAL_REO1_RING_TP(sc) - HAL_REO1_RING_HP(sc)) 7228 7229 /* REO2TCL R0 ring configuration address */ 7230 #define HAL_REO_TCL_RING_BASE_LSB(sc) \ 7231 (sc->hw_params.regs->hal_reo_tcl_ring_base_lsb) 7232 7233 /* REO2TCL R2 ring pointer (head/tail) address */ 7234 #define HAL_REO_TCL_RING_HP(sc) \ 7235 (sc->hw_params.regs->hal_reo_tcl_ring_hp) 7236 7237 /* REO CMD R0 address */ 7238 #define HAL_REO_CMD_RING_BASE_LSB(sc) \ 7239 (sc->hw_params.regs->hal_reo_cmd_ring_base_lsb) 7240 7241 /* REO CMD R2 address */ 7242 #define HAL_REO_CMD_HP(sc) \ 7243 (sc->hw_params.regs->hal_reo_cmd_ring_hp) 7244 7245 /* SW2REO R0 address */ 7246 #define HAL_SW2REO_RING_BASE_LSB(sc) \ 7247 (sc->hw_params.regs->hal_sw2reo_ring_base_lsb) 7248 7249 /* SW2REO R2 address */ 7250 #define HAL_SW2REO_RING_HP(sc) \ 7251 (sc->hw_params.regs->hal_sw2reo_ring_hp) 7252 7253 /* CE ring R0 address */ 7254 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 7255 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 7256 #define HAL_CE_DST_RING_CTRL 0x000000b0 7257 7258 /* CE ring R2 address */ 7259 #define HAL_CE_DST_RING_HP 0x00000400 7260 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 7261 7262 /* REO status address */ 7263 #define HAL_REO_STATUS_RING_BASE_LSB(sc) \ 7264 (sc->hw_params.regs->hal_reo_status_ring_base_lsb) 7265 #define HAL_REO_STATUS_HP(sc) \ 7266 (sc->hw_params.regs->hal_reo_status_hp) 7267 7268 /* WBM Idle R0 address */ 7269 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \ 7270 (sc->hw_params.regs->hal_wbm_idle_link_ring_base_lsb) 7271 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \ 7272 (sc->hw_params.regs->hal_wbm_idle_link_ring_misc) 7273 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 7274 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 7275 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 7276 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 7277 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 7278 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 7279 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 7280 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 7281 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 7282 7283 /* WBM Idle R2 address */ 7284 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 7285 7286 /* SW2WBM R0 release address */ 7287 #define HAL_WBM_RELEASE_RING_BASE_LSB(x) \ 7288 (sc->hw_params.regs->hal_wbm_release_ring_base_lsb) 7289 7290 /* SW2WBM R2 release address */ 7291 #define HAL_WBM_RELEASE_RING_HP 0x00003018 7292 7293 /* WBM2SW R0 release address */ 7294 #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \ 7295 (sc->hw_params.regs->hal_wbm0_release_ring_base_lsb) 7296 #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \ 7297 (sc->hw_params.regs->hal_wbm1_release_ring_base_lsb) 7298 7299 /* WBM2SW R2 release address */ 7300 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 7301 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 7302 7303 /* TCL ring field mask and offset */ 7304 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 7305 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 7306 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 7307 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 7308 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 7309 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 7310 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 7311 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 7312 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 7313 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 7314 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 7315 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 7316 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 7317 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 7318 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 7319 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 7320 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 7321 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 7322 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 7323 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 7324 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 7325 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 7326 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 7327 7328 /* REO ring field mask and offset */ 7329 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 7330 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 7331 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 7332 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 7333 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 7334 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 7335 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 7336 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 7337 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 7338 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 7339 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 7340 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 7341 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 7342 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 7343 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 7344 #define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17) 7345 7346 /* CE ring bit field mask and shift */ 7347 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 7348 7349 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 7350 7351 #define HAL_ADDR_MSB_REG_SHIFT 32 7352 7353 /* WBM ring bit field mask and shift */ 7354 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 7355 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 7356 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 7357 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 7358 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 7359 7360 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 7361 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 7362 7363 #define BASE_ADDR_MATCH_TAG_VAL 0x5 7364 7365 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 7366 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 7367 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 7368 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 7369 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7370 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 7371 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 7372 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7373 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 7374 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 7375 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 7376 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 7377 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 7378 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 7379 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 7380 7381 /* IPQ5018 ce registers */ 7382 #define HAL_IPQ5018_CE_WFSS_REG_BASE 0x08400000 7383 #define HAL_IPQ5018_CE_SIZE 0x200000 7384 7385 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 7386 7387 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 7388 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) 7389 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) 7390 7391 struct ath11k_buffer_addr { 7392 uint32_t info0; 7393 uint32_t info1; 7394 } __packed; 7395 7396 /* ath11k_buffer_addr 7397 * 7398 * info0 7399 * Address (lower 32 bits) of the msdu buffer or msdu extension 7400 * descriptor or Link descriptor 7401 * 7402 * addr 7403 * Address (upper 8 bits) of the msdu buffer or msdu extension 7404 * descriptor or Link descriptor 7405 * 7406 * return_buffer_manager (RBM) 7407 * Consumer: WBM 7408 * Producer: SW/FW 7409 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 7410 * descriptor or link descriptor that is being pointed to shall be 7411 * returned after the frame has been processed. It is used by WBM 7412 * for routing purposes. 7413 * 7414 * Values are defined in enum %HAL_RX_BUF_RBM_ 7415 * 7416 * sw_buffer_cookie 7417 * Cookie field exclusively used by SW. HW ignores the contents, 7418 * accept that it passes the programmed value on to other 7419 * descriptors together with the physical address. 7420 * 7421 * Field can be used by SW to for example associate the buffers 7422 * physical address with the virtual address. 7423 */ 7424 7425 enum hal_tlv_tag { 7426 HAL_MACTX_CBF_START = 0 /* 0x0 */, 7427 HAL_PHYRX_DATA = 1 /* 0x1 */, 7428 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 7429 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 7430 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 7431 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 7432 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 7433 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 7434 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, 7435 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, 7436 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, 7437 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, 7438 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, 7439 HAL_MACRX_ABORT_ACK = 13 /* 0xd */, 7440 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, 7441 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, 7442 HAL_MACRX_NAP_USER = 16 /* 0x10 */, 7443 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, 7444 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, 7445 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, 7446 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, 7447 HAL_PHYTX_PKT_END = 21 /* 0x15 */, 7448 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, 7449 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, 7450 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, 7451 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, 7452 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, 7453 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, 7454 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, 7455 HAL_PHYTX_ON_ACK = 29 /* 0x1d */, 7456 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, 7457 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, 7458 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, 7459 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, 7460 HAL_MACTX_PKT_END = 34 /* 0x22 */, 7461 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, 7462 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, 7463 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, 7464 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, 7465 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, 7466 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, 7467 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, 7468 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, 7469 HAL_MACTX_PHY_OFF = 43 /* 0x2b */, 7470 HAL_MACTX_PHY_ON = 44 /* 0x2c */, 7471 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, 7472 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, 7473 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, 7474 HAL_MACTX_PHY_DESC = 48 /* 0x30 */, 7475 HAL_MACTX_L_SIG_A = 49 /* 0x31 */, 7476 HAL_MACTX_L_SIG_B = 50 /* 0x32 */, 7477 HAL_MACTX_HT_SIG = 51 /* 0x33 */, 7478 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, 7479 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, 7480 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, 7481 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, 7482 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, 7483 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, 7484 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, 7485 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, 7486 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, 7487 HAL_MACTX_SERVICE = 61 /* 0x3d */, 7488 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, 7489 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, 7490 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, 7491 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, 7492 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, 7493 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, 7494 HAL_MACTX_DELETE_CV = 68 /* 0x44 */, 7495 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, 7496 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, 7497 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, 7498 HAL_MACTX_PHY_NAP = 72 /* 0x48 */, 7499 HAL_MACTX_DEBUG = 73 /* 0x49 */, 7500 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, 7501 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, 7502 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, 7503 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, 7504 HAL_PHYRX_USER_INFO = 78 /* 0x4e */, 7505 HAL_PHYRX_PKT_END = 79 /* 0x4f */, 7506 HAL_PHYRX_DEBUG = 80 /* 0x50 */, 7507 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, 7508 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, 7509 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, 7510 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, 7511 HAL_PHYRX_HT_SIG = 85 /* 0x55 */, 7512 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, 7513 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, 7514 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, 7515 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, 7516 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, 7517 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, 7518 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, 7519 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, 7520 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, 7521 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, 7522 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, 7523 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, 7524 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, 7525 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, 7526 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, 7527 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, 7528 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, 7529 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, 7530 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, 7531 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, 7532 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, 7533 HAL_RX_LOCATION_INFO = 107 /* 0x6b */, 7534 HAL_COEX_TX_REQ = 108 /* 0x6c */, 7535 HAL_DUMMY = 109 /* 0x6d */, 7536 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, 7537 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, 7538 HAL_MPDU_LIMIT = 112 /* 0x70 */, 7539 HAL_NA_LENGTH_END = 113 /* 0x71 */, 7540 HAL_OLE_BUF_STATUS = 114 /* 0x72 */, 7541 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, 7542 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, 7543 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, 7544 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, 7545 HAL_PDG_FES_SETUP = 119 /* 0x77 */, 7546 HAL_PDG_RESPONSE = 120 /* 0x78 */, 7547 HAL_PDG_TX_REQ = 121 /* 0x79 */, 7548 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, 7549 HAL_SCHEDULER_TLV = 123 /* 0x7b */, 7550 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, 7551 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, 7552 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, 7553 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, 7554 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, 7555 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, 7556 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, 7557 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, 7558 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, 7559 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, 7560 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, 7561 HAL_TQM_WRITE_CMD = 135 /* 0x87 */, 7562 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, 7563 HAL_TX_DATA = 137 /* 0x89 */, 7564 HAL_TX_FES_SETUP = 138 /* 0x8a */, 7565 HAL_RX_PACKET = 139 /* 0x8b */, 7566 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, 7567 HAL_TX_MPDU_END = 141 /* 0x8d */, 7568 HAL_TX_MPDU_START = 142 /* 0x8e */, 7569 HAL_TX_MSDU_END = 143 /* 0x8f */, 7570 HAL_TX_MSDU_START = 144 /* 0x90 */, 7571 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, 7572 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, 7573 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, 7574 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, 7575 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, 7576 HAL_MPDU_INFO = 150 /* 0x96 */, 7577 HAL_PDG_USER_SETUP = 151 /* 0x97 */, 7578 HAL_TX_11AH_SETUP = 152 /* 0x98 */, 7579 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, 7580 HAL_TX_PEER_ENTRY = 154 /* 0x9a */, 7581 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, 7582 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, 7583 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, 7584 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, 7585 HAL_PROT_RATE_SETTING = 159 /* 0x9f */, 7586 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, 7587 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, 7588 HAL_RX_MSDU_LINK = 162 /* 0xa2 */, 7589 HAL_RX_REO_QUEUE = 163 /* 0xa3 */, 7590 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, 7591 HAL_SCHEDULER_CMD = 165 /* 0xa5 */, 7592 HAL_TX_FLUSH = 166 /* 0xa6 */, 7593 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, 7594 HAL_TX_DATA_WORD = 168 /* 0xa8 */, 7595 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, 7596 HAL_TX_MPDU_LINK = 170 /* 0xaa */, 7597 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, 7598 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, 7599 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, 7600 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, 7601 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, 7602 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, 7603 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, 7604 HAL_TX_MSDU_LINK = 178 /* 0xb2 */, 7605 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, 7606 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, 7607 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, 7608 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, 7609 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, 7610 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, 7611 HAL_USER_RATE_SETTING = 185 /* 0xb9 */, 7612 HAL_WBM_BUFFER_RING = 186 /* 0xba */, 7613 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, 7614 HAL_WBM_RELEASE_RING = 188 /* 0xbc */, 7615 HAL_TX_FLUSH_REQ = 189 /* 0xbd */, 7616 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, 7617 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, 7618 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, 7619 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, 7620 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, 7621 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, 7622 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, 7623 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, 7624 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, 7625 HAL_RX_TRIG_INFO = 199 /* 0xc7 */, 7626 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, 7627 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, 7628 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, 7629 HAL_COEX_RX_STATUS = 203 /* 0xcb */, 7630 HAL_RX_START_PARAM = 204 /* 0xcc */, 7631 HAL_RX_PPDU_START = 205 /* 0xcd */, 7632 HAL_RX_PPDU_END = 206 /* 0xce */, 7633 HAL_RX_MPDU_START = 207 /* 0xcf */, 7634 HAL_RX_MPDU_END = 208 /* 0xd0 */, 7635 HAL_RX_MSDU_START = 209 /* 0xd1 */, 7636 HAL_RX_MSDU_END = 210 /* 0xd2 */, 7637 HAL_RX_ATTENTION = 211 /* 0xd3 */, 7638 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, 7639 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, 7640 HAL_RX_HEADER = 214 /* 0xd6 */, 7641 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, 7642 HAL_RX_FLUSH = 216 /* 0xd8 */, 7643 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, 7644 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, 7645 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, 7646 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, 7647 HAL_TX_CBF_INFO = 221 /* 0xdd */, 7648 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, 7649 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, 7650 HAL_RX_PM_INFO = 224 /* 0xe0 */, 7651 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, 7652 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, 7653 HAL_RX_PREAMBLE = 227 /* 0xe3 */, 7654 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, 7655 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, 7656 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, 7657 HAL_RXPCU_SETUP = 231 /* 0xe7 */, 7658 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, 7659 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, 7660 HAL_TQM_ACKED_MPDU = 234 /* 0xea */, 7661 HAL_COEX_TX_RESP = 235 /* 0xeb */, 7662 HAL_COEX_TX_STATUS = 236 /* 0xec */, 7663 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, 7664 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, 7665 HAL_RESPONSE_START_STATUS = 239 /* 0xef */, 7666 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, 7667 HAL_CRYPTO_STATUS = 241 /* 0xf1 */, 7668 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, 7669 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, 7670 HAL_RX_MPDU_LINK = 244 /* 0xf4 */, 7671 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, 7672 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, 7673 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, 7674 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, 7675 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, 7676 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, 7677 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, 7678 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, 7679 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, 7680 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, 7681 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, 7682 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, 7683 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, 7684 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, 7685 HAL_WHO_CCE_INFO = 259 /* 0x103 */, 7686 HAL_WHO_COMMIT = 260 /* 0x104 */, 7687 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, 7688 HAL_WHO_FLUSH = 262 /* 0x106 */, 7689 HAL_WHO_L2_LLC = 263 /* 0x107 */, 7690 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, 7691 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, 7692 HAL_WHO_L3_INFO = 266 /* 0x10a */, 7693 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, 7694 HAL_WHO_L4_INFO = 268 /* 0x10c */, 7695 HAL_WHO_MSDU = 269 /* 0x10d */, 7696 HAL_WHO_MSDU_MISC = 270 /* 0x10e */, 7697 HAL_WHO_PACKET_DATA = 271 /* 0x10f */, 7698 HAL_WHO_PACKET_HDR = 272 /* 0x110 */, 7699 HAL_WHO_PPDU_END = 273 /* 0x111 */, 7700 HAL_WHO_PPDU_START = 274 /* 0x112 */, 7701 HAL_WHO_TSO = 275 /* 0x113 */, 7702 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, 7703 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, 7704 HAL_WHO_WMAC_IV = 278 /* 0x116 */, 7705 HAL_MPDU_INFO_END = 279 /* 0x117 */, 7706 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, 7707 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, 7708 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, 7709 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, 7710 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, 7711 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, 7712 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, 7713 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, 7714 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, 7715 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, 7716 HAL_REO_DESTINATION_RING = 290 /* 0x122 */, 7717 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, 7718 HAL_WHO_TERMINATE = 292 /* 0x124 */, 7719 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, 7720 HAL_TX_CV_DATA = 294 /* 0x126 */, 7721 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, 7722 HAL_PPDU_TX_END = 296 /* 0x128 */, 7723 HAL_PROT_TX_END = 297 /* 0x129 */, 7724 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, 7725 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, 7726 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, 7727 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, 7728 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, 7729 HAL_NO_ACK_REPORT = 303 /* 0x12f */, 7730 HAL_ACK_REPORT = 304 /* 0x130 */, 7731 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, 7732 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, 7733 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, 7734 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, 7735 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, 7736 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, 7737 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, 7738 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, 7739 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, 7740 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, 7741 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, 7742 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, 7743 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, 7744 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, 7745 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, 7746 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, 7747 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, 7748 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, 7749 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, 7750 HAL_TCL_DATA_CMD = 324 /* 0x144 */, 7751 HAL_TCL_GSE_CMD = 325 /* 0x145 */, 7752 HAL_TCL_EXIT_BASE = 326 /* 0x146 */, 7753 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, 7754 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, 7755 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, 7756 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, 7757 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, 7758 HAL_TX_DATA_SYNC = 332 /* 0x14c */, 7759 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, 7760 HAL_TCL_STATUS_RING = 334 /* 0x14e */, 7761 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, 7762 HAL_TQM_SYNC_CMD = 336 /* 0x150 */, 7763 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, 7764 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, 7765 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, 7766 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, 7767 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, 7768 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, 7769 HAL_REO_TO_PPE_RING = 343 /* 0x157 */, 7770 HAL_RX_MPDU_INFO = 344 /* 0x158 */, 7771 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, 7772 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, 7773 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, 7774 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, 7775 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, 7776 HAL_RX_RING_MASK = 350 /* 0x15e */, 7777 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, 7778 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, 7779 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, 7780 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, 7781 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, 7782 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, 7783 HAL_COEX_MAC_NAP = 357 /* 0x165 */, 7784 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, 7785 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, 7786 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, 7787 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, 7788 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, 7789 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, 7790 HAL_L_SIG_A_INFO = 364 /* 0x16c */, 7791 HAL_L_SIG_B_INFO = 365 /* 0x16d */, 7792 HAL_HT_SIG_INFO = 366 /* 0x16e */, 7793 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, 7794 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, 7795 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, 7796 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, 7797 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, 7798 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, 7799 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, 7800 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, 7801 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, 7802 HAL_SERVICE_INFO = 376 /* 0x178 */, 7803 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, 7804 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, 7805 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, 7806 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, 7807 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, 7808 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, 7809 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, 7810 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, 7811 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, 7812 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, 7813 HAL_SCHEDULER_END = 387 /* 0x183 */, 7814 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, 7815 HAL_SW_PEER_INFO = 389 /* 0x185 */, 7816 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, 7817 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, 7818 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, 7819 HAL_TCL_CCE_INFO = 393 /* 0x189 */, 7820 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, 7821 HAL_CCE_RULE = 395 /* 0x18b */, 7822 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, 7823 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, 7824 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, 7825 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, 7826 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, 7827 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, 7828 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, 7829 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, 7830 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, 7831 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, 7832 HAL_CE_SRC_DESC = 406 /* 0x196 */, 7833 HAL_CE_STAT_DESC = 407 /* 0x197 */, 7834 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, 7835 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, 7836 HAL_CMD_PART_0_END = 410 /* 0x19a */, 7837 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, 7838 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, 7839 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, 7840 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, 7841 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, 7842 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, 7843 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, 7844 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, 7845 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, 7846 HAL_CE_DST_DESC = 420 /* 0x1a4 */, 7847 HAL_TLV_BASE = 511 /* 0x1ff */, 7848 }; 7849 7850 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 7851 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 7852 #define HAL_TLV_USR_ID GENMASK(31, 26) 7853 7854 #define HAL_TLV_ALIGN 4 7855 7856 struct hal_tlv_hdr { 7857 uint32_t tl; 7858 uint8_t value[]; 7859 } __packed; 7860 7861 #define RX_MPDU_DESC_INFO0_MSDU_COUNT 0xff 7862 #define RX_MPDU_DESC_INFO0_SEQ_NUM 0xfff00 7863 #define RX_MPDU_DESC_INFO0_FRAG_FLAG (1 << 20) 7864 #define RX_MPDU_DESC_INFO0_MPDU_RETRY (1 << 21) 7865 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG (1 << 22) 7866 #define RX_MPDU_DESC_INFO0_BAR_FRAME (1 << 23) 7867 #define RX_MPDU_DESC_INFO0_VALID_PN (1 << 24) 7868 #define RX_MPDU_DESC_INFO0_VALID_SA (1 << 25) 7869 #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT (1 << 26) 7870 #define RX_MPDU_DESC_INFO0_VALID_DA (1 << 27) 7871 #define RX_MPDU_DESC_INFO0_DA_MCBC (1 << 28) 7872 #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT (1 << 29) 7873 #define RX_MPDU_DESC_INFO0_RAW_MPDU (1 << 30) 7874 7875 #define RX_MPDU_DESC_META_DATA_PEER_ID 0xffff 7876 7877 struct rx_mpdu_desc { 7878 uint32_t info0; /* %RX_MPDU_DESC_INFO */ 7879 uint32_t meta_data; 7880 } __packed; 7881 7882 /* rx_mpdu_desc 7883 * Producer: RXDMA 7884 * Consumer: REO/SW/FW 7885 * 7886 * msdu_count 7887 * The number of MSDUs within the MPDU 7888 * 7889 * mpdu_sequence_number 7890 * The field can have two different meanings based on the setting 7891 * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU 7892 * start sequence number from the BAR frame otherwise it means 7893 * the MPDU sequence number of the received frame. 7894 * 7895 * fragment_flag 7896 * When set, this MPDU is a fragment and REO should forward this 7897 * fragment MPDU to the REO destination ring without any reorder 7898 * checks, pn checks or bitmap update. This implies that REO is 7899 * forwarding the pointer to the MSDU link descriptor. 7900 * 7901 * mpdu_retry_bit 7902 * The retry bit setting from the MPDU header of the received frame 7903 * 7904 * ampdu_flag 7905 * Indicates the MPDU was received as part of an A-MPDU. 7906 * 7907 * bar_frame 7908 * Indicates the received frame is a BAR frame. After processing, 7909 * this frame shall be pushed to SW or deleted. 7910 * 7911 * valid_pn 7912 * When not set, REO will not perform a PN sequence number check. 7913 * 7914 * valid_sa 7915 * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. 7916 * 7917 * sa_idx_timeout 7918 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 7919 * MAC source address search due to the expiration of search timer. 7920 * 7921 * valid_da 7922 * When set, OLE found a valid DA entry for all MSDUs in this MPDU. 7923 * 7924 * da_mcbc 7925 * Field Only valid if valid_da is set. Indicates at least one of 7926 * the DA addresses is a Multicast or Broadcast address. 7927 * 7928 * da_idx_timeout 7929 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 7930 * MAC destination address search due to the expiration of search 7931 * timer. 7932 * 7933 * raw_mpdu 7934 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 7935 * the contents in the MSDU buffer contains a 'RAW' MPDU. 7936 */ 7937 7938 enum hal_rx_msdu_desc_reo_dest_ind { 7939 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 7940 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 7941 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 7942 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 7943 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 7944 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 7945 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 7946 }; 7947 7948 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU (1 << 0) 7949 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU (1 << 1) 7950 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION (1 << 2) 7951 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 7952 #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) 7953 #define RX_MSDU_DESC_INFO0_MSDU_DROP (1 << 22) 7954 #define RX_MSDU_DESC_INFO0_VALID_SA (1 << 23) 7955 #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT (1 << 24) 7956 #define RX_MSDU_DESC_INFO0_VALID_DA (1 << 25) 7957 #define RX_MSDU_DESC_INFO0_DA_MCBC (1 << 26) 7958 #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT (1 << 27) 7959 7960 #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 7961 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) 7962 7963 struct rx_msdu_desc { 7964 uint32_t info0; 7965 uint32_t rsvd0; 7966 } __packed; 7967 7968 /* rx_msdu_desc 7969 * 7970 * first_msdu_in_mpdu 7971 * Indicates first msdu in mpdu. 7972 * 7973 * last_msdu_in_mpdu 7974 * Indicates last msdu in mpdu. This flag can be true only when 7975 * 'Msdu_continuation' set to 0. This implies that when an msdu 7976 * is spread out over multiple buffers and thus msdu_continuation 7977 * is set, only for the very last buffer of the msdu, can the 7978 * 'last_msdu_in_mpdu' be set. 7979 * 7980 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 7981 * the MPDU that this MSDU belongs to only contains a single MSDU. 7982 * 7983 * msdu_continuation 7984 * When set, this MSDU buffer was not able to hold the entire MSDU. 7985 * The next buffer will therefore contain additional information 7986 * related to this MSDU. 7987 * 7988 * msdu_length 7989 * Field is only valid in combination with the 'first_msdu_in_mpdu' 7990 * being set. Full MSDU length in bytes after decapsulation. This 7991 * field is still valid for MPDU frames without A-MSDU. It still 7992 * represents MSDU length after decapsulation Or in case of RAW 7993 * MPDUs, it indicates the length of the entire MPDU (without FCS 7994 * field). 7995 * 7996 * reo_destination_indication 7997 * The id of the reo exit ring where the msdu frame shall push 7998 * after (MPDU level) reordering has finished. Values are defined 7999 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 8000 * 8001 * msdu_drop 8002 * Indicates that REO shall drop this MSDU and not forward it to 8003 * any other ring. 8004 * 8005 * valid_sa 8006 * Indicates OLE found a valid SA entry for this MSDU. 8007 * 8008 * sa_idx_timeout 8009 * Indicates, an unsuccessful MAC source address search due to 8010 * the expiration of search timer for this MSDU. 8011 * 8012 * valid_da 8013 * When set, OLE found a valid DA entry for this MSDU. 8014 * 8015 * da_mcbc 8016 * Field Only valid if valid_da is set. Indicates the DA address 8017 * is a Multicast or Broadcast address for this MSDU. 8018 * 8019 * da_idx_timeout 8020 * Indicates, an unsuccessful MAC destination address search due 8021 * to the expiration of search timer for this MSDU. 8022 */ 8023 8024 enum hal_reo_dest_ring_buffer_type { 8025 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 8026 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 8027 }; 8028 8029 enum hal_reo_dest_ring_push_reason { 8030 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 8031 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 8032 }; 8033 8034 enum hal_reo_dest_ring_error_code { 8035 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 8036 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 8037 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 8038 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 8039 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 8040 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 8041 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 8042 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 8043 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 8044 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 8045 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 8046 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 8047 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 8048 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 8049 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 8050 HAL_REO_DEST_RING_ERROR_CODE_MAX, 8051 }; 8052 8053 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8054 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE (1 << 8) 8055 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) 8056 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) 8057 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) 8058 8059 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID (1 << 0) 8060 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) 8061 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) 8062 8063 #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) 8064 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 8065 8066 struct hal_reo_dest_ring { 8067 struct ath11k_buffer_addr buf_addr_info; 8068 struct rx_mpdu_desc rx_mpdu_info; 8069 struct rx_msdu_desc rx_msdu_info; 8070 uint32_t queue_addr_lo; 8071 uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */ 8072 uint32_t info1; /* %HAL_REO_DEST_RING_INFO1_ */ 8073 uint32_t rsvd0; 8074 uint32_t rsvd1; 8075 uint32_t rsvd2; 8076 uint32_t rsvd3; 8077 uint32_t rsvd4; 8078 uint32_t rsvd5; 8079 uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */ 8080 } __packed; 8081 8082 /* hal_reo_dest_ring 8083 * 8084 * Producer: RXDMA 8085 * Consumer: REO/SW/FW 8086 * 8087 * buf_addr_info 8088 * Details of the physical address of a buffer or MSDU 8089 * link descriptor. 8090 * 8091 * rx_mpdu_info 8092 * General information related to the MPDU that is passed 8093 * on from REO entrance ring to the REO destination ring. 8094 * 8095 * rx_msdu_info 8096 * General information related to the MSDU that is passed 8097 * on from RXDMA all the way to the REO destination ring. 8098 * 8099 * queue_addr_lo 8100 * Address (lower 32 bits) of the REO queue descriptor. 8101 * 8102 * queue_addr_hi 8103 * Address (upper 8 bits) of the REO queue descriptor. 8104 * 8105 * buffer_type 8106 * Indicates the type of address provided in the buf_addr_info. 8107 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 8108 * 8109 * push_reason 8110 * Reason for pushing this frame to this exit ring. Values are 8111 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 8112 * 8113 * error_code 8114 * Valid only when 'push_reason' is set. All error codes are 8115 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 8116 * 8117 * rx_queue_num 8118 * Indicates the REO MPDU reorder queue id from which this frame 8119 * originated. 8120 * 8121 * reorder_info_valid 8122 * When set, REO has been instructed to not perform the actual 8123 * re-ordering of frames for this queue, but just to insert 8124 * the reorder opcodes. 8125 * 8126 * reorder_opcode 8127 * Field is valid when 'reorder_info_valid' is set. This field is 8128 * always valid for debug purpose as well. 8129 * 8130 * reorder_slot_idx 8131 * Valid only when 'reorder_info_valid' is set. 8132 * 8133 * ring_id 8134 * The buffer pointer ring id. 8135 * 0 - Idle ring 8136 * 1 - N refers to other rings. 8137 * 8138 * looping_count 8139 * Indicates the number of times the producer of entries into 8140 * this ring has looped around the ring. 8141 */ 8142 8143 enum hal_reo_entr_rxdma_ecode { 8144 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 8145 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 8146 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 8147 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 8148 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 8149 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 8150 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 8151 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 8152 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 8153 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 8154 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 8155 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 8156 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 8157 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 8158 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 8159 }; 8160 8161 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8162 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 8163 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 8164 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 8165 8166 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 8167 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 8168 8169 struct hal_reo_entrance_ring { 8170 struct ath11k_buffer_addr buf_addr_info; 8171 struct rx_mpdu_desc rx_mpdu_info; 8172 uint32_t queue_addr_lo; 8173 uint32_t info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 8174 uint32_t info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 8175 uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */ 8176 8177 } __packed; 8178 8179 /* hal_reo_entrance_ring 8180 * 8181 * Producer: RXDMA 8182 * Consumer: REO 8183 * 8184 * buf_addr_info 8185 * Details of the physical address of a buffer or MSDU 8186 * link descriptor. 8187 * 8188 * rx_mpdu_info 8189 * General information related to the MPDU that is passed 8190 * on from REO entrance ring to the REO destination ring. 8191 * 8192 * queue_addr_lo 8193 * Address (lower 32 bits) of the REO queue descriptor. 8194 * 8195 * queue_addr_hi 8196 * Address (upper 8 bits) of the REO queue descriptor. 8197 * 8198 * mpdu_byte_count 8199 * An approximation of the number of bytes received in this MPDU. 8200 * Used to keeps stats on the amount of data flowing 8201 * through a queue. 8202 * 8203 * reo_destination_indication 8204 * The id of the reo exit ring where the msdu frame shall push 8205 * after (MPDU level) reordering has finished. Values are defined 8206 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 8207 * 8208 * frameless_bar 8209 * Indicates that this REO entrance ring struct contains BAR info 8210 * from a multi TID BAR frame. The original multi TID BAR frame 8211 * itself contained all the REO info for the first TID, but all 8212 * the subsequent TID info and their linkage to the REO descriptors 8213 * is passed down as 'frameless' BAR info. 8214 * 8215 * The only fields valid in this descriptor when this bit is set 8216 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 8217 * bar_frame and peer_meta_data. 8218 * 8219 * rxdma_push_reason 8220 * Reason for pushing this frame to this exit ring. Values are 8221 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 8222 * 8223 * rxdma_error_code 8224 * Valid only when 'push_reason' is set. All error codes are 8225 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 8226 * 8227 * ring_id 8228 * The buffer pointer ring id. 8229 * 0 - Idle ring 8230 * 1 - N refers to other rings. 8231 * 8232 * looping_count 8233 * Indicates the number of times the producer of entries into 8234 * this ring has looped around the ring. 8235 */ 8236 8237 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) 8238 #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) 8239 #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7) 8240 #define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11) 8241 #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12) 8242 #define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16) 8243 8244 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) 8245 #define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20) 8246 #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) 8247 8248 struct hal_sw_monitor_ring { 8249 struct ath11k_buffer_addr buf_addr_info; 8250 struct rx_mpdu_desc rx_mpdu_info; 8251 struct ath11k_buffer_addr status_buf_addr_info; 8252 uint32_t info0; 8253 uint32_t info1; 8254 } __packed; 8255 8256 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 8257 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 8258 8259 struct hal_reo_cmd_hdr { 8260 uint32_t info0; 8261 } __packed; 8262 8263 8264 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 8265 8266 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 8267 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 8268 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 8269 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 8270 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 8271 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 8272 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 8273 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 8274 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 8275 8276 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 8277 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 8278 #define HAL_REO_CMD_UPD0_VLD BIT(9) 8279 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 8280 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 8281 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 8282 #define HAL_REO_CMD_UPD0_AC BIT(13) 8283 #define HAL_REO_CMD_UPD0_BAR BIT(14) 8284 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 8285 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 8286 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 8287 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 8288 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 8289 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 8290 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 8291 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 8292 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 8293 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 8294 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 8295 #define HAL_REO_CMD_UPD0_SSN BIT(26) 8296 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 8297 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 8298 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 8299 #define HAL_REO_CMD_UPD0_PN BIT(30) 8300 8301 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 8302 #define HAL_REO_CMD_UPD1_VLD BIT(16) 8303 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 8304 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 8305 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 8306 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 8307 #define HAL_REO_CMD_UPD1_BAR BIT(23) 8308 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 8309 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 8310 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 8311 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 8312 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 8313 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 8314 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 8315 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 8316 8317 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 8318 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 8319 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 8320 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 8321 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 8322 8323 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 8324 8325 struct ath11k_hal_reo_cmd { 8326 uint32_t addr_lo; 8327 uint32_t flag; 8328 uint32_t upd0; 8329 uint32_t upd1; 8330 uint32_t upd2; 8331 uint32_t pn[4]; 8332 uint16_t rx_queue_num; 8333 uint16_t min_rel; 8334 uint16_t min_fwd; 8335 uint8_t addr_hi; 8336 uint8_t ac_list; 8337 uint8_t blocking_idx; 8338 uint16_t ba_window_size; 8339 uint8_t pn_size; 8340 }; 8341 8342 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 8343 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 8344 8345 struct hal_reo_get_queue_stats { 8346 struct hal_reo_cmd_hdr cmd; 8347 uint32_t queue_addr_lo; 8348 uint32_t info0; 8349 uint32_t rsvd0[6]; 8350 } __packed; 8351 8352 /* hal_reo_get_queue_stats 8353 * Producer: SW 8354 * Consumer: REO 8355 * 8356 * cmd 8357 * Details for command execution tracking purposes. 8358 * 8359 * queue_addr_lo 8360 * Address (lower 32 bits) of the REO queue descriptor. 8361 * 8362 * queue_addr_hi 8363 * Address (upper 8 bits) of the REO queue descriptor. 8364 * 8365 * clear_stats 8366 * Clear stats settings. When set, Clear the stats after 8367 * generating the status. 8368 * 8369 * Following stats will be cleared. 8370 * Timeout_count 8371 * Forward_due_to_bar_count 8372 * Duplicate_count 8373 * Frames_in_order_count 8374 * BAR_received_count 8375 * MPDU_Frames_processed_count 8376 * MSDU_Frames_processed_count 8377 * Total_processed_byte_count 8378 * Late_receive_MPDU_count 8379 * window_jump_2k 8380 * Hole_count 8381 */ 8382 8383 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 8384 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 8385 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 8386 8387 struct hal_reo_flush_queue { 8388 struct hal_reo_cmd_hdr cmd; 8389 uint32_t desc_addr_lo; 8390 uint32_t info0; 8391 uint32_t rsvd0[6]; 8392 } __packed; 8393 8394 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 8395 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 8396 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 8397 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 8398 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 8399 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 8400 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 8401 8402 struct hal_reo_flush_cache { 8403 struct hal_reo_cmd_hdr cmd; 8404 uint32_t cache_addr_lo; 8405 uint32_t info0; 8406 uint32_t rsvd0[6]; 8407 } __packed; 8408 8409 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) 8410 #define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) 8411 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) 8412 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) 8413 #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) 8414 #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) 8415 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) 8416 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) 8417 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) 8418 8419 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) 8420 #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) 8421 #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) 8422 #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) 8423 #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) 8424 #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) 8425 #define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) 8426 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) 8427 8428 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) 8429 #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) 8430 #define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) 8431 #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) 8432 #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) 8433 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) 8434 8435 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) 8436 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) 8437 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) 8438 #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30) 8439 8440 #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) 8441 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) 8442 8443 enum hal_encrypt_type { 8444 HAL_ENCRYPT_TYPE_WEP_40, 8445 HAL_ENCRYPT_TYPE_WEP_104, 8446 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 8447 HAL_ENCRYPT_TYPE_WEP_128, 8448 HAL_ENCRYPT_TYPE_TKIP_MIC, 8449 HAL_ENCRYPT_TYPE_WAPI, 8450 HAL_ENCRYPT_TYPE_CCMP_128, 8451 HAL_ENCRYPT_TYPE_OPEN, 8452 HAL_ENCRYPT_TYPE_CCMP_256, 8453 HAL_ENCRYPT_TYPE_GCMP_128, 8454 HAL_ENCRYPT_TYPE_AES_GCMP_256, 8455 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 8456 }; 8457 8458 enum hal_tcl_encap_type { 8459 HAL_TCL_ENCAP_TYPE_RAW, 8460 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 8461 HAL_TCL_ENCAP_TYPE_ETHERNET, 8462 HAL_TCL_ENCAP_TYPE_802_3 = 3, 8463 }; 8464 8465 enum hal_tcl_desc_type { 8466 HAL_TCL_DESC_TYPE_BUFFER, 8467 HAL_TCL_DESC_TYPE_EXT_DESC, 8468 }; 8469 8470 enum hal_wbm_htt_tx_comp_status { 8471 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 8472 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 8473 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 8474 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 8475 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 8476 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 8477 }; 8478 8479 struct hal_tcl_data_cmd { 8480 struct ath11k_buffer_addr buf_addr_info; 8481 uint32_t info0; 8482 uint32_t info1; 8483 uint32_t info2; 8484 uint32_t info3; 8485 uint32_t info4; 8486 } __packed; 8487 8488 /* hal_tcl_data_cmd 8489 * 8490 * buf_addr_info 8491 * Details of the physical address of a buffer or MSDU 8492 * link descriptor. 8493 * 8494 * desc_type 8495 * Indicates the type of address provided in the buf_addr_info. 8496 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 8497 * 8498 * epd 8499 * When this bit is set then input packet is an EPD type. 8500 * 8501 * encap_type 8502 * Indicates the encapsulation that HW will perform. Values are 8503 * defined in enum %HAL_TCL_ENCAP_TYPE_. 8504 * 8505 * encrypt_type 8506 * Field only valid for encap_type: RAW 8507 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 8508 * 8509 * src_buffer_swap 8510 * Treats source memory (packet buffer) organization as big-endian. 8511 * 1'b0: Source memory is little endian 8512 * 1'b1: Source memory is big endian 8513 * 8514 * link_meta_swap 8515 * Treats link descriptor and Metadata as big-endian. 8516 * 1'b0: memory is little endian 8517 * 1'b1: memory is big endian 8518 * 8519 * search_type 8520 * Search type select 8521 * 0 - Normal search, 1 - Index based address search, 8522 * 2 - Index based flow search 8523 * 8524 * addrx_en 8525 * addry_en 8526 * Address X/Y search enable in ASE correspondingly. 8527 * 1'b0: Search disable 8528 * 1'b1: Search Enable 8529 * 8530 * cmd_num 8531 * This number can be used to match against status. 8532 * 8533 * data_length 8534 * MSDU length in case of direct descriptor. Length of link 8535 * extension descriptor in case of Link extension descriptor. 8536 * 8537 * *_checksum_en 8538 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 8539 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 8540 * 8541 * to_fw 8542 * Forward packet to FW along with classification result. The 8543 * packet will not be forward to TQM when this bit is set. 8544 * 1'b0: Use classification result to forward the packet. 8545 * 1'b1: Override classification result & forward packet only to fw 8546 * 8547 * packet_offset 8548 * Packet offset from Metadata in case of direct buffer descriptor. 8549 * 8550 * buffer_timestamp 8551 * buffer_timestamp_valid 8552 * Frame system entrance timestamp. It shall be filled by first 8553 * module (SW, TCL or TQM) that sees the frames first. 8554 * 8555 * mesh_enable 8556 * For raw WiFi frames, this indicates transmission to a mesh STA, 8557 * enabling the interpretation of the 'Mesh Control Present' bit 8558 * (bit 8) of QoS Control. 8559 * For native WiFi frames, this indicates that a 'Mesh Control' 8560 * field is present between the header and the LLC. 8561 * 8562 * hlos_tid_overwrite 8563 * 8564 * When set, TCL shall ignore the IP DSCP and VLAN PCP 8565 * fields and use HLOS_TID as the final TID. Otherwise TCL 8566 * shall consider the DSCP and PCP fields as well as HLOS_TID 8567 * and choose a final TID based on the configured priority 8568 * 8569 * hlos_tid 8570 * HLOS MSDU priority 8571 * Field is used when HLOS_TID_overwrite is set. 8572 * 8573 * lmac_id 8574 * TCL uses this LMAC_ID in address search, i.e, while 8575 * finding matching entry for the packet in AST corresponding 8576 * to given LMAC_ID 8577 * 8578 * If LMAC ID is all 1s (=> value 3), it indicates wildcard 8579 * match for any MAC 8580 * 8581 * dscp_tid_table_num 8582 * DSCP to TID mapping table number that need to be used 8583 * for the MSDU. 8584 * 8585 * search_index 8586 * The index that will be used for index based address or 8587 * flow search. The field is valid when 'search_type' is 1 or 2. 8588 * 8589 * cache_set_num 8590 * 8591 * Cache set number that should be used to cache the index 8592 * based search results, for address and flow search. This 8593 * value should be equal to LSB four bits of the hash value of 8594 * match data, in case of search index points to an entry which 8595 * may be used in content based search also. The value can be 8596 * anything when the entry pointed by search index will not be 8597 * used for content based search. 8598 * 8599 * ring_id 8600 * The buffer pointer ring ID. 8601 * 0 refers to the IDLE ring 8602 * 1 - N refers to other rings 8603 * 8604 * looping_count 8605 * 8606 * A count value that indicates the number of times the 8607 * producer of entries into the Ring has looped around the 8608 * ring. 8609 * 8610 * At initialization time, this value is set to 0. On the 8611 * first loop, this value is set to 1. After the max value is 8612 * reached allowed by the number of bits for this field, the 8613 * count value continues with 0 again. 8614 * 8615 * In case SW is the consumer of the ring entries, it can 8616 * use this field to figure out up to where the producer of 8617 * entries has created new entries. This eliminates the need to 8618 * check where the head pointer' of the ring is located once 8619 * the SW starts processing an interrupt indicating that new 8620 * entries have been put into this ring... 8621 * 8622 * Also note that SW if it wants only needs to look at the 8623 * LSB bit of this count value. 8624 */ 8625 8626 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 8627 8628 enum hal_tcl_gse_ctrl { 8629 HAL_TCL_GSE_CTRL_RD_STAT, 8630 HAL_TCL_GSE_CTRL_SRCH_DIS, 8631 HAL_TCL_GSE_CTRL_WR_BK_SINGLE, 8632 HAL_TCL_GSE_CTRL_WR_BK_ALL, 8633 HAL_TCL_GSE_CTRL_INVAL_SINGLE, 8634 HAL_TCL_GSE_CTRL_INVAL_ALL, 8635 HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, 8636 HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, 8637 HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, 8638 }; 8639 8640 /* hal_tcl_gse_ctrl 8641 * 8642 * rd_stat 8643 * Report or Read statistics 8644 * srch_dis 8645 * Search disable. Report only Hash. 8646 * wr_bk_single 8647 * Write Back single entry 8648 * wr_bk_all 8649 * Write Back entire cache entry 8650 * inval_single 8651 * Invalidate single cache entry 8652 * inval_all 8653 * Invalidate entire cache 8654 * wr_bk_inval_single 8655 * Write back and invalidate single entry in cache 8656 * wr_bk_inval_all 8657 * Write back and invalidate entire cache 8658 * clr_stat_single 8659 * Clear statistics for single entry 8660 */ 8661 8662 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) 8663 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) 8664 #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) 8665 #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) 8666 #define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) 8667 8668 #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) 8669 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) 8670 8671 struct hal_tcl_gse_cmd { 8672 uint32_t ctrl_buf_addr_lo; 8673 uint32_t info0; 8674 uint32_t meta_data[2]; 8675 uint32_t rsvd0[2]; 8676 uint32_t info1; 8677 } __packed; 8678 8679 /* hal_tcl_gse_cmd 8680 * 8681 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 8682 * Address of a control buffer containing additional info needed 8683 * for this command execution. 8684 * 8685 * gse_ctrl 8686 * GSE control operations. This includes cache operations and table 8687 * entry statistics read/clear operation. Values are defined in 8688 * enum %HAL_TCL_GSE_CTRL. 8689 * 8690 * gse_sel 8691 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 8692 * 0: FSE select 1: ASE select 8693 * 8694 * status_destination_ring_id 8695 * TCL status ring to which the GSE status needs to be send. 8696 * 8697 * swap 8698 * Bit to enable byte swapping of contents of buffer. 8699 * 8700 * meta_data 8701 * Meta data to be returned in the status descriptor 8702 */ 8703 8704 enum hal_tcl_cache_op_res { 8705 HAL_TCL_CACHE_OP_RES_DONE, 8706 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 8707 HAL_TCL_CACHE_OP_RES_TIMEOUT, 8708 }; 8709 8710 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) 8711 #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) 8712 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) 8713 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) 8714 8715 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) 8716 8717 #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) 8718 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 8719 8720 struct hal_tcl_status_ring { 8721 uint32_t info0; 8722 uint32_t msdu_byte_count; 8723 uint32_t msdu_timestamp; 8724 uint32_t meta_data[2]; 8725 uint32_t info1; 8726 uint32_t rsvd0; 8727 uint32_t info2; 8728 } __packed; 8729 8730 /* hal_tcl_status_ring 8731 * 8732 * gse_ctrl 8733 * GSE control operations. This includes cache operations and table 8734 * entry statistics read/clear operation. Values are defined in 8735 * enum %HAL_TCL_GSE_CTRL. 8736 * 8737 * gse_sel 8738 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 8739 * 0: FSE select 1: ASE select 8740 * 8741 * cache_op_res 8742 * Cache operation result. Values are defined in enum 8743 * %HAL_TCL_CACHE_OP_RES_. 8744 * 8745 * msdu_cnt 8746 * msdu_byte_count 8747 * MSDU count of Entry and MSDU byte count for entry 1. 8748 * 8749 * hash_indx 8750 * Hash value of the entry in case of search failed or disabled. 8751 */ 8752 8753 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 8754 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 8755 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 8756 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 8757 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 8758 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 8759 8760 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 8761 8762 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 8763 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 8764 8765 struct hal_ce_srng_src_desc { 8766 uint32_t buffer_addr_low; 8767 uint32_t buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 8768 uint32_t meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 8769 uint32_t flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 8770 } __packed; 8771 8772 /* 8773 * hal_ce_srng_src_desc 8774 * 8775 * buffer_addr_lo 8776 * LSB 32 bits of the 40 Bit Pointer to the source buffer 8777 * 8778 * buffer_addr_hi 8779 * MSB 8 bits of the 40 Bit Pointer to the source buffer 8780 * 8781 * toeplitz_en 8782 * Enable generation of 32-bit Toeplitz-LFSR hash for 8783 * data transfer. In case of gather field in first source 8784 * ring entry of the gather copy cycle in taken into account. 8785 * 8786 * src_swap 8787 * Treats source memory organization as big-endian. For 8788 * each dword read (4 bytes), the byte 0 is swapped with byte 3 8789 * and byte 1 is swapped with byte 2. 8790 * In case of gather field in first source ring entry of 8791 * the gather copy cycle in taken into account. 8792 * 8793 * dest_swap 8794 * Treats destination memory organization as big-endian. 8795 * For each dword write (4 bytes), the byte 0 is swapped with 8796 * byte 3 and byte 1 is swapped with byte 2. 8797 * In case of gather field in first source ring entry of 8798 * the gather copy cycle in taken into account. 8799 * 8800 * gather 8801 * Enables gather of multiple copy engine source 8802 * descriptors to one destination. 8803 * 8804 * ce_res_0 8805 * Reserved 8806 * 8807 * 8808 * length 8809 * Length of the buffer in units of octets of the current 8810 * descriptor 8811 * 8812 * fw_metadata 8813 * Meta data used by FW. 8814 * In case of gather field in first source ring entry of 8815 * the gather copy cycle in taken into account. 8816 * 8817 * ce_res_1 8818 * Reserved 8819 * 8820 * ce_res_2 8821 * Reserved 8822 * 8823 * ring_id 8824 * The buffer pointer ring ID. 8825 * 0 refers to the IDLE ring 8826 * 1 - N refers to other rings 8827 * Helps with debugging when dumping ring contents. 8828 * 8829 * looping_count 8830 * A count value that indicates the number of times the 8831 * producer of entries into the Ring has looped around the 8832 * ring. 8833 * 8834 * At initialization time, this value is set to 0. On the 8835 * first loop, this value is set to 1. After the max value is 8836 * reached allowed by the number of bits for this field, the 8837 * count value continues with 0 again. 8838 * 8839 * In case SW is the consumer of the ring entries, it can 8840 * use this field to figure out up to where the producer of 8841 * entries has created new entries. This eliminates the need to 8842 * check where the head pointer' of the ring is located once 8843 * the SW starts processing an interrupt indicating that new 8844 * entries have been put into this ring... 8845 * 8846 * Also note that SW if it wants only needs to look at the 8847 * LSB bit of this count value. 8848 */ 8849 8850 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 8851 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 8852 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 8853 8854 struct hal_ce_srng_dest_desc { 8855 uint32_t buffer_addr_low; 8856 uint32_t buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 8857 } __packed; 8858 8859 /* hal_ce_srng_dest_desc 8860 * 8861 * dst_buffer_low 8862 * LSB 32 bits of the 40 Bit Pointer to the Destination 8863 * buffer 8864 * 8865 * dst_buffer_high 8866 * MSB 8 bits of the 40 Bit Pointer to the Destination 8867 * buffer 8868 * 8869 * ce_res_4 8870 * Reserved 8871 * 8872 * ring_id 8873 * The buffer pointer ring ID. 8874 * 0 refers to the IDLE ring 8875 * 1 - N refers to other rings 8876 * Helps with debugging when dumping ring contents. 8877 * 8878 * looping_count 8879 * A count value that indicates the number of times the 8880 * producer of entries into the Ring has looped around the 8881 * ring. 8882 * 8883 * At initialization time, this value is set to 0. On the 8884 * first loop, this value is set to 1. After the max value is 8885 * reached allowed by the number of bits for this field, the 8886 * count value continues with 0 again. 8887 * 8888 * In case SW is the consumer of the ring entries, it can 8889 * use this field to figure out up to where the producer of 8890 * entries has created new entries. This eliminates the need to 8891 * check where the head pointer' of the ring is located once 8892 * the SW starts processing an interrupt indicating that new 8893 * entries have been put into this ring... 8894 * 8895 * Also note that SW if it wants only needs to look at the 8896 * LSB bit of this count value. 8897 */ 8898 8899 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 8900 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 8901 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 8902 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 8903 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 8904 8905 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) 8906 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 8907 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 8908 8909 struct hal_ce_srng_dst_status_desc { 8910 uint32_t flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 8911 uint32_t toeplitz_hash0; 8912 uint32_t toeplitz_hash1; 8913 uint32_t meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 8914 } __packed; 8915 8916 /* hal_ce_srng_dst_status_desc 8917 * 8918 * ce_res_5 8919 * Reserved 8920 * 8921 * toeplitz_en 8922 * 8923 * src_swap 8924 * Source memory buffer swapped 8925 * 8926 * dest_swap 8927 * Destination memory buffer swapped 8928 * 8929 * gather 8930 * Gather of multiple copy engine source descriptors to one 8931 * destination enabled 8932 * 8933 * ce_res_6 8934 * Reserved 8935 * 8936 * length 8937 * Sum of all the Lengths of the source descriptor in the 8938 * gather chain 8939 * 8940 * toeplitz_hash_0 8941 * 32 LS bits of 64 bit Toeplitz LFSR hash result 8942 * 8943 * toeplitz_hash_1 8944 * 32 MS bits of 64 bit Toeplitz LFSR hash result 8945 * 8946 * fw_metadata 8947 * Meta data used by FW 8948 * In case of gather field in first source ring entry of 8949 * the gather copy cycle in taken into account. 8950 * 8951 * ce_res_7 8952 * Reserved 8953 * 8954 * ring_id 8955 * The buffer pointer ring ID. 8956 * 0 refers to the IDLE ring 8957 * 1 - N refers to other rings 8958 * Helps with debugging when dumping ring contents. 8959 * 8960 * looping_count 8961 * A count value that indicates the number of times the 8962 * producer of entries into the Ring has looped around the 8963 * ring. 8964 * 8965 * At initialization time, this value is set to 0. On the 8966 * first loop, this value is set to 1. After the max value is 8967 * reached allowed by the number of bits for this field, the 8968 * count value continues with 0 again. 8969 * 8970 * In case SW is the consumer of the ring entries, it can 8971 * use this field to figure out up to where the producer of 8972 * entries has created new entries. This eliminates the need to 8973 * check where the head pointer' of the ring is located once 8974 * the SW starts processing an interrupt indicating that new 8975 * entries have been put into this ring... 8976 * 8977 * Also note that SW if it wants only needs to look at the 8978 * LSB bit of this count value. 8979 */ 8980 8981 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 8982 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) 8983 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) 8984 #define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) 8985 #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) 8986 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) 8987 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) 8988 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) 8989 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) 8990 8991 enum hal_tx_rate_stats_bw { 8992 HAL_TX_RATE_STATS_BW_20, 8993 HAL_TX_RATE_STATS_BW_40, 8994 HAL_TX_RATE_STATS_BW_80, 8995 HAL_TX_RATE_STATS_BW_160, 8996 }; 8997 8998 enum hal_tx_rate_stats_pkt_type { 8999 HAL_TX_RATE_STATS_PKT_TYPE_11A, 9000 HAL_TX_RATE_STATS_PKT_TYPE_11B, 9001 HAL_TX_RATE_STATS_PKT_TYPE_11N, 9002 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 9003 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 9004 }; 9005 9006 enum hal_tx_rate_stats_sgi { 9007 HAL_TX_RATE_STATS_SGI_08US, 9008 HAL_TX_RATE_STATS_SGI_04US, 9009 HAL_TX_RATE_STATS_SGI_16US, 9010 HAL_TX_RATE_STATS_SGI_32US, 9011 }; 9012 9013 struct hal_tx_rate_stats { 9014 uint32_t info0; 9015 uint32_t tsf; 9016 } __packed; 9017 9018 struct hal_wbm_link_desc { 9019 struct ath11k_buffer_addr buf_addr_info; 9020 } __packed; 9021 9022 /* hal_wbm_link_desc 9023 * 9024 * Producer: WBM 9025 * Consumer: WBM 9026 * 9027 * buf_addr_info 9028 * Details of the physical address of a buffer or MSDU 9029 * link descriptor. 9030 */ 9031 9032 enum hal_wbm_rel_src_module { 9033 HAL_WBM_REL_SRC_MODULE_TQM, 9034 HAL_WBM_REL_SRC_MODULE_RXDMA, 9035 HAL_WBM_REL_SRC_MODULE_REO, 9036 HAL_WBM_REL_SRC_MODULE_FW, 9037 HAL_WBM_REL_SRC_MODULE_SW, 9038 }; 9039 9040 enum hal_wbm_rel_desc_type { 9041 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 9042 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 9043 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 9044 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 9045 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 9046 }; 9047 9048 /* hal_wbm_rel_desc_type 9049 * 9050 * msdu_buffer 9051 * The address points to an MSDU buffer 9052 * 9053 * msdu_link_descriptor 9054 * The address points to an Tx MSDU link descriptor 9055 * 9056 * mpdu_link_descriptor 9057 * The address points to an MPDU link descriptor 9058 * 9059 * msdu_ext_descriptor 9060 * The address points to an MSDU extension descriptor 9061 * 9062 * queue_ext_descriptor 9063 * The address points to an TQM queue extension descriptor. WBM should 9064 * treat this is the same way as a link descriptor. 9065 */ 9066 9067 enum hal_wbm_rel_bm_act { 9068 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 9069 HAL_WBM_REL_BM_ACT_REL_MSDU, 9070 }; 9071 9072 /* hal_wbm_rel_bm_act 9073 * 9074 * put_in_idle_list 9075 * Put the buffer or descriptor back in the idle list. In case of MSDU or 9076 * MDPU link descriptor, BM does not need to check to release any 9077 * individual MSDU buffers. 9078 * 9079 * release_msdu_list 9080 * This BM action can only be used in combination with desc_type being 9081 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 9082 * pointer in the MSDU link descriptor is the first of an MPDU that is 9083 * released. BM shall release all the MSDU buffers linked to this first 9084 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 9085 * set to value 0, which represents the 'NULL' pointer. When all MSDU 9086 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 9087 * descriptor itself shall also be released. 9088 */ 9089 9090 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 9091 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 9092 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 9093 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 9094 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 9095 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 9096 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 9097 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 9098 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 9099 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 9100 9101 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 9102 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 9103 9104 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 9105 #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) 9106 #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) 9107 #define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) 9108 #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) 9109 #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) 9110 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 9111 9112 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) 9113 #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) 9114 #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) 9115 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) 9116 9117 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) 9118 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) 9119 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) 9120 9121 struct hal_wbm_release_ring { 9122 struct ath11k_buffer_addr buf_addr_info; 9123 uint32_t info0; 9124 uint32_t info1; 9125 uint32_t info2; 9126 struct hal_tx_rate_stats rate_stats; 9127 uint32_t info3; 9128 } __packed; 9129 9130 /* hal_wbm_release_ring 9131 * 9132 * Producer: SW/TQM/RXDMA/REO/SWITCH 9133 * Consumer: WBM/SW/FW 9134 * 9135 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5 9136 * for software based completions. 9137 * 9138 * buf_addr_info 9139 * Details of the physical address of the buffer or link descriptor. 9140 * 9141 * release_source_module 9142 * Indicates which module initiated the release of this buffer/descriptor. 9143 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 9144 * 9145 * bm_action 9146 * Field only valid when the field return_buffer_manager in 9147 * Released_buff_or_desc_addr_info indicates: 9148 * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST 9149 * Values are defined in enum %HAL_WBM_REL_BM_ACT_. 9150 * 9151 * buffer_or_desc_type 9152 * Field only valid when WBM is marked as the return_buffer_manager in 9153 * the Released_Buffer_address_info. Indicates that type of buffer or 9154 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 9155 * 9156 * first_msdu_index 9157 * Field only valid for the bm_action release_msdu_list. The index of the 9158 * first MSDU in an MSDU link descriptor all belonging to the same MPDU. 9159 * 9160 * tqm_release_reason 9161 * Field only valid when Release_source_module is set to release_source_TQM 9162 * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. 9163 * 9164 * rxdma_push_reason 9165 * reo_push_reason 9166 * Indicates why rxdma/reo pushed the frame to this ring and values are 9167 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 9168 * 9169 * rxdma_error_code 9170 * Field only valid when 'rxdma_push_reason' set to 'error_detected'. 9171 * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 9172 * 9173 * reo_error_code 9174 * Field only valid when 'reo_push_reason' set to 'error_detected'. Values 9175 * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 9176 * 9177 * wbm_internal_error 9178 * Is set when WBM got a buffer pointer but the action was to push it to 9179 * the idle link descriptor ring or do link related activity OR 9180 * Is set when WBM got a link buffer pointer but the action was to push it 9181 * to the buffer descriptor ring. 9182 * 9183 * tqm_status_number 9184 * The value in this field is equal to tqm_cmd_number in TQM command. It is 9185 * used to correlate the statu with TQM commands. Only valid when 9186 * release_source_module is TQM. 9187 * 9188 * transmit_count 9189 * The number of times the frame has been transmitted, valid only when 9190 * release source in TQM. 9191 * 9192 * ack_frame_rssi 9193 * This field is only valid when the source is TQM. If this frame is 9194 * removed as the result of the reception of an ACK or BA, this field 9195 * indicates the RSSI of the received ACK or BA frame. 9196 * 9197 * sw_release_details_valid 9198 * This is set when WMB got a 'release_msdu_list' command from TQM and 9199 * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs 9200 * and pass them one at a time on to the 'buffer owner'. 9201 * 9202 * first_msdu 9203 * Field only valid when SW_release_details_valid is set. 9204 * When set, this MSDU is the first MSDU pointed to in the 9205 * 'release_msdu_list' command. 9206 * 9207 * last_msdu 9208 * Field only valid when SW_release_details_valid is set. 9209 * When set, this MSDU is the last MSDU pointed to in the 9210 * 'release_msdu_list' command. 9211 * 9212 * msdu_part_of_amsdu 9213 * Field only valid when SW_release_details_valid is set. 9214 * When set, this MSDU was part of an A-MSDU in MPDU 9215 * 9216 * fw_tx_notify_frame 9217 * Field only valid when SW_release_details_valid is set. 9218 * 9219 * buffer_timestamp 9220 * Field only valid when SW_release_details_valid is set. 9221 * This is the Buffer_timestamp field from the 9222 * Timestamp in units of 1024 us 9223 * 9224 * struct hal_tx_rate_stats rate_stats 9225 * Details for command execution tracking purposes. 9226 * 9227 * sw_peer_id 9228 * tid 9229 * Field only valid when Release_source_module is set to 9230 * release_source_TQM 9231 * 9232 * 1) Release of msdu buffer due to drop_frame = 1. Flow is 9233 * not fetched and hence sw_peer_id and tid = 0 9234 * 9235 * buffer_or_desc_type = e_num 0 9236 * MSDU_rel_buffertqm_release_reason = e_num 1 9237 * tqm_rr_rem_cmd_rem 9238 * 9239 * 2) Release of msdu buffer due to Flow is not fetched and 9240 * hence sw_peer_id and tid = 0 9241 * 9242 * buffer_or_desc_type = e_num 0 9243 * MSDU_rel_buffertqm_release_reason = e_num 1 9244 * tqm_rr_rem_cmd_rem 9245 * 9246 * 3) Release of msdu link due to remove_mpdu or acked_mpdu 9247 * command. 9248 * 9249 * buffer_or_desc_type = e_num1 9250 * msdu_link_descriptortqm_release_reason can be:e_num 1 9251 * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 9252 * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged 9253 * 9254 * This field represents the TID from the TX_MSDU_FLOW 9255 * descriptor or TX_MPDU_QUEUE descriptor 9256 * 9257 * rind_id 9258 * For debugging. 9259 * This field is filled in by the SRNG module. 9260 * It help to identify the ring that is being looked 9261 * 9262 * looping_count 9263 * A count value that indicates the number of times the 9264 * producer of entries into the Buffer Manager Ring has looped 9265 * around the ring. 9266 * 9267 * At initialization time, this value is set to 0. On the 9268 * first loop, this value is set to 1. After the max value is 9269 * reached allowed by the number of bits for this field, the 9270 * count value continues with 0 again. 9271 * 9272 * In case SW is the consumer of the ring entries, it can 9273 * use this field to figure out up to where the producer of 9274 * entries has created new entries. This eliminates the need to 9275 * check where the head pointer' of the ring is located once 9276 * the SW starts processing an interrupt indicating that new 9277 * entries have been put into this ring... 9278 * 9279 * Also note that SW if it wants only needs to look at the 9280 * LSB bit of this count value. 9281 */ 9282 9283 /** 9284 * enum hal_wbm_tqm_rel_reason - TQM release reason code 9285 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 9286 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 9287 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 9288 * initiated by sw. 9289 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 9290 * initiated by sw. 9291 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 9292 * mpdus. 9293 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 9294 * fw with fw_reason1. 9295 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 9296 * fw with fw_reason2. 9297 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 9298 * fw with fw_reason3. 9299 */ 9300 enum hal_wbm_tqm_rel_reason { 9301 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 9302 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 9303 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 9304 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 9305 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 9306 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 9307 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 9308 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 9309 }; 9310 9311 struct hal_wbm_buffer_ring { 9312 struct ath11k_buffer_addr buf_addr_info; 9313 }; 9314 9315 enum hal_desc_owner { 9316 HAL_DESC_OWNER_WBM, 9317 HAL_DESC_OWNER_SW, 9318 HAL_DESC_OWNER_TQM, 9319 HAL_DESC_OWNER_RXDMA, 9320 HAL_DESC_OWNER_REO, 9321 HAL_DESC_OWNER_SWITCH, 9322 }; 9323 9324 enum hal_desc_buf_type { 9325 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 9326 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 9327 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 9328 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 9329 HAL_DESC_BUF_TYPE_TX_FLOW, 9330 HAL_DESC_BUF_TYPE_TX_BUFFER, 9331 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 9332 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 9333 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 9334 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 9335 HAL_DESC_BUF_TYPE_RX_BUFFER, 9336 HAL_DESC_BUF_TYPE_IDLE_LINK, 9337 }; 9338 9339 #define HAL_DESC_REO_OWNED 4 9340 #define HAL_DESC_REO_QUEUE_DESC 8 9341 #define HAL_DESC_REO_QUEUE_EXT_DESC 9 9342 #define HAL_DESC_REO_NON_QOS_TID 16 9343 9344 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 9345 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 9346 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 9347 9348 struct hal_desc_header { 9349 uint32_t info0; 9350 } __packed; 9351 9352 struct hal_rx_mpdu_link_ptr { 9353 struct ath11k_buffer_addr addr_info; 9354 } __packed; 9355 9356 struct hal_rx_msdu_details { 9357 struct ath11k_buffer_addr buf_addr_info; 9358 struct rx_msdu_desc rx_msdu_info; 9359 } __packed; 9360 9361 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 9362 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 9363 9364 struct hal_rx_msdu_link { 9365 struct hal_desc_header desc_hdr; 9366 struct ath11k_buffer_addr buf_addr_info; 9367 uint32_t info0; 9368 uint32_t pn[4]; 9369 struct hal_rx_msdu_details msdu_link[6]; 9370 } __packed; 9371 9372 struct hal_rx_reo_queue_ext { 9373 struct hal_desc_header desc_hdr; 9374 uint32_t rsvd; 9375 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 9376 } __packed; 9377 9378 /* hal_rx_reo_queue_ext 9379 * Consumer: REO 9380 * Producer: REO 9381 * 9382 * descriptor_header 9383 * Details about which module owns this struct. 9384 * 9385 * mpdu_link 9386 * Pointer to the next MPDU_link descriptor in the MPDU queue. 9387 */ 9388 9389 enum hal_rx_reo_queue_pn_size { 9390 HAL_RX_REO_QUEUE_PN_SIZE_24, 9391 HAL_RX_REO_QUEUE_PN_SIZE_48, 9392 HAL_RX_REO_QUEUE_PN_SIZE_128, 9393 }; 9394 9395 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 9396 9397 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 9398 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 9399 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 9400 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 9401 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 9402 #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 9403 #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 9404 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 9405 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 9406 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) 9407 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) 9408 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) 9409 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) 9410 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) 9411 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) 9412 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) 9413 9414 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 9415 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 9416 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) 9417 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) 9418 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) 9419 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 9420 9421 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 9422 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 9423 9424 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 9425 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 9426 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) 9427 9428 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 9429 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 9430 9431 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 9432 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 9433 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 9434 9435 struct hal_rx_reo_queue { 9436 struct hal_desc_header desc_hdr; 9437 uint32_t rx_queue_num; 9438 uint32_t info0; 9439 uint32_t info1; 9440 uint32_t pn[4]; 9441 uint32_t last_rx_enqueue_timestamp; 9442 uint32_t last_rx_dequeue_timestamp; 9443 uint32_t next_aging_queue[2]; 9444 uint32_t prev_aging_queue[2]; 9445 uint32_t rx_bitmap[8]; 9446 uint32_t info2; 9447 uint32_t info3; 9448 uint32_t info4; 9449 uint32_t processed_mpdus; 9450 uint32_t processed_msdus; 9451 uint32_t processed_total_bytes; 9452 uint32_t info5; 9453 uint32_t rsvd[3]; 9454 struct hal_rx_reo_queue_ext ext_desc[]; 9455 } __packed; 9456 9457 /* hal_rx_reo_queue 9458 * 9459 * descriptor_header 9460 * Details about which module owns this struct. Note that sub field 9461 * Buffer_type shall be set to receive_reo_queue_descriptor. 9462 * 9463 * receive_queue_number 9464 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 9465 * 9466 * vld 9467 * Valid bit indicating a session is established and the queue descriptor 9468 * is valid. 9469 * associated_link_descriptor_counter 9470 * Indicates which of the 3 link descriptor counters shall be incremented 9471 * or decremented when link descriptors are added or removed from this 9472 * flow queue. 9473 * disable_duplicate_detection 9474 * When set, do not perform any duplicate detection. 9475 * soft_reorder_enable 9476 * When set, REO has been instructed to not perform the actual re-ordering 9477 * of frames for this queue, but just to insert the reorder opcodes. 9478 * ac 9479 * Indicates the access category of the queue descriptor. 9480 * bar 9481 * Indicates if BAR has been received. 9482 * retry 9483 * Retry bit is checked if this bit is set. 9484 * chk_2k_mode 9485 * Indicates what type of operation is expected from Reo when the received 9486 * frame SN falls within the 2K window. 9487 * oor_mode 9488 * Indicates what type of operation is expected when the received frame 9489 * falls within the OOR window. 9490 * ba_window_size 9491 * Indicates the negotiated (window size + 1). Max of 256 bits. 9492 * 9493 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 9494 * session, with window size of 0). The 3 values here are the main values 9495 * validated, but other values should work as well. 9496 * 9497 * A BA window size of 0 (=> one frame entry bitmat), means that there is 9498 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 9499 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 9500 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 9501 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 9502 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 9503 * pn_size 9504 * REO shall perform the PN increment check, even number check, uneven 9505 * number check, PN error check and size of the PN field check. 9506 * ignore_ampdu_flag 9507 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 9508 * 9509 * svld 9510 * Sequence number in next field is valid one. 9511 * ssn 9512 * Starting Sequence number of the session. 9513 * current_index 9514 * Points to last forwarded packet 9515 * seq_2k_error_detected_flag 9516 * REO has detected a 2k error jump in the sequence number and from that 9517 * moment forward, all new frames are forwarded directly to FW, without 9518 * duplicate detect, reordering, etc. 9519 * pn_error_detected_flag 9520 * REO has detected a PN error. 9521 */ 9522 9523 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 9524 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 9525 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 9526 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 9527 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 9528 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 9529 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 9530 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 9531 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 9532 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 9533 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 9534 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 9535 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 9536 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 9537 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 9538 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 9539 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 9540 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 9541 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 9542 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 9543 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 9544 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 9545 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 9546 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 9547 9548 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 9549 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 9550 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 9551 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 9552 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 9553 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 9554 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 9555 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 9556 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 9557 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 9558 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 9559 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 9560 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 9561 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 9562 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 9563 9564 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) 9565 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) 9566 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) 9567 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) 9568 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) 9569 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) 9570 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) 9571 9572 struct hal_reo_update_rx_queue { 9573 struct hal_reo_cmd_hdr cmd; 9574 uint32_t queue_addr_lo; 9575 uint32_t info0; 9576 uint32_t info1; 9577 uint32_t info2; 9578 uint32_t pn[4]; 9579 } __packed; 9580 9581 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 9582 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 9583 9584 struct hal_reo_unblock_cache { 9585 struct hal_reo_cmd_hdr cmd; 9586 uint32_t info0; 9587 uint32_t rsvd[7]; 9588 } __packed; 9589 9590 enum hal_reo_exec_status { 9591 HAL_REO_EXEC_STATUS_SUCCESS, 9592 HAL_REO_EXEC_STATUS_BLOCKED, 9593 HAL_REO_EXEC_STATUS_FAILED, 9594 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 9595 }; 9596 9597 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 9598 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 9599 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 9600 9601 #define HAL_HASH_ROUTING_RING_TCL 0 9602 #define HAL_HASH_ROUTING_RING_SW1 1 9603 #define HAL_HASH_ROUTING_RING_SW2 2 9604 #define HAL_HASH_ROUTING_RING_SW3 3 9605 #define HAL_HASH_ROUTING_RING_SW4 4 9606 #define HAL_HASH_ROUTING_RING_REL 5 9607 #define HAL_HASH_ROUTING_RING_FW 6 9608 9609 struct hal_reo_status_hdr { 9610 uint32_t info0; 9611 uint32_t timestamp; 9612 } __packed; 9613 9614 /* hal_reo_status_hdr 9615 * Producer: REO 9616 * Consumer: SW 9617 * 9618 * status_num 9619 * The value in this field is equal to value of the reo command 9620 * number. This field helps to correlate the statuses with the REO 9621 * commands. 9622 * 9623 * execution_time (in us) 9624 * The amount of time REO took to execute the command. Note that 9625 * this time does not include the duration of the command waiting 9626 * in the command ring, before the execution started. 9627 * 9628 * execution_status 9629 * Execution status of the command. Values are defined in 9630 * enum %HAL_REO_EXEC_STATUS_. 9631 */ 9632 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 9633 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) 9634 9635 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 9636 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 9637 9638 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 9639 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 9640 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 9641 9642 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 9643 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 9644 9645 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 9646 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) 9647 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) 9648 9649 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 9650 9651 struct hal_reo_get_queue_stats_status { 9652 struct hal_reo_status_hdr hdr; 9653 uint32_t info0; 9654 uint32_t pn[4]; 9655 uint32_t last_rx_enqueue_timestamp; 9656 uint32_t last_rx_dequeue_timestamp; 9657 uint32_t rx_bitmap[8]; 9658 uint32_t info1; 9659 uint32_t info2; 9660 uint32_t info3; 9661 uint32_t num_mpdu_frames; 9662 uint32_t num_msdu_frames; 9663 uint32_t total_bytes; 9664 uint32_t info4; 9665 uint32_t info5; 9666 } __packed; 9667 9668 /* hal_reo_get_queue_stats_status 9669 * Producer: REO 9670 * Consumer: SW 9671 * 9672 * status_hdr 9673 * Details that can link this status with the original command. It 9674 * also contains info on how long REO took to execute this command. 9675 * 9676 * ssn 9677 * Starting Sequence number of the session, this changes whenever 9678 * window moves (can be filled by SW then maintained by REO). 9679 * 9680 * current_index 9681 * Points to last forwarded packet. 9682 * 9683 * pn 9684 * Bits of the PN number. 9685 * 9686 * last_rx_enqueue_timestamp 9687 * last_rx_dequeue_timestamp 9688 * Timestamp of arrival of the last MPDU for this queue and 9689 * Timestamp of forwarding an MPDU accordingly. 9690 * 9691 * rx_bitmap 9692 * When a bit is set, the corresponding frame is currently held 9693 * in the re-order queue. The bitmap is Fully managed by HW. 9694 * 9695 * current_mpdu_count 9696 * current_msdu_count 9697 * The number of MPDUs and MSDUs in the queue. 9698 * 9699 * timeout_count 9700 * The number of times REO started forwarding frames even though 9701 * there is a hole in the bitmap. Forwarding reason is timeout. 9702 * 9703 * forward_due_to_bar_count 9704 * The number of times REO started forwarding frames even though 9705 * there is a hole in the bitmap. Fwd reason is reception of BAR. 9706 * 9707 * duplicate_count 9708 * The number of duplicate frames that have been detected. 9709 * 9710 * frames_in_order_count 9711 * The number of frames that have been received in order (without 9712 * a hole that prevented them from being forwarded immediately). 9713 * 9714 * bar_received_count 9715 * The number of times a BAR frame is received. 9716 * 9717 * mpdu_frames_processed_count 9718 * msdu_frames_processed_count 9719 * The total number of MPDU/MSDU frames that have been processed. 9720 * 9721 * total_bytes 9722 * An approximation of the number of bytes received for this queue. 9723 * 9724 * late_receive_mpdu_count 9725 * The number of MPDUs received after the window had already moved 9726 * on. The 'late' sequence window is defined as 9727 * (Window SSN - 256) - (Window SSN - 1). 9728 * 9729 * window_jump_2k 9730 * The number of times the window moved more than 2K 9731 * 9732 * hole_count 9733 * The number of times a hole was created in the receive bitmap. 9734 * 9735 * looping_count 9736 * A count value that indicates the number of times the producer of 9737 * entries into this Ring has looped around the ring. 9738 */ 9739 9740 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 9741 9742 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 9743 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 9744 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 9745 9746 struct hal_reo_flush_queue_status { 9747 struct hal_reo_status_hdr hdr; 9748 uint32_t info0; 9749 uint32_t rsvd0[21]; 9750 uint32_t info1; 9751 } __packed; 9752 9753 /* hal_reo_flush_queue_status 9754 * Producer: REO 9755 * Consumer: SW 9756 * 9757 * status_hdr 9758 * Details that can link this status with the original command. It 9759 * also contains info on how long REO took to execute this command. 9760 * 9761 * error_detected 9762 * Status of blocking resource 9763 * 9764 * 0 - No error has been detected while executing this command 9765 * 1 - Error detected. The resource to be used for blocking was 9766 * already in use. 9767 * 9768 * looping_count 9769 * A count value that indicates the number of times the producer of 9770 * entries into this Ring has looped around the ring. 9771 */ 9772 9773 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 9774 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 9775 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 9776 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 9777 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 9778 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 9779 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 9780 9781 struct hal_reo_flush_cache_status { 9782 struct hal_reo_status_hdr hdr; 9783 uint32_t info0; 9784 uint32_t rsvd0[21]; 9785 uint32_t info1; 9786 } __packed; 9787 9788 /* hal_reo_flush_cache_status 9789 * Producer: REO 9790 * Consumer: SW 9791 * 9792 * status_hdr 9793 * Details that can link this status with the original command. It 9794 * also contains info on how long REO took to execute this command. 9795 * 9796 * error_detected 9797 * Status for blocking resource handling 9798 * 9799 * 0 - No error has been detected while executing this command 9800 * 1 - An error in the blocking resource management was detected 9801 * 9802 * block_error_details 9803 * only valid when error_detected is set 9804 * 9805 * 0 - No blocking related errors found 9806 * 1 - Blocking resource is already in use 9807 * 2 - Resource requested to be unblocked, was not blocked 9808 * 9809 * cache_controller_flush_status_hit 9810 * The status that the cache controller returned on executing the 9811 * flush command. 9812 * 9813 * 0 - miss; 1 - hit 9814 * 9815 * cache_controller_flush_status_desc_type 9816 * Flush descriptor type 9817 * 9818 * cache_controller_flush_status_client_id 9819 * Module who made the flush request 9820 * 9821 * In REO, this is always 0 9822 * 9823 * cache_controller_flush_status_error 9824 * Error condition 9825 * 9826 * 0 - No error found 9827 * 1 - HW interface is still busy 9828 * 2 - Line currently locked. Used for one line flush command 9829 * 3 - At least one line is still locked. 9830 * Used for cache flush command. 9831 * 9832 * cache_controller_flush_count 9833 * The number of lines that were actually flushed out 9834 * 9835 * looping_count 9836 * A count value that indicates the number of times the producer of 9837 * entries into this Ring has looped around the ring. 9838 */ 9839 9840 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 9841 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 9842 9843 struct hal_reo_unblock_cache_status { 9844 struct hal_reo_status_hdr hdr; 9845 uint32_t info0; 9846 uint32_t rsvd0[21]; 9847 uint32_t info1; 9848 } __packed; 9849 9850 /* hal_reo_unblock_cache_status 9851 * Producer: REO 9852 * Consumer: SW 9853 * 9854 * status_hdr 9855 * Details that can link this status with the original command. It 9856 * also contains info on how long REO took to execute this command. 9857 * 9858 * error_detected 9859 * 0 - No error has been detected while executing this command 9860 * 1 - The blocking resource was not in use, and therefore it could 9861 * not be unblocked. 9862 * 9863 * unblock_type 9864 * Reference to the type of unblock command 9865 * 0 - Unblock a blocking resource 9866 * 1 - The entire cache usage is unblock 9867 * 9868 * looping_count 9869 * A count value that indicates the number of times the producer of 9870 * entries into this Ring has looped around the ring. 9871 */ 9872 9873 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 9874 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 9875 9876 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 9877 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 9878 9879 struct hal_reo_flush_timeout_list_status { 9880 struct hal_reo_status_hdr hdr; 9881 uint32_t info0; 9882 uint32_t info1; 9883 uint32_t rsvd0[20]; 9884 uint32_t info2; 9885 } __packed; 9886 9887 /* hal_reo_flush_timeout_list_status 9888 * Producer: REO 9889 * Consumer: SW 9890 * 9891 * status_hdr 9892 * Details that can link this status with the original command. It 9893 * also contains info on how long REO took to execute this command. 9894 * 9895 * error_detected 9896 * 0 - No error has been detected while executing this command 9897 * 1 - Command not properly executed and returned with error 9898 * 9899 * timeout_list_empty 9900 * When set, REO has depleted the timeout list and all entries are 9901 * gone. 9902 * 9903 * release_desc_count 9904 * Producer: SW; Consumer: REO 9905 * The number of link descriptor released 9906 * 9907 * forward_buf_count 9908 * Producer: SW; Consumer: REO 9909 * The number of buffers forwarded to the REO destination rings 9910 * 9911 * looping_count 9912 * A count value that indicates the number of times the producer of 9913 * entries into this Ring has looped around the ring. 9914 */ 9915 9916 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 9917 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 9918 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 9919 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 9920 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) 9921 9922 struct hal_reo_desc_thresh_reached_status { 9923 struct hal_reo_status_hdr hdr; 9924 uint32_t info0; 9925 uint32_t info1; 9926 uint32_t info2; 9927 uint32_t info3; 9928 uint32_t info4; 9929 uint32_t rsvd0[17]; 9930 uint32_t info5; 9931 } __packed; 9932 9933 /* hal_reo_desc_thresh_reached_status 9934 * Producer: REO 9935 * Consumer: SW 9936 * 9937 * status_hdr 9938 * Details that can link this status with the original command. It 9939 * also contains info on how long REO took to execute this command. 9940 * 9941 * threshold_index 9942 * The index of the threshold register whose value got reached 9943 * 9944 * link_descriptor_counter0 9945 * link_descriptor_counter1 9946 * link_descriptor_counter2 9947 * link_descriptor_counter_sum 9948 * Value of the respective counters at generation of this message 9949 * 9950 * looping_count 9951 * A count value that indicates the number of times the producer of 9952 * entries into this Ring has looped around the ring. 9953 */ 9954 9955 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF 9956 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF 9957 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF 9958 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF 9959 9960 #define HAL_TX_ADDRX_EN 1 9961 #define HAL_TX_ADDRY_EN 2 9962 9963 #define HAL_TX_ADDR_SEARCH_DEFAULT 0 9964 #define HAL_TX_ADDR_SEARCH_INDEX 1 9965 9966 /* 9967 * Copy Engine 9968 */ 9969 9970 #define CE_COUNT_MAX 12 9971 9972 /* Byte swap data words */ 9973 #define CE_ATTR_BYTE_SWAP_DATA 2 9974 9975 /* no interrupt on copy completion */ 9976 #define CE_ATTR_DIS_INTR 8 9977 9978 /* Host software's Copy Engine configuration. */ 9979 #ifdef __BIG_ENDIAN 9980 #define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA 9981 #else 9982 #define CE_ATTR_FLAGS 0 9983 #endif 9984 9985 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */ 9986 #define ATH11K_CE_USAGE_THRESHOLD 32 9987 9988 /* 9989 * Directions for interconnect pipe configuration. 9990 * These definitions may be used during configuration and are shared 9991 * between Host and Target. 9992 * 9993 * Pipe Directions are relative to the Host, so PIPEDIR_IN means 9994 * "coming IN over air through Target to Host" as with a WiFi Rx operation. 9995 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" 9996 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" 9997 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target 9998 * over the interconnect. 9999 */ 10000 #define PIPEDIR_NONE 0 10001 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ 10002 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ 10003 #define PIPEDIR_INOUT 3 /* bidirectional */ 10004 #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ 10005 10006 /* CE address/mask */ 10007 #define CE_HOST_IE_ADDRESS 0x00A1803C 10008 #define CE_HOST_IE_2_ADDRESS 0x00A18040 10009 #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS 10010 10011 /* CE IE registers are different for IPQ5018 */ 10012 #define CE_HOST_IPQ5018_IE_ADDRESS 0x0841804C 10013 #define CE_HOST_IPQ5018_IE_2_ADDRESS 0x08418050 10014 #define CE_HOST_IPQ5018_IE_3_ADDRESS CE_HOST_IPQ5018_IE_ADDRESS 10015 10016 #define CE_HOST_IE_3_SHIFT 0xC 10017 10018 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 10019 10020 /* 10021 * Establish a mapping between a service/direction and a pipe. 10022 * Configuration information for a Copy Engine pipe and services. 10023 * Passed from Host to Target through QMI message and must be in 10024 * little endian format. 10025 */ 10026 struct service_to_pipe { 10027 uint32_t service_id; 10028 uint32_t pipedir; 10029 uint32_t pipenum; 10030 }; 10031 10032 /* 10033 * Configuration information for a Copy Engine pipe. 10034 * Passed from Host to Target through QMI message during startup (one per CE). 10035 * 10036 * NOTE: Structure is shared between Host software and Target firmware! 10037 */ 10038 struct ce_pipe_config { 10039 uint32_t pipenum; 10040 uint32_t pipedir; 10041 uint32_t nentries; 10042 uint32_t nbytes_max; 10043 uint32_t flags; 10044 uint32_t reserved; 10045 }; 10046 10047 /* 10048 * HTC 10049 */ 10050 10051 #define HTC_HDR_ENDPOINTID GENMASK(7, 0) 10052 #define HTC_HDR_FLAGS GENMASK(15, 8) 10053 #define HTC_HDR_PAYLOADLEN GENMASK(31, 16) 10054 #define HTC_HDR_CONTROLBYTES0 GENMASK(7, 0) 10055 #define HTC_HDR_CONTROLBYTES1 GENMASK(15, 8) 10056 #define HTC_HDR_RESERVED GENMASK(31, 16) 10057 10058 #define HTC_SVC_MSG_SERVICE_ID GENMASK(31, 16) 10059 #define HTC_SVC_MSG_CONNECTIONFLAGS GENMASK(15, 0) 10060 #define HTC_SVC_MSG_SERVICEMETALENGTH GENMASK(23, 16) 10061 #define HTC_READY_MSG_CREDITCOUNT GENMASK(31, 16) 10062 #define HTC_READY_MSG_CREDITSIZE GENMASK(15, 0) 10063 #define HTC_READY_MSG_MAXENDPOINTS GENMASK(23, 16) 10064 10065 #define HTC_READY_EX_MSG_HTCVERSION GENMASK(7, 0) 10066 #define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE GENMASK(15, 8) 10067 10068 #define HTC_SVC_RESP_MSG_SERVICEID GENMASK(31, 16) 10069 #define HTC_SVC_RESP_MSG_STATUS GENMASK(7, 0) 10070 #define HTC_SVC_RESP_MSG_ENDPOINTID GENMASK(15, 8) 10071 #define HTC_SVC_RESP_MSG_MAXMSGSIZE GENMASK(31, 16) 10072 #define HTC_SVC_RESP_MSG_SERVICEMETALENGTH GENMASK(7, 0) 10073 10074 #define HTC_MSG_MESSAGEID GENMASK(15, 0) 10075 #define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS GENMASK(31, 0) 10076 #define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV GENMASK(7, 0) 10077 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD0 GENMASK(15, 8) 10078 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD1 GENMASK(23, 16) 10079 #define HTC_SETUP_COMPLETE_EX_MSG_RSVD2 GENMASK(31, 24) 10080 10081 enum ath11k_htc_tx_flags { 10082 ATH11K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01, 10083 ATH11K_HTC_FLAG_SEND_BUNDLE = 0x02 10084 }; 10085 10086 enum ath11k_htc_rx_flags { 10087 ATH11K_HTC_FLAG_TRAILER_PRESENT = 0x02, 10088 ATH11K_HTC_FLAG_BUNDLE_MASK = 0xF0 10089 }; 10090 10091 10092 struct ath11k_htc_hdr { 10093 uint32_t htc_info; 10094 uint32_t ctrl_info; 10095 } __packed __aligned(4); 10096 10097 enum ath11k_htc_msg_id { 10098 ATH11K_HTC_MSG_READY_ID = 1, 10099 ATH11K_HTC_MSG_CONNECT_SERVICE_ID = 2, 10100 ATH11K_HTC_MSG_CONNECT_SERVICE_RESP_ID = 3, 10101 ATH11K_HTC_MSG_SETUP_COMPLETE_ID = 4, 10102 ATH11K_HTC_MSG_SETUP_COMPLETE_EX_ID = 5, 10103 ATH11K_HTC_MSG_SEND_SUSPEND_COMPLETE = 6, 10104 ATH11K_HTC_MSG_NACK_SUSPEND = 7, 10105 ATH11K_HTC_MSG_WAKEUP_FROM_SUSPEND_ID = 8, 10106 }; 10107 10108 enum ath11k_htc_version { 10109 ATH11K_HTC_VERSION_2P0 = 0x00, /* 2.0 */ 10110 ATH11K_HTC_VERSION_2P1 = 0x01, /* 2.1 */ 10111 }; 10112 10113 #define ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0) 10114 #define ATH11K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8) 10115 10116 enum ath11k_htc_conn_flags { 10117 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH = 0x0, 10118 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_HALF = 0x1, 10119 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS = 0x2, 10120 ATH11K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_UNITY = 0x3, 10121 ATH11K_HTC_CONN_FLAGS_REDUCE_CREDIT_DRIBBLE = 0x4, 10122 ATH11K_HTC_CONN_FLAGS_DISABLE_CREDIT_FLOW_CTRL = 0x8, 10123 }; 10124 10125 enum ath11k_htc_conn_svc_status { 10126 ATH11K_HTC_CONN_SVC_STATUS_SUCCESS = 0, 10127 ATH11K_HTC_CONN_SVC_STATUS_NOT_FOUND = 1, 10128 ATH11K_HTC_CONN_SVC_STATUS_FAILED = 2, 10129 ATH11K_HTC_CONN_SVC_STATUS_NO_RESOURCES = 3, 10130 ATH11K_HTC_CONN_SVC_STATUS_NO_MORE_EP = 4 10131 }; 10132 10133 struct ath11k_htc_ready { 10134 uint32_t id_credit_count; 10135 uint32_t size_ep; 10136 } __packed; 10137 10138 struct ath11k_htc_ready_extended { 10139 struct ath11k_htc_ready base; 10140 uint32_t ver_bundle; 10141 } __packed; 10142 10143 struct ath11k_htc_conn_svc { 10144 uint32_t msg_svc_id; 10145 uint32_t flags_len; 10146 } __packed; 10147 10148 struct ath11k_htc_conn_svc_resp { 10149 uint32_t msg_svc_id; 10150 uint32_t flags_len; 10151 uint32_t svc_meta_pad; 10152 } __packed; 10153 10154 #define ATH11K_GLOBAL_DISABLE_CREDIT_FLOW BIT(1) 10155 10156 struct ath11k_htc_setup_complete_extended { 10157 uint32_t msg_id; 10158 uint32_t flags; 10159 uint32_t max_msgs_per_bundled_recv; 10160 } __packed; 10161 10162 struct ath11k_htc_msg { 10163 uint32_t msg_svc_id; 10164 uint32_t flags_len; 10165 } __packed __aligned(4); 10166 10167 enum ath11k_htc_record_id { 10168 ATH11K_HTC_RECORD_NULL = 0, 10169 ATH11K_HTC_RECORD_CREDITS = 1 10170 }; 10171 10172 struct ath11k_htc_record_hdr { 10173 uint8_t id; /* @enum ath11k_htc_record_id */ 10174 uint8_t len; 10175 uint8_t pad0; 10176 uint8_t pad1; 10177 } __packed; 10178 10179 struct ath11k_htc_credit_report { 10180 uint8_t eid; /* @enum ath11k_htc_ep_id */ 10181 uint8_t credits; 10182 uint8_t pad0; 10183 uint8_t pad1; 10184 } __packed; 10185 10186 struct ath11k_htc_record { 10187 struct ath11k_htc_record_hdr hdr; 10188 union { 10189 struct ath11k_htc_credit_report credit_report[0]; 10190 uint8_t payload[0]; 10191 }; 10192 } __packed __aligned(4); 10193 10194 /* note: the trailer offset is dynamic depending 10195 * on payload length. this is only a struct layout draft 10196 */ 10197 struct ath11k_htc_frame { 10198 struct ath11k_htc_hdr hdr; 10199 union { 10200 struct ath11k_htc_msg msg; 10201 uint8_t payload[0]; 10202 }; 10203 struct ath11k_htc_record trailer[0]; 10204 } __packed __aligned(4); 10205 10206 enum ath11k_htc_svc_gid { 10207 ATH11K_HTC_SVC_GRP_RSVD = 0, 10208 ATH11K_HTC_SVC_GRP_WMI = 1, 10209 ATH11K_HTC_SVC_GRP_NMI = 2, 10210 ATH11K_HTC_SVC_GRP_HTT = 3, 10211 ATH11K_HTC_SVC_GRP_CFG = 4, 10212 ATH11K_HTC_SVC_GRP_IPA = 5, 10213 ATH11K_HTC_SVC_GRP_PKTLOG = 6, 10214 10215 ATH11K_HTC_SVC_GRP_TEST = 254, 10216 ATH11K_HTC_SVC_GRP_LAST = 255, 10217 }; 10218 10219 #define SVC(group, idx) \ 10220 (int)(((int)(group) << 8) | (int)(idx)) 10221 10222 enum ath11k_htc_svc_id { 10223 /* NOTE: service ID of 0x0000 is reserved and should never be used */ 10224 ATH11K_HTC_SVC_ID_RESERVED = 0x0000, 10225 ATH11K_HTC_SVC_ID_UNUSED = ATH11K_HTC_SVC_ID_RESERVED, 10226 10227 ATH11K_HTC_SVC_ID_RSVD_CTRL = SVC(ATH11K_HTC_SVC_GRP_RSVD, 1), 10228 ATH11K_HTC_SVC_ID_WMI_CONTROL = SVC(ATH11K_HTC_SVC_GRP_WMI, 0), 10229 ATH11K_HTC_SVC_ID_WMI_DATA_BE = SVC(ATH11K_HTC_SVC_GRP_WMI, 1), 10230 ATH11K_HTC_SVC_ID_WMI_DATA_BK = SVC(ATH11K_HTC_SVC_GRP_WMI, 2), 10231 ATH11K_HTC_SVC_ID_WMI_DATA_VI = SVC(ATH11K_HTC_SVC_GRP_WMI, 3), 10232 ATH11K_HTC_SVC_ID_WMI_DATA_VO = SVC(ATH11K_HTC_SVC_GRP_WMI, 4), 10233 ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1 = SVC(ATH11K_HTC_SVC_GRP_WMI, 5), 10234 ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2 = SVC(ATH11K_HTC_SVC_GRP_WMI, 6), 10235 10236 ATH11K_HTC_SVC_ID_NMI_CONTROL = SVC(ATH11K_HTC_SVC_GRP_NMI, 0), 10237 ATH11K_HTC_SVC_ID_NMI_DATA = SVC(ATH11K_HTC_SVC_GRP_NMI, 1), 10238 10239 ATH11K_HTC_SVC_ID_HTT_DATA_MSG = SVC(ATH11K_HTC_SVC_GRP_HTT, 0), 10240 10241 /* raw stream service (i.e. flash, tcmd, calibration apps) */ 10242 ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH11K_HTC_SVC_GRP_TEST, 0), 10243 ATH11K_HTC_SVC_ID_IPA_TX = SVC(ATH11K_HTC_SVC_GRP_IPA, 0), 10244 ATH11K_HTC_SVC_ID_PKT_LOG = SVC(ATH11K_HTC_SVC_GRP_PKTLOG, 0), 10245 }; 10246 10247 #undef SVC 10248 10249 enum ath11k_htc_ep_id { 10250 ATH11K_HTC_EP_UNUSED = -1, 10251 ATH11K_HTC_EP_0 = 0, 10252 ATH11K_HTC_EP_1 = 1, 10253 ATH11K_HTC_EP_2, 10254 ATH11K_HTC_EP_3, 10255 ATH11K_HTC_EP_4, 10256 ATH11K_HTC_EP_5, 10257 ATH11K_HTC_EP_6, 10258 ATH11K_HTC_EP_7, 10259 ATH11K_HTC_EP_8, 10260 ATH11K_HTC_EP_COUNT, 10261 }; 10262 10263 /* 10264 * hw.h 10265 */ 10266 10267 /* Target configuration defines */ 10268 10269 /* Num VDEVS per radio */ 10270 #define TARGET_NUM_VDEVS(sc) (sc->hw_params.num_vdevs) 10271 10272 #define TARGET_NUM_PEERS_PDEV(sc) (sc->hw_params.num_peers + TARGET_NUM_VDEVS(sc)) 10273 10274 /* Num of peers for Single Radio mode */ 10275 #define TARGET_NUM_PEERS_SINGLE(sc) (TARGET_NUM_PEERS_PDEV(sc)) 10276 10277 /* Num of peers for DBS */ 10278 #define TARGET_NUM_PEERS_DBS(sc) (2 * TARGET_NUM_PEERS_PDEV(sc)) 10279 10280 /* Num of peers for DBS_SBS */ 10281 #define TARGET_NUM_PEERS_DBS_SBS(sc) (3 * TARGET_NUM_PEERS_PDEV(sc)) 10282 10283 /* Max num of stations (per radio) */ 10284 #define TARGET_NUM_STATIONS(sc) (sc->hw_params.num_peers) 10285 10286 #define TARGET_NUM_PEERS(sc, x) TARGET_NUM_PEERS_##x(sc) 10287 #define TARGET_NUM_PEER_KEYS 2 10288 #define TARGET_NUM_TIDS(sc, x) (2 * TARGET_NUM_PEERS(sc, x) + \ 10289 4 * TARGET_NUM_VDEVS(sc) + 8) 10290 10291 #define TARGET_AST_SKID_LIMIT 16 10292 #define TARGET_NUM_OFFLD_PEERS 4 10293 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 10294 10295 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 10296 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 10297 #define TARGET_RX_TIMEOUT_LO_PRI 100 10298 #define TARGET_RX_TIMEOUT_HI_PRI 40 10299 10300 #define TARGET_DECAP_MODE_RAW 0 10301 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 10302 #define TARGET_DECAP_MODE_ETH 2 10303 10304 #define TARGET_SCAN_MAX_PENDING_REQS 4 10305 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 10306 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 10307 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 10308 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 10309 #define TARGET_NUM_MCAST_GROUPS 12 10310 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 10311 #define TARGET_MCAST2UCAST_MODE 2 10312 #define TARGET_TX_DBG_LOG_SIZE 1024 10313 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 10314 #define TARGET_VOW_CONFIG 0 10315 #define TARGET_NUM_MSDU_DESC (2500) 10316 #define TARGET_MAX_FRAG_ENTRIES 6 10317 #define TARGET_MAX_BCN_OFFLD 16 10318 #define TARGET_NUM_WDS_ENTRIES 32 10319 #define TARGET_DMA_BURST_SIZE 1 10320 #define TARGET_RX_BATCHMODE 1 10321 #define TARGET_EMA_MAX_PROFILE_PERIOD 8 10322 10323 #define ATH11K_HW_MAX_QUEUES 4 10324 #define ATH11K_QUEUE_LEN 4096 10325 10326 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 10327 10328 enum ath11k_hw_rate_cck { 10329 ATH11K_HW_RATE_CCK_LP_11M = 0, 10330 ATH11K_HW_RATE_CCK_LP_5_5M, 10331 ATH11K_HW_RATE_CCK_LP_2M, 10332 ATH11K_HW_RATE_CCK_LP_1M, 10333 ATH11K_HW_RATE_CCK_SP_11M, 10334 ATH11K_HW_RATE_CCK_SP_5_5M, 10335 ATH11K_HW_RATE_CCK_SP_2M, 10336 }; 10337 10338 enum ath11k_hw_rate_ofdm { 10339 ATH11K_HW_RATE_OFDM_48M = 0, 10340 ATH11K_HW_RATE_OFDM_24M, 10341 ATH11K_HW_RATE_OFDM_12M, 10342 ATH11K_HW_RATE_OFDM_6M, 10343 ATH11K_HW_RATE_OFDM_54M, 10344 ATH11K_HW_RATE_OFDM_36M, 10345 ATH11K_HW_RATE_OFDM_18M, 10346 ATH11K_HW_RATE_OFDM_9M, 10347 }; 10348 10349 enum ath11k_bus { 10350 ATH11K_BUS_AHB, 10351 ATH11K_BUS_PCI, 10352 }; 10353 10354 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11 10355 10356 /* 10357 * rx_desc.h 10358 */ 10359 10360 enum rx_desc_rxpcu_filter { 10361 RX_DESC_RXPCU_FILTER_PASS, 10362 RX_DESC_RXPCU_FILTER_MONITOR_CLIENT, 10363 RX_DESC_RXPCU_FILTER_MONITOR_OTHER, 10364 }; 10365 10366 /* rxpcu_filter_pass 10367 * This MPDU passed the normal frame filter programming of rxpcu. 10368 * 10369 * rxpcu_filter_monitor_client 10370 * This MPDU did not pass the regular frame filter and would 10371 * have been dropped, were it not for the frame fitting into the 10372 * 'monitor_client' category. 10373 * 10374 * rxpcu_filter_monitor_other 10375 * This MPDU did not pass the regular frame filter and also did 10376 * not pass the rxpcu_monitor_client filter. It would have been 10377 * dropped accept that it did pass the 'monitor_other' category. 10378 */ 10379 10380 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 10381 #define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 10382 10383 enum rx_desc_sw_frame_grp_id { 10384 RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME, 10385 RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA, 10386 RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA, 10387 RX_DESC_SW_FRAME_GRP_ID_NULL_DATA, 10388 RX_DESC_SW_FRAME_GRP_ID_MGMT_0000, 10389 RX_DESC_SW_FRAME_GRP_ID_MGMT_0001, 10390 RX_DESC_SW_FRAME_GRP_ID_MGMT_0010, 10391 RX_DESC_SW_FRAME_GRP_ID_MGMT_0011, 10392 RX_DESC_SW_FRAME_GRP_ID_MGMT_0100, 10393 RX_DESC_SW_FRAME_GRP_ID_MGMT_0101, 10394 RX_DESC_SW_FRAME_GRP_ID_MGMT_0110, 10395 RX_DESC_SW_FRAME_GRP_ID_MGMT_0111, 10396 RX_DESC_SW_FRAME_GRP_ID_MGMT_1000, 10397 RX_DESC_SW_FRAME_GRP_ID_MGMT_1001, 10398 RX_DESC_SW_FRAME_GRP_ID_MGMT_1010, 10399 RX_DESC_SW_FRAME_GRP_ID_MGMT_1011, 10400 RX_DESC_SW_FRAME_GRP_ID_MGMT_1100, 10401 RX_DESC_SW_FRAME_GRP_ID_MGMT_1101, 10402 RX_DESC_SW_FRAME_GRP_ID_MGMT_1110, 10403 RX_DESC_SW_FRAME_GRP_ID_MGMT_1111, 10404 RX_DESC_SW_FRAME_GRP_ID_CTRL_0000, 10405 RX_DESC_SW_FRAME_GRP_ID_CTRL_0001, 10406 RX_DESC_SW_FRAME_GRP_ID_CTRL_0010, 10407 RX_DESC_SW_FRAME_GRP_ID_CTRL_0011, 10408 RX_DESC_SW_FRAME_GRP_ID_CTRL_0100, 10409 RX_DESC_SW_FRAME_GRP_ID_CTRL_0101, 10410 RX_DESC_SW_FRAME_GRP_ID_CTRL_0110, 10411 RX_DESC_SW_FRAME_GRP_ID_CTRL_0111, 10412 RX_DESC_SW_FRAME_GRP_ID_CTRL_1000, 10413 RX_DESC_SW_FRAME_GRP_ID_CTRL_1001, 10414 RX_DESC_SW_FRAME_GRP_ID_CTRL_1010, 10415 RX_DESC_SW_FRAME_GRP_ID_CTRL_1011, 10416 RX_DESC_SW_FRAME_GRP_ID_CTRL_1100, 10417 RX_DESC_SW_FRAME_GRP_ID_CTRL_1101, 10418 RX_DESC_SW_FRAME_GRP_ID_CTRL_1110, 10419 RX_DESC_SW_FRAME_GRP_ID_CTRL_1111, 10420 RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED, 10421 RX_DESC_SW_FRAME_GRP_ID_PHY_ERR, 10422 }; 10423 10424 #define DP_MAX_NWIFI_HDR_LEN 30 10425 10426 #define DP_RX_MPDU_ERR_FCS BIT(0) 10427 #define DP_RX_MPDU_ERR_DECRYPT BIT(1) 10428 #define DP_RX_MPDU_ERR_TKIP_MIC BIT(2) 10429 #define DP_RX_MPDU_ERR_AMSDU_ERR BIT(3) 10430 #define DP_RX_MPDU_ERR_OVERFLOW BIT(4) 10431 #define DP_RX_MPDU_ERR_MSDU_LEN BIT(5) 10432 #define DP_RX_MPDU_ERR_MPDU_LEN BIT(6) 10433 #define DP_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7) 10434 10435 enum dp_rx_decap_type { 10436 DP_RX_DECAP_TYPE_RAW, 10437 DP_RX_DECAP_TYPE_NATIVE_WIFI, 10438 DP_RX_DECAP_TYPE_ETHERNET2_DIX, 10439 DP_RX_DECAP_TYPE_8023, 10440 }; 10441 10442 enum rx_desc_decap_type { 10443 RX_DESC_DECAP_TYPE_RAW, 10444 RX_DESC_DECAP_TYPE_NATIVE_WIFI, 10445 RX_DESC_DECAP_TYPE_ETHERNET2_DIX, 10446 RX_DESC_DECAP_TYPE_8023, 10447 }; 10448 10449 enum rx_desc_decrypt_status_code { 10450 RX_DESC_DECRYPT_STATUS_CODE_OK, 10451 RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME, 10452 RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR, 10453 RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID, 10454 RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID, 10455 RX_DESC_DECRYPT_STATUS_CODE_OTHER, 10456 }; 10457 10458 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0) 10459 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1) 10460 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2) 10461 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3) 10462 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4) 10463 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5) 10464 #define RX_ATTENTION_INFO1_NON_QOS BIT(6) 10465 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7) 10466 #define RX_ATTENTION_INFO1_MGMT_TYPE BIT(8) 10467 #define RX_ATTENTION_INFO1_CTRL_TYPE BIT(9) 10468 #define RX_ATTENTION_INFO1_MORE_DATA BIT(10) 10469 #define RX_ATTENTION_INFO1_EOSP BIT(11) 10470 #define RX_ATTENTION_INFO1_A_MSDU_ERROR BIT(12) 10471 #define RX_ATTENTION_INFO1_FRAGMENT BIT(13) 10472 #define RX_ATTENTION_INFO1_ORDER BIT(14) 10473 #define RX_ATTENTION_INFO1_CCE_MATCH BIT(15) 10474 #define RX_ATTENTION_INFO1_OVERFLOW_ERR BIT(16) 10475 #define RX_ATTENTION_INFO1_MSDU_LEN_ERR BIT(17) 10476 #define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL BIT(18) 10477 #define RX_ATTENTION_INFO1_IP_CKSUM_FAIL BIT(19) 10478 #define RX_ATTENTION_INFO1_SA_IDX_INVALID BIT(20) 10479 #define RX_ATTENTION_INFO1_DA_IDX_INVALID BIT(21) 10480 #define RX_ATTENTION_INFO1_RSVD_1B BIT(22) 10481 #define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP BIT(23) 10482 #define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED BIT(24) 10483 #define RX_ATTENTION_INFO1_DIRECTED BIT(25) 10484 #define RX_ATTENTION_INFO1_BUFFER_FRAGMENT BIT(26) 10485 #define RX_ATTENTION_INFO1_MPDU_LEN_ERR BIT(27) 10486 #define RX_ATTENTION_INFO1_TKIP_MIC_ERR BIT(28) 10487 #define RX_ATTENTION_INFO1_DECRYPT_ERR BIT(29) 10488 #define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR BIT(30) 10489 #define RX_ATTENTION_INFO1_FCS_ERR BIT(31) 10490 10491 #define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT BIT(0) 10492 #define RX_ATTENTION_INFO2_FLOW_IDX_INVALID BIT(1) 10493 #define RX_ATTENTION_INFO2_WIFI_PARSER_ERR BIT(2) 10494 #define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR BIT(3) 10495 #define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT BIT(4) 10496 #define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT BIT(5) 10497 #define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR BIT(6) 10498 #define RX_ATTENTION_INFO2_DA_IS_VALID BIT(7) 10499 #define RX_ATTENTION_INFO2_DA_IS_MCBC BIT(8) 10500 #define RX_ATTENTION_INFO2_SA_IS_VALID BIT(9) 10501 #define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE GENMASK(12, 10) 10502 #define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED BIT(13) 10503 #define RX_ATTENTION_INFO2_MSDU_DONE BIT(31) 10504 10505 struct rx_attention { 10506 uint16_t info0; 10507 uint16_t phy_ppdu_id; 10508 uint32_t info1; 10509 uint32_t info2; 10510 } __packed; 10511 10512 /* rx_attention 10513 * 10514 * rxpcu_mpdu_filter_in_category 10515 * Field indicates what the reason was that this mpdu frame 10516 * was allowed to come into the receive path by rxpcu. Values 10517 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 10518 * 10519 * sw_frame_group_id 10520 * SW processes frames based on certain classifications. Values 10521 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 10522 * 10523 * phy_ppdu_id 10524 * A ppdu counter value that PHY increments for every PPDU 10525 * received. The counter value wraps around. 10526 * 10527 * first_mpdu 10528 * Indicates the first MSDU of the PPDU. If both first_mpdu 10529 * and last_mpdu are set in the MSDU then this is a not an 10530 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 10531 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 10532 * 0. The PPDU start status will only be valid when this bit 10533 * is set. 10534 * 10535 * mcast_bcast 10536 * Multicast / broadcast indicator. Only set when the MAC 10537 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 10538 * matches one of the 4 BSSID registers. Only set when 10539 * first_msdu is set. 10540 * 10541 * ast_index_not_found 10542 * Only valid when first_msdu is set. Indicates no AST matching 10543 * entries within the max search count. 10544 * 10545 * ast_index_timeout 10546 * Only valid when first_msdu is set. Indicates an unsuccessful 10547 * search in the address search table due to timeout. 10548 * 10549 * power_mgmt 10550 * Power management bit set in the 802.11 header. Only set 10551 * when first_msdu is set. 10552 * 10553 * non_qos 10554 * Set if packet is not a non-QoS data frame. Only set when 10555 * first_msdu is set. 10556 * 10557 * null_data 10558 * Set if frame type indicates either null data or QoS null 10559 * data format. Only set when first_msdu is set. 10560 * 10561 * mgmt_type 10562 * Set if packet is a management packet. Only set when 10563 * first_msdu is set. 10564 * 10565 * ctrl_type 10566 * Set if packet is a control packet. Only set when first_msdu 10567 * is set. 10568 * 10569 * more_data 10570 * Set if more bit in frame control is set. Only set when 10571 * first_msdu is set. 10572 * 10573 * eosp 10574 * Set if the EOSP (end of service period) bit in the QoS 10575 * control field is set. Only set when first_msdu is set. 10576 * 10577 * a_msdu_error 10578 * Set if number of MSDUs in A-MSDU is above a threshold or if the 10579 * size of the MSDU is invalid. This receive buffer will contain 10580 * all of the remainder of MSDUs in this MPDU w/o decapsulation. 10581 * 10582 * fragment 10583 * Indicates that this is an 802.11 fragment frame. This is 10584 * set when either the more_frag bit is set in the frame 10585 * control or the fragment number is not zero. Only set when 10586 * first_msdu is set. 10587 * 10588 * order 10589 * Set if the order bit in the frame control is set. Only set 10590 * when first_msdu is set. 10591 * 10592 * cce_match 10593 * Indicates that this status has a corresponding MSDU that 10594 * requires FW processing. The OLE will have classification 10595 * ring mask registers which will indicate the ring(s) for 10596 * packets and descriptors which need FW attention. 10597 * 10598 * overflow_err 10599 * PCU Receive FIFO does not have enough space to store the 10600 * full receive packet. Enough space is reserved in the 10601 * receive FIFO for the status is written. This MPDU remaining 10602 * packets in the PPDU will be filtered and no Ack response 10603 * will be transmitted. 10604 * 10605 * msdu_length_err 10606 * Indicates that the MSDU length from the 802.3 encapsulated 10607 * length field extends beyond the MPDU boundary. 10608 * 10609 * tcp_udp_chksum_fail 10610 * Indicates that the computed checksum (tcp_udp_chksum) did 10611 * not match the checksum in the TCP/UDP header. 10612 * 10613 * ip_chksum_fail 10614 * Indicates that the computed checksum did not match the 10615 * checksum in the IP header. 10616 * 10617 * sa_idx_invalid 10618 * Indicates no matching entry was found in the address search 10619 * table for the source MAC address. 10620 * 10621 * da_idx_invalid 10622 * Indicates no matching entry was found in the address search 10623 * table for the destination MAC address. 10624 * 10625 * rx_in_tx_decrypt_byp 10626 * Indicates that RX packet is not decrypted as Crypto is busy 10627 * with TX packet processing. 10628 * 10629 * encrypt_required 10630 * Indicates that this data type frame is not encrypted even if 10631 * the policy for this MPDU requires encryption as indicated in 10632 * the peer table key type. 10633 * 10634 * directed 10635 * MPDU is a directed packet which means that the RA matched 10636 * our STA addresses. In proxySTA it means that the TA matched 10637 * an entry in our address search table with the corresponding 10638 * 'no_ack' bit is the address search entry cleared. 10639 * 10640 * buffer_fragment 10641 * Indicates that at least one of the rx buffers has been 10642 * fragmented. If set the FW should look at the rx_frag_info 10643 * descriptor described below. 10644 * 10645 * mpdu_length_err 10646 * Indicates that the MPDU was pre-maturely terminated 10647 * resulting in a truncated MPDU. Don't trust the MPDU length 10648 * field. 10649 * 10650 * tkip_mic_err 10651 * Indicates that the MPDU Michael integrity check failed 10652 * 10653 * decrypt_err 10654 * Indicates that the MPDU decrypt integrity check failed 10655 * 10656 * fcs_err 10657 * Indicates that the MPDU FCS check failed 10658 * 10659 * flow_idx_timeout 10660 * Indicates an unsuccessful flow search due to the expiring of 10661 * the search timer. 10662 * 10663 * flow_idx_invalid 10664 * flow id is not valid. 10665 * 10666 * amsdu_parser_error 10667 * A-MSDU could not be properly de-agregated. 10668 * 10669 * sa_idx_timeout 10670 * Indicates an unsuccessful search for the source MAC address 10671 * due to the expiring of the search timer. 10672 * 10673 * da_idx_timeout 10674 * Indicates an unsuccessful search for the destination MAC 10675 * address due to the expiring of the search timer. 10676 * 10677 * msdu_limit_error 10678 * Indicates that the MSDU threshold was exceeded and thus 10679 * all the rest of the MSDUs will not be scattered and will not 10680 * be decasulated but will be DMA'ed in RAW format as a single 10681 * MSDU buffer. 10682 * 10683 * da_is_valid 10684 * Indicates that OLE found a valid DA entry. 10685 * 10686 * da_is_mcbc 10687 * Field Only valid if da_is_valid is set. Indicates the DA address 10688 * was a Multicast or Broadcast address. 10689 * 10690 * sa_is_valid 10691 * Indicates that OLE found a valid SA entry. 10692 * 10693 * decrypt_status_code 10694 * Field provides insight into the decryption performed. Values are 10695 * defined in enum %RX_DESC_DECRYPT_STATUS_CODE*. 10696 * 10697 * rx_bitmap_not_updated 10698 * Frame is received, but RXPCU could not update the receive bitmap 10699 * due to (temporary) fifo constraints. 10700 * 10701 * msdu_done 10702 * If set indicates that the RX packet data, RX header data, RX 10703 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 10704 * start/end descriptors and RX Attention descriptor are all 10705 * valid. This bit must be in the last octet of the 10706 * descriptor. 10707 */ 10708 10709 #define RX_MPDU_START_INFO0_NDP_FRAME BIT(9) 10710 #define RX_MPDU_START_INFO0_PHY_ERR BIT(10) 10711 #define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR BIT(11) 10712 #define RX_MPDU_START_INFO0_PROTO_VER_ERR BIT(12) 10713 #define RX_MPDU_START_INFO0_AST_LOOKUP_VALID BIT(13) 10714 10715 #define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID BIT(0) 10716 #define RX_MPDU_START_INFO1_MPDU_DUR_VALID BIT(1) 10717 #define RX_MPDU_START_INFO1_MAC_ADDR1_VALID BIT(2) 10718 #define RX_MPDU_START_INFO1_MAC_ADDR2_VALID BIT(3) 10719 #define RX_MPDU_START_INFO1_MAC_ADDR3_VALID BIT(4) 10720 #define RX_MPDU_START_INFO1_MAC_ADDR4_VALID BIT(5) 10721 #define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID BIT(6) 10722 #define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID BIT(7) 10723 #define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID BIT(8) 10724 #define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID BIT(9) 10725 #define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER GENMASK(13, 10) 10726 #define RX_MPDU_START_INFO1_MORE_FRAG_FLAG BIT(14) 10727 #define RX_MPDU_START_INFO1_FROM_DS BIT(16) 10728 #define RX_MPDU_START_INFO1_TO_DS BIT(17) 10729 #define RX_MPDU_START_INFO1_ENCRYPTED BIT(18) 10730 #define RX_MPDU_START_INFO1_MPDU_RETRY BIT(19) 10731 #define RX_MPDU_START_INFO1_MPDU_SEQ_NUM GENMASK(31, 20) 10732 10733 #define RX_MPDU_START_INFO2_EPD_EN BIT(0) 10734 #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD BIT(1) 10735 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2) 10736 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH GENMASK(7, 6) 10737 #define RX_MPDU_START_INFO2_MESH_STA BIT(8) 10738 #define RX_MPDU_START_INFO2_BSSID_HIT BIT(9) 10739 #define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10) 10740 #define RX_MPDU_START_INFO2_TID GENMASK(17, 14) 10741 #define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15) 10742 10743 #define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0) 10744 #define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ BIT(7) 10745 #define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA BIT(8) 10746 #define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA BIT(9) 10747 #define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR BIT(10) 10748 #define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL GENMASK(12, 11) 10749 #define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL GENMASK(14, 13) 10750 10751 #define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI GENMASK(7, 0) 10752 #define RX_MPDU_START_INFO4_RECV_QUEUE_NUM GENMASK(23, 8) 10753 #define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN BIT(24) 10754 #define RX_MPDU_START_INFO4_FIRST_DELIM_ERR BIT(25) 10755 10756 #define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0) 10757 #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY BIT(8) 10758 #define RX_MPDU_START_INFO5_DECRYPT_NEEDED BIT(9) 10759 #define RX_MPDU_START_INFO5_DECAP_TYPE GENMASK(11, 10) 10760 #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING BIT(12) 10761 #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING BIT(13) 10762 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C BIT(14) 10763 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S BIT(15) 10764 #define RX_MPDU_START_INFO5_PRE_DELIM_COUNT GENMASK(27, 16) 10765 #define RX_MPDU_START_INFO5_AMPDU_FLAG BIT(28) 10766 #define RX_MPDU_START_INFO5_BAR_FRAME BIT(29) 10767 10768 #define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0) 10769 #define RX_MPDU_START_INFO6_FIRST_MPDU BIT(14) 10770 #define RX_MPDU_START_INFO6_MCAST_BCAST BIT(15) 10771 #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND BIT(16) 10772 #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT BIT(17) 10773 #define RX_MPDU_START_INFO6_POWER_MGMT BIT(18) 10774 #define RX_MPDU_START_INFO6_NON_QOS BIT(19) 10775 #define RX_MPDU_START_INFO6_NULL_DATA BIT(20) 10776 #define RX_MPDU_START_INFO6_MGMT_TYPE BIT(21) 10777 #define RX_MPDU_START_INFO6_CTRL_TYPE BIT(22) 10778 #define RX_MPDU_START_INFO6_MORE_DATA BIT(23) 10779 #define RX_MPDU_START_INFO6_EOSP BIT(24) 10780 #define RX_MPDU_START_INFO6_FRAGMENT BIT(25) 10781 #define RX_MPDU_START_INFO6_ORDER BIT(26) 10782 #define RX_MPDU_START_INFO6_UAPSD_TRIGGER BIT(27) 10783 #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED BIT(28) 10784 #define RX_MPDU_START_INFO6_DIRECTED BIT(29) 10785 10786 #define RX_MPDU_START_RAW_MPDU BIT(0) 10787 10788 struct rx_mpdu_start_ipq8074 { 10789 uint16_t info0; 10790 uint16_t phy_ppdu_id; 10791 uint16_t ast_index; 10792 uint16_t sw_peer_id; 10793 uint32_t info1; 10794 uint32_t info2; 10795 uint32_t pn[4]; 10796 uint32_t peer_meta_data; 10797 uint32_t info3; 10798 uint32_t reo_queue_desc_lo; 10799 uint32_t info4; 10800 uint32_t info5; 10801 uint32_t info6; 10802 uint16_t frame_ctrl; 10803 uint16_t duration; 10804 uint8_t addr1[IEEE80211_ADDR_LEN]; 10805 uint8_t addr2[IEEE80211_ADDR_LEN]; 10806 uint8_t addr3[IEEE80211_ADDR_LEN]; 10807 uint16_t seq_ctrl; 10808 uint8_t addr4[IEEE80211_ADDR_LEN]; 10809 uint16_t qos_ctrl; 10810 uint32_t ht_ctrl; 10811 uint32_t raw; 10812 } __packed; 10813 10814 #define RX_MPDU_START_INFO7_REO_DEST_IND GENMASK(4, 0) 10815 #define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB GENMASK(6, 5) 10816 #define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ BIT(7) 10817 #define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA BIT(8) 10818 #define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA BIT(9) 10819 #define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR BIT(10) 10820 #define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL GENMASK(12, 11) 10821 #define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL GENMASK(14, 13) 10822 10823 #define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI GENMASK(7, 0) 10824 #define RX_MPDU_START_INFO8_RECV_QUEUE_NUM GENMASK(23, 8) 10825 #define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN BIT(24) 10826 #define RX_MPDU_START_INFO8_FIRST_DELIM_ERR BIT(25) 10827 10828 #define RX_MPDU_START_INFO9_EPD_EN BIT(0) 10829 #define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD BIT(1) 10830 #define RX_MPDU_START_INFO9_ENC_TYPE GENMASK(5, 2) 10831 #define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH GENMASK(7, 6) 10832 #define RX_MPDU_START_INFO9_MESH_STA GENMASK(9, 8) 10833 #define RX_MPDU_START_INFO9_BSSID_HIT BIT(10) 10834 #define RX_MPDU_START_INFO9_BSSID_NUM GENMASK(14, 11) 10835 #define RX_MPDU_START_INFO9_TID GENMASK(18, 15) 10836 10837 #define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR GENMASK(1, 0) 10838 #define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID GENMASK(8, 2) 10839 #define RX_MPDU_START_INFO10_NDP_FRAME BIT(9) 10840 #define RX_MPDU_START_INFO10_PHY_ERR BIT(10) 10841 #define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR BIT(11) 10842 #define RX_MPDU_START_INFO10_PROTO_VER_ERR BIT(12) 10843 #define RX_MPDU_START_INFO10_AST_LOOKUP_VALID BIT(13) 10844 10845 #define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID BIT(0) 10846 #define RX_MPDU_START_INFO11_MPDU_DUR_VALID BIT(1) 10847 #define RX_MPDU_START_INFO11_MAC_ADDR1_VALID BIT(2) 10848 #define RX_MPDU_START_INFO11_MAC_ADDR2_VALID BIT(3) 10849 #define RX_MPDU_START_INFO11_MAC_ADDR3_VALID BIT(4) 10850 #define RX_MPDU_START_INFO11_MAC_ADDR4_VALID BIT(5) 10851 #define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID BIT(6) 10852 #define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID BIT(7) 10853 #define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID BIT(8) 10854 #define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID BIT(9) 10855 #define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER GENMASK(13, 10) 10856 #define RX_MPDU_START_INFO11_MORE_FRAG_FLAG BIT(14) 10857 #define RX_MPDU_START_INFO11_FROM_DS BIT(16) 10858 #define RX_MPDU_START_INFO11_TO_DS BIT(17) 10859 #define RX_MPDU_START_INFO11_ENCRYPTED BIT(18) 10860 #define RX_MPDU_START_INFO11_MPDU_RETRY BIT(19) 10861 #define RX_MPDU_START_INFO11_MPDU_SEQ_NUM GENMASK(31, 20) 10862 10863 #define RX_MPDU_START_INFO12_KEY_ID GENMASK(7, 0) 10864 #define RX_MPDU_START_INFO12_NEW_PEER_ENTRY BIT(8) 10865 #define RX_MPDU_START_INFO12_DECRYPT_NEEDED BIT(9) 10866 #define RX_MPDU_START_INFO12_DECAP_TYPE GENMASK(11, 10) 10867 #define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING BIT(12) 10868 #define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING BIT(13) 10869 #define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C BIT(14) 10870 #define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S BIT(15) 10871 #define RX_MPDU_START_INFO12_PRE_DELIM_COUNT GENMASK(27, 16) 10872 #define RX_MPDU_START_INFO12_AMPDU_FLAG BIT(28) 10873 #define RX_MPDU_START_INFO12_BAR_FRAME BIT(29) 10874 #define RX_MPDU_START_INFO12_RAW_MPDU BIT(30) 10875 10876 #define RX_MPDU_START_INFO13_MPDU_LEN GENMASK(13, 0) 10877 #define RX_MPDU_START_INFO13_FIRST_MPDU BIT(14) 10878 #define RX_MPDU_START_INFO13_MCAST_BCAST BIT(15) 10879 #define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND BIT(16) 10880 #define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT BIT(17) 10881 #define RX_MPDU_START_INFO13_POWER_MGMT BIT(18) 10882 #define RX_MPDU_START_INFO13_NON_QOS BIT(19) 10883 #define RX_MPDU_START_INFO13_NULL_DATA BIT(20) 10884 #define RX_MPDU_START_INFO13_MGMT_TYPE BIT(21) 10885 #define RX_MPDU_START_INFO13_CTRL_TYPE BIT(22) 10886 #define RX_MPDU_START_INFO13_MORE_DATA BIT(23) 10887 #define RX_MPDU_START_INFO13_EOSP BIT(24) 10888 #define RX_MPDU_START_INFO13_FRAGMENT BIT(25) 10889 #define RX_MPDU_START_INFO13_ORDER BIT(26) 10890 #define RX_MPDU_START_INFO13_UAPSD_TRIGGER BIT(27) 10891 #define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED BIT(28) 10892 #define RX_MPDU_START_INFO13_DIRECTED BIT(29) 10893 #define RX_MPDU_START_INFO13_AMSDU_PRESENT BIT(30) 10894 10895 struct rx_mpdu_start_qcn9074 { 10896 uint32_t info7; 10897 uint32_t reo_queue_desc_lo; 10898 uint32_t info8; 10899 uint32_t pn[4]; 10900 uint32_t info9; 10901 uint32_t peer_meta_data; 10902 uint16_t info10; 10903 uint16_t phy_ppdu_id; 10904 uint16_t ast_index; 10905 uint16_t sw_peer_id; 10906 uint32_t info11; 10907 uint32_t info12; 10908 uint32_t info13; 10909 uint16_t frame_ctrl; 10910 uint16_t duration; 10911 uint8_t addr1[IEEE80211_ADDR_LEN]; 10912 uint8_t addr2[IEEE80211_ADDR_LEN]; 10913 uint8_t addr3[IEEE80211_ADDR_LEN]; 10914 uint16_t seq_ctrl; 10915 uint8_t addr4[IEEE80211_ADDR_LEN]; 10916 uint16_t qos_ctrl; 10917 uint32_t ht_ctrl; 10918 } __packed; 10919 10920 struct rx_mpdu_start_wcn6855 { 10921 uint32_t info3; 10922 uint32_t reo_queue_desc_lo; 10923 uint32_t info4; 10924 uint32_t pn[4]; 10925 uint32_t info2; 10926 uint32_t peer_meta_data; 10927 uint16_t info0; 10928 uint16_t phy_ppdu_id; 10929 uint16_t ast_index; 10930 uint16_t sw_peer_id; 10931 uint32_t info1; 10932 uint32_t info5; 10933 uint32_t info6; 10934 uint16_t frame_ctrl; 10935 uint16_t duration; 10936 uint8_t addr1[IEEE80211_ADDR_LEN]; 10937 uint8_t addr2[IEEE80211_ADDR_LEN]; 10938 uint8_t addr3[IEEE80211_ADDR_LEN]; 10939 uint16_t seq_ctrl; 10940 uint8_t addr4[IEEE80211_ADDR_LEN]; 10941 uint16_t qos_ctrl; 10942 uint32_t ht_ctrl; 10943 } __packed; 10944 10945 /* rx_mpdu_start 10946 * 10947 * rxpcu_mpdu_filter_in_category 10948 * Field indicates what the reason was that this mpdu frame 10949 * was allowed to come into the receive path by rxpcu. Values 10950 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 10951 * Note: for ndp frame, if it was expected because the preceding 10952 * NDPA was filter_pass, the setting rxpcu_filter_pass will be 10953 * used. This setting will also be used for every ndp frame in 10954 * case Promiscuous mode is enabled. 10955 * 10956 * sw_frame_group_id 10957 * SW processes frames based on certain classifications. Values 10958 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 10959 * 10960 * ndp_frame 10961 * Indicates that the received frame was an NDP frame. 10962 * 10963 * phy_err 10964 * Indicates that PHY error was received before MAC received data. 10965 * 10966 * phy_err_during_mpdu_header 10967 * PHY error was received before MAC received the complete MPDU 10968 * header which was needed for proper decoding. 10969 * 10970 * protocol_version_err 10971 * RXPCU detected a version error in the frame control field. 10972 * 10973 * ast_based_lookup_valid 10974 * AST based lookup for this frame has found a valid result. 10975 * 10976 * phy_ppdu_id 10977 * A ppdu counter value that PHY increments for every PPDU 10978 * received. The counter value wraps around. 10979 * 10980 * ast_index 10981 * This field indicates the index of the AST entry corresponding 10982 * to this MPDU. It is provided by the GSE module instantiated in 10983 * RXPCU. A value of 0xFFFF indicates an invalid AST index. 10984 * 10985 * sw_peer_id 10986 * This field indicates a unique peer identifier. It is set equal 10987 * to field 'sw_peer_id' from the AST entry. 10988 * 10989 * mpdu_frame_control_valid, mpdu_duration_valid, mpdu_qos_control_valid, 10990 * mpdu_ht_control_valid, frame_encryption_info_valid 10991 * Indicates that each fields have valid entries. 10992 * 10993 * mac_addr_adx_valid 10994 * Corresponding mac_addr_adx_{lo/hi} has valid entries. 10995 * 10996 * from_ds, to_ds 10997 * Valid only when mpdu_frame_control_valid is set. Indicates that 10998 * frame is received from DS and sent to DS. 10999 * 11000 * encrypted 11001 * Protected bit from the frame control. 11002 * 11003 * mpdu_retry 11004 * Retry bit from frame control. Only valid when first_msdu is set. 11005 * 11006 * mpdu_sequence_number 11007 * The sequence number from the 802.11 header. 11008 * 11009 * epd_en 11010 * If set, use EPD instead of LPD. 11011 * 11012 * all_frames_shall_be_encrypted 11013 * If set, all frames (data only?) shall be encrypted. If not, 11014 * RX CRYPTO shall set an error flag. 11015 * 11016 * encrypt_type 11017 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 11018 * 11019 * mesh_sta 11020 * Indicates a Mesh (11s) STA. 11021 * 11022 * bssid_hit 11023 * BSSID of the incoming frame matched one of the 8 BSSID 11024 * register values. 11025 * 11026 * bssid_number 11027 * This number indicates which one out of the 8 BSSID register 11028 * values matched the incoming frame. 11029 * 11030 * tid 11031 * TID field in the QoS control field 11032 * 11033 * pn 11034 * The PN number. 11035 * 11036 * peer_meta_data 11037 * Meta data that SW has programmed in the Peer table entry 11038 * of the transmitting STA. 11039 * 11040 * rx_reo_queue_desc_addr_lo 11041 * Address (lower 32 bits) of the REO queue descriptor. 11042 * 11043 * rx_reo_queue_desc_addr_hi 11044 * Address (upper 8 bits) of the REO queue descriptor. 11045 * 11046 * receive_queue_number 11047 * Indicates the MPDU queue ID to which this MPDU link 11048 * descriptor belongs. 11049 * 11050 * pre_delim_err_warning 11051 * Indicates that a delimiter FCS error was found in between the 11052 * previous MPDU and this MPDU. Note that this is just a warning, 11053 * and does not mean that this MPDU is corrupted in any way. If 11054 * it is, there will be other errors indicated such as FCS or 11055 * decrypt errors. 11056 * 11057 * first_delim_err 11058 * Indicates that the first delimiter had a FCS failure. 11059 * 11060 * key_id 11061 * The key ID octet from the IV. 11062 * 11063 * new_peer_entry 11064 * Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 11065 * doesn't follow so RX DECRYPTION module either uses old peer 11066 * entry or not decrypt. 11067 * 11068 * decrypt_needed 11069 * When RXPCU sets bit 'ast_index_not_found or ast_index_timeout', 11070 * RXPCU will also ensure that this bit is NOT set. CRYPTO for that 11071 * reason only needs to evaluate this bit and non of the other ones 11072 * 11073 * decap_type 11074 * Used by the OLE during decapsulation. Values are defined in 11075 * enum %MPDU_START_DECAP_TYPE_*. 11076 * 11077 * rx_insert_vlan_c_tag_padding 11078 * rx_insert_vlan_s_tag_padding 11079 * Insert 4 byte of all zeros as VLAN tag or double VLAN tag if 11080 * the rx payload does not have VLAN. 11081 * 11082 * strip_vlan_c_tag_decap 11083 * strip_vlan_s_tag_decap 11084 * Strip VLAN or double VLAN during decapsulation. 11085 * 11086 * pre_delim_count 11087 * The number of delimiters before this MPDU. Note that this 11088 * number is cleared at PPDU start. If this MPDU is the first 11089 * received MPDU in the PPDU and this MPDU gets filtered-in, 11090 * this field will indicate the number of delimiters located 11091 * after the last MPDU in the previous PPDU. 11092 * 11093 * If this MPDU is located after the first received MPDU in 11094 * an PPDU, this field will indicate the number of delimiters 11095 * located between the previous MPDU and this MPDU. 11096 * 11097 * ampdu_flag 11098 * Received frame was part of an A-MPDU. 11099 * 11100 * bar_frame 11101 * Received frame is a BAR frame 11102 * 11103 * mpdu_length 11104 * MPDU length before decapsulation. 11105 * 11106 * first_mpdu..directed 11107 * See definition in RX attention descriptor 11108 * 11109 */ 11110 11111 enum rx_msdu_start_pkt_type { 11112 RX_MSDU_START_PKT_TYPE_11A, 11113 RX_MSDU_START_PKT_TYPE_11B, 11114 RX_MSDU_START_PKT_TYPE_11N, 11115 RX_MSDU_START_PKT_TYPE_11AC, 11116 RX_MSDU_START_PKT_TYPE_11AX, 11117 }; 11118 11119 enum rx_msdu_start_sgi { 11120 RX_MSDU_START_SGI_0_8_US, 11121 RX_MSDU_START_SGI_0_4_US, 11122 RX_MSDU_START_SGI_1_6_US, 11123 RX_MSDU_START_SGI_3_2_US, 11124 }; 11125 11126 enum rx_msdu_start_recv_bw { 11127 RX_MSDU_START_RECV_BW_20MHZ, 11128 RX_MSDU_START_RECV_BW_40MHZ, 11129 RX_MSDU_START_RECV_BW_80MHZ, 11130 RX_MSDU_START_RECV_BW_160MHZ, 11131 }; 11132 11133 enum rx_msdu_start_reception_type { 11134 RX_MSDU_START_RECEPTION_TYPE_SU, 11135 RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO, 11136 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA, 11137 RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 11138 RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO, 11139 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA, 11140 RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, 11141 }; 11142 11143 #define RX_MSDU_START_INFO1_MSDU_LENGTH GENMASK(13, 0) 11144 #define RX_MSDU_START_INFO1_RSVD_1A BIT(14) 11145 #define RX_MSDU_START_INFO1_IPSEC_ESP BIT(15) 11146 #define RX_MSDU_START_INFO1_L3_OFFSET GENMASK(22, 16) 11147 #define RX_MSDU_START_INFO1_IPSEC_AH BIT(23) 11148 #define RX_MSDU_START_INFO1_L4_OFFSET GENMASK(31, 24) 11149 11150 #define RX_MSDU_START_INFO2_MSDU_NUMBER GENMASK(7, 0) 11151 #define RX_MSDU_START_INFO2_DECAP_TYPE GENMASK(9, 8) 11152 #define RX_MSDU_START_INFO2_IPV4 BIT(10) 11153 #define RX_MSDU_START_INFO2_IPV6 BIT(11) 11154 #define RX_MSDU_START_INFO2_TCP BIT(12) 11155 #define RX_MSDU_START_INFO2_UDP BIT(13) 11156 #define RX_MSDU_START_INFO2_IP_FRAG BIT(14) 11157 #define RX_MSDU_START_INFO2_TCP_ONLY_ACK BIT(15) 11158 #define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST BIT(16) 11159 #define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH GENMASK(18, 17) 11160 #define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID BIT(19) 11161 #define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID BIT(20) 11162 #define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID BIT(21) 11163 #define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT BIT(22) 11164 #define RX_MSDU_START_INFO2_LDPC BIT(23) 11165 #define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR GENMASK(31, 24) 11166 #define RX_MSDU_START_INFO2_DECAP_FORMAT GENMASK(9, 8) 11167 11168 #define RX_MSDU_START_INFO3_USER_RSSI GENMASK(7, 0) 11169 #define RX_MSDU_START_INFO3_PKT_TYPE GENMASK(11, 8) 11170 #define RX_MSDU_START_INFO3_STBC BIT(12) 11171 #define RX_MSDU_START_INFO3_SGI GENMASK(14, 13) 11172 #define RX_MSDU_START_INFO3_RATE_MCS GENMASK(18, 15) 11173 #define RX_MSDU_START_INFO3_RECV_BW GENMASK(20, 19) 11174 #define RX_MSDU_START_INFO3_RECEPTION_TYPE GENMASK(23, 21) 11175 #define RX_MSDU_START_INFO3_MIMO_SS_BITMAP GENMASK(31, 24) 11176 11177 struct rx_msdu_start_ipq8074 { 11178 uint16_t info0; 11179 uint16_t phy_ppdu_id; 11180 uint32_t info1; 11181 uint32_t info2; 11182 uint32_t toeplitz_hash; 11183 uint32_t flow_id_toeplitz; 11184 uint32_t info3; 11185 uint32_t ppdu_start_timestamp; 11186 uint32_t phy_meta_data; 11187 } __packed; 11188 11189 struct rx_msdu_start_qcn9074 { 11190 uint16_t info0; 11191 uint16_t phy_ppdu_id; 11192 uint32_t info1; 11193 uint32_t info2; 11194 uint32_t toeplitz_hash; 11195 uint32_t flow_id_toeplitz; 11196 uint32_t info3; 11197 uint32_t ppdu_start_timestamp; 11198 uint32_t phy_meta_data; 11199 uint16_t vlan_ctag_c1; 11200 uint16_t vlan_stag_c1; 11201 } __packed; 11202 11203 struct rx_msdu_start_wcn6855 { 11204 uint16_t info0; 11205 uint16_t phy_ppdu_id; 11206 uint32_t info1; 11207 uint32_t info2; 11208 uint32_t toeplitz_hash; 11209 uint32_t flow_id_toeplitz; 11210 uint32_t info3; 11211 uint32_t ppdu_start_timestamp; 11212 uint32_t phy_meta_data; 11213 uint16_t vlan_ctag_ci; 11214 uint16_t vlan_stag_ci; 11215 } __packed; 11216 11217 /* rx_msdu_start 11218 * 11219 * rxpcu_mpdu_filter_in_category 11220 * Field indicates what the reason was that this mpdu frame 11221 * was allowed to come into the receive path by rxpcu. Values 11222 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11223 * 11224 * sw_frame_group_id 11225 * SW processes frames based on certain classifications. Values 11226 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11227 * 11228 * phy_ppdu_id 11229 * A ppdu counter value that PHY increments for every PPDU 11230 * received. The counter value wraps around. 11231 * 11232 * msdu_length 11233 * MSDU length in bytes after decapsulation. 11234 * 11235 * ipsec_esp 11236 * Set if IPv4/v6 packet is using IPsec ESP. 11237 * 11238 * l3_offset 11239 * Depending upon mode bit, this field either indicates the 11240 * L3 offset in bytes from the start of the RX_HEADER or the IP 11241 * offset in bytes from the start of the packet after 11242 * decapsulation. The latter is only valid if ipv4_proto or 11243 * ipv6_proto is set. 11244 * 11245 * ipsec_ah 11246 * Set if IPv4/v6 packet is using IPsec AH 11247 * 11248 * l4_offset 11249 * Depending upon mode bit, this field either indicates the 11250 * L4 offset in bytes from the start of RX_HEADER (only valid 11251 * if either ipv4_proto or ipv6_proto is set to 1) or indicates 11252 * the offset in bytes to the start of TCP or UDP header from 11253 * the start of the IP header after decapsulation (Only valid if 11254 * tcp_proto or udp_proto is set). The value 0 indicates that 11255 * the offset is longer than 127 bytes. 11256 * 11257 * msdu_number 11258 * Indicates the MSDU number within a MPDU. This value is 11259 * reset to zero at the start of each MPDU. If the number of 11260 * MSDU exceeds 255 this number will wrap using modulo 256. 11261 * 11262 * decap_type 11263 * Indicates the format after decapsulation. Values are defined in 11264 * enum %MPDU_START_DECAP_TYPE_*. 11265 * 11266 * ipv4_proto 11267 * Set if L2 layer indicates IPv4 protocol. 11268 * 11269 * ipv6_proto 11270 * Set if L2 layer indicates IPv6 protocol. 11271 * 11272 * tcp_proto 11273 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 11274 * indicates TCP. 11275 * 11276 * udp_proto 11277 * Set if the ipv4_proto or ipv6_proto are set and the IP protocol 11278 * indicates UDP. 11279 * 11280 * ip_frag 11281 * Indicates that either the IP More frag bit is set or IP frag 11282 * number is non-zero. If set indicates that this is a fragmented 11283 * IP packet. 11284 * 11285 * tcp_only_ack 11286 * Set if only the TCP Ack bit is set in the TCP flags and if 11287 * the TCP payload is 0. 11288 * 11289 * da_is_bcast_mcast 11290 * The destination address is broadcast or multicast. 11291 * 11292 * toeplitz_hash 11293 * Actual chosen Hash. 11294 * 0 - Toeplitz hash of 2-tuple (IP source address, IP 11295 * destination address) 11296 * 1 - Toeplitz hash of 4-tuple (IP source address, 11297 * IP destination address, L4 (TCP/UDP) source port, 11298 * L4 (TCP/UDP) destination port) 11299 * 2 - Toeplitz of flow_id 11300 * 3 - Zero is used 11301 * 11302 * ip_fixed_header_valid 11303 * Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed 11304 * fully within first 256 bytes of the packet 11305 * 11306 * ip_extn_header_valid 11307 * IPv6/IPv6 header, including IPv4 options and 11308 * recognizable extension headers parsed fully within first 256 11309 * bytes of the packet 11310 * 11311 * tcp_udp_header_valid 11312 * Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP 11313 * header parsed fully within first 256 bytes of the packet 11314 * 11315 * mesh_control_present 11316 * When set, this MSDU includes the 'Mesh Control' field 11317 * 11318 * ldpc 11319 * 11320 * ip4_protocol_ip6_next_header 11321 * For IPv4, this is the 8 bit protocol field set). For IPv6 this 11322 * is the 8 bit next_header field. 11323 * 11324 * toeplitz_hash_2_or_4 11325 * Controlled by RxOLE register - If register bit set to 0, 11326 * Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest 11327 * addresses; otherwise, toeplitz hash is computed over 4-tuple 11328 * IPv4 or IPv6 src/dest addresses and src/dest ports. 11329 * 11330 * flow_id_toeplitz 11331 * Toeplitz hash of 5-tuple 11332 * {IP source address, IP destination address, IP source port, IP 11333 * destination port, L4 protocol} in case of non-IPSec. 11334 * 11335 * In case of IPSec - Toeplitz hash of 4-tuple 11336 * {IP source address, IP destination address, SPI, L4 protocol} 11337 * 11338 * The relevant Toeplitz key registers are provided in RxOLE's 11339 * instance of common parser module. These registers are separate 11340 * from the Toeplitz keys used by ASE/FSE modules inside RxOLE. 11341 * The actual value will be passed on from common parser module 11342 * to RxOLE in one of the WHO_* TLVs. 11343 * 11344 * user_rssi 11345 * RSSI for this user 11346 * 11347 * pkt_type 11348 * Values are defined in enum %RX_MSDU_START_PKT_TYPE_*. 11349 * 11350 * stbc 11351 * When set, use STBC transmission rates. 11352 * 11353 * sgi 11354 * Field only valid when pkt type is HT, VHT or HE. Values are 11355 * defined in enum %RX_MSDU_START_SGI_*. 11356 * 11357 * rate_mcs 11358 * MCS Rate used. 11359 * 11360 * receive_bandwidth 11361 * Full receive Bandwidth. Values are defined in enum 11362 * %RX_MSDU_START_RECV_*. 11363 * 11364 * reception_type 11365 * Indicates what type of reception this is and defined in enum 11366 * %RX_MSDU_START_RECEPTION_TYPE_*. 11367 * 11368 * mimo_ss_bitmap 11369 * Field only valid when 11370 * Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or 11371 * RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO. 11372 * 11373 * Bitmap, with each bit indicating if the related spatial 11374 * stream is used for this STA 11375 * 11376 * LSB related to SS 0 11377 * 11378 * 0 - spatial stream not used for this reception 11379 * 1 - spatial stream used for this reception 11380 * 11381 * ppdu_start_timestamp 11382 * Timestamp that indicates when the PPDU that contained this MPDU 11383 * started on the medium. 11384 * 11385 * phy_meta_data 11386 * SW programmed Meta data provided by the PHY. Can be used for SW 11387 * to indicate the channel the device is on. 11388 */ 11389 11390 #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) 11391 #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) 11392 11393 #define RX_MSDU_END_INFO1_KEY_ID GENMASK(7, 0) 11394 #define RX_MSDU_END_INFO1_CCE_SUPER_RULE GENMASK(13, 8) 11395 #define RX_MSDU_END_INFO1_CCND_TRUNCATE BIT(14) 11396 #define RX_MSDU_END_INFO1_CCND_CCE_DIS BIT(15) 11397 #define RX_MSDU_END_INFO1_EXT_WAPI_PN GENMASK(31, 16) 11398 11399 #define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0) 11400 #define RX_MSDU_END_INFO2_FIRST_MSDU BIT(14) 11401 #define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855 BIT(28) 11402 #define RX_MSDU_END_INFO2_LAST_MSDU BIT(15) 11403 #define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855 BIT(29) 11404 #define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT BIT(16) 11405 #define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT BIT(17) 11406 #define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR BIT(18) 11407 #define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT BIT(19) 11408 #define RX_MSDU_END_INFO2_FLOW_IDX_INVALID BIT(20) 11409 #define RX_MSDU_END_INFO2_WIFI_PARSER_ERR BIT(21) 11410 #define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR BIT(22) 11411 #define RX_MSDU_END_INFO2_SA_IS_VALID BIT(23) 11412 #define RX_MSDU_END_INFO2_DA_IS_VALID BIT(24) 11413 #define RX_MSDU_END_INFO2_DA_IS_MCBC BIT(25) 11414 #define RX_MSDU_END_INFO2_L3_HDR_PADDING GENMASK(27, 26) 11415 11416 #define RX_MSDU_END_INFO3_TCP_FLAG GENMASK(8, 0) 11417 #define RX_MSDU_END_INFO3_LRO_ELIGIBLE BIT(9) 11418 11419 #define RX_MSDU_END_INFO4_DA_OFFSET GENMASK(5, 0) 11420 #define RX_MSDU_END_INFO4_SA_OFFSET GENMASK(11, 6) 11421 #define RX_MSDU_END_INFO4_DA_OFFSET_VALID BIT(12) 11422 #define RX_MSDU_END_INFO4_SA_OFFSET_VALID BIT(13) 11423 #define RX_MSDU_END_INFO4_L3_TYPE GENMASK(31, 16) 11424 11425 #define RX_MSDU_END_INFO5_MSDU_DROP BIT(0) 11426 #define RX_MSDU_END_INFO5_REO_DEST_IND GENMASK(5, 1) 11427 #define RX_MSDU_END_INFO5_FLOW_IDX GENMASK(25, 6) 11428 11429 struct rx_msdu_end_ipq8074 { 11430 uint16_t info0; 11431 uint16_t phy_ppdu_id; 11432 uint16_t ip_hdr_cksum; 11433 uint16_t tcp_udp_cksum; 11434 uint32_t info1; 11435 uint32_t ext_wapi_pn[2]; 11436 uint32_t info2; 11437 uint32_t ipv6_options_crc; 11438 uint32_t tcp_seq_num; 11439 uint32_t tcp_ack_num; 11440 uint16_t info3; 11441 uint16_t window_size; 11442 uint32_t info4; 11443 uint32_t rule_indication[2]; 11444 uint16_t sa_idx; 11445 uint16_t da_idx; 11446 uint32_t info5; 11447 uint32_t fse_metadata; 11448 uint16_t cce_metadata; 11449 uint16_t sa_sw_peer_id; 11450 } __packed; 11451 11452 struct rx_msdu_end_wcn6855 { 11453 uint16_t info0; 11454 uint16_t phy_ppdu_id; 11455 uint16_t ip_hdr_cksum; 11456 uint16_t reported_mpdu_len; 11457 uint32_t info1; 11458 uint32_t ext_wapi_pn[2]; 11459 uint32_t info4; 11460 uint32_t ipv6_options_crc; 11461 uint32_t tcp_seq_num; 11462 uint32_t tcp_ack_num; 11463 uint16_t info3; 11464 uint16_t window_size; 11465 uint32_t info2; 11466 uint16_t sa_idx; 11467 uint16_t da_idx; 11468 uint32_t info5; 11469 uint32_t fse_metadata; 11470 uint16_t cce_metadata; 11471 uint16_t sa_sw_peer_id; 11472 uint32_t rule_indication[2]; 11473 uint32_t info6; 11474 uint32_t info7; 11475 } __packed; 11476 11477 #define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0) 11478 11479 #define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0) 11480 #define RX_MSDU_END_INFO2_SA_OFFSET GENMASK(11, 6) 11481 #define RX_MSDU_END_INFO2_DA_OFFSET_VALID BIT(12) 11482 #define RX_MSDU_END_INFO2_SA_OFFSET_VALID BIT(13) 11483 #define RX_MSDU_END_INFO2_L3_TYPE GENMASK(31, 16) 11484 11485 #define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT BIT(0) 11486 #define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT BIT(1) 11487 #define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR BIT(2) 11488 #define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT BIT(3) 11489 #define RX_MSDU_END_INFO4_FLOW_IDX_INVALID BIT(4) 11490 #define RX_MSDU_END_INFO4_WIFI_PARSER_ERR BIT(5) 11491 #define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR BIT(6) 11492 #define RX_MSDU_END_INFO4_SA_IS_VALID BIT(7) 11493 #define RX_MSDU_END_INFO4_DA_IS_VALID BIT(8) 11494 #define RX_MSDU_END_INFO4_DA_IS_MCBC BIT(9) 11495 #define RX_MSDU_END_INFO4_L3_HDR_PADDING GENMASK(11, 10) 11496 #define RX_MSDU_END_INFO4_FIRST_MSDU BIT(12) 11497 #define RX_MSDU_END_INFO4_LAST_MSDU BIT(13) 11498 11499 #define RX_MSDU_END_INFO6_AGGR_COUNT GENMASK(7, 0) 11500 #define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN BIT(8) 11501 #define RX_MSDU_END_INFO6_FISA_TIMEOUT BIT(9) 11502 11503 struct rx_msdu_end_qcn9074 { 11504 uint16_t info0; 11505 uint16_t phy_ppdu_id; 11506 uint16_t ip_hdr_cksum; 11507 uint16_t mpdu_length_info; 11508 uint32_t info1; 11509 uint32_t rule_indication[2]; 11510 uint32_t info2; 11511 uint32_t ipv6_options_crc; 11512 uint32_t tcp_seq_num; 11513 uint32_t tcp_ack_num; 11514 uint16_t info3; 11515 uint16_t window_size; 11516 uint16_t tcp_udp_cksum; 11517 uint16_t info4; 11518 uint16_t sa_idx; 11519 uint16_t da_idx; 11520 uint32_t info5; 11521 uint32_t fse_metadata; 11522 uint16_t cce_metadata; 11523 uint16_t sa_sw_peer_id; 11524 uint32_t info6; 11525 uint16_t cum_l4_cksum; 11526 uint16_t cum_ip_length; 11527 } __packed; 11528 11529 /* rx_msdu_end 11530 * 11531 * rxpcu_mpdu_filter_in_category 11532 * Field indicates what the reason was that this mpdu frame 11533 * was allowed to come into the receive path by rxpcu. Values 11534 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11535 * 11536 * sw_frame_group_id 11537 * SW processes frames based on certain classifications. Values 11538 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11539 * 11540 * phy_ppdu_id 11541 * A ppdu counter value that PHY increments for every PPDU 11542 * received. The counter value wraps around. 11543 * 11544 * ip_hdr_cksum 11545 * This can include the IP header checksum or the pseudo 11546 * header checksum used by TCP/UDP checksum. 11547 * 11548 * tcp_udp_chksum 11549 * The value of the computed TCP/UDP checksum. A mode bit 11550 * selects whether this checksum is the full checksum or the 11551 * partial checksum which does not include the pseudo header. 11552 * 11553 * key_id 11554 * The key ID octet from the IV. Only valid when first_msdu is set. 11555 * 11556 * cce_super_rule 11557 * Indicates the super filter rule. 11558 * 11559 * cce_classify_not_done_truncate 11560 * Classification failed due to truncated frame. 11561 * 11562 * cce_classify_not_done_cce_dis 11563 * Classification failed due to CCE global disable 11564 * 11565 * ext_wapi_pn* 11566 * Extension PN (packet number) which is only used by WAPI. 11567 * 11568 * reported_mpdu_length 11569 * MPDU length before decapsulation. Only valid when first_msdu is 11570 * set. This field is taken directly from the length field of the 11571 * A-MPDU delimiter or the preamble length field for non-A-MPDU 11572 * frames. 11573 * 11574 * first_msdu 11575 * Indicates the first MSDU of A-MSDU. If both first_msdu and 11576 * last_msdu are set in the MSDU then this is a non-aggregated MSDU 11577 * frame: normal MPDU. Interior MSDU in an A-MSDU shall have both 11578 * first_mpdu and last_mpdu bits set to 0. 11579 * 11580 * last_msdu 11581 * Indicates the last MSDU of the A-MSDU. MPDU end status is only 11582 * valid when last_msdu is set. 11583 * 11584 * sa_idx_timeout 11585 * Indicates an unsuccessful MAC source address search due to the 11586 * expiring of the search timer. 11587 * 11588 * da_idx_timeout 11589 * Indicates an unsuccessful MAC destination address search due to 11590 * the expiring of the search timer. 11591 * 11592 * msdu_limit_error 11593 * Indicates that the MSDU threshold was exceeded and thus all the 11594 * rest of the MSDUs will not be scattered and will not be 11595 * decapsulated but will be DMA'ed in RAW format as a single MSDU. 11596 * 11597 * flow_idx_timeout 11598 * Indicates an unsuccessful flow search due to the expiring of 11599 * the search timer. 11600 * 11601 * flow_idx_invalid 11602 * flow id is not valid. 11603 * 11604 * amsdu_parser_error 11605 * A-MSDU could not be properly de-agregated. 11606 * 11607 * sa_is_valid 11608 * Indicates that OLE found a valid SA entry. 11609 * 11610 * da_is_valid 11611 * Indicates that OLE found a valid DA entry. 11612 * 11613 * da_is_mcbc 11614 * Field Only valid if da_is_valid is set. Indicates the DA address 11615 * was a Multicast of Broadcast address. 11616 * 11617 * l3_header_padding 11618 * Number of bytes padded to make sure that the L3 header will 11619 * always start of a Dword boundary. 11620 * 11621 * ipv6_options_crc 11622 * 32 bit CRC computed out of IP v6 extension headers. 11623 * 11624 * tcp_seq_number 11625 * TCP sequence number. 11626 * 11627 * tcp_ack_number 11628 * TCP acknowledge number. 11629 * 11630 * tcp_flag 11631 * TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}. 11632 * 11633 * lro_eligible 11634 * Computed out of TCP and IP fields to indicate that this 11635 * MSDU is eligible for LRO. 11636 * 11637 * window_size 11638 * TCP receive window size. 11639 * 11640 * da_offset 11641 * Offset into MSDU buffer for DA. 11642 * 11643 * sa_offset 11644 * Offset into MSDU buffer for SA. 11645 * 11646 * da_offset_valid 11647 * da_offset field is valid. This will be set to 0 in case 11648 * of a dynamic A-MSDU when DA is compressed. 11649 * 11650 * sa_offset_valid 11651 * sa_offset field is valid. This will be set to 0 in case 11652 * of a dynamic A-MSDU when SA is compressed. 11653 * 11654 * l3_type 11655 * The 16-bit type value indicating the type of L3 later 11656 * extracted from LLC/SNAP, set to zero if SNAP is not 11657 * available. 11658 * 11659 * rule_indication 11660 * Bitmap indicating which of rules have matched. 11661 * 11662 * sa_idx 11663 * The offset in the address table which matches MAC source address 11664 * 11665 * da_idx 11666 * The offset in the address table which matches MAC destination 11667 * address. 11668 * 11669 * msdu_drop 11670 * REO shall drop this MSDU and not forward it to any other ring. 11671 * 11672 * reo_destination_indication 11673 * The id of the reo exit ring where the msdu frame shall push 11674 * after (MPDU level) reordering has finished. Values are defined 11675 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 11676 * 11677 * flow_idx 11678 * Flow table index. 11679 * 11680 * fse_metadata 11681 * FSE related meta data. 11682 * 11683 * cce_metadata 11684 * CCE related meta data. 11685 * 11686 * sa_sw_peer_id 11687 * sw_peer_id from the address search entry corresponding to the 11688 * source address of the MSDU. 11689 */ 11690 11691 enum rx_mpdu_end_rxdma_dest_ring { 11692 RX_MPDU_END_RXDMA_DEST_RING_RELEASE, 11693 RX_MPDU_END_RXDMA_DEST_RING_FW, 11694 RX_MPDU_END_RXDMA_DEST_RING_SW, 11695 RX_MPDU_END_RXDMA_DEST_RING_REO, 11696 }; 11697 11698 #define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME BIT(11) 11699 #define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT BIT(12) 11700 #define RX_MPDU_END_INFO1_OVERFLOW_ERR BIT(13) 11701 #define RX_MPDU_END_INFO1_MPDU_LEN_ERR BIT(14) 11702 #define RX_MPDU_END_INFO1_TKIP_MIC_ERR BIT(15) 11703 #define RX_MPDU_END_INFO1_DECRYPT_ERR BIT(16) 11704 #define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR BIT(17) 11705 #define RX_MPDU_END_INFO1_PN_FIELDS_VALID BIT(18) 11706 #define RX_MPDU_END_INFO1_FCS_ERR BIT(19) 11707 #define RX_MPDU_END_INFO1_MSDU_LEN_ERR BIT(20) 11708 #define RX_MPDU_END_INFO1_RXDMA0_DEST_RING GENMASK(22, 21) 11709 #define RX_MPDU_END_INFO1_RXDMA1_DEST_RING GENMASK(24, 23) 11710 #define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE GENMASK(27, 25) 11711 #define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD BIT(28) 11712 11713 struct rx_mpdu_end { 11714 uint16_t info0; 11715 uint16_t phy_ppdu_id; 11716 uint32_t info1; 11717 } __packed; 11718 11719 /* rx_mpdu_end 11720 * 11721 * rxpcu_mpdu_filter_in_category 11722 * Field indicates what the reason was that this mpdu frame 11723 * was allowed to come into the receive path by rxpcu. Values 11724 * are defined in enum %RX_DESC_RXPCU_FILTER_*. 11725 * 11726 * sw_frame_group_id 11727 * SW processes frames based on certain classifications. Values 11728 * are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*. 11729 * 11730 * phy_ppdu_id 11731 * A ppdu counter value that PHY increments for every PPDU 11732 * received. The counter value wraps around. 11733 * 11734 * unsup_ktype_short_frame 11735 * This bit will be '1' when WEP or TKIP or WAPI key type is 11736 * received for 11ah short frame. Crypto will bypass the received 11737 * packet without decryption to RxOLE after setting this bit. 11738 * 11739 * rx_in_tx_decrypt_byp 11740 * Indicates that RX packet is not decrypted as Crypto is 11741 * busy with TX packet processing. 11742 * 11743 * overflow_err 11744 * RXPCU Receive FIFO ran out of space to receive the full MPDU. 11745 * Therefore this MPDU is terminated early and is thus corrupted. 11746 * 11747 * This MPDU will not be ACKed. 11748 * 11749 * RXPCU might still be able to correctly receive the following 11750 * MPDUs in the PPDU if enough fifo space became available in time. 11751 * 11752 * mpdu_length_err 11753 * Set by RXPCU if the expected MPDU length does not correspond 11754 * with the actually received number of bytes in the MPDU. 11755 * 11756 * tkip_mic_err 11757 * Set by Rx crypto when crypto detected a TKIP MIC error for 11758 * this MPDU. 11759 * 11760 * decrypt_err 11761 * Set by RX CRYPTO when CRYPTO detected a decrypt error for this 11762 * MPDU or CRYPTO received an encrypted frame, but did not get a 11763 * valid corresponding key id in the peer entry. 11764 * 11765 * unencrypted_frame_err 11766 * Set by RX CRYPTO when CRYPTO detected an unencrypted frame while 11767 * in the peer entry field 'All_frames_shall_be_encrypted' is set. 11768 * 11769 * pn_fields_contain_valid_info 11770 * Set by RX CRYPTO to indicate that there is a valid PN field 11771 * present in this MPDU. 11772 * 11773 * fcs_err 11774 * Set by RXPCU when there is an FCS error detected for this MPDU. 11775 * 11776 * msdu_length_err 11777 * Set by RXOLE when there is an msdu length error detected 11778 * in at least 1 of the MSDUs embedded within the MPDU. 11779 * 11780 * rxdma0_destination_ring 11781 * rxdma1_destination_ring 11782 * The ring to which RXDMA0/1 shall push the frame, assuming 11783 * no MPDU level errors are detected. In case of MPDU level 11784 * errors, RXDMA0/1 might change the RXDMA0/1 destination. Values 11785 * are defined in %enum RX_MPDU_END_RXDMA_DEST_RING_*. 11786 * 11787 * decrypt_status_code 11788 * Field provides insight into the decryption performed. Values 11789 * are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*. 11790 * 11791 * rx_bitmap_not_updated 11792 * Frame is received, but RXPCU could not update the receive bitmap 11793 * due to (temporary) fifo constraints. 11794 */ 11795 11796 /* Padding bytes to avoid TLV's spanning across 128 byte boundary */ 11797 #define HAL_RX_DESC_PADDING0_BYTES 4 11798 #define HAL_RX_DESC_PADDING1_BYTES 16 11799 11800 #define HAL_RX_DESC_HDR_STATUS_LEN 120 11801 11802 struct hal_rx_desc_ipq8074 { 11803 uint32_t msdu_end_tag; 11804 struct rx_msdu_end_ipq8074 msdu_end; 11805 uint32_t rx_attn_tag; 11806 struct rx_attention attention; 11807 uint32_t msdu_start_tag; 11808 struct rx_msdu_start_ipq8074 msdu_start; 11809 uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES]; 11810 uint32_t mpdu_start_tag; 11811 struct rx_mpdu_start_ipq8074 mpdu_start; 11812 uint32_t mpdu_end_tag; 11813 struct rx_mpdu_end mpdu_end; 11814 uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES]; 11815 uint32_t hdr_status_tag; 11816 uint32_t phy_ppdu_id; 11817 uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN]; 11818 uint8_t msdu_payload[]; 11819 } __packed; 11820 11821 struct hal_rx_desc_qcn9074 { 11822 uint32_t msdu_end_tag; 11823 struct rx_msdu_end_qcn9074 msdu_end; 11824 uint32_t rx_attn_tag; 11825 struct rx_attention attention; 11826 uint32_t msdu_start_tag; 11827 struct rx_msdu_start_qcn9074 msdu_start; 11828 uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES]; 11829 uint32_t mpdu_start_tag; 11830 struct rx_mpdu_start_qcn9074 mpdu_start; 11831 uint32_t mpdu_end_tag; 11832 struct rx_mpdu_end mpdu_end; 11833 uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES]; 11834 uint32_t hdr_status_tag; 11835 uint32_t phy_ppdu_id; 11836 uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN]; 11837 uint8_t msdu_payload[]; 11838 } __packed; 11839 11840 struct hal_rx_desc_wcn6855 { 11841 uint32_t msdu_end_tag; 11842 struct rx_msdu_end_wcn6855 msdu_end; 11843 uint32_t rx_attn_tag; 11844 struct rx_attention attention; 11845 uint32_t msdu_start_tag; 11846 struct rx_msdu_start_wcn6855 msdu_start; 11847 uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES]; 11848 uint32_t mpdu_start_tag; 11849 struct rx_mpdu_start_wcn6855 mpdu_start; 11850 uint32_t mpdu_end_tag; 11851 struct rx_mpdu_end mpdu_end; 11852 uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES]; 11853 uint32_t hdr_status_tag; 11854 uint32_t phy_ppdu_id; 11855 uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN]; 11856 uint8_t msdu_payload[]; 11857 } __packed; 11858 11859 struct hal_rx_desc { 11860 union { 11861 struct hal_rx_desc_ipq8074 ipq8074; 11862 struct hal_rx_desc_qcn9074 qcn9074; 11863 struct hal_rx_desc_wcn6855 wcn6855; 11864 } u; 11865 } __packed; 11866 11867 #define HAL_RX_RU_ALLOC_TYPE_MAX 6 11868 #define RU_26 1 11869 #define RU_52 2 11870 #define RU_106 4 11871 #define RU_242 9 11872 #define RU_484 18 11873 #define RU_996 37 11874 11875 /* 11876 * dp.h 11877 */ 11878 11879 /* HTT definitions */ 11880 11881 #define HTT_TCL_META_DATA_TYPE BIT(0) 11882 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 11883 11884 /* vdev meta data */ 11885 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 11886 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 11887 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 11888 11889 /* peer meta data */ 11890 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 11891 11892 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 11893 11894 #define HTT_INVALID_PEER_ID 0xffff 11895 11896 /* HTT tx completion is overlaid in wbm_release_ring */ 11897 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 11898 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 11899 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 11900 11901 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 11902 #define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0) 11903 #define HTT_TX_WBM_COMP_INFO2_VALID BIT(21) 11904 11905 struct htt_tx_wbm_completion { 11906 uint32_t info0; 11907 uint32_t info1; 11908 uint32_t info2; 11909 uint32_t info3; 11910 } __packed; 11911 11912 enum htt_h2t_msg_type { 11913 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 11914 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 11915 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 11916 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 11917 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 11918 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 11919 }; 11920 11921 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 11922 11923 struct htt_ver_req_cmd { 11924 uint32_t ver_reg_info; 11925 } __packed; 11926 11927 enum htt_srng_ring_type { 11928 HTT_HW_TO_SW_RING, 11929 HTT_SW_TO_HW_RING, 11930 HTT_SW_TO_SW_RING, 11931 }; 11932 11933 enum htt_srng_ring_id { 11934 HTT_RXDMA_HOST_BUF_RING, 11935 HTT_RXDMA_MONITOR_STATUS_RING, 11936 HTT_RXDMA_MONITOR_BUF_RING, 11937 HTT_RXDMA_MONITOR_DESC_RING, 11938 HTT_RXDMA_MONITOR_DEST_RING, 11939 HTT_HOST1_TO_FW_RXBUF_RING, 11940 HTT_HOST2_TO_FW_RXBUF_RING, 11941 HTT_RXDMA_NON_MONITOR_DEST_RING, 11942 }; 11943 11944 /* host -> target HTT_SRING_SETUP message 11945 * 11946 * After target is booted up, Host can send SRING setup message for 11947 * each host facing LMAC SRING. Target setups up HW registers based 11948 * on setup message and confirms back to Host if response_required is set. 11949 * Host should wait for confirmation message before sending new SRING 11950 * setup message 11951 * 11952 * The message would appear as follows: 11953 * 11954 * |31 24|23 20|19|18 16|15|14 8|7 0| 11955 * |--------------- +-----------------+----------------+------------------| 11956 * | ring_type | ring_id | pdev_id | msg_type | 11957 * |----------------------------------------------------------------------| 11958 * | ring_base_addr_lo | 11959 * |----------------------------------------------------------------------| 11960 * | ring_base_addr_hi | 11961 * |----------------------------------------------------------------------| 11962 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 11963 * |----------------------------------------------------------------------| 11964 * | ring_head_offset32_remote_addr_lo | 11965 * |----------------------------------------------------------------------| 11966 * | ring_head_offset32_remote_addr_hi | 11967 * |----------------------------------------------------------------------| 11968 * | ring_tail_offset32_remote_addr_lo | 11969 * |----------------------------------------------------------------------| 11970 * | ring_tail_offset32_remote_addr_hi | 11971 * |----------------------------------------------------------------------| 11972 * | ring_msi_addr_lo | 11973 * |----------------------------------------------------------------------| 11974 * | ring_msi_addr_hi | 11975 * |----------------------------------------------------------------------| 11976 * | ring_msi_data | 11977 * |----------------------------------------------------------------------| 11978 * | intr_timer_th |IM| intr_batch_counter_th | 11979 * |----------------------------------------------------------------------| 11980 * | reserved |RR|PTCF| intr_low_threshold | 11981 * |----------------------------------------------------------------------| 11982 * Where 11983 * IM = sw_intr_mode 11984 * RR = response_required 11985 * PTCF = prefetch_timer_cfg 11986 * 11987 * The message is interpreted as follows: 11988 * dword0 - b'0:7 - msg_type: This will be set to 11989 * HTT_H2T_MSG_TYPE_SRING_SETUP 11990 * b'8:15 - pdev_id: 11991 * 0 (for rings at SOC/UMAC level), 11992 * 1/2/3 mac id (for rings at LMAC level) 11993 * b'16:23 - ring_id: identify which ring is to setup, 11994 * more details can be got from enum htt_srng_ring_id 11995 * b'24:31 - ring_type: identify type of host rings, 11996 * more details can be got from enum htt_srng_ring_type 11997 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 11998 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 11999 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 12000 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 12001 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 12002 * SW_TO_HW_RING. 12003 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 12004 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 12005 * Lower 32 bits of memory address of the remote variable 12006 * storing the 4-byte word offset that identifies the head 12007 * element within the ring. 12008 * (The head offset variable has type uint32_t.) 12009 * Valid for HW_TO_SW and SW_TO_SW rings. 12010 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 12011 * Upper 32 bits of memory address of the remote variable 12012 * storing the 4-byte word offset that identifies the head 12013 * element within the ring. 12014 * (The head offset variable has type uint32_t.) 12015 * Valid for HW_TO_SW and SW_TO_SW rings. 12016 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 12017 * Lower 32 bits of memory address of the remote variable 12018 * storing the 4-byte word offset that identifies the tail 12019 * element within the ring. 12020 * (The tail offset variable has type uint32_t.) 12021 * Valid for HW_TO_SW and SW_TO_SW rings. 12022 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 12023 * Upper 32 bits of memory address of the remote variable 12024 * storing the 4-byte word offset that identifies the tail 12025 * element within the ring. 12026 * (The tail offset variable has type uint32_t.) 12027 * Valid for HW_TO_SW and SW_TO_SW rings. 12028 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 12029 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12030 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 12031 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12032 * dword10 - b'0:31 - ring_msi_data: MSI data 12033 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 12034 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 12035 * dword11 - b'0:14 - intr_batch_counter_th: 12036 * batch counter threshold is in units of 4-byte words. 12037 * HW internally maintains and increments batch count. 12038 * (see SRING spec for detail description). 12039 * When batch count reaches threshold value, an interrupt 12040 * is generated by HW. 12041 * b'15 - sw_intr_mode: 12042 * This configuration shall be static. 12043 * Only programmed at power up. 12044 * 0: generate pulse style sw interrupts 12045 * 1: generate level style sw interrupts 12046 * b'16:31 - intr_timer_th: 12047 * The timer init value when timer is idle or is 12048 * initialized to start downcounting. 12049 * In 8us units (to cover a range of 0 to 524 ms) 12050 * dword12 - b'0:15 - intr_low_threshold: 12051 * Used only by Consumer ring to generate ring_sw_int_p. 12052 * Ring entries low threshold water mark, that is used 12053 * in combination with the interrupt timer as well as 12054 * the clearing of the level interrupt. 12055 * b'16:18 - prefetch_timer_cfg: 12056 * Used only by Consumer ring to set timer mode to 12057 * support Application prefetch handling. 12058 * The external tail offset/pointer will be updated 12059 * at following intervals: 12060 * 3'b000: (Prefetch feature disabled; used only for debug) 12061 * 3'b001: 1 usec 12062 * 3'b010: 4 usec 12063 * 3'b011: 8 usec (default) 12064 * 3'b100: 16 usec 12065 * Others: Reserved 12066 * b'19 - response_required: 12067 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 12068 * b'20:31 - reserved: reserved for future use 12069 */ 12070 12071 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12072 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12073 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 12074 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 12075 12076 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 12077 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 12078 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 12079 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 12080 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 12081 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 12082 12083 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 12084 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 12085 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 12086 12087 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 12088 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 12089 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 12090 12091 struct htt_srng_setup_cmd { 12092 uint32_t info0; 12093 uint32_t ring_base_addr_lo; 12094 uint32_t ring_base_addr_hi; 12095 uint32_t info1; 12096 uint32_t ring_head_off32_remote_addr_lo; 12097 uint32_t ring_head_off32_remote_addr_hi; 12098 uint32_t ring_tail_off32_remote_addr_lo; 12099 uint32_t ring_tail_off32_remote_addr_hi; 12100 uint32_t ring_msi_addr_lo; 12101 uint32_t ring_msi_addr_hi; 12102 uint32_t msi_data; 12103 uint32_t intr_info; 12104 uint32_t info2; 12105 } __packed; 12106 12107 /* host -> target FW PPDU_STATS config message 12108 * 12109 * @details 12110 * The following field definitions describe the format of the HTT host 12111 * to target FW for PPDU_STATS_CFG msg. 12112 * The message allows the host to configure the PPDU_STATS_IND messages 12113 * produced by the target. 12114 * 12115 * |31 24|23 16|15 8|7 0| 12116 * |-----------------------------------------------------------| 12117 * | REQ bit mask | pdev_mask | msg type | 12118 * |-----------------------------------------------------------| 12119 * Header fields: 12120 * - MSG_TYPE 12121 * Bits 7:0 12122 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 12123 * Value: 0x11 12124 * - PDEV_MASK 12125 * Bits 8:15 12126 * Purpose: identifies which pdevs this PPDU stats configuration applies to 12127 * Value: This is a overloaded field, refer to usage and interpretation of 12128 * PDEV in interface document. 12129 * Bit 8 : Reserved for SOC stats 12130 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 12131 * Indicates MACID_MASK in DBS 12132 * - REQ_TLV_BIT_MASK 12133 * Bits 16:31 12134 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 12135 * needs to be included in the target's PPDU_STATS_IND messages. 12136 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 12137 * 12138 */ 12139 12140 struct htt_ppdu_stats_cfg_cmd { 12141 uint32_t msg; 12142 } __packed; 12143 12144 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 12145 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 12146 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 12147 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 12148 12149 enum htt_ppdu_stats_tag_type { 12150 HTT_PPDU_STATS_TAG_COMMON, 12151 HTT_PPDU_STATS_TAG_USR_COMMON, 12152 HTT_PPDU_STATS_TAG_USR_RATE, 12153 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 12154 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 12155 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 12156 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 12157 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 12158 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 12159 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 12160 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 12161 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 12162 HTT_PPDU_STATS_TAG_INFO, 12163 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 12164 12165 /* New TLV's are added above to this line */ 12166 HTT_PPDU_STATS_TAG_MAX, 12167 }; 12168 12169 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 12170 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 12171 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 12172 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 12173 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 12174 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 12175 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 12176 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 12177 12178 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 12179 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 12180 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 12181 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 12182 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 12183 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 12184 HTT_PPDU_STATS_TAG_DEFAULT) 12185 12186 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 12187 * 12188 * details: 12189 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 12190 * configure RXDMA rings. 12191 * The configuration is per ring based and includes both packet subtypes 12192 * and PPDU/MPDU TLVs. 12193 * 12194 * The message would appear as follows: 12195 * 12196 * |31 26|25|24|23 16|15 8|7 0| 12197 * |-----------------+----------------+----------------+---------------| 12198 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 12199 * |-------------------------------------------------------------------| 12200 * | rsvd2 | ring_buffer_size | 12201 * |-------------------------------------------------------------------| 12202 * | packet_type_enable_flags_0 | 12203 * |-------------------------------------------------------------------| 12204 * | packet_type_enable_flags_1 | 12205 * |-------------------------------------------------------------------| 12206 * | packet_type_enable_flags_2 | 12207 * |-------------------------------------------------------------------| 12208 * | packet_type_enable_flags_3 | 12209 * |-------------------------------------------------------------------| 12210 * | tlv_filter_in_flags | 12211 * |-------------------------------------------------------------------| 12212 * Where: 12213 * PS = pkt_swap 12214 * SS = status_swap 12215 * The message is interpreted as follows: 12216 * dword0 - b'0:7 - msg_type: This will be set to 12217 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 12218 * b'8:15 - pdev_id: 12219 * 0 (for rings at SOC/UMAC level), 12220 * 1/2/3 mac id (for rings at LMAC level) 12221 * b'16:23 - ring_id : Identify the ring to configure. 12222 * More details can be got from enum htt_srng_ring_id 12223 * b'24 - status_swap: 1 is to swap status TLV 12224 * b'25 - pkt_swap: 1 is to swap packet TLV 12225 * b'26:31 - rsvd1: reserved for future use 12226 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 12227 * in byte units. 12228 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 12229 * - b'16:31 - rsvd2: Reserved for future use 12230 * dword2 - b'0:31 - packet_type_enable_flags_0: 12231 * Enable MGMT packet from 0b0000 to 0b1001 12232 * bits from low to high: FP, MD, MO - 3 bits 12233 * FP: Filter_Pass 12234 * MD: Monitor_Direct 12235 * MO: Monitor_Other 12236 * 10 mgmt subtypes * 3 bits -> 30 bits 12237 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 12238 * dword3 - b'0:31 - packet_type_enable_flags_1: 12239 * Enable MGMT packet from 0b1010 to 0b1111 12240 * bits from low to high: FP, MD, MO - 3 bits 12241 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 12242 * dword4 - b'0:31 - packet_type_enable_flags_2: 12243 * Enable CTRL packet from 0b0000 to 0b1001 12244 * bits from low to high: FP, MD, MO - 3 bits 12245 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 12246 * dword5 - b'0:31 - packet_type_enable_flags_3: 12247 * Enable CTRL packet from 0b1010 to 0b1111, 12248 * MCAST_DATA, UCAST_DATA, NULL_DATA 12249 * bits from low to high: FP, MD, MO - 3 bits 12250 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 12251 * dword6 - b'0:31 - tlv_filter_in_flags: 12252 * Filter in Attention/MPDU/PPDU/Header/User tlvs 12253 * Refer to CFG_TLV_FILTER_IN_FLAG defs 12254 */ 12255 12256 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12257 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12258 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 12259 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 12260 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 12261 12262 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 12263 12264 enum htt_rx_filter_tlv_flags { 12265 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 12266 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 12267 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 12268 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 12269 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 12270 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 12271 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 12272 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 12273 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 12274 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 12275 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 12276 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 12277 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 12278 }; 12279 12280 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 12281 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 12282 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 12283 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 12284 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 12285 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 12286 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 12287 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 12288 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 12289 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 12290 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 12291 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 12292 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 12293 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 12294 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 12295 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 12296 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 12297 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 12298 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 12299 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 12300 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 12301 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 12302 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 12303 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 12304 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 12305 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 12306 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 12307 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 12308 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 12309 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 12310 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 12311 }; 12312 12313 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 12314 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 12315 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 12316 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 12317 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 12318 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 12319 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 12320 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 12321 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 12322 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 12323 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 12324 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 12325 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 12326 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 12327 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 12328 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 12329 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 12330 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 12331 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 12332 }; 12333 12334 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 12335 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 12336 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 12337 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 12338 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 12339 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 12340 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 12341 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 12342 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 12343 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 12344 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 12345 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 12346 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 12347 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 12348 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 12349 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 12350 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 12351 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 12352 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 12353 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 12354 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 12355 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 12356 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 12357 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 12358 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 12359 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 12360 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 12361 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 12362 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 12363 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 12364 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 12365 }; 12366 12367 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 12368 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 12369 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 12370 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 12371 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 12372 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 12373 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 12374 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 12375 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 12376 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 12377 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 12378 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 12379 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 12380 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 12381 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 12382 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 12383 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 12384 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 12385 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 12386 }; 12387 12388 enum htt_rx_data_pkt_filter_tlv_flasg3 { 12389 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 12390 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 12391 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 12392 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 12393 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 12394 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 12395 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 12396 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 12397 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 12398 }; 12399 12400 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 12401 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12402 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12403 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12404 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12405 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12406 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12407 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12408 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12409 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12410 12411 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 12412 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12413 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12414 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12415 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12416 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12417 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12418 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12419 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12420 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12421 12422 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 12423 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 12424 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 12425 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 12426 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 12427 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 12428 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 12429 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 12430 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 12431 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 12432 12433 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12434 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12435 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12436 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12437 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12438 12439 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12440 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12441 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12442 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12443 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12444 12445 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 12446 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 12447 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 12448 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 12449 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 12450 12451 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12452 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12453 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12454 12455 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12456 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12457 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12458 12459 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 12460 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 12461 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 12462 12463 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 12464 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 12465 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 12466 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 12467 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 12468 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 12469 12470 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 12471 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 12472 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 12473 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 12474 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 12475 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 12476 12477 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 12478 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 12479 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 12480 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 12481 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 12482 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 12483 12484 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 12485 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 12486 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 12487 12488 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 12489 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 12490 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 12491 12492 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 12493 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 12494 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 12495 12496 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 12497 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 12498 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 12499 12500 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 12501 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 12502 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 12503 12504 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 12505 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 12506 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 12507 12508 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 12509 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 12510 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 12511 12512 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 12513 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 12514 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 12515 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 12516 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 12517 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 12518 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 12519 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 12520 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 12521 12522 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 12523 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 12524 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 12525 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 12526 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 12527 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 12528 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 12529 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 12530 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 12531 12532 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 12533 12534 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 12535 12536 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 12537 12538 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 12539 12540 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 12541 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 12542 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 12543 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 12544 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 12545 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 12546 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 12547 12548 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 12549 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 12550 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 12551 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 12552 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 12553 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 12554 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 12555 12556 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 12557 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 12558 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 12559 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 12560 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 12561 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 12562 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 12563 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 12564 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 12565 12566 struct htt_rx_ring_selection_cfg_cmd { 12567 uint32_t info0; 12568 uint32_t info1; 12569 uint32_t pkt_type_en_flags0; 12570 uint32_t pkt_type_en_flags1; 12571 uint32_t pkt_type_en_flags2; 12572 uint32_t pkt_type_en_flags3; 12573 uint32_t rx_filter_tlv; 12574 } __packed; 12575 12576 struct htt_rx_ring_tlv_filter { 12577 uint32_t rx_filter; /* see htt_rx_filter_tlv_flags */ 12578 uint32_t pkt_filter_flags0; /* MGMT */ 12579 uint32_t pkt_filter_flags1; /* MGMT */ 12580 uint32_t pkt_filter_flags2; /* CTRL */ 12581 uint32_t pkt_filter_flags3; /* DATA */ 12582 }; 12583 12584 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 12585 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 12586 12587 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0) 12588 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1) 12589 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2) 12590 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3) 12591 12592 /* Enumeration for full monitor mode destination ring select 12593 * 0 - REO destination ring select 12594 * 1 - FW destination ring select 12595 * 2 - SW destination ring select 12596 * 3 - Release destination ring select 12597 */ 12598 enum htt_rx_full_mon_release_ring { 12599 HTT_RX_MON_RING_REO, 12600 HTT_RX_MON_RING_FW, 12601 HTT_RX_MON_RING_SW, 12602 HTT_RX_MON_RING_RELEASE, 12603 }; 12604 12605 struct htt_rx_full_monitor_mode_cfg_cmd { 12606 uint32_t info0; 12607 uint32_t cfg; 12608 } __packed; 12609 12610 /* HTT message target->host */ 12611 12612 enum htt_t2h_msg_type { 12613 HTT_T2H_MSG_TYPE_VERSION_CONF, 12614 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 12615 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 12616 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 12617 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 12618 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 12619 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 12620 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 12621 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 12622 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 12623 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 12624 }; 12625 12626 #define HTT_TARGET_VERSION_MAJOR 3 12627 12628 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 12629 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 12630 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 12631 12632 struct htt_t2h_version_conf_msg { 12633 uint32_t version; 12634 } __packed; 12635 12636 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 12637 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 12638 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 12639 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 12640 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 12641 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 12642 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 12643 12644 struct htt_t2h_peer_map_event { 12645 uint32_t info; 12646 uint32_t mac_addr_l32; 12647 uint32_t info1; 12648 uint32_t info2; 12649 } __packed; 12650 12651 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 12652 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 12653 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 12654 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 12655 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 12656 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 12657 12658 struct htt_t2h_peer_unmap_event { 12659 uint32_t info; 12660 uint32_t mac_addr_l32; 12661 uint32_t info1; 12662 } __packed; 12663 12664 struct htt_resp_msg { 12665 union { 12666 struct htt_t2h_version_conf_msg version_msg; 12667 struct htt_t2h_peer_map_event peer_map_ev; 12668 struct htt_t2h_peer_unmap_event peer_unmap_ev; 12669 }; 12670 } __packed; 12671 12672 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 12673 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 12674 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 12675 12676 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 12677 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 12678 12679 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 12680 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 12681 12682 enum htt_backpressure_umac_ringid { 12683 HTT_SW_RING_IDX_REO_REO2SW1_RING, 12684 HTT_SW_RING_IDX_REO_REO2SW2_RING, 12685 HTT_SW_RING_IDX_REO_REO2SW3_RING, 12686 HTT_SW_RING_IDX_REO_REO2SW4_RING, 12687 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 12688 HTT_SW_RING_IDX_REO_REO2TCL_RING, 12689 HTT_SW_RING_IDX_REO_REO2FW_RING, 12690 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 12691 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 12692 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 12693 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 12694 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 12695 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 12696 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 12697 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 12698 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 12699 HTT_SW_RING_IDX_REO_REO_CMD_RING, 12700 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 12701 HTT_SW_UMAC_RING_IDX_MAX, 12702 }; 12703 12704 enum htt_backpressure_lmac_ringid { 12705 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 12706 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 12707 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 12708 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 12709 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 12710 HTT_SW_RING_IDX_RXDMA2FW_RING, 12711 HTT_SW_RING_IDX_RXDMA2SW_RING, 12712 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 12713 HTT_SW_RING_IDX_RXDMA2REO_RING, 12714 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 12715 HTT_SW_RING_IDX_MONITOR_BUF_RING, 12716 HTT_SW_RING_IDX_MONITOR_DESC_RING, 12717 HTT_SW_RING_IDX_MONITOR_DEST_RING, 12718 HTT_SW_LMAC_RING_IDX_MAX, 12719 }; 12720 12721 /* ppdu stats 12722 * 12723 * @details 12724 * The following field definitions describe the format of the HTT target 12725 * to host ppdu stats indication message. 12726 * 12727 * 12728 * |31 16|15 12|11 10|9 8|7 0 | 12729 * |----------------------------------------------------------------------| 12730 * | payload_size | rsvd |pdev_id|mac_id | msg type | 12731 * |----------------------------------------------------------------------| 12732 * | ppdu_id | 12733 * |----------------------------------------------------------------------| 12734 * | Timestamp in us | 12735 * |----------------------------------------------------------------------| 12736 * | reserved | 12737 * |----------------------------------------------------------------------| 12738 * | type-specific stats info | 12739 * | (see htt_ppdu_stats.h) | 12740 * |----------------------------------------------------------------------| 12741 * Header fields: 12742 * - MSG_TYPE 12743 * Bits 7:0 12744 * Purpose: Identifies this is a PPDU STATS indication 12745 * message. 12746 * Value: 0x1d 12747 * - mac_id 12748 * Bits 9:8 12749 * Purpose: mac_id of this ppdu_id 12750 * Value: 0-3 12751 * - pdev_id 12752 * Bits 11:10 12753 * Purpose: pdev_id of this ppdu_id 12754 * Value: 0-3 12755 * 0 (for rings at SOC level), 12756 * 1/2/3 PDEV -> 0/1/2 12757 * - payload_size 12758 * Bits 31:16 12759 * Purpose: total tlv size 12760 * Value: payload_size in bytes 12761 */ 12762 12763 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 12764 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 12765 12766 struct ath11k_htt_ppdu_stats_msg { 12767 uint32_t info; 12768 uint32_t ppdu_id; 12769 uint32_t timestamp; 12770 uint32_t rsvd; 12771 uint8_t data[]; 12772 } __packed; 12773 12774 struct htt_tlv { 12775 uint32_t header; 12776 uint8_t *value; 12777 } __packed; 12778 12779 #define HTT_TLV_TAG GENMASK(11, 0) 12780 #define HTT_TLV_LEN GENMASK(23, 12) 12781 12782 enum HTT_PPDU_STATS_BW { 12783 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 12784 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 12785 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 12786 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 12787 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 12788 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 12789 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 12790 }; 12791 12792 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 12793 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 12794 /* bw - HTT_PPDU_STATS_BW */ 12795 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 12796 12797 struct htt_ppdu_stats_common { 12798 uint32_t ppdu_id; 12799 uint16_t sched_cmdid; 12800 uint8_t ring_id; 12801 uint8_t num_users; 12802 uint32_t flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 12803 uint32_t chain_mask; 12804 uint32_t fes_duration_us; /* frame exchange sequence */ 12805 uint32_t ppdu_sch_eval_start_tstmp_us; 12806 uint32_t ppdu_sch_end_tstmp_us; 12807 uint32_t ppdu_start_tstmp_us; 12808 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 12809 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 12810 */ 12811 uint16_t phy_mode; 12812 uint16_t bw_mhz; 12813 } __packed; 12814 12815 enum htt_ppdu_stats_gi { 12816 HTT_PPDU_STATS_SGI_0_8_US, 12817 HTT_PPDU_STATS_SGI_0_4_US, 12818 HTT_PPDU_STATS_SGI_1_6_US, 12819 HTT_PPDU_STATS_SGI_3_2_US, 12820 }; 12821 12822 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 12823 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 12824 12825 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 12826 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 12827 12828 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 12829 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 12830 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 12831 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 12832 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 12833 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 12834 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 12835 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 12836 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 12837 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 12838 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 12839 12840 #define HTT_USR_RATE_PREAMBLE(_val) \ 12841 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 12842 #define HTT_USR_RATE_BW(_val) \ 12843 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 12844 #define HTT_USR_RATE_NSS(_val) \ 12845 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 12846 #define HTT_USR_RATE_MCS(_val) \ 12847 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 12848 #define HTT_USR_RATE_GI(_val) \ 12849 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 12850 #define HTT_USR_RATE_DCM(_val) \ 12851 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 12852 12853 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 12854 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 12855 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 12856 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 12857 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 12858 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 12859 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 12860 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 12861 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 12862 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 12863 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 12864 12865 struct htt_ppdu_stats_user_rate { 12866 uint8_t tid_num; 12867 uint8_t reserved0; 12868 uint16_t sw_peer_id; 12869 uint32_t info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 12870 uint16_t ru_end; 12871 uint16_t ru_start; 12872 uint16_t resp_ru_end; 12873 uint16_t resp_ru_start; 12874 uint32_t info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 12875 uint32_t rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 12876 /* Note: resp_rate_info is only valid for if resp_type is UL */ 12877 uint32_t resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 12878 } __packed; 12879 12880 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 12881 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 12882 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 12883 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 12884 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 12885 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 12886 12887 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 12888 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 12889 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 12890 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 12891 #define HTT_TX_INFO_RATECODE(_flags) \ 12892 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 12893 #define HTT_TX_INFO_PEERID(_flags) \ 12894 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 12895 12896 struct htt_tx_ppdu_stats_info { 12897 struct htt_tlv tlv_hdr; 12898 uint32_t tx_success_bytes; 12899 uint32_t tx_retry_bytes; 12900 uint32_t tx_failed_bytes; 12901 uint32_t flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 12902 uint16_t tx_success_msdus; 12903 uint16_t tx_retry_msdus; 12904 uint16_t tx_failed_msdus; 12905 uint16_t tx_duration; /* united in us */ 12906 } __packed; 12907 12908 enum htt_ppdu_stats_usr_compln_status { 12909 HTT_PPDU_STATS_USER_STATUS_OK, 12910 HTT_PPDU_STATS_USER_STATUS_FILTERED, 12911 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 12912 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 12913 HTT_PPDU_STATS_USER_STATUS_ABORT, 12914 }; 12915 12916 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 12917 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 12918 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 12919 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 12920 12921 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 12922 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 12923 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 12924 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 12925 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 12926 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 12927 12928 struct htt_ppdu_stats_usr_cmpltn_cmn { 12929 uint8_t status; 12930 uint8_t tid_num; 12931 uint16_t sw_peer_id; 12932 /* RSSI value of last ack packet (units = dB above noise floor) */ 12933 uint32_t ack_rssi; 12934 uint16_t mpdu_tried; 12935 uint16_t mpdu_success; 12936 uint32_t flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 12937 } __packed; 12938 12939 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 12940 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 12941 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 12942 12943 #define HTT_PPDU_STATS_NON_QOS_TID 16 12944 12945 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 12946 uint32_t ppdu_id; 12947 uint16_t sw_peer_id; 12948 uint16_t reserved0; 12949 uint32_t info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 12950 uint16_t current_seq; 12951 uint16_t start_seq; 12952 uint32_t success_bytes; 12953 } __packed; 12954 12955 struct htt_ppdu_stats_usr_cmn_array { 12956 struct htt_tlv tlv_hdr; 12957 uint32_t num_ppdu_stats; 12958 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 12959 * elements. 12960 * tx_ppdu_stats_info is variable length, with length = 12961 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 12962 */ 12963 struct htt_tx_ppdu_stats_info tx_ppdu_info[]; 12964 } __packed; 12965 12966 struct htt_ppdu_user_stats { 12967 uint16_t peer_id; 12968 uint32_t tlv_flags; 12969 bool is_valid_peer_id; 12970 struct htt_ppdu_stats_user_rate rate; 12971 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 12972 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 12973 }; 12974 12975 #define HTT_PPDU_STATS_MAX_USERS 8 12976 #define HTT_PPDU_DESC_MAX_DEPTH 16 12977 12978 struct htt_ppdu_stats { 12979 struct htt_ppdu_stats_common common; 12980 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 12981 }; 12982 12983 struct htt_ppdu_stats_info { 12984 uint32_t ppdu_id; 12985 struct htt_ppdu_stats ppdu_stats; 12986 #if 0 12987 struct list_head list; 12988 #endif 12989 }; 12990 12991 /* @brief target -> host packet log message 12992 * 12993 * @details 12994 * The following field definitions describe the format of the packet log 12995 * message sent from the target to the host. 12996 * The message consists of a 4-octet header,followed by a variable number 12997 * of 32-bit character values. 12998 * 12999 * |31 16|15 12|11 10|9 8|7 0| 13000 * |------------------------------------------------------------------| 13001 * | payload_size | rsvd |pdev_id|mac_id| msg type | 13002 * |------------------------------------------------------------------| 13003 * | payload | 13004 * |------------------------------------------------------------------| 13005 * - MSG_TYPE 13006 * Bits 7:0 13007 * Purpose: identifies this as a pktlog message 13008 * Value: HTT_T2H_MSG_TYPE_PKTLOG 13009 * - mac_id 13010 * Bits 9:8 13011 * Purpose: identifies which MAC/PHY instance generated this pktlog info 13012 * Value: 0-3 13013 * - pdev_id 13014 * Bits 11:10 13015 * Purpose: pdev_id 13016 * Value: 0-3 13017 * 0 (for rings at SOC level), 13018 * 1/2/3 PDEV -> 0/1/2 13019 * - payload_size 13020 * Bits 31:16 13021 * Purpose: explicitly specify the payload size 13022 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 13023 */ 13024 struct htt_pktlog_msg { 13025 uint32_t hdr; 13026 uint8_t payload[]; 13027 }; 13028 13029 /* @brief host -> target FW extended statistics retrieve 13030 * 13031 * @details 13032 * The following field definitions describe the format of the HTT host 13033 * to target FW extended stats retrieve message. 13034 * The message specifies the type of stats the host wants to retrieve. 13035 * 13036 * |31 24|23 16|15 8|7 0| 13037 * |-----------------------------------------------------------| 13038 * | reserved | stats type | pdev_mask | msg type | 13039 * |-----------------------------------------------------------| 13040 * | config param [0] | 13041 * |-----------------------------------------------------------| 13042 * | config param [1] | 13043 * |-----------------------------------------------------------| 13044 * | config param [2] | 13045 * |-----------------------------------------------------------| 13046 * | config param [3] | 13047 * |-----------------------------------------------------------| 13048 * | reserved | 13049 * |-----------------------------------------------------------| 13050 * | cookie LSBs | 13051 * |-----------------------------------------------------------| 13052 * | cookie MSBs | 13053 * |-----------------------------------------------------------| 13054 * Header fields: 13055 * - MSG_TYPE 13056 * Bits 7:0 13057 * Purpose: identifies this is a extended stats upload request message 13058 * Value: 0x10 13059 * - PDEV_MASK 13060 * Bits 8:15 13061 * Purpose: identifies the mask of PDEVs to retrieve stats from 13062 * Value: This is a overloaded field, refer to usage and interpretation of 13063 * PDEV in interface document. 13064 * Bit 8 : Reserved for SOC stats 13065 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 13066 * Indicates MACID_MASK in DBS 13067 * - STATS_TYPE 13068 * Bits 23:16 13069 * Purpose: identifies which FW statistics to upload 13070 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 13071 * - Reserved 13072 * Bits 31:24 13073 * - CONFIG_PARAM [0] 13074 * Bits 31:0 13075 * Purpose: give an opaque configuration value to the specified stats type 13076 * Value: stats-type specific configuration value 13077 * Refer to htt_stats.h for interpretation for each stats sub_type 13078 * - CONFIG_PARAM [1] 13079 * Bits 31:0 13080 * Purpose: give an opaque configuration value to the specified stats type 13081 * Value: stats-type specific configuration value 13082 * Refer to htt_stats.h for interpretation for each stats sub_type 13083 * - CONFIG_PARAM [2] 13084 * Bits 31:0 13085 * Purpose: give an opaque configuration value to the specified stats type 13086 * Value: stats-type specific configuration value 13087 * Refer to htt_stats.h for interpretation for each stats sub_type 13088 * - CONFIG_PARAM [3] 13089 * Bits 31:0 13090 * Purpose: give an opaque configuration value to the specified stats type 13091 * Value: stats-type specific configuration value 13092 * Refer to htt_stats.h for interpretation for each stats sub_type 13093 * - Reserved [31:0] for future use. 13094 * - COOKIE_LSBS 13095 * Bits 31:0 13096 * Purpose: Provide a mechanism to match a target->host stats confirmation 13097 * message with its preceding host->target stats request message. 13098 * Value: LSBs of the opaque cookie specified by the host-side requestor 13099 * - COOKIE_MSBS 13100 * Bits 31:0 13101 * Purpose: Provide a mechanism to match a target->host stats confirmation 13102 * message with its preceding host->target stats request message. 13103 * Value: MSBs of the opaque cookie specified by the host-side requestor 13104 */ 13105 13106 struct htt_ext_stats_cfg_hdr { 13107 uint8_t msg_type; 13108 uint8_t pdev_mask; 13109 uint8_t stats_type; 13110 uint8_t reserved; 13111 } __packed; 13112 13113 struct htt_ext_stats_cfg_cmd { 13114 struct htt_ext_stats_cfg_hdr hdr; 13115 uint32_t cfg_param0; 13116 uint32_t cfg_param1; 13117 uint32_t cfg_param2; 13118 uint32_t cfg_param3; 13119 uint32_t reserved; 13120 uint32_t cookie_lsb; 13121 uint32_t cookie_msb; 13122 } __packed; 13123 13124 /* htt stats config default params */ 13125 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 13126 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 13127 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 13128 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 13129 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 13130 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 13131 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 13132 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 13133 13134 /* HTT_DBG_EXT_STATS_PEER_INFO 13135 * PARAMS: 13136 * @config_param0: 13137 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 13138 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 13139 * [Bit31 : Bit16] sw_peer_id 13140 * @config_param1: 13141 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 13142 * 0 bit htt_peer_stats_cmn_tlv 13143 * 1 bit htt_peer_details_tlv 13144 * 2 bit htt_tx_peer_rate_stats_tlv 13145 * 3 bit htt_rx_peer_rate_stats_tlv 13146 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 13147 * 5 bit htt_rx_tid_stats_tlv 13148 * 6 bit htt_msdu_flow_stats_tlv 13149 * @config_param2: [Bit31 : Bit0] mac_addr31to0 13150 * @config_param3: [Bit15 : Bit0] mac_addr47to32 13151 * [Bit31 : Bit16] reserved 13152 */ 13153 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 13154 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 13155 13156 /* Used to set different configs to the specified stats type.*/ 13157 struct htt_ext_stats_cfg_params { 13158 uint32_t cfg0; 13159 uint32_t cfg1; 13160 uint32_t cfg2; 13161 uint32_t cfg3; 13162 }; 13163 13164 /* @brief target -> host extended statistics upload 13165 * 13166 * @details 13167 * The following field definitions describe the format of the HTT target 13168 * to host stats upload confirmation message. 13169 * The message contains a cookie echoed from the HTT host->target stats 13170 * upload request, which identifies which request the confirmation is 13171 * for, and a single stats can span over multiple HTT stats indication 13172 * due to the HTT message size limitation so every HTT ext stats indication 13173 * will have tag-length-value stats information elements. 13174 * The tag-length header for each HTT stats IND message also includes a 13175 * status field, to indicate whether the request for the stat type in 13176 * question was fully met, partially met, unable to be met, or invalid 13177 * (if the stat type in question is disabled in the target). 13178 * A Done bit 1's indicate the end of the of stats info elements. 13179 * 13180 * 13181 * |31 16|15 12|11|10 8|7 5|4 0| 13182 * |--------------------------------------------------------------| 13183 * | reserved | msg type | 13184 * |--------------------------------------------------------------| 13185 * | cookie LSBs | 13186 * |--------------------------------------------------------------| 13187 * | cookie MSBs | 13188 * |--------------------------------------------------------------| 13189 * | stats entry length | rsvd | D| S | stat type | 13190 * |--------------------------------------------------------------| 13191 * | type-specific stats info | 13192 * | (see htt_stats.h) | 13193 * |--------------------------------------------------------------| 13194 * Header fields: 13195 * - MSG_TYPE 13196 * Bits 7:0 13197 * Purpose: Identifies this is a extended statistics upload confirmation 13198 * message. 13199 * Value: 0x1c 13200 * - COOKIE_LSBS 13201 * Bits 31:0 13202 * Purpose: Provide a mechanism to match a target->host stats confirmation 13203 * message with its preceding host->target stats request message. 13204 * Value: LSBs of the opaque cookie specified by the host-side requestor 13205 * - COOKIE_MSBS 13206 * Bits 31:0 13207 * Purpose: Provide a mechanism to match a target->host stats confirmation 13208 * message with its preceding host->target stats request message. 13209 * Value: MSBs of the opaque cookie specified by the host-side requestor 13210 * 13211 * Stats Information Element tag-length header fields: 13212 * - STAT_TYPE 13213 * Bits 7:0 13214 * Purpose: identifies the type of statistics info held in the 13215 * following information element 13216 * Value: htt_dbg_ext_stats_type 13217 * - STATUS 13218 * Bits 10:8 13219 * Purpose: indicate whether the requested stats are present 13220 * Value: htt_dbg_ext_stats_status 13221 * - DONE 13222 * Bits 11 13223 * Purpose: 13224 * Indicates the completion of the stats entry, this will be the last 13225 * stats conf HTT segment for the requested stats type. 13226 * Value: 13227 * 0 -> the stats retrieval is ongoing 13228 * 1 -> the stats retrieval is complete 13229 * - LENGTH 13230 * Bits 31:16 13231 * Purpose: indicate the stats information size 13232 * Value: This field specifies the number of bytes of stats information 13233 * that follows the element tag-length header. 13234 * It is expected but not required that this length is a multiple of 13235 * 4 bytes. 13236 */ 13237 13238 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 13239 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 13240 13241 struct ath11k_htt_extd_stats_msg { 13242 uint32_t info0; 13243 uint64_t cookie; 13244 uint32_t info1; 13245 uint8_t data[]; 13246 } __packed; 13247 13248 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 13249 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 13250 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 13251 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 13252 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 13253 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 13254