1 /* $OpenBSD: rt2860.c,v 1.97 2019/09/12 12:55:07 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Ralink Technology RT2860/RT3090/RT3290/RT3390/RT3562/RT5390/ 21 * RT5392 chipset driver 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/timeout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/endian.h> 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #if NBPFILTER > 0 44 #include <net/bpf.h> 45 #endif 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_amrr.h> 55 #include <net80211/ieee80211_radiotap.h> 56 57 #include <dev/ic/rt2860var.h> 58 #include <dev/ic/rt2860reg.h> 59 60 #include <dev/pci/pcidevs.h> 61 62 #ifdef RAL_DEBUG 63 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0) 65 int rt2860_debug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 void rt2860_attachhook(struct device *); 72 int rt2860_alloc_tx_ring(struct rt2860_softc *, 73 struct rt2860_tx_ring *); 74 void rt2860_reset_tx_ring(struct rt2860_softc *, 75 struct rt2860_tx_ring *); 76 void rt2860_free_tx_ring(struct rt2860_softc *, 77 struct rt2860_tx_ring *); 78 int rt2860_alloc_tx_pool(struct rt2860_softc *); 79 void rt2860_free_tx_pool(struct rt2860_softc *); 80 int rt2860_alloc_rx_ring(struct rt2860_softc *, 81 struct rt2860_rx_ring *); 82 void rt2860_reset_rx_ring(struct rt2860_softc *, 83 struct rt2860_rx_ring *); 84 void rt2860_free_rx_ring(struct rt2860_softc *, 85 struct rt2860_rx_ring *); 86 struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *); 87 int rt2860_media_change(struct ifnet *); 88 void rt2860_iter_func(void *, struct ieee80211_node *); 89 void rt2860_updatestats(struct rt2860_softc *); 90 void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *, 91 int); 92 void rt2860_node_leave(struct ieee80211com *, 93 struct ieee80211_node *); 94 int rt2860_ampdu_rx_start(struct ieee80211com *, 95 struct ieee80211_node *, uint8_t); 96 void rt2860_ampdu_rx_stop(struct ieee80211com *, 97 struct ieee80211_node *, uint8_t); 98 int rt2860_newstate(struct ieee80211com *, enum ieee80211_state, 99 int); 100 uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 101 uint16_t rt3290_efuse_read_2(struct rt2860_softc *, uint16_t); 102 uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 103 void rt2860_intr_coherent(struct rt2860_softc *); 104 void rt2860_drain_stats_fifo(struct rt2860_softc *); 105 void rt2860_tx_intr(struct rt2860_softc *, int); 106 void rt2860_rx_intr(struct rt2860_softc *); 107 void rt2860_tbtt_intr(struct rt2860_softc *); 108 void rt2860_gp_intr(struct rt2860_softc *); 109 int rt2860_tx(struct rt2860_softc *, struct mbuf *, 110 struct ieee80211_node *); 111 void rt2860_start(struct ifnet *); 112 void rt2860_watchdog(struct ifnet *); 113 int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 114 void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 115 uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 116 void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 117 uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 118 void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 119 int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 120 void rt2860_enable_mrr(struct rt2860_softc *); 121 void rt2860_set_txpreamble(struct rt2860_softc *); 122 void rt2860_set_basicrates(struct rt2860_softc *); 123 void rt2860_select_chan_group(struct rt2860_softc *, int); 124 void rt2860_set_chan(struct rt2860_softc *, u_int); 125 void rt3090_set_chan(struct rt2860_softc *, u_int); 126 void rt5390_set_chan(struct rt2860_softc *, u_int); 127 int rt3090_rf_init(struct rt2860_softc *); 128 void rt5390_rf_init(struct rt2860_softc *); 129 void rt3090_rf_wakeup(struct rt2860_softc *); 130 void rt5390_rf_wakeup(struct rt2860_softc *); 131 int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 132 uint8_t *); 133 void rt3090_rf_setup(struct rt2860_softc *); 134 void rt2860_set_leds(struct rt2860_softc *, uint16_t); 135 void rt2860_set_gp_timer(struct rt2860_softc *, int); 136 void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 137 void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 138 void rt2860_updateslot(struct ieee80211com *); 139 void rt2860_updateprot(struct ieee80211com *); 140 void rt2860_updateedca(struct ieee80211com *); 141 int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 142 struct ieee80211_key *); 143 void rt2860_delete_key(struct ieee80211com *, 144 struct ieee80211_node *, struct ieee80211_key *); 145 #if NBPFILTER > 0 146 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 147 #endif 148 const char * rt2860_get_rf(uint16_t); 149 int rt2860_read_eeprom(struct rt2860_softc *); 150 int rt2860_bbp_init(struct rt2860_softc *); 151 void rt5390_bbp_init(struct rt2860_softc *); 152 int rt3290_wlan_enable(struct rt2860_softc *); 153 int rt2860_txrx_enable(struct rt2860_softc *); 154 int rt2860_init(struct ifnet *); 155 void rt2860_stop(struct ifnet *, int); 156 int rt2860_load_microcode(struct rt2860_softc *); 157 void rt2860_calib(struct rt2860_softc *); 158 void rt3090_set_rx_antenna(struct rt2860_softc *, int); 159 void rt2860_switch_chan(struct rt2860_softc *, 160 struct ieee80211_channel *); 161 #ifndef IEEE80211_STA_ONLY 162 int rt2860_setup_beacon(struct rt2860_softc *); 163 #endif 164 void rt2860_enable_tsf_sync(struct rt2860_softc *); 165 166 static const struct { 167 uint32_t reg; 168 uint32_t val; 169 } rt2860_def_mac[] = { 170 RT2860_DEF_MAC 171 }; 172 173 static const struct { 174 uint8_t reg; 175 uint8_t val; 176 } rt2860_def_bbp[] = { 177 RT2860_DEF_BBP 178 },rt3290_def_bbp[] = { 179 RT3290_DEF_BBP 180 },rt5390_def_bbp[] = { 181 RT5390_DEF_BBP 182 }; 183 184 static const struct rfprog { 185 uint8_t chan; 186 uint32_t r1, r2, r3, r4; 187 } rt2860_rf2850[] = { 188 RT2860_RF2850 189 }; 190 191 struct { 192 uint8_t n, r, k; 193 } rt3090_freqs[] = { 194 RT3070_RF3052 195 }; 196 197 static const struct { 198 uint8_t reg; 199 uint8_t val; 200 } rt3090_def_rf[] = { 201 RT3070_DEF_RF 202 }, rt3290_def_rf[] = { 203 RT3290_DEF_RF 204 }, rt3572_def_rf[] = { 205 RT3572_DEF_RF 206 }, rt5390_def_rf[] = { 207 RT5390_DEF_RF 208 }, rt5392_def_rf[] = { 209 RT5392_DEF_RF 210 }; 211 212 int 213 rt2860_attach(void *xsc, int id) 214 { 215 struct rt2860_softc *sc = xsc; 216 struct ieee80211com *ic = &sc->sc_ic; 217 int qid, ntries, error; 218 uint32_t tmp, reg; 219 220 sc->amrr.amrr_min_success_threshold = 1; 221 sc->amrr.amrr_max_success_threshold = 15; 222 223 if (id == PCI_PRODUCT_RALINK_RT3290) 224 reg = RT2860_PCI_CFG; 225 else 226 reg = RT2860_ASIC_VER_ID; 227 228 /* wait for NIC to initialize */ 229 for (ntries = 0; ntries < 100; ntries++) { 230 tmp = RAL_READ(sc, reg); 231 if (tmp != 0 && tmp != 0xffffffff) 232 break; 233 DELAY(10); 234 } 235 if (ntries == 100) { 236 printf("%s: timeout waiting for NIC to initialize\n", 237 sc->sc_dev.dv_xname); 238 return ETIMEDOUT; 239 } 240 sc->mac_ver = tmp >> 16; 241 sc->mac_rev = tmp & 0xffff; 242 243 if (sc->mac_ver != 0x2860 && 244 (id == PCI_PRODUCT_RALINK_RT2890 || 245 id == PCI_PRODUCT_RALINK_RT2790 || 246 id == PCI_PRODUCT_AWT_RT2890)) 247 sc->sc_flags |= RT2860_ADVANCED_PS; 248 249 /* retrieve RF rev. no and various other things from EEPROM */ 250 rt2860_read_eeprom(sc); 251 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 252 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n", 253 sc->sc_dev.dv_xname, sc->mac_ver, sc->mac_rev, 254 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains); 255 256 /* 257 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 258 */ 259 for (qid = 0; qid < 6; qid++) { 260 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 261 printf("%s: could not allocate Tx ring %d\n", 262 sc->sc_dev.dv_xname, qid); 263 goto fail1; 264 } 265 } 266 267 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 268 printf("%s: could not allocate Rx ring\n", 269 sc->sc_dev.dv_xname); 270 goto fail1; 271 } 272 273 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 274 printf("%s: could not allocate Tx pool\n", 275 sc->sc_dev.dv_xname); 276 goto fail2; 277 } 278 279 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 280 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 281 EDCA_AC_VO : 5; 282 283 config_mountroot(xsc, rt2860_attachhook); 284 285 return 0; 286 287 fail2: rt2860_free_rx_ring(sc, &sc->rxq); 288 fail1: while (--qid >= 0) 289 rt2860_free_tx_ring(sc, &sc->txq[qid]); 290 return error; 291 } 292 293 void 294 rt2860_attachhook(struct device *self) 295 { 296 struct rt2860_softc *sc = (struct rt2860_softc *)self; 297 struct ieee80211com *ic = &sc->sc_ic; 298 struct ifnet *ifp = &ic->ic_if; 299 int i, error; 300 301 if (sc->mac_ver == 0x3290) { 302 error = loadfirmware("ral-rt3290", &sc->ucode, &sc->ucsize); 303 } else { 304 error = loadfirmware("ral-rt2860", &sc->ucode, &sc->ucsize); 305 } 306 if (error != 0) { 307 printf("%s: error %d, could not read firmware file %s\n", 308 sc->sc_dev.dv_xname, error, "ral-rt2860"); 309 return; 310 } 311 312 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 313 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 314 ic->ic_state = IEEE80211_S_INIT; 315 316 /* set device capabilities */ 317 ic->ic_caps = 318 IEEE80211_C_MONITOR | /* monitor mode supported */ 319 #ifndef IEEE80211_STA_ONLY 320 IEEE80211_C_IBSS | /* IBSS mode supported */ 321 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 322 IEEE80211_C_APPMGT | /* HostAP power management */ 323 #endif 324 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 325 IEEE80211_C_SHSLOT | /* short slot time supported */ 326 IEEE80211_C_WEP | /* s/w WEP */ 327 IEEE80211_C_RSN; /* WPA/RSN */ 328 329 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 330 /* set supported .11a rates */ 331 ic->ic_sup_rates[IEEE80211_MODE_11A] = 332 ieee80211_std_rateset_11a; 333 334 /* set supported .11a channels */ 335 for (i = 14; i < nitems(rt2860_rf2850); i++) { 336 uint8_t chan = rt2860_rf2850[i].chan; 337 ic->ic_channels[chan].ic_freq = 338 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 339 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 340 } 341 } 342 343 /* set supported .11b and .11g rates */ 344 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 345 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 346 347 /* set supported .11b and .11g channels (1 through 14) */ 348 for (i = 1; i <= 14; i++) { 349 ic->ic_channels[i].ic_freq = 350 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 351 ic->ic_channels[i].ic_flags = 352 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 353 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 354 } 355 356 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 357 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 358 359 ifp->if_softc = sc; 360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 361 ifp->if_ioctl = rt2860_ioctl; 362 ifp->if_start = rt2860_start; 363 ifp->if_watchdog = rt2860_watchdog; 364 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 365 366 if_attach(ifp); 367 ieee80211_ifattach(ifp); 368 ic->ic_node_alloc = rt2860_node_alloc; 369 ic->ic_newassoc = rt2860_newassoc; 370 #ifndef IEEE80211_STA_ONLY 371 ic->ic_node_leave = rt2860_node_leave; 372 #endif 373 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start; 374 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop; 375 ic->ic_updateslot = rt2860_updateslot; 376 ic->ic_updateedca = rt2860_updateedca; 377 ic->ic_set_key = rt2860_set_key; 378 ic->ic_delete_key = rt2860_delete_key; 379 /* override state transition machine */ 380 sc->sc_newstate = ic->ic_newstate; 381 ic->ic_newstate = rt2860_newstate; 382 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status); 383 384 #if NBPFILTER > 0 385 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 386 sizeof (struct ieee80211_frame) + 64); 387 388 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 389 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 390 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT); 391 392 sc->sc_txtap_len = sizeof sc->sc_txtapu; 393 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 394 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT); 395 #endif 396 } 397 398 int 399 rt2860_detach(void *xsc) 400 { 401 struct rt2860_softc *sc = xsc; 402 struct ifnet *ifp = &sc->sc_ic.ic_if; 403 int qid; 404 405 ieee80211_ifdetach(ifp); /* free all nodes */ 406 if_detach(ifp); 407 408 for (qid = 0; qid < 6; qid++) 409 rt2860_free_tx_ring(sc, &sc->txq[qid]); 410 rt2860_free_rx_ring(sc, &sc->rxq); 411 rt2860_free_tx_pool(sc); 412 413 if (sc->ucode != NULL) 414 free(sc->ucode, M_DEVBUF, sc->ucsize); 415 416 return 0; 417 } 418 419 void 420 rt2860_suspend(void *xsc) 421 { 422 struct rt2860_softc *sc = xsc; 423 struct ifnet *ifp = &sc->sc_ic.ic_if; 424 425 if (ifp->if_flags & IFF_RUNNING) 426 rt2860_stop(ifp, 1); 427 } 428 429 void 430 rt2860_wakeup(void *xsc) 431 { 432 struct rt2860_softc *sc = xsc; 433 struct ifnet *ifp = &sc->sc_ic.ic_if; 434 435 if (ifp->if_flags & IFF_UP) 436 rt2860_init(ifp); 437 } 438 439 int 440 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 441 { 442 int nsegs, size, error; 443 444 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 445 446 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 447 BUS_DMA_NOWAIT, &ring->map); 448 if (error != 0) { 449 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 450 goto fail; 451 } 452 453 /* Tx rings must be 4-DWORD aligned */ 454 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 455 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 456 if (error != 0) { 457 printf("%s: could not allocate DMA memory\n", 458 sc->sc_dev.dv_xname); 459 goto fail; 460 } 461 462 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 463 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT); 464 if (error != 0) { 465 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 466 goto fail; 467 } 468 469 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL, 470 BUS_DMA_NOWAIT); 471 if (error != 0) { 472 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 473 goto fail; 474 } 475 476 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 477 478 ring->paddr = ring->map->dm_segs[0].ds_addr; 479 480 return 0; 481 482 fail: rt2860_free_tx_ring(sc, ring); 483 return error; 484 } 485 486 void 487 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 488 { 489 struct rt2860_tx_data *data; 490 int i; 491 492 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 493 if ((data = ring->data[i]) == NULL) 494 continue; /* nothing mapped in this slot */ 495 496 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 497 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 498 bus_dmamap_unload(sc->sc_dmat, data->map); 499 m_freem(data->m); 500 data->m= NULL; 501 data->ni = NULL; /* node already freed */ 502 503 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 504 ring->data[i] = NULL; 505 } 506 507 ring->queued = 0; 508 ring->cur = ring->next = 0; 509 } 510 511 void 512 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 513 { 514 struct rt2860_tx_data *data; 515 int i; 516 517 if (ring->txd != NULL) { 518 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 519 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 520 bus_dmamap_unload(sc->sc_dmat, ring->map); 521 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd, 522 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd)); 523 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 524 } 525 if (ring->map != NULL) 526 bus_dmamap_destroy(sc->sc_dmat, ring->map); 527 528 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 529 if ((data = ring->data[i]) == NULL) 530 continue; /* nothing mapped in this slot */ 531 532 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 533 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 534 bus_dmamap_unload(sc->sc_dmat, data->map); 535 m_freem(data->m); 536 537 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 538 } 539 } 540 541 /* 542 * Allocate a pool of TX Wireless Information blocks. 543 */ 544 int 545 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 546 { 547 caddr_t vaddr; 548 bus_addr_t paddr; 549 int i, nsegs, size, error; 550 551 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 552 553 /* init data_pool early in case of failure.. */ 554 SLIST_INIT(&sc->data_pool); 555 556 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 557 BUS_DMA_NOWAIT, &sc->txwi_map); 558 if (error != 0) { 559 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 560 goto fail; 561 } 562 563 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 564 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 565 if (error != 0) { 566 printf("%s: could not allocate DMA memory\n", 567 sc->sc_dev.dv_xname); 568 goto fail; 569 } 570 571 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size, 572 &sc->txwi_vaddr, BUS_DMA_NOWAIT); 573 if (error != 0) { 574 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 575 goto fail; 576 } 577 578 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr, 579 size, NULL, BUS_DMA_NOWAIT); 580 if (error != 0) { 581 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 582 goto fail; 583 } 584 585 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size, 586 BUS_DMASYNC_PREWRITE); 587 588 vaddr = sc->txwi_vaddr; 589 paddr = sc->txwi_map->dm_segs[0].ds_addr; 590 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 591 struct rt2860_tx_data *data = &sc->data[i]; 592 593 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 594 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 595 &data->map); /* <0> */ 596 if (error != 0) { 597 printf("%s: could not create DMA map\n", 598 sc->sc_dev.dv_xname); 599 goto fail; 600 } 601 data->txwi = (struct rt2860_txwi *)vaddr; 602 data->paddr = paddr; 603 vaddr += RT2860_TXWI_DMASZ; 604 paddr += RT2860_TXWI_DMASZ; 605 606 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 607 } 608 609 return 0; 610 611 fail: rt2860_free_tx_pool(sc); 612 return error; 613 } 614 615 void 616 rt2860_free_tx_pool(struct rt2860_softc *sc) 617 { 618 if (sc->txwi_vaddr != NULL) { 619 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, 620 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 621 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map); 622 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr, 623 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ); 624 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1); 625 } 626 if (sc->txwi_map != NULL) 627 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map); 628 629 while (!SLIST_EMPTY(&sc->data_pool)) { 630 struct rt2860_tx_data *data; 631 data = SLIST_FIRST(&sc->data_pool); 632 bus_dmamap_destroy(sc->sc_dmat, data->map); 633 SLIST_REMOVE_HEAD(&sc->data_pool, next); 634 } 635 } 636 637 int 638 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 639 { 640 int i, nsegs, size, error; 641 642 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 643 644 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 645 BUS_DMA_NOWAIT, &ring->map); 646 if (error != 0) { 647 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname); 648 goto fail; 649 } 650 651 /* Rx ring must be 4-DWORD aligned */ 652 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1, 653 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 654 if (error != 0) { 655 printf("%s: could not allocate DMA memory\n", 656 sc->sc_dev.dv_xname); 657 goto fail; 658 } 659 660 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size, 661 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT); 662 if (error != 0) { 663 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname); 664 goto fail; 665 } 666 667 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL, 668 BUS_DMA_NOWAIT); 669 if (error != 0) { 670 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname); 671 goto fail; 672 } 673 674 ring->paddr = ring->map->dm_segs[0].ds_addr; 675 676 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 677 struct rt2860_rx_data *data = &ring->data[i]; 678 struct rt2860_rxd *rxd = &ring->rxd[i]; 679 680 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 681 0, BUS_DMA_NOWAIT, &data->map); 682 if (error != 0) { 683 printf("%s: could not create DMA map\n", 684 sc->sc_dev.dv_xname); 685 goto fail; 686 } 687 688 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 689 if (data->m == NULL) { 690 printf("%s: could not allocate Rx mbuf\n", 691 sc->sc_dev.dv_xname); 692 error = ENOBUFS; 693 goto fail; 694 } 695 696 error = bus_dmamap_load(sc->sc_dmat, data->map, 697 mtod(data->m, void *), MCLBYTES, NULL, 698 BUS_DMA_READ | BUS_DMA_NOWAIT); 699 if (error != 0) { 700 printf("%s: could not load DMA map\n", 701 sc->sc_dev.dv_xname); 702 goto fail; 703 } 704 705 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 706 rxd->sdl0 = htole16(MCLBYTES); 707 } 708 709 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE); 710 711 return 0; 712 713 fail: rt2860_free_rx_ring(sc, ring); 714 return error; 715 } 716 717 void 718 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 719 { 720 int i; 721 722 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 723 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 724 725 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 726 BUS_DMASYNC_PREWRITE); 727 728 ring->cur = 0; 729 } 730 731 void 732 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 733 { 734 int i; 735 736 if (ring->rxd != NULL) { 737 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 738 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 739 bus_dmamap_unload(sc->sc_dmat, ring->map); 740 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd, 741 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd)); 742 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 743 } 744 if (ring->map != NULL) 745 bus_dmamap_destroy(sc->sc_dmat, ring->map); 746 747 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 748 struct rt2860_rx_data *data = &ring->data[i]; 749 750 if (data->m != NULL) { 751 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 752 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 753 bus_dmamap_unload(sc->sc_dmat, data->map); 754 m_freem(data->m); 755 } 756 if (data->map != NULL) 757 bus_dmamap_destroy(sc->sc_dmat, data->map); 758 } 759 } 760 761 struct ieee80211_node * 762 rt2860_node_alloc(struct ieee80211com *ic) 763 { 764 return malloc(sizeof (struct rt2860_node), M_DEVBUF, 765 M_NOWAIT | M_ZERO); 766 } 767 768 int 769 rt2860_media_change(struct ifnet *ifp) 770 { 771 struct rt2860_softc *sc = ifp->if_softc; 772 struct ieee80211com *ic = &sc->sc_ic; 773 uint8_t rate, ridx; 774 int error; 775 776 error = ieee80211_media_change(ifp); 777 if (error != ENETRESET) 778 return error; 779 780 if (ic->ic_fixed_rate != -1) { 781 rate = ic->ic_sup_rates[ic->ic_curmode]. 782 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 783 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 784 if (rt2860_rates[ridx].rate == rate) 785 break; 786 sc->fixed_ridx = ridx; 787 } 788 789 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 790 (IFF_UP | IFF_RUNNING)) { 791 rt2860_stop(ifp, 0); 792 rt2860_init(ifp); 793 } 794 return 0; 795 } 796 797 void 798 rt2860_iter_func(void *arg, struct ieee80211_node *ni) 799 { 800 struct rt2860_softc *sc = arg; 801 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 802 803 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]); 804 } 805 806 void 807 rt2860_updatestats(struct rt2860_softc *sc) 808 { 809 struct ieee80211com *ic = &sc->sc_ic; 810 811 #ifndef IEEE80211_STA_ONLY 812 /* 813 * In IBSS or HostAP modes (when the hardware sends beacons), the 814 * MAC can run into a livelock and start sending CTS-to-self frames 815 * like crazy if protection is enabled. Fortunately, we can detect 816 * when such a situation occurs and reset the MAC. 817 */ 818 if (ic->ic_curmode != IEEE80211_M_STA) { 819 /* check if we're in a livelock situation.. */ 820 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 821 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 822 /* ..and reset MAC/BBP for a while.. */ 823 DPRINTF(("CTS-to-self livelock detected\n")); 824 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 825 RAL_BARRIER_WRITE(sc); 826 DELAY(1); 827 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 828 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 829 } 830 } 831 #endif 832 if (ic->ic_opmode == IEEE80211_M_STA) 833 rt2860_iter_func(sc, ic->ic_bss); 834 #ifndef IEEE80211_STA_ONLY 835 else 836 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc); 837 #endif 838 } 839 840 void 841 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 842 { 843 struct rt2860_softc *sc = ic->ic_softc; 844 struct rt2860_node *rn = (void *)ni; 845 struct ieee80211_rateset *rs = &ni->ni_rates; 846 uint8_t rate, wcid = 0; 847 int ridx, i, j; 848 849 if (isnew && ni->ni_associd != 0) { 850 /* only interested in true associations */ 851 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd); 852 853 /* init WCID table entry */ 854 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 855 ni->ni_macaddr, IEEE80211_ADDR_LEN); 856 } 857 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 858 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 859 860 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]); 861 /* start at lowest available bit-rate, AMRR will raise */ 862 ni->ni_txrate = 0; 863 864 for (i = 0; i < rs->rs_nrates; i++) { 865 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 866 /* convert 802.11 rate to hardware rate index */ 867 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 868 if (rt2860_rates[ridx].rate == rate) 869 break; 870 rn->ridx[i] = ridx; 871 /* determine rate of control response frames */ 872 for (j = i; j >= 0; j--) { 873 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 874 rt2860_rates[rn->ridx[i]].phy == 875 rt2860_rates[rn->ridx[j]].phy) 876 break; 877 } 878 if (j >= 0) { 879 rn->ctl_ridx[i] = rn->ridx[j]; 880 } else { 881 /* no basic rate found, use mandatory one */ 882 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 883 } 884 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 885 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 886 } 887 } 888 889 #ifndef IEEE80211_STA_ONLY 890 void 891 rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni) 892 { 893 struct rt2860_softc *sc = ic->ic_softc; 894 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 895 896 /* clear Rx WCID search table entry */ 897 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 898 } 899 #endif 900 901 int 902 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 903 uint8_t tid) 904 { 905 struct rt2860_softc *sc = ic->ic_softc; 906 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 907 uint32_t tmp; 908 909 /* update BA session mask */ 910 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 911 tmp |= (1 << tid) << 16; 912 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 913 return 0; 914 } 915 916 void 917 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 918 uint8_t tid) 919 { 920 struct rt2860_softc *sc = ic->ic_softc; 921 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 922 uint32_t tmp; 923 924 /* update BA session mask */ 925 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 926 tmp &= ~((1 << tid) << 16); 927 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 928 } 929 930 int 931 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 932 { 933 struct rt2860_softc *sc = ic->ic_if.if_softc; 934 enum ieee80211_state ostate; 935 uint32_t tmp; 936 937 ostate = ic->ic_state; 938 939 if (ostate == IEEE80211_S_RUN) { 940 /* turn link LED off */ 941 rt2860_set_leds(sc, RT2860_LED_RADIO); 942 } 943 944 switch (nstate) { 945 case IEEE80211_S_INIT: 946 if (ostate == IEEE80211_S_RUN) { 947 /* abort TSF synchronization */ 948 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 949 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 950 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 951 RT2860_TBTT_TIMER_EN)); 952 } 953 rt2860_set_gp_timer(sc, 0); 954 break; 955 956 case IEEE80211_S_SCAN: 957 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 958 if (ostate != IEEE80211_S_SCAN) 959 rt2860_set_gp_timer(sc, 150); 960 break; 961 962 case IEEE80211_S_AUTH: 963 case IEEE80211_S_ASSOC: 964 rt2860_set_gp_timer(sc, 0); 965 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 966 break; 967 968 case IEEE80211_S_RUN: 969 rt2860_set_gp_timer(sc, 0); 970 rt2860_switch_chan(sc, ic->ic_bss->ni_chan); 971 972 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 973 rt2860_updateslot(ic); 974 rt2860_enable_mrr(sc); 975 rt2860_set_txpreamble(sc); 976 rt2860_set_basicrates(sc); 977 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid); 978 } 979 980 #ifndef IEEE80211_STA_ONLY 981 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 982 ic->ic_opmode == IEEE80211_M_IBSS) 983 (void)rt2860_setup_beacon(sc); 984 #endif 985 986 if (ic->ic_opmode == IEEE80211_M_STA) { 987 /* fake a join to init the tx rate */ 988 rt2860_newassoc(ic, ic->ic_bss, 1); 989 } 990 991 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 992 rt2860_enable_tsf_sync(sc); 993 rt2860_set_gp_timer(sc, 500); 994 } 995 996 /* turn link LED on */ 997 rt2860_set_leds(sc, RT2860_LED_RADIO | 998 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 999 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1000 break; 1001 } 1002 1003 return sc->sc_newstate(ic, nstate, arg); 1004 } 1005 1006 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 1007 uint16_t 1008 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1009 { 1010 uint32_t tmp; 1011 uint16_t reg; 1012 int ntries; 1013 1014 addr *= 2; 1015 /*- 1016 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1017 * DATA0: F E D C 1018 * DATA1: B A 9 8 1019 * DATA2: 7 6 5 4 1020 * DATA3: 3 2 1 0 1021 */ 1022 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1023 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1024 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1025 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1026 for (ntries = 0; ntries < 500; ntries++) { 1027 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1028 if (!(tmp & RT3070_EFSROM_KICK)) 1029 break; 1030 DELAY(2); 1031 } 1032 if (ntries == 500) 1033 return 0xffff; 1034 1035 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1036 return 0xffff; /* address not found */ 1037 1038 /* determine to which 32-bit register our 16-bit word belongs */ 1039 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1040 tmp = RAL_READ(sc, reg); 1041 1042 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1043 } 1044 1045 /* Read 16 bits from eFUSE ROM (RT3290 only) */ 1046 uint16_t 1047 rt3290_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 1048 { 1049 uint32_t tmp; 1050 uint16_t reg; 1051 int ntries; 1052 1053 addr *= 2; 1054 /*- 1055 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1056 * DATA3: 3 2 1 0 1057 * DATA2: 7 6 5 4 1058 * DATA1: B A 9 8 1059 * DATA0: F E D C 1060 */ 1061 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL); 1062 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1063 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1064 RAL_WRITE(sc, RT3290_EFUSE_CTRL, tmp); 1065 for (ntries = 0; ntries < 500; ntries++) { 1066 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL); 1067 if (!(tmp & RT3070_EFSROM_KICK)) 1068 break; 1069 DELAY(2); 1070 } 1071 if (ntries == 500) 1072 return 0xffff; 1073 1074 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1075 return 0xffff; /* address not found */ 1076 1077 /* determine to which 32-bit register our 16-bit word belongs */ 1078 reg = RT3290_EFUSE_DATA3 + (addr & 0xc); 1079 tmp = RAL_READ(sc, reg); 1080 1081 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1082 } 1083 1084 /* 1085 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1086 * 93C66 or 93C86). 1087 */ 1088 uint16_t 1089 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1090 { 1091 uint32_t tmp; 1092 uint16_t val; 1093 int n; 1094 1095 /* clock C once before the first command */ 1096 RT2860_EEPROM_CTL(sc, 0); 1097 1098 RT2860_EEPROM_CTL(sc, RT2860_S); 1099 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1100 RT2860_EEPROM_CTL(sc, RT2860_S); 1101 1102 /* write start bit (1) */ 1103 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1104 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1105 1106 /* write READ opcode (10) */ 1107 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1108 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1109 RT2860_EEPROM_CTL(sc, RT2860_S); 1110 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1111 1112 /* write address (A5-A0 or A7-A0) */ 1113 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1114 for (; n >= 0; n--) { 1115 RT2860_EEPROM_CTL(sc, RT2860_S | 1116 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1117 RT2860_EEPROM_CTL(sc, RT2860_S | 1118 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1119 } 1120 1121 RT2860_EEPROM_CTL(sc, RT2860_S); 1122 1123 /* read data Q15-Q0 */ 1124 val = 0; 1125 for (n = 15; n >= 0; n--) { 1126 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1127 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1128 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1129 RT2860_EEPROM_CTL(sc, RT2860_S); 1130 } 1131 1132 RT2860_EEPROM_CTL(sc, 0); 1133 1134 /* clear Chip Select and clock C */ 1135 RT2860_EEPROM_CTL(sc, RT2860_S); 1136 RT2860_EEPROM_CTL(sc, 0); 1137 RT2860_EEPROM_CTL(sc, RT2860_C); 1138 1139 return val; 1140 } 1141 1142 static __inline uint16_t 1143 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1144 { 1145 /* either eFUSE ROM or EEPROM */ 1146 return sc->sc_srom_read(sc, addr); 1147 } 1148 1149 void 1150 rt2860_intr_coherent(struct rt2860_softc *sc) 1151 { 1152 uint32_t tmp; 1153 1154 /* DMA finds data coherent event when checking the DDONE bit */ 1155 1156 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1157 1158 /* restart DMA engine */ 1159 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1160 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1161 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1162 1163 (void)rt2860_txrx_enable(sc); 1164 } 1165 1166 void 1167 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1168 { 1169 struct ifnet *ifp = &sc->sc_ic.ic_if; 1170 struct ieee80211_amrr_node *amn; 1171 uint32_t stat; 1172 uint8_t wcid, mcs, pid; 1173 1174 /* drain Tx status FIFO (maxsize = 16) */ 1175 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1176 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1177 1178 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1179 1180 /* if no ACK was requested, no feedback is available */ 1181 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff) 1182 continue; 1183 1184 /* update per-STA AMRR stats */ 1185 amn = &sc->amn[wcid]; 1186 amn->amn_txcnt++; 1187 if (stat & RT2860_TXQ_OK) { 1188 /* 1189 * Check if there were retries, ie if the Tx success 1190 * rate is different from the requested rate. Note 1191 * that it works only because we do not allow rate 1192 * fallback from OFDM to CCK. 1193 */ 1194 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1195 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1196 if (mcs + 1 != pid) 1197 amn->amn_retrycnt++; 1198 } else { 1199 amn->amn_retrycnt++; 1200 ifp->if_oerrors++; 1201 } 1202 } 1203 } 1204 1205 void 1206 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1207 { 1208 struct ieee80211com *ic = &sc->sc_ic; 1209 struct ifnet *ifp = &ic->ic_if; 1210 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1211 uint32_t hw; 1212 1213 rt2860_drain_stats_fifo(sc); 1214 1215 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1216 while (ring->next != hw) { 1217 struct rt2860_tx_data *data = ring->data[ring->next]; 1218 1219 if (data != NULL) { 1220 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1221 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1222 bus_dmamap_unload(sc->sc_dmat, data->map); 1223 m_freem(data->m); 1224 data->m= NULL; 1225 ieee80211_release_node(ic, data->ni); 1226 data->ni = NULL; 1227 1228 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1229 ring->data[ring->next] = NULL; 1230 } 1231 ring->queued--; 1232 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1233 } 1234 1235 sc->sc_tx_timer = 0; 1236 if (ring->queued <= RT2860_TX_RING_ONEMORE) 1237 sc->qfullmsk &= ~(1 << qid); 1238 ifq_clr_oactive(&ifp->if_snd); 1239 rt2860_start(ifp); 1240 } 1241 1242 /* 1243 * Return the Rx chain with the highest RSSI for a given frame. 1244 */ 1245 static __inline uint8_t 1246 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1247 { 1248 uint8_t rxchain = 0; 1249 1250 if (sc->nrxchains > 1) { 1251 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1252 rxchain = 1; 1253 if (sc->nrxchains > 2) 1254 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1255 rxchain = 2; 1256 } 1257 return rxchain; 1258 } 1259 1260 void 1261 rt2860_rx_intr(struct rt2860_softc *sc) 1262 { 1263 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1264 struct ieee80211com *ic = &sc->sc_ic; 1265 struct ifnet *ifp = &ic->ic_if; 1266 struct ieee80211_frame *wh; 1267 struct ieee80211_rxinfo rxi; 1268 struct ieee80211_node *ni; 1269 struct mbuf *m, *m1; 1270 uint32_t hw; 1271 uint8_t ant, rssi; 1272 int error; 1273 #if NBPFILTER > 0 1274 struct rt2860_rx_radiotap_header *tap; 1275 struct mbuf mb; 1276 uint16_t phy; 1277 #endif 1278 1279 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1280 while (sc->rxq.cur != hw) { 1281 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1282 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1283 struct rt2860_rxwi *rxwi; 1284 1285 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1286 sc->rxq.cur * sizeof (struct rt2860_rxd), 1287 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD); 1288 1289 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1290 DPRINTF(("RXD DDONE bit not set!\n")); 1291 break; /* should not happen */ 1292 } 1293 1294 if (__predict_false(rxd->flags & 1295 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1296 ifp->if_ierrors++; 1297 goto skip; 1298 } 1299 1300 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1301 /* report MIC failures to net80211 for TKIP */ 1302 ic->ic_stats.is_rx_locmicfail++; 1303 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1304 ifp->if_ierrors++; 1305 goto skip; 1306 } 1307 1308 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, MCLBYTES); 1309 if (__predict_false(m1 == NULL)) { 1310 ifp->if_ierrors++; 1311 goto skip; 1312 } 1313 1314 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1315 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1316 bus_dmamap_unload(sc->sc_dmat, data->map); 1317 1318 error = bus_dmamap_load(sc->sc_dmat, data->map, 1319 mtod(m1, void *), MCLBYTES, NULL, 1320 BUS_DMA_READ | BUS_DMA_NOWAIT); 1321 if (__predict_false(error != 0)) { 1322 m_freem(m1); 1323 1324 /* try to reload the old mbuf */ 1325 error = bus_dmamap_load(sc->sc_dmat, data->map, 1326 mtod(data->m, void *), MCLBYTES, NULL, 1327 BUS_DMA_READ | BUS_DMA_NOWAIT); 1328 if (__predict_false(error != 0)) { 1329 panic("%s: could not load old rx mbuf", 1330 sc->sc_dev.dv_xname); 1331 } 1332 /* physical address may have changed */ 1333 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1334 ifp->if_ierrors++; 1335 goto skip; 1336 } 1337 1338 /* 1339 * New mbuf successfully loaded, update Rx ring and continue 1340 * processing. 1341 */ 1342 m = data->m; 1343 data->m = m1; 1344 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr); 1345 1346 rxwi = mtod(m, struct rt2860_rxwi *); 1347 1348 /* finalize mbuf */ 1349 m->m_data = (caddr_t)(rxwi + 1); 1350 m->m_pkthdr.len = m->m_len = letoh16(rxwi->len) & 0xfff; 1351 1352 wh = mtod(m, struct ieee80211_frame *); 1353 rxi.rxi_flags = 0; 1354 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1355 /* frame is decrypted by hardware */ 1356 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1357 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1358 } 1359 1360 /* HW may insert 2 padding bytes after 802.11 header */ 1361 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1362 u_int hdrlen = ieee80211_get_hdrlen(wh); 1363 memmove((caddr_t)wh + 2, wh, hdrlen); 1364 m->m_data += 2; 1365 wh = mtod(m, struct ieee80211_frame *); 1366 } 1367 1368 ant = rt2860_maxrssi_chain(sc, rxwi); 1369 rssi = rxwi->rssi[ant]; 1370 1371 #if NBPFILTER > 0 1372 if (__predict_true(sc->sc_drvbpf == NULL)) 1373 goto skipbpf; 1374 1375 tap = &sc->sc_rxtap; 1376 tap->wr_flags = 0; 1377 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1378 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1379 tap->wr_antsignal = rssi; 1380 tap->wr_antenna = ant; 1381 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant); 1382 tap->wr_rate = 2; /* in case it can't be found below */ 1383 phy = letoh16(rxwi->phy); 1384 switch (phy & RT2860_PHY_MODE) { 1385 case RT2860_PHY_CCK: 1386 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1387 case 0: tap->wr_rate = 2; break; 1388 case 1: tap->wr_rate = 4; break; 1389 case 2: tap->wr_rate = 11; break; 1390 case 3: tap->wr_rate = 22; break; 1391 } 1392 if (phy & RT2860_PHY_SHPRE) 1393 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1394 break; 1395 case RT2860_PHY_OFDM: 1396 switch (phy & RT2860_PHY_MCS) { 1397 case 0: tap->wr_rate = 12; break; 1398 case 1: tap->wr_rate = 18; break; 1399 case 2: tap->wr_rate = 24; break; 1400 case 3: tap->wr_rate = 36; break; 1401 case 4: tap->wr_rate = 48; break; 1402 case 5: tap->wr_rate = 72; break; 1403 case 6: tap->wr_rate = 96; break; 1404 case 7: tap->wr_rate = 108; break; 1405 } 1406 break; 1407 } 1408 mb.m_data = (caddr_t)tap; 1409 mb.m_len = sc->sc_rxtap_len; 1410 mb.m_next = m; 1411 mb.m_nextpkt = NULL; 1412 mb.m_type = 0; 1413 mb.m_flags = 0; 1414 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1415 skipbpf: 1416 #endif 1417 /* grab a reference to the source node */ 1418 ni = ieee80211_find_rxnode(ic, wh); 1419 1420 /* send the frame to the 802.11 layer */ 1421 rxi.rxi_rssi = rssi; 1422 rxi.rxi_tstamp = 0; /* unused */ 1423 ieee80211_inputm(ifp, m, ni, &rxi, &ml); 1424 1425 /* node is no longer needed */ 1426 ieee80211_release_node(ic, ni); 1427 1428 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1429 1430 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1431 sc->rxq.cur * sizeof (struct rt2860_rxd), 1432 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE); 1433 1434 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1435 } 1436 if_input(ifp, &ml); 1437 1438 /* tell HW what we have processed */ 1439 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1440 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1441 } 1442 1443 void 1444 rt2860_tbtt_intr(struct rt2860_softc *sc) 1445 { 1446 struct ieee80211com *ic = &sc->sc_ic; 1447 1448 #ifndef IEEE80211_STA_ONLY 1449 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1450 /* one less beacon until next DTIM */ 1451 if (ic->ic_dtim_count == 0) 1452 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1453 else 1454 ic->ic_dtim_count--; 1455 1456 /* update dynamic parts of beacon */ 1457 rt2860_setup_beacon(sc); 1458 1459 /* flush buffered multicast frames */ 1460 if (ic->ic_dtim_count == 0) 1461 ieee80211_notify_dtim(ic); 1462 } 1463 #endif 1464 /* check if protection mode has changed */ 1465 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1466 rt2860_updateprot(ic); 1467 sc->sc_ic_flags = ic->ic_flags; 1468 } 1469 } 1470 1471 void 1472 rt2860_gp_intr(struct rt2860_softc *sc) 1473 { 1474 struct ieee80211com *ic = &sc->sc_ic; 1475 1476 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state)); 1477 1478 if (ic->ic_state == IEEE80211_S_SCAN) 1479 ieee80211_next_scan(&ic->ic_if); 1480 else if (ic->ic_state == IEEE80211_S_RUN) 1481 rt2860_updatestats(sc); 1482 } 1483 1484 int 1485 rt2860_intr(void *arg) 1486 { 1487 struct rt2860_softc *sc = arg; 1488 uint32_t r; 1489 1490 r = RAL_READ(sc, RT2860_INT_STATUS); 1491 if (__predict_false(r == 0xffffffff)) 1492 return 0; /* device likely went away */ 1493 if (r == 0) 1494 return 0; /* not for us */ 1495 1496 /* acknowledge interrupts */ 1497 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1498 1499 if (r & RT2860_TX_RX_COHERENT) 1500 rt2860_intr_coherent(sc); 1501 1502 if (r & RT2860_MAC_INT_2) /* TX status */ 1503 rt2860_drain_stats_fifo(sc); 1504 1505 if (r & RT2860_TX_DONE_INT5) 1506 rt2860_tx_intr(sc, 5); 1507 1508 if (r & RT2860_RX_DONE_INT) 1509 rt2860_rx_intr(sc); 1510 1511 if (r & RT2860_TX_DONE_INT4) 1512 rt2860_tx_intr(sc, 4); 1513 1514 if (r & RT2860_TX_DONE_INT3) 1515 rt2860_tx_intr(sc, 3); 1516 1517 if (r & RT2860_TX_DONE_INT2) 1518 rt2860_tx_intr(sc, 2); 1519 1520 if (r & RT2860_TX_DONE_INT1) 1521 rt2860_tx_intr(sc, 1); 1522 1523 if (r & RT2860_TX_DONE_INT0) 1524 rt2860_tx_intr(sc, 0); 1525 1526 if (r & RT2860_MAC_INT_0) /* TBTT */ 1527 rt2860_tbtt_intr(sc); 1528 1529 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1530 /* TBD wakeup */; 1531 1532 if (r & RT2860_MAC_INT_4) /* GP timer */ 1533 rt2860_gp_intr(sc); 1534 1535 return 1; 1536 } 1537 1538 int 1539 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1540 { 1541 struct ieee80211com *ic = &sc->sc_ic; 1542 struct rt2860_node *rn = (void *)ni; 1543 struct rt2860_tx_ring *ring; 1544 struct rt2860_tx_data *data; 1545 struct rt2860_txd *txd; 1546 struct rt2860_txwi *txwi; 1547 struct ieee80211_frame *wh; 1548 bus_dma_segment_t *seg; 1549 u_int hdrlen; 1550 uint16_t qos, dur; 1551 uint8_t type, qsel, mcs, pid, tid, qid; 1552 int nsegs, hasqos, ridx, ctl_ridx; 1553 1554 /* the data pool contains at least one element, pick the first */ 1555 data = SLIST_FIRST(&sc->data_pool); 1556 1557 wh = mtod(m, struct ieee80211_frame *); 1558 hdrlen = ieee80211_get_hdrlen(wh); 1559 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1560 1561 if ((hasqos = ieee80211_has_qos(wh))) { 1562 qos = ieee80211_get_qos(wh); 1563 tid = qos & IEEE80211_QOS_TID; 1564 qid = ieee80211_up_to_ac(ic, tid); 1565 } else { 1566 qos = 0; 1567 tid = 0; 1568 qid = (type == IEEE80211_FC0_TYPE_MGT) ? 1569 sc->mgtqid : EDCA_AC_BE; 1570 } 1571 ring = &sc->txq[qid]; 1572 1573 /* pickup a rate index */ 1574 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1575 type != IEEE80211_FC0_TYPE_DATA) { 1576 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1577 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 1578 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1579 } else if (ic->ic_fixed_rate != -1) { 1580 ridx = sc->fixed_ridx; 1581 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 1582 } else { 1583 ridx = rn->ridx[ni->ni_txrate]; 1584 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 1585 } 1586 1587 /* get MCS code from rate index */ 1588 mcs = rt2860_rates[ridx].mcs; 1589 1590 /* setup TX Wireless Information */ 1591 txwi = data->txwi; 1592 txwi->flags = 0; 1593 /* let HW generate seq numbers for non-QoS frames */ 1594 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 1595 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff; 1596 txwi->len = htole16(m->m_pkthdr.len); 1597 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1598 txwi->phy = htole16(RT2860_PHY_CCK); 1599 if (ridx != RT2860_RIDX_CCK1 && 1600 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1601 mcs |= RT2860_PHY_SHPRE; 1602 } else 1603 txwi->phy = htole16(RT2860_PHY_OFDM); 1604 txwi->phy |= htole16(mcs); 1605 1606 /* 1607 * We store the MCS code into the driver-private PacketID field. 1608 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1609 * that we know at which initial rate the frame was transmitted. 1610 * We add 1 to the MCS code because setting the PacketID field to 1611 * 0 means that we don't want feedback in TX_STAT_FIFO. 1612 */ 1613 pid = (mcs + 1) & 0xf; 1614 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1615 1616 /* check if RTS/CTS or CTS-to-self protection is required */ 1617 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1618 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold || 1619 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1620 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1621 txwi->txop = RT2860_TX_TXOP_HT; 1622 else 1623 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1624 1625 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1626 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 1627 IEEE80211_QOS_ACK_POLICY_NOACK)) { 1628 txwi->xflags |= RT2860_TX_ACK; 1629 1630 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1631 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 1632 else 1633 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 1634 *(uint16_t *)wh->i_dur = htole16(dur); 1635 } 1636 #ifndef IEEE80211_STA_ONLY 1637 /* ask MAC to insert timestamp into probe responses */ 1638 if ((wh->i_fc[0] & 1639 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1640 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1641 /* NOTE: beacons do not pass through tx_data() */ 1642 txwi->flags |= RT2860_TX_TS; 1643 #endif 1644 1645 #if NBPFILTER > 0 1646 if (__predict_false(sc->sc_drvbpf != NULL)) { 1647 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1648 struct mbuf mb; 1649 1650 tap->wt_flags = 0; 1651 tap->wt_rate = rt2860_rates[ridx].rate; 1652 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1653 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1654 tap->wt_hwqueue = qid; 1655 if (mcs & RT2860_PHY_SHPRE) 1656 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1657 1658 mb.m_data = (caddr_t)tap; 1659 mb.m_len = sc->sc_txtap_len; 1660 mb.m_next = m; 1661 mb.m_nextpkt = NULL; 1662 mb.m_type = 0; 1663 mb.m_flags = 0; 1664 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1665 } 1666 #endif 1667 1668 /* copy and trim 802.11 header */ 1669 memcpy(txwi + 1, wh, hdrlen); 1670 m_adj(m, hdrlen); 1671 1672 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE); /* <1> */ 1673 1674 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)) { 1675 if (m_defrag(m, M_DONTWAIT)) 1676 return (ENOBUFS); 1677 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1678 data->map, m, BUS_DMA_NOWAIT)) 1679 return (EFBIG); 1680 } 1681 1682 /* The map will fit into the tx ring: (a "full" ring may have a few 1683 * unused descriptors, at most (txds(MAX_SCATTER) - 1)) 1684 * 1685 * ring->queued + txds(data->map->nsegs) 1686 * <= { <0> data->map->nsegs <= MAX_SCATTER } 1687 * ring->queued + txds(MAX_SCATTER) 1688 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) } 1689 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER) 1690 * <= { arithmetic } 1691 * TX_RING_MAX 1692 */ 1693 1694 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1695 1696 /* first segment is TXWI + 802.11 header */ 1697 txd = &ring->txd[ring->cur]; 1698 txd->sdp0 = htole32(data->paddr); 1699 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen); 1700 txd->flags = qsel; 1701 1702 /* setup payload segments */ 1703 seg = data->map->dm_segs; 1704 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) { 1705 txd->sdp1 = htole32(seg->ds_addr); 1706 txd->sdl1 = htole16(seg->ds_len); 1707 seg++; 1708 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1709 /* grab a new Tx descriptor */ 1710 txd = &ring->txd[ring->cur]; 1711 txd->sdp0 = htole32(seg->ds_addr); 1712 txd->sdl0 = htole16(seg->ds_len); 1713 txd->flags = qsel; 1714 seg++; 1715 } 1716 /* finalize last segment */ 1717 if (nsegs > 0) { 1718 txd->sdp1 = htole32(seg->ds_addr); 1719 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1720 } else { 1721 txd->sdl0 |= htole16(RT2860_TX_LS0); 1722 txd->sdl1 = 0; 1723 } 1724 1725 /* remove from the free pool and link it into the SW Tx slot */ 1726 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1727 data->m = m; 1728 data->ni = ni; 1729 ring->data[ring->cur] = data; 1730 1731 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 1732 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ, 1733 BUS_DMASYNC_PREWRITE); 1734 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1735 BUS_DMASYNC_PREWRITE); 1736 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 1737 BUS_DMASYNC_PREWRITE); 1738 1739 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1740 qid, txwi->wcid, data->map->dm_nsegs, ridx)); 1741 1742 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1743 ring->queued += 1 + (data->map->dm_nsegs / 2); 1744 if (ring->queued > RT2860_TX_RING_ONEMORE) 1745 sc->qfullmsk |= 1 << qid; 1746 1747 /* kick Tx */ 1748 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1749 1750 return 0; 1751 } 1752 1753 void 1754 rt2860_start(struct ifnet *ifp) 1755 { 1756 struct rt2860_softc *sc = ifp->if_softc; 1757 struct ieee80211com *ic = &sc->sc_ic; 1758 struct ieee80211_node *ni; 1759 struct mbuf *m; 1760 1761 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1762 return; 1763 1764 for (;;) { 1765 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1766 ifq_set_oactive(&ifp->if_snd); 1767 break; 1768 } 1769 /* send pending management frames first */ 1770 m = mq_dequeue(&ic->ic_mgtq); 1771 if (m != NULL) { 1772 ni = m->m_pkthdr.ph_cookie; 1773 goto sendit; 1774 } 1775 if (ic->ic_state != IEEE80211_S_RUN) 1776 break; 1777 1778 /* send buffered frames for power-save mode */ 1779 m = mq_dequeue(&ic->ic_pwrsaveq); 1780 if (m != NULL) { 1781 ni = m->m_pkthdr.ph_cookie; 1782 goto sendit; 1783 } 1784 1785 /* encapsulate and send data frames */ 1786 IFQ_DEQUEUE(&ifp->if_snd, m); 1787 if (m == NULL) 1788 break; 1789 #if NBPFILTER > 0 1790 if (ifp->if_bpf != NULL) 1791 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1792 #endif 1793 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1794 continue; 1795 sendit: 1796 #if NBPFILTER > 0 1797 if (ic->ic_rawbpf != NULL) 1798 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1799 #endif 1800 if (rt2860_tx(sc, m, ni) != 0) { 1801 m_freem(m); 1802 ieee80211_release_node(ic, ni); 1803 ifp->if_oerrors++; 1804 continue; 1805 } 1806 1807 sc->sc_tx_timer = 5; 1808 ifp->if_timer = 1; 1809 } 1810 } 1811 1812 void 1813 rt2860_watchdog(struct ifnet *ifp) 1814 { 1815 struct rt2860_softc *sc = ifp->if_softc; 1816 1817 ifp->if_timer = 0; 1818 1819 if (sc->sc_tx_timer > 0) { 1820 if (--sc->sc_tx_timer == 0) { 1821 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1822 rt2860_stop(ifp, 0); 1823 rt2860_init(ifp); 1824 ifp->if_oerrors++; 1825 return; 1826 } 1827 ifp->if_timer = 1; 1828 } 1829 1830 ieee80211_watchdog(ifp); 1831 } 1832 1833 int 1834 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1835 { 1836 struct rt2860_softc *sc = ifp->if_softc; 1837 struct ieee80211com *ic = &sc->sc_ic; 1838 int s, error = 0; 1839 1840 s = splnet(); 1841 1842 switch (cmd) { 1843 case SIOCSIFADDR: 1844 ifp->if_flags |= IFF_UP; 1845 /* FALLTHROUGH */ 1846 case SIOCSIFFLAGS: 1847 if (ifp->if_flags & IFF_UP) { 1848 if (!(ifp->if_flags & IFF_RUNNING)) 1849 rt2860_init(ifp); 1850 } else { 1851 if (ifp->if_flags & IFF_RUNNING) 1852 rt2860_stop(ifp, 1); 1853 } 1854 break; 1855 1856 case SIOCS80211CHANNEL: 1857 /* 1858 * This allows for fast channel switching in monitor mode 1859 * (used by kismet). In IBSS mode, we must explicitly reset 1860 * the interface to generate a new beacon frame. 1861 */ 1862 error = ieee80211_ioctl(ifp, cmd, data); 1863 if (error == ENETRESET && 1864 ic->ic_opmode == IEEE80211_M_MONITOR) { 1865 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1866 (IFF_UP | IFF_RUNNING)) 1867 rt2860_switch_chan(sc, ic->ic_ibss_chan); 1868 error = 0; 1869 } 1870 break; 1871 1872 default: 1873 error = ieee80211_ioctl(ifp, cmd, data); 1874 } 1875 1876 if (error == ENETRESET) { 1877 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1878 (IFF_UP | IFF_RUNNING)) { 1879 rt2860_stop(ifp, 0); 1880 rt2860_init(ifp); 1881 } 1882 error = 0; 1883 } 1884 1885 splx(s); 1886 1887 return error; 1888 } 1889 1890 /* 1891 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 1892 * We access the BBP through the 8051 microcontroller unit which means that 1893 * the microcode must be loaded first. 1894 */ 1895 void 1896 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 1897 { 1898 int ntries; 1899 1900 for (ntries = 0; ntries < 100; ntries++) { 1901 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1902 break; 1903 DELAY(1); 1904 } 1905 if (ntries == 100) { 1906 printf("%s: could not write to BBP through MCU\n", 1907 sc->sc_dev.dv_xname); 1908 return; 1909 } 1910 1911 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1912 RT2860_BBP_CSR_KICK | reg << 8 | val); 1913 RAL_BARRIER_WRITE(sc); 1914 1915 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1916 DELAY(1000); 1917 } 1918 1919 uint8_t 1920 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 1921 { 1922 uint32_t val; 1923 int ntries; 1924 1925 for (ntries = 0; ntries < 100; ntries++) { 1926 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 1927 break; 1928 DELAY(1); 1929 } 1930 if (ntries == 100) { 1931 printf("%s: could not read from BBP through MCU\n", 1932 sc->sc_dev.dv_xname); 1933 return 0; 1934 } 1935 1936 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 1937 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 1938 RAL_BARRIER_WRITE(sc); 1939 1940 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 1941 DELAY(1000); 1942 1943 for (ntries = 0; ntries < 100; ntries++) { 1944 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 1945 if (!(val & RT2860_BBP_CSR_KICK)) 1946 return val & 0xff; 1947 DELAY(1); 1948 } 1949 printf("%s: could not read from BBP through MCU\n", 1950 sc->sc_dev.dv_xname); 1951 1952 return 0; 1953 } 1954 1955 /* 1956 * Write to one of the 4 programmable 24-bit RF registers. 1957 */ 1958 void 1959 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 1960 { 1961 uint32_t tmp; 1962 int ntries; 1963 1964 for (ntries = 0; ntries < 100; ntries++) { 1965 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 1966 break; 1967 DELAY(1); 1968 } 1969 if (ntries == 100) { 1970 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 1971 return; 1972 } 1973 1974 /* RF registers are 24-bit on the RT2860 */ 1975 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1976 (val & 0x3fffff) << 2 | (reg & 3); 1977 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 1978 } 1979 1980 uint8_t 1981 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 1982 { 1983 uint32_t tmp; 1984 int ntries; 1985 1986 for (ntries = 0; ntries < 100; ntries++) { 1987 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 1988 break; 1989 DELAY(1); 1990 } 1991 if (ntries == 100) { 1992 printf("%s: could not read RF register\n", 1993 sc->sc_dev.dv_xname); 1994 return 0xff; 1995 } 1996 tmp = RT3070_RF_KICK | reg << 8; 1997 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 1998 1999 for (ntries = 0; ntries < 100; ntries++) { 2000 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2001 if (!(tmp & RT3070_RF_KICK)) 2002 break; 2003 DELAY(1); 2004 } 2005 if (ntries == 100) { 2006 printf("%s: could not read RF register\n", 2007 sc->sc_dev.dv_xname); 2008 return 0xff; 2009 } 2010 return tmp & 0xff; 2011 } 2012 2013 void 2014 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2015 { 2016 uint32_t tmp; 2017 int ntries; 2018 2019 for (ntries = 0; ntries < 10; ntries++) { 2020 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2021 break; 2022 DELAY(10); 2023 } 2024 if (ntries == 10) { 2025 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2026 return; 2027 } 2028 2029 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2030 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2031 } 2032 2033 /* 2034 * Send a command to the 8051 microcontroller unit. 2035 */ 2036 int 2037 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2038 { 2039 int slot, ntries; 2040 uint32_t tmp; 2041 uint8_t cid; 2042 2043 for (ntries = 0; ntries < 100; ntries++) { 2044 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2045 break; 2046 DELAY(2); 2047 } 2048 if (ntries == 100) 2049 return EIO; 2050 2051 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2052 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2053 RAL_BARRIER_WRITE(sc); 2054 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2055 2056 if (!wait) 2057 return 0; 2058 /* wait for the command to complete */ 2059 for (ntries = 0; ntries < 200; ntries++) { 2060 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2061 /* find the command slot */ 2062 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2063 if ((tmp & 0xff) == cid) 2064 break; 2065 if (slot < 4) 2066 break; 2067 DELAY(100); 2068 } 2069 if (ntries == 200) { 2070 /* clear command and status */ 2071 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2072 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2073 return ETIMEDOUT; 2074 } 2075 /* get command status (1 means success) */ 2076 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2077 tmp = (tmp >> (slot * 8)) & 0xff; 2078 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2079 cmd, slot, tmp)); 2080 /* clear command and status */ 2081 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2082 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2083 return (tmp == 1) ? 0 : EIO; 2084 } 2085 2086 void 2087 rt2860_enable_mrr(struct rt2860_softc *sc) 2088 { 2089 #define CCK(mcs) (mcs) 2090 #define OFDM(mcs) (1 << 3 | (mcs)) 2091 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2092 OFDM(6) << 28 | /* 54->48 */ 2093 OFDM(5) << 24 | /* 48->36 */ 2094 OFDM(4) << 20 | /* 36->24 */ 2095 OFDM(3) << 16 | /* 24->18 */ 2096 OFDM(2) << 12 | /* 18->12 */ 2097 OFDM(1) << 8 | /* 12-> 9 */ 2098 OFDM(0) << 4 | /* 9-> 6 */ 2099 OFDM(0)); /* 6-> 6 */ 2100 2101 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2102 CCK(2) << 12 | /* 11->5.5 */ 2103 CCK(1) << 8 | /* 5.5-> 2 */ 2104 CCK(0) << 4 | /* 2-> 1 */ 2105 CCK(0)); /* 1-> 1 */ 2106 #undef OFDM 2107 #undef CCK 2108 } 2109 2110 void 2111 rt2860_set_txpreamble(struct rt2860_softc *sc) 2112 { 2113 uint32_t tmp; 2114 2115 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2116 tmp &= ~RT2860_CCK_SHORT_EN; 2117 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2118 tmp |= RT2860_CCK_SHORT_EN; 2119 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2120 } 2121 2122 void 2123 rt2860_set_basicrates(struct rt2860_softc *sc) 2124 { 2125 struct ieee80211com *ic = &sc->sc_ic; 2126 2127 /* set basic rates mask */ 2128 if (ic->ic_curmode == IEEE80211_MODE_11B) 2129 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 2130 else if (ic->ic_curmode == IEEE80211_MODE_11A) 2131 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 2132 else /* 11g */ 2133 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 2134 } 2135 2136 void 2137 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2138 { 2139 uint32_t tmp; 2140 uint8_t agc; 2141 2142 /* Wait for BBP to settle */ 2143 DELAY(1000); 2144 2145 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2146 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2147 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2148 rt2860_mcu_bbp_write(sc, 86, 0x00); 2149 2150 if (group == 0) { 2151 if (sc->ext_2ghz_lna) { 2152 rt2860_mcu_bbp_write(sc, 82, 0x62); 2153 rt2860_mcu_bbp_write(sc, 75, 0x46); 2154 } else { 2155 rt2860_mcu_bbp_write(sc, 82, 0x84); 2156 rt2860_mcu_bbp_write(sc, 75, 0x50); 2157 } 2158 } else { 2159 if (sc->mac_ver == 0x3572) 2160 rt2860_mcu_bbp_write(sc, 82, 0x94); 2161 else 2162 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2163 2164 if (sc->ext_5ghz_lna) 2165 rt2860_mcu_bbp_write(sc, 75, 0x46); 2166 else 2167 rt2860_mcu_bbp_write(sc, 75, 0x50); 2168 } 2169 2170 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2171 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2172 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2173 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2174 2175 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2176 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2177 if (sc->nrxchains > 1) 2178 tmp |= RT2860_LNA_PE1_EN; 2179 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2180 tmp |= RT3593_LNA_PE2_EN; 2181 if (group == 0) { /* 2GHz */ 2182 tmp |= RT2860_PA_PE_G0_EN; 2183 if (sc->ntxchains > 1) 2184 tmp |= RT2860_PA_PE_G1_EN; 2185 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2186 tmp |= RT3593_PA_PE_G2_EN; 2187 } else { /* 5GHz */ 2188 tmp |= RT2860_PA_PE_A0_EN; 2189 if (sc->ntxchains > 1) 2190 tmp |= RT2860_PA_PE_A1_EN; 2191 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2192 tmp |= RT3593_PA_PE_A2_EN; 2193 } 2194 if (sc->mac_ver == 0x3572) { 2195 rt3090_rf_write(sc, 8, 0x00); 2196 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2197 rt3090_rf_write(sc, 8, 0x80); 2198 } else 2199 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2200 2201 if (sc->mac_ver == 0x3593) { 2202 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2203 if (sc->sc_flags & RT2860_PCIE) { 2204 tmp &= ~0x01010000; 2205 if (group == 0) 2206 tmp |= 0x00010000; 2207 } else { 2208 tmp &= ~0x00008080; 2209 if (group == 0) 2210 tmp |= 0x00000080; 2211 } 2212 tmp = (tmp & ~0x00001000) | 0x00000010; 2213 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2214 } 2215 2216 /* set initial AGC value */ 2217 if (group == 0) { /* 2GHz band */ 2218 if (sc->mac_ver >= 0x3071) 2219 agc = 0x1c + sc->lna[0] * 2; 2220 else 2221 agc = 0x2e + sc->lna[0]; 2222 } else { /* 5GHz band */ 2223 if (sc->mac_ver == 0x3572) 2224 agc = 0x22 + (sc->lna[group] * 5) / 3; 2225 else 2226 agc = 0x32 + (sc->lna[group] * 5) / 3; 2227 } 2228 rt2860_mcu_bbp_write(sc, 66, agc); 2229 2230 DELAY(1000); 2231 } 2232 2233 void 2234 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2235 { 2236 const struct rfprog *rfprog = rt2860_rf2850; 2237 uint32_t r2, r3, r4; 2238 int8_t txpow1, txpow2; 2239 u_int i; 2240 2241 /* find the settings for this channel (we know it exists) */ 2242 for (i = 0; rfprog[i].chan != chan; i++); 2243 2244 r2 = rfprog[i].r2; 2245 if (sc->ntxchains == 1) 2246 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2247 if (sc->nrxchains == 1) 2248 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2249 else if (sc->nrxchains == 2) 2250 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2251 2252 /* use Tx power values from EEPROM */ 2253 txpow1 = sc->txpow1[i]; 2254 txpow2 = sc->txpow2[i]; 2255 if (chan > 14) { 2256 if (txpow1 >= 0) 2257 txpow1 = txpow1 << 1 | 1; 2258 else 2259 txpow1 = (7 + txpow1) << 1; 2260 if (txpow2 >= 0) 2261 txpow2 = txpow2 << 1 | 1; 2262 else 2263 txpow2 = (7 + txpow2) << 1; 2264 } 2265 r3 = rfprog[i].r3 | txpow1 << 7; 2266 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2267 2268 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2269 rt2860_rf_write(sc, RT2860_RF2, r2); 2270 rt2860_rf_write(sc, RT2860_RF3, r3); 2271 rt2860_rf_write(sc, RT2860_RF4, r4); 2272 2273 DELAY(200); 2274 2275 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2276 rt2860_rf_write(sc, RT2860_RF2, r2); 2277 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2278 rt2860_rf_write(sc, RT2860_RF4, r4); 2279 2280 DELAY(200); 2281 2282 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2283 rt2860_rf_write(sc, RT2860_RF2, r2); 2284 rt2860_rf_write(sc, RT2860_RF3, r3); 2285 rt2860_rf_write(sc, RT2860_RF4, r4); 2286 } 2287 2288 void 2289 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2290 { 2291 int8_t txpow1, txpow2; 2292 uint8_t rf; 2293 int i; 2294 2295 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */ 2296 2297 /* find the settings for this channel (we know it exists) */ 2298 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2299 2300 /* use Tx power values from EEPROM */ 2301 txpow1 = sc->txpow1[i]; 2302 txpow2 = sc->txpow2[i]; 2303 2304 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2305 rf = rt3090_rf_read(sc, 3); 2306 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2307 rt3090_rf_write(sc, 3, rf); 2308 rf = rt3090_rf_read(sc, 6); 2309 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2310 rt3090_rf_write(sc, 6, rf); 2311 2312 /* set Tx0 power */ 2313 rf = rt3090_rf_read(sc, 12); 2314 rf = (rf & ~0x1f) | txpow1; 2315 rt3090_rf_write(sc, 12, rf); 2316 2317 /* set Tx1 power */ 2318 rf = rt3090_rf_read(sc, 13); 2319 rf = (rf & ~0x1f) | txpow2; 2320 rt3090_rf_write(sc, 13, rf); 2321 2322 rf = rt3090_rf_read(sc, 1); 2323 rf &= ~0xfc; 2324 if (sc->ntxchains == 1) 2325 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2326 else if (sc->ntxchains == 2) 2327 rf |= RT3070_TX2_PD; 2328 if (sc->nrxchains == 1) 2329 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2330 else if (sc->nrxchains == 2) 2331 rf |= RT3070_RX2_PD; 2332 rt3090_rf_write(sc, 1, rf); 2333 2334 /* set RF offset */ 2335 rf = rt3090_rf_read(sc, 23); 2336 rf = (rf & ~0x7f) | sc->freq; 2337 rt3090_rf_write(sc, 23, rf); 2338 2339 /* program RF filter */ 2340 rf = rt3090_rf_read(sc, 24); /* Tx */ 2341 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2342 rt3090_rf_write(sc, 24, rf); 2343 rf = rt3090_rf_read(sc, 31); /* Rx */ 2344 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2345 rt3090_rf_write(sc, 31, rf); 2346 2347 /* enable RF tuning */ 2348 rf = rt3090_rf_read(sc, 7); 2349 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2350 } 2351 2352 void 2353 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2354 { 2355 uint8_t h20mhz, rf, tmp; 2356 int8_t txpow1, txpow2; 2357 int i; 2358 2359 /* RT5390 is 2GHz only */ 2360 KASSERT(chan >= 1 && chan <= 14); 2361 2362 /* find the settings for this channel (we know it exists) */ 2363 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2364 2365 /* use Tx power values from EEPROM */ 2366 txpow1 = sc->txpow1[i]; 2367 txpow2 = sc->txpow2[i]; 2368 2369 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2370 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2371 rf = rt3090_rf_read(sc, 11); 2372 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2373 rt3090_rf_write(sc, 11, rf); 2374 2375 rf = rt3090_rf_read(sc, 49); 2376 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2377 /* the valid range of the RF R49 is 0x00~0x27 */ 2378 if ((rf & 0x3f) > 0x27) 2379 rf = (rf & ~0x3f) | 0x27; 2380 rt3090_rf_write(sc, 49, rf); 2381 if (sc->mac_ver == 0x5392) { 2382 rf = rt3090_rf_read(sc, 50); 2383 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2384 /* the valid range of the RF R50 is 0x00~0x27 */ 2385 if ((rf & 0x3f) > 0x27) 2386 rf = (rf & ~0x3f) | 0x27; 2387 rt3090_rf_write(sc, 50, rf); 2388 } 2389 2390 rf = rt3090_rf_read(sc, 1); 2391 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2392 if (sc->mac_ver == 0x5392) 2393 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2394 rt3090_rf_write(sc, 1, rf); 2395 2396 rf = rt3090_rf_read(sc, 2); 2397 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2398 DELAY(1000); 2399 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2400 2401 rf = rt3090_rf_read(sc, 17); 2402 tmp = rf; 2403 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2404 rf = MIN(rf, 0x5f); 2405 if (tmp != rf) 2406 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2407 2408 if (sc->mac_ver == 0x5390) { 2409 if (chan <= 4) 2410 rf = 0x73; 2411 else if (chan >= 5 && chan <= 6) 2412 rf = 0x63; 2413 else if (chan >= 7 && chan <= 10) 2414 rf = 0x53; 2415 else 2416 rf = 43; 2417 rt3090_rf_write(sc, 55, rf); 2418 2419 if (chan == 1) 2420 rf = 0x0c; 2421 else if (chan == 2) 2422 rf = 0x0b; 2423 else if (chan == 3) 2424 rf = 0x0a; 2425 else if (chan >= 4 && chan <= 6) 2426 rf = 0x09; 2427 else if (chan >= 7 && chan <= 12) 2428 rf = 0x08; 2429 else if (chan == 13) 2430 rf = 0x07; 2431 else 2432 rf = 0x06; 2433 rt3090_rf_write(sc, 59, rf); 2434 } else if (sc->mac_ver == 0x3290) { 2435 if (chan == 6) 2436 rt2860_mcu_bbp_write(sc, 68, 0x0c); 2437 else 2438 rt2860_mcu_bbp_write(sc, 68, 0x0b); 2439 2440 if (chan >= 1 && chan < 6) 2441 rf = 0x0f; 2442 else if (chan >= 7 && chan <= 11) 2443 rf = 0x0e; 2444 else if (chan >= 12 && chan <= 14) 2445 rf = 0x0d; 2446 rt3090_rf_write(sc, 59, rf); 2447 } 2448 2449 /* Tx/Rx h20M */ 2450 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2451 rf = rt3090_rf_read(sc, 30); 2452 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2453 rt3090_rf_write(sc, 30, rf); 2454 2455 /* Rx BB filter VCM */ 2456 rf = rt3090_rf_read(sc, 30); 2457 rf = (rf & ~0x18) | 0x10; 2458 rt3090_rf_write(sc, 30, rf); 2459 2460 /* Initiate VCO calibration. */ 2461 rf = rt3090_rf_read(sc, 3); 2462 rf |= RT3593_VCOCAL; 2463 rt3090_rf_write(sc, 3, rf); 2464 } 2465 2466 int 2467 rt3090_rf_init(struct rt2860_softc *sc) 2468 { 2469 uint32_t tmp; 2470 uint8_t rf, bbp; 2471 int i; 2472 2473 rf = rt3090_rf_read(sc, 30); 2474 /* toggle RF R30 bit 7 */ 2475 rt3090_rf_write(sc, 30, rf | 0x80); 2476 DELAY(1000); 2477 rt3090_rf_write(sc, 30, rf & ~0x80); 2478 2479 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2480 tmp &= ~0x1f000000; 2481 if (sc->patch_dac && sc->mac_rev < 0x0211) 2482 tmp |= 0x0d000000; /* 1.35V */ 2483 else 2484 tmp |= 0x01000000; /* 1.2V */ 2485 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2486 2487 /* patch LNA_PE_G1 */ 2488 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2489 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2490 2491 /* initialize RF registers to default value */ 2492 if (sc->mac_ver == 0x3572) { 2493 for (i = 0; i < nitems(rt3572_def_rf); i++) { 2494 rt3090_rf_write(sc, rt3572_def_rf[i].reg, 2495 rt3572_def_rf[i].val); 2496 } 2497 } else { 2498 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2499 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2500 rt3090_def_rf[i].val); 2501 } 2502 } 2503 2504 /* select 20MHz bandwidth */ 2505 rt3090_rf_write(sc, 31, 0x14); 2506 2507 rf = rt3090_rf_read(sc, 6); 2508 rt3090_rf_write(sc, 6, rf | 0x40); 2509 2510 if (sc->mac_ver != 0x3593) { 2511 /* calibrate filter for 20MHz bandwidth */ 2512 sc->rf24_20mhz = 0x1f; /* default value */ 2513 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2514 2515 /* select 40MHz bandwidth */ 2516 bbp = rt2860_mcu_bbp_read(sc, 4); 2517 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2518 rf = rt3090_rf_read(sc, 31); 2519 rt3090_rf_write(sc, 31, rf | 0x20); 2520 2521 /* calibrate filter for 40MHz bandwidth */ 2522 sc->rf24_40mhz = 0x2f; /* default value */ 2523 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2524 2525 /* go back to 20MHz bandwidth */ 2526 bbp = rt2860_mcu_bbp_read(sc, 4); 2527 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2528 } 2529 if (sc->mac_rev < 0x0211) 2530 rt3090_rf_write(sc, 27, 0x03); 2531 2532 tmp = RAL_READ(sc, RT3070_OPT_14); 2533 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2534 2535 if (sc->rf_rev == RT3070_RF_3020) 2536 rt3090_set_rx_antenna(sc, 0); 2537 2538 bbp = rt2860_mcu_bbp_read(sc, 138); 2539 if (sc->mac_ver == 0x3593) { 2540 if (sc->ntxchains == 1) 2541 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2542 else if (sc->ntxchains == 2) 2543 bbp |= 0x40; /* turn off DAC2 */ 2544 if (sc->nrxchains == 1) 2545 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2546 else if (sc->nrxchains == 2) 2547 bbp &= ~0x04; /* turn off ADC2 */ 2548 } else { 2549 if (sc->ntxchains == 1) 2550 bbp |= 0x20; /* turn off DAC1 */ 2551 if (sc->nrxchains == 1) 2552 bbp &= ~0x02; /* turn off ADC1 */ 2553 } 2554 rt2860_mcu_bbp_write(sc, 138, bbp); 2555 2556 rf = rt3090_rf_read(sc, 1); 2557 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2558 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2559 rt3090_rf_write(sc, 1, rf); 2560 2561 rf = rt3090_rf_read(sc, 15); 2562 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2563 2564 rf = rt3090_rf_read(sc, 17); 2565 rf &= ~RT3070_TX_LO1; 2566 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2567 rf |= 0x20; /* fix for long range Rx issue */ 2568 if (sc->txmixgain_2ghz >= 2) 2569 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2570 rt3090_rf_write(sc, 17, rf); 2571 2572 rf = rt3090_rf_read(sc, 20); 2573 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2574 2575 rf = rt3090_rf_read(sc, 21); 2576 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2577 2578 return 0; 2579 } 2580 2581 void 2582 rt5390_rf_init(struct rt2860_softc *sc) 2583 { 2584 uint8_t rf, bbp; 2585 int i; 2586 2587 rf = rt3090_rf_read(sc, 2); 2588 /* Toggle RF R2 bit 7. */ 2589 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2590 DELAY(1000); 2591 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2592 2593 /* Initialize RF registers to default value. */ 2594 if (sc->mac_ver == 0x5392) { 2595 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2596 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2597 rt5392_def_rf[i].val); 2598 } 2599 } else if (sc->mac_ver == 0x3290) { 2600 for (i = 0; i < nitems(rt3290_def_rf); i++) { 2601 rt3090_rf_write(sc, rt3290_def_rf[i].reg, 2602 rt3290_def_rf[i].val); 2603 } 2604 } else { 2605 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2606 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2607 rt5390_def_rf[i].val); 2608 } 2609 } 2610 2611 sc->rf24_20mhz = 0x1f; 2612 sc->rf24_40mhz = 0x2f; 2613 2614 if (sc->mac_rev < 0x0211) 2615 rt3090_rf_write(sc, 27, 0x03); 2616 2617 /* Set led open drain enable. */ 2618 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2619 2620 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2621 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2622 2623 if (sc->mac_ver == 0x3290 || 2624 sc->mac_ver == 0x5390) 2625 rt3090_set_rx_antenna(sc, 0); 2626 2627 /* Patch RSSI inaccurate issue. */ 2628 rt2860_mcu_bbp_write(sc, 79, 0x13); 2629 rt2860_mcu_bbp_write(sc, 80, 0x05); 2630 rt2860_mcu_bbp_write(sc, 81, 0x33); 2631 2632 /* Enable DC filter. */ 2633 if (sc->mac_rev >= 0x0211 || 2634 sc->mac_ver == 0x3290) 2635 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2636 2637 bbp = rt2860_mcu_bbp_read(sc, 138); 2638 if (sc->ntxchains == 1) 2639 bbp |= 0x20; /* Turn off DAC1. */ 2640 if (sc->nrxchains == 1) 2641 bbp &= ~0x02; /* Turn off ADC1. */ 2642 rt2860_mcu_bbp_write(sc, 138, bbp); 2643 2644 /* Enable RX LO1 and LO2. */ 2645 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2646 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2647 2648 /* Avoid data lost and CRC error. */ 2649 rt2860_mcu_bbp_write(sc, 4, 2650 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2651 2652 rf = rt3090_rf_read(sc, 30); 2653 rf = (rf & ~0x18) | 0x10; 2654 rt3090_rf_write(sc, 30, rf); 2655 2656 /* Disable hardware antenna diversity. */ 2657 if (sc->mac_ver == 0x5390) 2658 rt2860_mcu_bbp_write(sc, 154, 0); 2659 } 2660 2661 void 2662 rt3090_rf_wakeup(struct rt2860_softc *sc) 2663 { 2664 uint32_t tmp; 2665 uint8_t rf; 2666 2667 if (sc->mac_ver == 0x3593) { 2668 /* enable VCO */ 2669 rf = rt3090_rf_read(sc, 1); 2670 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2671 2672 /* initiate VCO calibration */ 2673 rf = rt3090_rf_read(sc, 3); 2674 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2675 2676 /* enable VCO bias current control */ 2677 rf = rt3090_rf_read(sc, 6); 2678 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2679 2680 /* initiate res calibration */ 2681 rf = rt3090_rf_read(sc, 2); 2682 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2683 2684 /* set reference current control to 0.33 mA */ 2685 rf = rt3090_rf_read(sc, 22); 2686 rf &= ~RT3593_CP_IC_MASK; 2687 rf |= 1 << RT3593_CP_IC_SHIFT; 2688 rt3090_rf_write(sc, 22, rf); 2689 2690 /* enable RX CTB */ 2691 rf = rt3090_rf_read(sc, 46); 2692 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2693 2694 rf = rt3090_rf_read(sc, 20); 2695 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2696 rt3090_rf_write(sc, 20, rf); 2697 } else { 2698 /* enable RF block */ 2699 rf = rt3090_rf_read(sc, 1); 2700 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2701 2702 /* enable VCO bias current control */ 2703 rf = rt3090_rf_read(sc, 7); 2704 rt3090_rf_write(sc, 7, rf | 0x30); 2705 2706 rf = rt3090_rf_read(sc, 9); 2707 rt3090_rf_write(sc, 9, rf | 0x0e); 2708 2709 /* enable RX CTB */ 2710 rf = rt3090_rf_read(sc, 21); 2711 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2712 2713 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2714 rf = rt3090_rf_read(sc, 27); 2715 rf &= ~0x77; 2716 if (sc->mac_rev < 0x0211) 2717 rf |= 0x03; 2718 rt3090_rf_write(sc, 27, rf); 2719 } 2720 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2721 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2722 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2723 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2724 } 2725 } 2726 2727 void 2728 rt5390_rf_wakeup(struct rt2860_softc *sc) 2729 { 2730 uint32_t tmp; 2731 uint8_t rf; 2732 2733 rf = rt3090_rf_read(sc, 1); 2734 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2735 RT3070_TX0_PD; 2736 if (sc->mac_ver == 0x5392) 2737 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2738 rt3090_rf_write(sc, 1, rf); 2739 2740 rf = rt3090_rf_read(sc, 6); 2741 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2742 if (sc->mac_ver == 0x5390) 2743 rf &= ~RT3593_VCO_IC; 2744 rt3090_rf_write(sc, 6, rf); 2745 2746 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2747 2748 rf = rt3090_rf_read(sc, 22); 2749 rf = (rf & ~0xe0) | 0x20; 2750 rt3090_rf_write(sc, 22, rf); 2751 2752 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2753 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2754 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2755 2756 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2757 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2758 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2759 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2760 } 2761 } 2762 2763 int 2764 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2765 uint8_t *val) 2766 { 2767 uint8_t rf22, rf24; 2768 uint8_t bbp55_pb, bbp55_sb, delta; 2769 int ntries; 2770 2771 /* program filter */ 2772 rf24 = rt3090_rf_read(sc, 24); 2773 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2774 rt3090_rf_write(sc, 24, rf24); 2775 2776 /* enable baseband loopback mode */ 2777 rf22 = rt3090_rf_read(sc, 22); 2778 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2779 2780 /* set power and frequency of passband test tone */ 2781 rt2860_mcu_bbp_write(sc, 24, 0x00); 2782 for (ntries = 0; ntries < 100; ntries++) { 2783 /* transmit test tone */ 2784 rt2860_mcu_bbp_write(sc, 25, 0x90); 2785 DELAY(1000); 2786 /* read received power */ 2787 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2788 if (bbp55_pb != 0) 2789 break; 2790 } 2791 if (ntries == 100) 2792 return ETIMEDOUT; 2793 2794 /* set power and frequency of stopband test tone */ 2795 rt2860_mcu_bbp_write(sc, 24, 0x06); 2796 for (ntries = 0; ntries < 100; ntries++) { 2797 /* transmit test tone */ 2798 rt2860_mcu_bbp_write(sc, 25, 0x90); 2799 DELAY(1000); 2800 /* read received power */ 2801 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2802 2803 delta = bbp55_pb - bbp55_sb; 2804 if (delta > target) 2805 break; 2806 2807 /* reprogram filter */ 2808 rf24++; 2809 rt3090_rf_write(sc, 24, rf24); 2810 } 2811 if (ntries < 100) { 2812 if (rf24 != init) 2813 rf24--; /* backtrack */ 2814 *val = rf24; 2815 rt3090_rf_write(sc, 24, rf24); 2816 } 2817 2818 /* restore initial state */ 2819 rt2860_mcu_bbp_write(sc, 24, 0x00); 2820 2821 /* disable baseband loopback mode */ 2822 rf22 = rt3090_rf_read(sc, 22); 2823 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2824 2825 return 0; 2826 } 2827 2828 void 2829 rt3090_rf_setup(struct rt2860_softc *sc) 2830 { 2831 uint8_t bbp; 2832 int i; 2833 2834 if (sc->mac_rev >= 0x0211) { 2835 /* enable DC filter */ 2836 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2837 2838 /* improve power consumption */ 2839 bbp = rt2860_mcu_bbp_read(sc, 31); 2840 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2841 } 2842 2843 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2844 if (sc->mac_rev < 0x0211) { 2845 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2846 sc->patch_dac ? 0x2c : 0x0f); 2847 } else 2848 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2849 2850 /* initialize RF registers from ROM */ 2851 if (sc->mac_ver < 0x5390) { 2852 for (i = 0; i < 10; i++) { 2853 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2854 continue; 2855 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2856 } 2857 } 2858 } 2859 2860 void 2861 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2862 { 2863 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2864 which | (sc->leds & 0x7f), 0); 2865 } 2866 2867 /* 2868 * Hardware has a general-purpose programmable timer interrupt that can 2869 * periodically raise MAC_INT_4. 2870 */ 2871 void 2872 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2873 { 2874 uint32_t tmp; 2875 2876 /* disable GP timer before reprogramming it */ 2877 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2878 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2879 2880 if (ms == 0) 2881 return; 2882 2883 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2884 ms *= 16; /* Unit: 64us */ 2885 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2886 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2887 2888 /* enable GP timer */ 2889 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2890 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2891 } 2892 2893 void 2894 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2895 { 2896 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2897 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2898 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2899 bssid[4] | bssid[5] << 8); 2900 } 2901 2902 void 2903 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2904 { 2905 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2906 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2907 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2908 addr[4] | addr[5] << 8 | 0xff << 16); 2909 } 2910 2911 void 2912 rt2860_updateslot(struct ieee80211com *ic) 2913 { 2914 struct rt2860_softc *sc = ic->ic_softc; 2915 uint32_t tmp; 2916 2917 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2918 tmp &= ~0xff; 2919 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 2920 IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT; 2921 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2922 } 2923 2924 void 2925 rt2860_updateprot(struct ieee80211com *ic) 2926 { 2927 struct rt2860_softc *sc = ic->ic_softc; 2928 uint32_t tmp; 2929 2930 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2931 /* setup protection frame rate (MCS code) */ 2932 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 2933 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2934 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2935 2936 /* CCK frames don't require protection */ 2937 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2938 2939 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2940 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2941 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2942 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2943 tmp |= RT2860_PROT_CTRL_CTS; 2944 } 2945 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2946 } 2947 2948 void 2949 rt2860_updateedca(struct ieee80211com *ic) 2950 { 2951 struct rt2860_softc *sc = ic->ic_softc; 2952 int aci; 2953 2954 /* update MAC TX configuration registers */ 2955 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2956 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2957 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 2958 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 2959 ic->ic_edca_ac[aci].ac_aifsn << 8 | 2960 ic->ic_edca_ac[aci].ac_txoplimit); 2961 } 2962 2963 /* update SCH/DMA registers too */ 2964 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2965 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 2966 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 2967 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 2968 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 2969 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2970 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 2971 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 2972 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 2973 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 2974 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2975 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 2976 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 2977 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 2978 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 2979 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2980 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 2981 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 2982 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2983 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 2984 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 2985 } 2986 2987 int 2988 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2989 struct ieee80211_key *k) 2990 { 2991 struct rt2860_softc *sc = ic->ic_softc; 2992 bus_size_t base; 2993 uint32_t attr; 2994 uint8_t mode, wcid, iv[8]; 2995 2996 /* defer setting of WEP keys until interface is brought up */ 2997 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2998 (IFF_UP | IFF_RUNNING)) 2999 return 0; 3000 3001 /* map net80211 cipher to RT2860 security mode */ 3002 switch (k->k_cipher) { 3003 case IEEE80211_CIPHER_WEP40: 3004 mode = RT2860_MODE_WEP40; 3005 break; 3006 case IEEE80211_CIPHER_WEP104: 3007 mode = RT2860_MODE_WEP104; 3008 break; 3009 case IEEE80211_CIPHER_TKIP: 3010 mode = RT2860_MODE_TKIP; 3011 break; 3012 case IEEE80211_CIPHER_CCMP: 3013 mode = RT2860_MODE_AES_CCMP; 3014 break; 3015 default: 3016 return EINVAL; 3017 } 3018 3019 if (k->k_flags & IEEE80211_KEY_GROUP) { 3020 wcid = 0; /* NB: update WCID0 for group keys */ 3021 base = RT2860_SKEY(0, k->k_id); 3022 } else { 3023 wcid = ((struct rt2860_node *)ni)->wcid; 3024 base = RT2860_PKEY(wcid); 3025 } 3026 3027 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3028 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3029 #ifndef IEEE80211_STA_ONLY 3030 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3031 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3032 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3033 } else 3034 #endif 3035 { 3036 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3037 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3038 } 3039 } else 3040 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3041 3042 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3043 (k->k_flags & IEEE80211_KEY_TX)) { 3044 /* set initial packet number in IV+EIV */ 3045 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3046 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3047 uint32_t val = arc4random(); 3048 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3049 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3050 val += 0x000100; 3051 iv[0] = val; 3052 iv[1] = val >> 8; 3053 iv[2] = val >> 16; 3054 iv[3] = k->k_id << 6; 3055 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3056 } else { 3057 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3058 iv[0] = k->k_tsc >> 8; 3059 iv[1] = (iv[0] | 0x20) & 0x7f; 3060 iv[2] = k->k_tsc; 3061 } else /* CCMP */ { 3062 iv[0] = k->k_tsc; 3063 iv[1] = k->k_tsc >> 8; 3064 iv[2] = 0; 3065 } 3066 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3067 iv[4] = k->k_tsc >> 16; 3068 iv[5] = k->k_tsc >> 24; 3069 iv[6] = k->k_tsc >> 32; 3070 iv[7] = k->k_tsc >> 40; 3071 } 3072 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3073 } 3074 3075 if (k->k_flags & IEEE80211_KEY_GROUP) { 3076 /* install group key */ 3077 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3078 attr &= ~(0xf << (k->k_id * 4)); 3079 attr |= mode << (k->k_id * 4); 3080 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3081 } else { 3082 /* install pairwise key */ 3083 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3084 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3085 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3086 } 3087 return 0; 3088 } 3089 3090 void 3091 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3092 struct ieee80211_key *k) 3093 { 3094 struct rt2860_softc *sc = ic->ic_softc; 3095 uint32_t attr; 3096 uint8_t wcid; 3097 3098 if (k->k_flags & IEEE80211_KEY_GROUP) { 3099 /* remove group key */ 3100 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3101 attr &= ~(0xf << (k->k_id * 4)); 3102 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3103 3104 } else { 3105 /* remove pairwise key */ 3106 wcid = ((struct rt2860_node *)ni)->wcid; 3107 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3108 attr &= ~0xf; 3109 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3110 } 3111 } 3112 3113 #if NBPFILTER > 0 3114 int8_t 3115 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3116 { 3117 struct ieee80211com *ic = &sc->sc_ic; 3118 struct ieee80211_channel *c = ic->ic_ibss_chan; 3119 int delta; 3120 3121 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3122 u_int chan = ieee80211_chan2ieee(ic, c); 3123 delta = sc->rssi_5ghz[rxchain]; 3124 3125 /* determine channel group */ 3126 if (chan <= 64) 3127 delta -= sc->lna[1]; 3128 else if (chan <= 128) 3129 delta -= sc->lna[2]; 3130 else 3131 delta -= sc->lna[3]; 3132 } else 3133 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3134 3135 return -12 - delta - rssi; 3136 } 3137 #endif 3138 3139 /* 3140 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3141 * Used to adjust per-rate Tx power registers. 3142 */ 3143 static __inline uint32_t 3144 b4inc(uint32_t b32, int8_t delta) 3145 { 3146 int8_t i, b4; 3147 3148 for (i = 0; i < 8; i++) { 3149 b4 = b32 & 0xf; 3150 b4 += delta; 3151 if (b4 < 0) 3152 b4 = 0; 3153 else if (b4 > 0xf) 3154 b4 = 0xf; 3155 b32 = b32 >> 4 | b4 << 28; 3156 } 3157 return b32; 3158 } 3159 3160 const char * 3161 rt2860_get_rf(uint16_t rev) 3162 { 3163 switch (rev) { 3164 case RT2860_RF_2820: return "RT2820"; 3165 case RT2860_RF_2850: return "RT2850"; 3166 case RT2860_RF_2720: return "RT2720"; 3167 case RT2860_RF_2750: return "RT2750"; 3168 case RT3070_RF_3020: return "RT3020"; 3169 case RT3070_RF_2020: return "RT2020"; 3170 case RT3070_RF_3021: return "RT3021"; 3171 case RT3070_RF_3022: return "RT3022"; 3172 case RT3070_RF_3052: return "RT3052"; 3173 case RT3070_RF_3320: return "RT3320"; 3174 case RT3070_RF_3053: return "RT3053"; 3175 case RT3290_RF_3290: return "RT3290"; 3176 case RT5390_RF_5360: return "RT5360"; 3177 case RT5390_RF_5390: return "RT5390"; 3178 case RT5390_RF_5392: return "RT5392"; 3179 default: return "unknown"; 3180 } 3181 } 3182 3183 int 3184 rt2860_read_eeprom(struct rt2860_softc *sc) 3185 { 3186 struct ieee80211com *ic = &sc->sc_ic; 3187 int8_t delta_2ghz, delta_5ghz; 3188 uint32_t tmp; 3189 uint16_t val; 3190 int ridx, ant, i; 3191 3192 /* check whether the ROM is eFUSE ROM or EEPROM */ 3193 sc->sc_srom_read = rt2860_eeprom_read_2; 3194 if (sc->mac_ver == 0x3290) { 3195 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL); 3196 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3197 if (tmp & RT3070_SEL_EFUSE) 3198 sc->sc_srom_read = rt3290_efuse_read_2; 3199 } else if (sc->mac_ver >= 0x3071) { 3200 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3201 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3202 if (tmp & RT3070_SEL_EFUSE) 3203 sc->sc_srom_read = rt3090_efuse_read_2; 3204 } 3205 3206 /* read EEPROM version */ 3207 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3208 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3209 3210 /* read MAC address */ 3211 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3212 ic->ic_myaddr[0] = val & 0xff; 3213 ic->ic_myaddr[1] = val >> 8; 3214 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3215 ic->ic_myaddr[2] = val & 0xff; 3216 ic->ic_myaddr[3] = val >> 8; 3217 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3218 ic->ic_myaddr[4] = val & 0xff; 3219 ic->ic_myaddr[5] = val >> 8; 3220 3221 /* read country code */ 3222 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3223 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3224 3225 /* read vendor BBP settings */ 3226 for (i = 0; i < 8; i++) { 3227 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3228 sc->bbp[i].val = val & 0xff; 3229 sc->bbp[i].reg = val >> 8; 3230 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3231 } 3232 if (sc->mac_ver >= 0x3071) { 3233 /* read vendor RF settings */ 3234 for (i = 0; i < 10; i++) { 3235 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3236 sc->rf[i].val = val & 0xff; 3237 sc->rf[i].reg = val >> 8; 3238 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3239 sc->rf[i].val)); 3240 } 3241 } 3242 3243 /* read RF frequency offset from EEPROM */ 3244 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3245 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3246 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3247 if ((val >> 8) != 0xff) { 3248 /* read LEDs operating mode */ 3249 sc->leds = val >> 8; 3250 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3251 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3252 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3253 } else { 3254 /* broken EEPROM, use default settings */ 3255 sc->leds = 0x01; 3256 sc->led[0] = 0x5555; 3257 sc->led[1] = 0x2221; 3258 sc->led[2] = 0xa9f8; 3259 } 3260 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3261 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3262 3263 /* read RF information */ 3264 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3265 DPRINTF(("EEPROM ANT 0x%04x\n", val)); 3266 if (sc->mac_ver >= 0x5390 || sc->mac_ver == 0x3290) 3267 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3268 else 3269 sc->rf_rev = (val >> 8) & 0xf; 3270 sc->ntxchains = (val >> 4) & 0xf; 3271 sc->nrxchains = val & 0xf; 3272 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3273 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3274 3275 /* check if RF supports automatic Tx access gain control */ 3276 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3277 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3278 /* check if driver should patch the DAC issue */ 3279 if ((val >> 8) != 0xff) 3280 sc->patch_dac = (val >> 15) & 1; 3281 if ((val & 0xff) != 0xff) { 3282 sc->ext_5ghz_lna = (val >> 3) & 1; 3283 sc->ext_2ghz_lna = (val >> 2) & 1; 3284 /* check if RF supports automatic Tx access gain control */ 3285 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3286 /* check if we have a hardware radio switch */ 3287 sc->rfswitch = val & 1; 3288 } 3289 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3290 /* read PCIe power save level */ 3291 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3292 if ((val & 0xff) != 0xff) { 3293 sc->pslevel = val & 0x3; 3294 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3295 if ((val & 0xff80) != 0x9280) 3296 sc->pslevel = MIN(sc->pslevel, 1); 3297 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3298 } 3299 } 3300 3301 /* read power settings for 2GHz channels */ 3302 for (i = 0; i < 14; i += 2) { 3303 val = rt2860_srom_read(sc, 3304 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3305 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3306 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3307 3308 if (sc->mac_ver != 0x5390) { 3309 val = rt2860_srom_read(sc, 3310 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3311 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3312 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3313 } 3314 } 3315 /* fix broken Tx power entries */ 3316 for (i = 0; i < 14; i++) { 3317 if (sc->txpow1[i] < 0 || 3318 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3319 sc->txpow1[i] = 5; 3320 if (sc->mac_ver != 0x5390) { 3321 if (sc->txpow2[i] < 0 || 3322 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3323 sc->txpow2[i] = 5; 3324 } 3325 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3326 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3327 } 3328 /* read power settings for 5GHz channels */ 3329 for (i = 0; i < 40; i += 2) { 3330 val = rt2860_srom_read(sc, 3331 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3332 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3333 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3334 3335 val = rt2860_srom_read(sc, 3336 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3337 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3338 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3339 } 3340 /* fix broken Tx power entries */ 3341 for (i = 0; i < 40; i++) { 3342 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3343 sc->txpow1[14 + i] = 5; 3344 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3345 sc->txpow2[14 + i] = 5; 3346 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3347 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3348 sc->txpow2[14 + i])); 3349 } 3350 3351 /* read Tx power compensation for each Tx rate */ 3352 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3353 delta_2ghz = delta_5ghz = 0; 3354 if ((val & 0xff) != 0xff && (val & 0x80)) { 3355 delta_2ghz = val & 0xf; 3356 if (!(val & 0x40)) /* negative number */ 3357 delta_2ghz = -delta_2ghz; 3358 } 3359 val >>= 8; 3360 if ((val & 0xff) != 0xff && (val & 0x80)) { 3361 delta_5ghz = val & 0xf; 3362 if (!(val & 0x40)) /* negative number */ 3363 delta_5ghz = -delta_5ghz; 3364 } 3365 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3366 delta_2ghz, delta_5ghz)); 3367 3368 for (ridx = 0; ridx < 5; ridx++) { 3369 uint32_t reg; 3370 3371 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3372 reg = val; 3373 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3374 reg |= (uint32_t)val << 16; 3375 3376 sc->txpow20mhz[ridx] = reg; 3377 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3378 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3379 3380 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3381 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3382 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3383 } 3384 3385 /* read factory-calibrated samples for temperature compensation */ 3386 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3387 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3388 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3389 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3390 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3391 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3392 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3393 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3394 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3395 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3396 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3397 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3398 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3399 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3400 sc->step_2ghz = val >> 8; 3401 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3402 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3403 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3404 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3405 sc->tssi_2ghz[8], sc->step_2ghz)); 3406 /* check that ref value is correct, otherwise disable calibration */ 3407 if (sc->tssi_2ghz[4] == 0xff) 3408 sc->calib_2ghz = 0; 3409 3410 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3411 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3412 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3413 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3414 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3415 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3416 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3417 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3418 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3419 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3420 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3421 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3422 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3423 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3424 sc->step_5ghz = val >> 8; 3425 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3426 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3427 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3428 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3429 sc->tssi_5ghz[8], sc->step_5ghz)); 3430 /* check that ref value is correct, otherwise disable calibration */ 3431 if (sc->tssi_5ghz[4] == 0xff) 3432 sc->calib_5ghz = 0; 3433 3434 /* read RSSI offsets and LNA gains from EEPROM */ 3435 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3436 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3437 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3438 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3439 if (sc->mac_ver >= 0x3071) { 3440 /* 3441 * On RT3090 chips (limited to 2 Rx chains), this ROM 3442 * field contains the Tx mixer gain for the 2GHz band. 3443 */ 3444 if ((val & 0xff) != 0xff) 3445 sc->txmixgain_2ghz = val & 0x7; 3446 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3447 } else 3448 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3449 sc->lna[2] = val >> 8; /* channel group 2 */ 3450 3451 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3452 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3453 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3454 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3455 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3456 sc->lna[3] = val >> 8; /* channel group 3 */ 3457 3458 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3459 if (sc->mac_ver >= 0x3071) 3460 sc->lna[0] = RT3090_DEF_LNA; 3461 else /* channel group 0 */ 3462 sc->lna[0] = val & 0xff; 3463 sc->lna[1] = val >> 8; /* channel group 1 */ 3464 3465 /* fix broken 5GHz LNA entries */ 3466 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3467 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3468 sc->lna[2] = sc->lna[1]; 3469 } 3470 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3471 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3472 sc->lna[3] = sc->lna[1]; 3473 } 3474 3475 /* fix broken RSSI offset entries */ 3476 for (ant = 0; ant < 3; ant++) { 3477 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3478 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3479 ant + 1, sc->rssi_2ghz[ant])); 3480 sc->rssi_2ghz[ant] = 0; 3481 } 3482 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3483 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3484 ant + 1, sc->rssi_5ghz[ant])); 3485 sc->rssi_5ghz[ant] = 0; 3486 } 3487 } 3488 3489 return 0; 3490 } 3491 3492 int 3493 rt2860_bbp_init(struct rt2860_softc *sc) 3494 { 3495 int i, ntries; 3496 3497 /* wait for BBP to wake up */ 3498 for (ntries = 0; ntries < 20; ntries++) { 3499 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3500 if (bbp0 != 0 && bbp0 != 0xff) 3501 break; 3502 } 3503 if (ntries == 20) { 3504 printf("%s: timeout waiting for BBP to wake up\n", 3505 sc->sc_dev.dv_xname); 3506 return ETIMEDOUT; 3507 } 3508 3509 /* initialize BBP registers to default values */ 3510 if (sc->mac_ver >= 0x5390 || 3511 sc->mac_ver == 0x3290) 3512 rt5390_bbp_init(sc); 3513 else { 3514 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3515 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3516 rt2860_def_bbp[i].val); 3517 } 3518 } 3519 3520 /* fix BBP84 for RT2860E */ 3521 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3522 rt2860_mcu_bbp_write(sc, 84, 0x19); 3523 3524 if (sc->mac_ver >= 0x3071) { 3525 rt2860_mcu_bbp_write(sc, 79, 0x13); 3526 rt2860_mcu_bbp_write(sc, 80, 0x05); 3527 rt2860_mcu_bbp_write(sc, 81, 0x33); 3528 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3529 rt2860_mcu_bbp_write(sc, 69, 0x16); 3530 rt2860_mcu_bbp_write(sc, 73, 0x12); 3531 } 3532 3533 return 0; 3534 } 3535 3536 void 3537 rt5390_bbp_init(struct rt2860_softc *sc) 3538 { 3539 uint8_t bbp; 3540 int i; 3541 3542 /* Apply maximum likelihood detection for 2 stream case. */ 3543 if (sc->nrxchains > 1) { 3544 bbp = rt2860_mcu_bbp_read(sc, 105); 3545 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3546 } 3547 3548 /* Avoid data lost and CRC error. */ 3549 bbp = rt2860_mcu_bbp_read(sc, 4); 3550 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3551 if (sc->mac_ver == 0x3290) { 3552 for (i = 0; i < nitems(rt3290_def_bbp); i++) { 3553 rt2860_mcu_bbp_write(sc, rt3290_def_bbp[i].reg, 3554 rt3290_def_bbp[i].val); 3555 } 3556 } else { 3557 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3558 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3559 rt5390_def_bbp[i].val); 3560 } 3561 } 3562 3563 if (sc->mac_ver == 0x5392) { 3564 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3565 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3566 rt2860_mcu_bbp_write(sc, 98, 0x12); 3567 rt2860_mcu_bbp_write(sc, 106, 0x05); 3568 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3569 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3570 } 3571 3572 bbp = rt2860_mcu_bbp_read(sc, 152); 3573 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3574 3575 /* Disable hardware antenna diversity. */ 3576 if (sc->mac_ver == 0x5390) 3577 rt2860_mcu_bbp_write(sc, 154, 0); 3578 } 3579 3580 int 3581 rt3290_wlan_enable(struct rt2860_softc *sc) 3582 { 3583 uint32_t tmp; 3584 int ntries; 3585 3586 /* enable chip and check readiness */ 3587 tmp = RAL_READ(sc, RT3290_WLAN_CTRL); 3588 tmp |= RT3290_WLAN_EN | RT3290_FRC_WL_ANT_SET | 3589 RT3290_GPIO_OUT_OE_ALL; 3590 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp); 3591 3592 for (ntries = 0; ntries < 200; ntries++) { 3593 tmp = RAL_READ(sc, RT3290_CMB_CTRL); 3594 if ((tmp & RT3290_PLL_LD) && 3595 (tmp & RT3290_XTAL_RDY)) 3596 break; 3597 DELAY(20); 3598 } 3599 if (ntries == 200) 3600 return EIO; 3601 3602 /* toggle reset */ 3603 tmp = RAL_READ(sc, RT3290_WLAN_CTRL); 3604 tmp |= RT3290_WLAN_RESET | RT3290_WLAN_CLK_EN; 3605 tmp &= ~RT3290_PCIE_APP0_CLK_REQ; 3606 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp); 3607 DELAY(20); 3608 tmp &= ~RT3290_WLAN_RESET; 3609 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp); 3610 DELAY(1000); 3611 3612 /* clear garbage interrupts */ 3613 RAL_WRITE(sc, RT2860_INT_STATUS, 0x7fffffff); 3614 3615 return 0; 3616 } 3617 3618 int 3619 rt2860_txrx_enable(struct rt2860_softc *sc) 3620 { 3621 uint32_t tmp; 3622 int ntries; 3623 3624 /* enable Tx/Rx DMA engine */ 3625 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3626 RAL_BARRIER_READ_WRITE(sc); 3627 for (ntries = 0; ntries < 200; ntries++) { 3628 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3629 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3630 break; 3631 DELAY(1000); 3632 } 3633 if (ntries == 200) { 3634 printf("%s: timeout waiting for DMA engine\n", 3635 sc->sc_dev.dv_xname); 3636 return ETIMEDOUT; 3637 } 3638 3639 DELAY(50); 3640 3641 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3642 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3643 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3644 3645 /* set Rx filter */ 3646 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3647 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 3648 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3649 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3650 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3651 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3652 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 3653 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3654 } 3655 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3656 3657 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3658 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3659 3660 return 0; 3661 } 3662 3663 int 3664 rt2860_init(struct ifnet *ifp) 3665 { 3666 struct rt2860_softc *sc = ifp->if_softc; 3667 struct ieee80211com *ic = &sc->sc_ic; 3668 uint32_t tmp; 3669 uint8_t bbp1, bbp3; 3670 int i, qid, ridx, ntries, error; 3671 3672 /* for CardBus, power on the socket */ 3673 if (!(sc->sc_flags & RT2860_ENABLED)) { 3674 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 3675 printf("%s: could not enable device\n", 3676 sc->sc_dev.dv_xname); 3677 return EIO; 3678 } 3679 sc->sc_flags |= RT2860_ENABLED; 3680 } 3681 3682 if (sc->mac_ver == 0x3290) { 3683 if ((error = rt3290_wlan_enable(sc)) != 0) { 3684 printf("%s: could not enable wlan\n", 3685 sc->sc_dev.dv_xname); 3686 rt2860_stop(ifp, 1); 3687 return error; 3688 } 3689 } 3690 3691 if (sc->mac_ver == 0x3290 && sc->rfswitch){ 3692 /* hardware has a radio switch on GPIO pin 0 */ 3693 if (!(RAL_READ(sc, RT3290_WLAN_CTRL) & RT3290_RADIO_EN)) { 3694 printf("%s: radio is disabled by hardware switch\n", 3695 sc->sc_dev.dv_xname); 3696 } 3697 } else if (sc->rfswitch) { 3698 /* hardware has a radio switch on GPIO pin 2 */ 3699 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3700 printf("%s: radio is disabled by hardware switch\n", 3701 sc->sc_dev.dv_xname); 3702 #ifdef notyet 3703 rt2860_stop(ifp, 1); 3704 return EPERM; 3705 #endif 3706 } 3707 } 3708 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3709 3710 /* disable DMA */ 3711 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3712 tmp &= 0xff0; 3713 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3714 3715 /* PBF hardware reset */ 3716 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3717 RAL_BARRIER_WRITE(sc); 3718 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3719 3720 if ((error = rt2860_load_microcode(sc)) != 0) { 3721 printf("%s: could not load 8051 microcode\n", 3722 sc->sc_dev.dv_xname); 3723 rt2860_stop(ifp, 1); 3724 return error; 3725 } 3726 3727 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3728 rt2860_set_macaddr(sc, ic->ic_myaddr); 3729 3730 /* init Tx power for all Tx rates (from EEPROM) */ 3731 for (ridx = 0; ridx < 5; ridx++) { 3732 if (sc->txpow20mhz[ridx] == 0xffffffff) 3733 continue; 3734 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3735 } 3736 3737 for (ntries = 0; ntries < 100; ntries++) { 3738 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3739 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3740 break; 3741 DELAY(1000); 3742 } 3743 if (ntries == 100) { 3744 printf("%s: timeout waiting for DMA engine\n", 3745 sc->sc_dev.dv_xname); 3746 rt2860_stop(ifp, 1); 3747 return ETIMEDOUT; 3748 } 3749 tmp &= 0xff0; 3750 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3751 3752 /* reset Rx ring and all 6 Tx rings */ 3753 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3754 3755 /* PBF hardware reset */ 3756 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3757 RAL_BARRIER_WRITE(sc); 3758 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3759 3760 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3761 3762 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3763 RAL_BARRIER_WRITE(sc); 3764 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3765 3766 for (i = 0; i < nitems(rt2860_def_mac); i++) 3767 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3768 if (sc->mac_ver == 0x3290 || 3769 sc->mac_ver >= 0x5390) 3770 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3771 else if (sc->mac_ver >= 0x3071) { 3772 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3773 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3774 4 << RT2860_DLY_PAPE_EN_SHIFT); 3775 } 3776 3777 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3778 sc->sc_flags |= RT2860_PCIE; 3779 /* PCIe has different clock cycle count than PCI */ 3780 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3781 tmp = (tmp & ~0xff) | 0x7d; 3782 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3783 } 3784 3785 /* wait while MAC is busy */ 3786 for (ntries = 0; ntries < 100; ntries++) { 3787 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3788 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3789 break; 3790 DELAY(1000); 3791 } 3792 if (ntries == 100) { 3793 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname); 3794 rt2860_stop(ifp, 1); 3795 return ETIMEDOUT; 3796 } 3797 3798 /* clear Host to MCU mailbox */ 3799 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3800 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3801 3802 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3803 DELAY(1000); 3804 3805 if ((error = rt2860_bbp_init(sc)) != 0) { 3806 rt2860_stop(ifp, 1); 3807 return error; 3808 } 3809 3810 /* clear RX WCID search table */ 3811 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3812 /* clear pairwise key table */ 3813 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3814 /* clear IV/EIV table */ 3815 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3816 /* clear WCID attribute table */ 3817 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3818 /* clear shared key table */ 3819 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3820 /* clear shared key mode */ 3821 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3822 3823 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3824 for (qid = 0; qid < 6; qid++) { 3825 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3826 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3827 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3828 } 3829 3830 /* init Rx ring */ 3831 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3832 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3833 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3834 3835 /* setup maximum buffer sizes */ 3836 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3837 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3838 3839 for (ntries = 0; ntries < 100; ntries++) { 3840 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3841 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3842 break; 3843 DELAY(1000); 3844 } 3845 if (ntries == 100) { 3846 printf("%s: timeout waiting for DMA engine\n", 3847 sc->sc_dev.dv_xname); 3848 rt2860_stop(ifp, 1); 3849 return ETIMEDOUT; 3850 } 3851 tmp &= 0xff0; 3852 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3853 3854 /* disable interrupts mitigation */ 3855 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3856 3857 /* write vendor-specific BBP values (from EEPROM) */ 3858 for (i = 0; i < 8; i++) { 3859 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3860 continue; 3861 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3862 } 3863 3864 /* select Main antenna for 1T1R devices */ 3865 if (sc->rf_rev == RT3070_RF_2020 || 3866 sc->rf_rev == RT3070_RF_3020 || 3867 sc->rf_rev == RT3290_RF_3290 || 3868 sc->rf_rev == RT3070_RF_3320 || 3869 sc->rf_rev == RT5390_RF_5390) 3870 rt3090_set_rx_antenna(sc, 0); 3871 3872 /* send LEDs operating mode to microcontroller */ 3873 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3874 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3875 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3876 3877 if (sc->mac_ver == 0x3290 || 3878 sc->mac_ver >= 0x5390) 3879 rt5390_rf_init(sc); 3880 else if (sc->mac_ver >= 0x3071) 3881 rt3090_rf_init(sc); 3882 3883 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3884 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3885 3886 if (sc->mac_ver == 0x3290 || 3887 sc->mac_ver >= 0x5390) 3888 rt5390_rf_wakeup(sc); 3889 else if (sc->mac_ver >= 0x3071) 3890 rt3090_rf_wakeup(sc); 3891 3892 /* disable non-existing Rx chains */ 3893 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3894 bbp3 &= ~(1 << 3 | 1 << 4); 3895 if (sc->nrxchains == 2) 3896 bbp3 |= 1 << 3; 3897 else if (sc->nrxchains == 3) 3898 bbp3 |= 1 << 4; 3899 rt2860_mcu_bbp_write(sc, 3, bbp3); 3900 3901 /* disable non-existing Tx chains */ 3902 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3903 if (sc->ntxchains == 1) 3904 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3905 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3906 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3907 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3908 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3909 rt2860_mcu_bbp_write(sc, 1, bbp1); 3910 3911 if (sc->mac_ver >= 0x3071) 3912 rt3090_rf_setup(sc); 3913 3914 /* select default channel */ 3915 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3916 rt2860_switch_chan(sc, ic->ic_ibss_chan); 3917 3918 /* reset RF from MCU */ 3919 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3920 3921 /* set RTS threshold */ 3922 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3923 tmp &= ~0xffff00; 3924 tmp |= ic->ic_rtsthreshold << 8; 3925 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3926 3927 /* setup initial protection mode */ 3928 sc->sc_ic_flags = ic->ic_flags; 3929 rt2860_updateprot(ic); 3930 3931 /* turn radio LED on */ 3932 rt2860_set_leds(sc, RT2860_LED_RADIO); 3933 3934 /* enable Tx/Rx DMA engine */ 3935 if ((error = rt2860_txrx_enable(sc)) != 0) { 3936 rt2860_stop(ifp, 1); 3937 return error; 3938 } 3939 3940 /* clear pending interrupts */ 3941 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3942 /* enable interrupts */ 3943 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3944 3945 if (sc->sc_flags & RT2860_ADVANCED_PS) 3946 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3947 3948 ifp->if_flags |= IFF_RUNNING; 3949 ifq_clr_oactive(&ifp->if_snd); 3950 3951 if (ic->ic_flags & IEEE80211_F_WEPON) { 3952 /* install WEP keys */ 3953 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3954 (void)rt2860_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3955 } 3956 3957 if (ic->ic_opmode != IEEE80211_M_MONITOR) 3958 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3959 else 3960 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3961 3962 return 0; 3963 } 3964 3965 void 3966 rt2860_stop(struct ifnet *ifp, int disable) 3967 { 3968 struct rt2860_softc *sc = ifp->if_softc; 3969 struct ieee80211com *ic = &sc->sc_ic; 3970 uint32_t tmp; 3971 int qid; 3972 3973 if (ifp->if_flags & IFF_RUNNING) 3974 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3975 3976 sc->sc_tx_timer = 0; 3977 ifp->if_timer = 0; 3978 ifp->if_flags &= ~IFF_RUNNING; 3979 ifq_clr_oactive(&ifp->if_snd); 3980 3981 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */ 3982 3983 /* disable interrupts */ 3984 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3985 3986 /* disable GP timer */ 3987 rt2860_set_gp_timer(sc, 0); 3988 3989 /* disable Rx */ 3990 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3991 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3992 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3993 3994 /* reset adapter */ 3995 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3996 RAL_BARRIER_WRITE(sc); 3997 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3998 3999 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4000 sc->qfullmsk = 0; 4001 for (qid = 0; qid < 6; qid++) 4002 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4003 rt2860_reset_rx_ring(sc, &sc->rxq); 4004 4005 /* for CardBus, power down the socket */ 4006 if (disable && sc->sc_disable != NULL) { 4007 if (sc->sc_flags & RT2860_ENABLED) { 4008 (*sc->sc_disable)(sc); 4009 sc->sc_flags &= ~RT2860_ENABLED; 4010 } 4011 } 4012 } 4013 4014 int 4015 rt2860_load_microcode(struct rt2860_softc *sc) 4016 { 4017 int ntries; 4018 4019 /* set "host program ram write selection" bit */ 4020 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4021 /* write microcode image */ 4022 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize); 4023 /* kick microcontroller unit */ 4024 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4025 RAL_BARRIER_WRITE(sc); 4026 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4027 4028 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4029 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4030 4031 /* wait until microcontroller is ready */ 4032 RAL_BARRIER_READ_WRITE(sc); 4033 for (ntries = 0; ntries < 1000; ntries++) { 4034 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4035 break; 4036 DELAY(1000); 4037 } 4038 if (ntries == 1000) { 4039 printf("%s: timeout waiting for MCU to initialize\n", 4040 sc->sc_dev.dv_xname); 4041 return ETIMEDOUT; 4042 } 4043 return 0; 4044 } 4045 4046 /* 4047 * This function is called periodically to adjust Tx power based on 4048 * temperature variation. 4049 */ 4050 void 4051 rt2860_calib(struct rt2860_softc *sc) 4052 { 4053 struct ieee80211com *ic = &sc->sc_ic; 4054 const uint8_t *tssi; 4055 uint8_t step, bbp49; 4056 int8_t ridx, d; 4057 4058 /* read current temperature */ 4059 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4060 4061 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4062 tssi = &sc->tssi_2ghz[4]; 4063 step = sc->step_2ghz; 4064 } else { 4065 tssi = &sc->tssi_5ghz[4]; 4066 step = sc->step_5ghz; 4067 } 4068 4069 if (bbp49 < tssi[0]) { /* lower than reference */ 4070 /* use higher Tx power than default */ 4071 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4072 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4073 /* use lower Tx power than default */ 4074 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4075 } else { 4076 /* use default Tx power */ 4077 d = 0; 4078 } 4079 d *= step; 4080 4081 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4082 4083 /* write adjusted Tx power values for each Tx rate */ 4084 for (ridx = 0; ridx < 5; ridx++) { 4085 if (sc->txpow20mhz[ridx] == 0xffffffff) 4086 continue; 4087 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4088 b4inc(sc->txpow20mhz[ridx], d)); 4089 } 4090 } 4091 4092 void 4093 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4094 { 4095 uint32_t tmp; 4096 if (aux) { 4097 if (sc->mac_ver == 0x5390) { 4098 rt2860_mcu_bbp_write(sc, 152, 4099 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4100 } else { 4101 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4102 RAL_WRITE(sc, RT2860_PCI_EECTRL, 4103 tmp & ~RT2860_C); 4104 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4105 RAL_WRITE(sc, RT2860_GPIO_CTRL, 4106 (tmp & ~0x0808) | 0x08); 4107 } 4108 } else { 4109 if (sc->mac_ver == 0x5390) { 4110 rt2860_mcu_bbp_write(sc, 152, 4111 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4112 } else { 4113 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4114 RAL_WRITE(sc, RT2860_PCI_EECTRL, 4115 tmp | RT2860_C); 4116 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4117 RAL_WRITE(sc, RT2860_GPIO_CTRL, 4118 tmp & ~0x0808); 4119 } 4120 } 4121 } 4122 4123 void 4124 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4125 { 4126 struct ieee80211com *ic = &sc->sc_ic; 4127 u_int chan, group; 4128 4129 chan = ieee80211_chan2ieee(ic, c); 4130 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4131 return; 4132 4133 if (sc->mac_ver == 0x3290 || 4134 sc->mac_ver >= 0x5390) 4135 rt5390_set_chan(sc, chan); 4136 else if (sc->mac_ver >= 0x3071) 4137 rt3090_set_chan(sc, chan); 4138 else 4139 rt2860_set_chan(sc, chan); 4140 4141 /* determine channel group */ 4142 if (chan <= 14) 4143 group = 0; 4144 else if (chan <= 64) 4145 group = 1; 4146 else if (chan <= 128) 4147 group = 2; 4148 else 4149 group = 3; 4150 4151 /* XXX necessary only when group has changed! */ 4152 if (sc->mac_ver <= 0x5390) 4153 rt2860_select_chan_group(sc, group); 4154 4155 DELAY(1000); 4156 } 4157 4158 #ifndef IEEE80211_STA_ONLY 4159 int 4160 rt2860_setup_beacon(struct rt2860_softc *sc) 4161 { 4162 struct ieee80211com *ic = &sc->sc_ic; 4163 struct rt2860_txwi txwi; 4164 struct mbuf *m; 4165 int ridx; 4166 4167 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL) 4168 return ENOBUFS; 4169 4170 memset(&txwi, 0, sizeof txwi); 4171 txwi.wcid = 0xff; 4172 txwi.len = htole16(m->m_pkthdr.len); 4173 /* send beacons at the lowest available rate */ 4174 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4175 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4176 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4177 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4178 txwi.phy |= htole16(RT2860_PHY_OFDM); 4179 txwi.txop = RT2860_TX_TXOP_HT; 4180 txwi.flags = RT2860_TX_TS; 4181 txwi.xflags = RT2860_TX_NSEQ; 4182 4183 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4184 (uint8_t *)&txwi, sizeof txwi); 4185 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4186 mtod(m, uint8_t *), m->m_pkthdr.len); 4187 4188 m_freem(m); 4189 4190 return 0; 4191 } 4192 #endif 4193 4194 void 4195 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4196 { 4197 struct ieee80211com *ic = &sc->sc_ic; 4198 uint32_t tmp; 4199 4200 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4201 4202 tmp &= ~0x1fffff; 4203 tmp |= ic->ic_bss->ni_intval * 16; 4204 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4205 if (ic->ic_opmode == IEEE80211_M_STA) { 4206 /* 4207 * Local TSF is always updated with remote TSF on beacon 4208 * reception. 4209 */ 4210 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4211 } 4212 #ifndef IEEE80211_STA_ONLY 4213 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 4214 tmp |= RT2860_BCN_TX_EN; 4215 /* 4216 * Local TSF is updated with remote TSF on beacon reception 4217 * only if the remote TSF is greater than local TSF. 4218 */ 4219 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4220 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 4221 tmp |= RT2860_BCN_TX_EN; 4222 /* SYNC with nobody */ 4223 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4224 } 4225 #endif 4226 4227 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4228 } 4229