1 /* $OpenBSD: rtl81x9reg.h,v 1.88 2014/11/24 02:03:37 brad Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ 35 */ 36 37 /* 38 * Realtek 8129/8139 register offsets 39 */ 40 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 41 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42 #define RL_IDR2 0x0002 43 #define RL_IDR3 0x0003 44 #define RL_IDR4 0x0004 45 #define RL_IDR5 0x0005 46 /* 0006-0007 reserved */ 47 #define RL_MAR0 0x0008 /* Multicast hash table */ 48 #define RL_MAR1 0x0009 49 #define RL_MAR2 0x000A 50 #define RL_MAR3 0x000B 51 #define RL_MAR4 0x000C 52 #define RL_MAR5 0x000D 53 #define RL_MAR6 0x000E 54 #define RL_MAR7 0x000F 55 56 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66 #define RL_RXADDR 0x0030 /* RX ring start address */ 67 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 69 #define RL_COMMAND 0x0037 /* command register */ 70 #define RL_CURRXADDR 0x0038 /* current address of packet read */ 71 #define RL_CURRXBUF 0x003A /* current RX buffer address */ 72 #define RL_IMR 0x003C /* interrupt mask register */ 73 #define RL_ISR 0x003E /* interrupt status register */ 74 #define RL_TXCFG 0x0040 /* transmit config */ 75 #define RL_RXCFG 0x0044 /* receive config */ 76 #define RL_TIMERCNT 0x0048 /* timer count register */ 77 #define RL_MISSEDPKT 0x004C /* missed packet counter */ 78 #define RL_EECMD 0x0050 /* EEPROM command register */ 79 #define RL_CFG0 0x0051 /* config register #0 */ 80 #define RL_CFG1 0x0052 /* config register #1 */ 81 #define RL_CFG2 0x0053 /* config register #2 */ 82 #define RL_CFG3 0x0054 /* config register #3 */ 83 #define RL_CFG4 0x0055 /* config register #4 */ 84 #define RL_CFG5 0x0056 /* config register #5 */ 85 /* 0057 reserved */ 86 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 87 /* 0059-005A reserved */ 88 #define RL_MII 0x005A /* 8129 chip only */ 89 #define RL_HALTCLK 0x005B 90 #define RL_MULTIINTR 0x005C /* multiple interrupt */ 91 #define RL_PCIREV 0x005E /* PCI revision value */ 92 /* 005F reserved */ 93 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 94 95 #define RL_CSIDR 0x0064 96 #define RL_CSIAR 0x0068 97 98 /* Direct PHY access registers only available on 8139 */ 99 #define RL_BMCR 0x0062 /* PHY basic mode control */ 100 #define RL_BMSR 0x0064 /* PHY basic mode status */ 101 #define RL_ANAR 0x0066 /* PHY autoneg advert */ 102 #define RL_LPAR 0x0068 /* PHY link partner ability */ 103 #define RL_ANER 0x006A /* PHY autoneg expansion */ 104 105 #define RL_DISCCNT 0x006C /* disconnect counter */ 106 #define RL_FALSECAR 0x006E /* false carrier counter */ 107 #define RL_NWAYTST 0x0070 /* NWAY test register */ 108 #define RL_RX_ER 0x0072 /* RX_ER counter */ 109 #define RL_CSCFG 0x0074 /* CS configuration register */ 110 111 /* 112 * When operating in special C+ mode, some of the registers in an 113 * 8139C+ chip have different definitions. These are also used for 114 * the 8169 gigE chip. 115 */ 116 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 117 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 118 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 119 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 120 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ 121 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ 122 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 123 #define RL_TXSTART 0x00D9 /* 8 bits */ 124 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 125 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 126 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 127 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 128 129 /* 130 * Registers specific to the 8169 gigE chip 131 */ 132 #define RL_GTXSTART 0x0038 /* 8 bits */ 133 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 134 #define RL_PHYAR 0x0060 135 #define RL_TBICSR 0x0064 136 #define RL_TBI_ANAR 0x0068 137 #define RL_TBI_LPAR 0x006A 138 #define RL_GMEDIASTAT 0x006C /* 8 bits */ 139 #define RL_MACDBG 0x006D /* 8 bits */ 140 #define RL_GPIO 0x006E /* 8 bits */ 141 #define RL_PMCH 0x006F /* 8 bits */ 142 #define RL_LDPS 0x0082 /* Link Down Power Saving */ 143 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 144 #define RL_IM 0x00E2 145 #define RL_MISC 0x00F0 146 147 /* 148 * TX config register bits 149 */ 150 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 151 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 152 #define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ 153 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 154 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 155 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 156 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 157 #define RL_TXCFG_HWREV 0x7C800000 158 159 #define RL_LOOPTEST_OFF 0x00000000 160 #define RL_LOOPTEST_ON 0x00020000 161 #define RL_LOOPTEST_ON_CPLUS 0x00060000 162 163 /* Known revision codes. */ 164 165 #define RL_HWREV_8169 0x00000000 166 #define RL_HWREV_8169S 0x00800000 167 #define RL_HWREV_8110S 0x04000000 168 #define RL_HWREV_8169_8110SB 0x10000000 169 #define RL_HWREV_8169_8110SCd 0x18000000 170 #define RL_HWREV_8401E 0x24000000 171 #define RL_HWREV_8102EL 0x24800000 172 #define RL_HWREV_8102EL_SPIN1 0x24C00000 173 #define RL_HWREV_8168D 0x28000000 174 #define RL_HWREV_8168DP 0x28800000 175 #define RL_HWREV_8168E 0x2C000000 176 #define RL_HWREV_8168E_VL 0x2C800000 177 #define RL_HWREV_8168B_SPIN1 0x30000000 178 #define RL_HWREV_8100E 0x30800000 179 #define RL_HWREV_8101E 0x34000000 180 #define RL_HWREV_8102E 0x34800000 181 #define RL_HWREV_8103E 0x34C00000 182 #define RL_HWREV_8168B_SPIN2 0x38000000 183 #define RL_HWREV_8168B_SPIN3 0x38400000 184 #define RL_HWREV_8100E_SPIN2 0x38800000 185 #define RL_HWREV_8168C 0x3c000000 186 #define RL_HWREV_8168C_SPIN2 0x3c400000 187 #define RL_HWREV_8168CP 0x3c800000 188 #define RL_HWREV_8105E 0x40800000 189 #define RL_HWREV_8105E_SPIN1 0x40C00000 190 #define RL_HWREV_8402 0x44000000 191 #define RL_HWREV_8106E 0x44800000 192 #define RL_HWREV_8168F 0x48000000 193 #define RL_HWREV_8411 0x48800000 194 #define RL_HWREV_8168G 0x4c000000 195 #define RL_HWREV_8168EP 0x50000000 196 #define RL_HWREV_8168GU 0x50800000 197 #define RL_HWREV_8411B 0x5c800000 198 #define RL_HWREV_8139 0x60000000 199 #define RL_HWREV_8139A 0x70000000 200 #define RL_HWREV_8139AG 0x70800000 201 #define RL_HWREV_8139B 0x78000000 202 #define RL_HWREV_8130 0x7C000000 203 #define RL_HWREV_8139C 0x74000000 204 #define RL_HWREV_8139D 0x74400000 205 #define RL_HWREV_8139CPLUS 0x74800000 206 #define RL_HWREV_8101 0x74c00000 207 #define RL_HWREV_8100 0x78800000 208 #define RL_HWREV_8169_8110SBL 0x7cc00000 209 #define RL_HWREV_8169_8110SCe 0x98000000 210 211 #define RL_TXDMA_16BYTES 0x00000000 212 #define RL_TXDMA_32BYTES 0x00000100 213 #define RL_TXDMA_64BYTES 0x00000200 214 #define RL_TXDMA_128BYTES 0x00000300 215 #define RL_TXDMA_256BYTES 0x00000400 216 #define RL_TXDMA_512BYTES 0x00000500 217 #define RL_TXDMA_1024BYTES 0x00000600 218 #define RL_TXDMA_2048BYTES 0x00000700 219 220 /* 221 * Transmit descriptor status register bits. 222 */ 223 #define RL_TXSTAT_LENMASK 0x00001FFF 224 #define RL_TXSTAT_OWN 0x00002000 225 #define RL_TXSTAT_TX_UNDERRUN 0x00004000 226 #define RL_TXSTAT_TX_OK 0x00008000 227 #define RL_TXSTAT_EARLY_THRESH 0x003F0000 228 #define RL_TXSTAT_COLLCNT 0x0F000000 229 #define RL_TXSTAT_CARR_HBEAT 0x10000000 230 #define RL_TXSTAT_OUTOFWIN 0x20000000 231 #define RL_TXSTAT_TXABRT 0x40000000 232 #define RL_TXSTAT_CARRLOSS 0x80000000 233 234 /* 235 * Interrupt status register bits. 236 */ 237 #define RL_ISR_RX_OK 0x0001 238 #define RL_ISR_RX_ERR 0x0002 239 #define RL_ISR_TX_OK 0x0004 240 #define RL_ISR_TX_ERR 0x0008 241 #define RL_ISR_RX_OVERRUN 0x0010 242 #define RL_ISR_PKT_UNDERRUN 0x0020 243 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 244 #define RL_ISR_FIFO_OFLOW 0x0040 245 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 246 #define RL_ISR_SWI 0x0100 /* C+ only */ 247 #define RL_ISR_CABLE_LEN_CHGD 0x2000 248 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 249 #define RL_ISR_TIMEOUT_EXPIRED 0x4000 250 #define RL_ISR_SYSTEM_ERR 0x8000 251 252 #define RL_INTRS \ 253 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 254 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 255 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 256 257 #define RL_INTRS_CPLUS \ 258 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 259 RL_ISR_RX_OVERRUN|RL_ISR_FIFO_OFLOW|RL_ISR_LINKCHG| \ 260 RL_ISR_SYSTEM_ERR|RL_ISR_TX_OK) 261 262 #define RL_INTRS_TIMER \ 263 (RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 264 RL_ISR_LINKCHG|RL_ISR_SYSTEM_ERR| \ 265 RL_ISR_TIMEOUT_EXPIRED) 266 267 /* 268 * Media status register. (8139 only) 269 */ 270 #define RL_MEDIASTAT_RXPAUSE 0x01 271 #define RL_MEDIASTAT_TXPAUSE 0x02 272 #define RL_MEDIASTAT_LINK 0x04 273 #define RL_MEDIASTAT_SPEED10 0x08 274 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 275 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 276 277 /* 278 * Receive config register. 279 */ 280 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 281 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 282 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 283 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 284 #define RL_RXCFG_RX_RUNT 0x00000010 285 #define RL_RXCFG_RX_ERRPKT 0x00000020 286 #define RL_RXCFG_WRAP 0x00000080 287 #define RL_RXCFG_EARLYOFFV2 0x00000800 288 #define RL_RXCFG_MAXDMA 0x00000700 289 #define RL_RXCFG_BURSZ 0x00001800 290 #define RL_RXCFG_EARLYOFF 0x00003800 291 #define RL_RXCFG_FIFOTHRESH 0x0000E000 292 #define RL_RXCFG_EARLYTHRESH 0x07000000 293 294 #define RL_RXDMA_16BYTES 0x00000000 295 #define RL_RXDMA_32BYTES 0x00000100 296 #define RL_RXDMA_64BYTES 0x00000200 297 #define RL_RXDMA_128BYTES 0x00000300 298 #define RL_RXDMA_256BYTES 0x00000400 299 #define RL_RXDMA_512BYTES 0x00000500 300 #define RL_RXDMA_1024BYTES 0x00000600 301 #define RL_RXDMA_UNLIMITED 0x00000700 302 303 #define RL_RXBUF_8 0x00000000 304 #define RL_RXBUF_16 0x00000800 305 #define RL_RXBUF_32 0x00001000 306 #define RL_RXBUF_64 0x00001800 307 308 #define RL_RXFIFO_16BYTES 0x00000000 309 #define RL_RXFIFO_32BYTES 0x00002000 310 #define RL_RXFIFO_64BYTES 0x00004000 311 #define RL_RXFIFO_128BYTES 0x00006000 312 #define RL_RXFIFO_256BYTES 0x00008000 313 #define RL_RXFIFO_512BYTES 0x0000A000 314 #define RL_RXFIFO_1024BYTES 0x0000C000 315 #define RL_RXFIFO_NOTHRESH 0x0000E000 316 317 /* 318 * Bits in RX status header (included with RX'ed packet 319 * in ring buffer). 320 */ 321 #define RL_RXSTAT_RXOK 0x00000001 322 #define RL_RXSTAT_ALIGNERR 0x00000002 323 #define RL_RXSTAT_CRCERR 0x00000004 324 #define RL_RXSTAT_GIANT 0x00000008 325 #define RL_RXSTAT_RUNT 0x00000010 326 #define RL_RXSTAT_BADSYM 0x00000020 327 #define RL_RXSTAT_BROAD 0x00002000 328 #define RL_RXSTAT_INDIV 0x00004000 329 #define RL_RXSTAT_MULTI 0x00008000 330 #define RL_RXSTAT_LENMASK 0xFFFF0000 331 332 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 333 /* 334 * Command register. 335 */ 336 #define RL_CMD_EMPTY_RXBUF 0x0001 337 #define RL_CMD_TX_ENB 0x0004 338 #define RL_CMD_RX_ENB 0x0008 339 #define RL_CMD_RESET 0x0010 340 #define RL_CMD_STOPREQ 0x0080 341 342 /* 343 * EEPROM control register 344 */ 345 #define RL_EE_DATAOUT 0x01 /* Data out */ 346 #define RL_EE_DATAIN 0x02 /* Data in */ 347 #define RL_EE_CLK 0x04 /* clock */ 348 #define RL_EE_SEL 0x08 /* chip select */ 349 #define RL_EE_MODE (0x40|0x80) 350 351 #define RL_EEMODE_OFF 0x00 352 #define RL_EEMODE_AUTOLOAD 0x40 353 #define RL_EEMODE_PROGRAM 0x80 354 #define RL_EEMODE_WRITECFG (0x80|0x40) 355 356 /* 9346/9356 EEPROM commands */ 357 358 #define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 359 #define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 360 361 #define RL_9346_WRITE 0x5 362 #define RL_9346_READ 0x6 363 #define RL_9346_ERASE 0x7 364 #define RL_9346_EWEN 0x4 365 #define RL_9346_EWEN_ADDR 0x30 366 #define RL_9456_EWDS 0x4 367 #define RL_9346_EWDS_ADDR 0x00 368 369 #define RL_EECMD_WRITE 0x5 /* 0101b */ 370 #define RL_EECMD_READ 0x6 /* 0110b */ 371 #define RL_EECMD_ERASE 0x7 /* 0111b */ 372 #define RL_EECMD_LEN 4 373 374 #define RL_EEADDR_LEN0 6 /* 9346 */ 375 #define RL_EEADDR_LEN1 8 /* 9356 */ 376 377 #define RL_EECMD_READ_6BIT 0x180 /* XXX */ 378 #define RL_EECMD_READ_8BIT 0x600 /* EECMD_READ above maybe wrong? */ 379 380 #define RL_EE_ID 0x00 381 #define RL_EE_PCI_VID 0x01 382 #define RL_EE_PCI_DID 0x02 383 /* Location of station address inside EEPROM */ 384 #define RL_EE_EADDR 0x07 385 386 /* 387 * MII register (8129 only) 388 */ 389 #define RL_MII_CLK 0x01 390 #define RL_MII_DATAIN 0x02 391 #define RL_MII_DATAOUT 0x04 392 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 393 394 /* 395 * Config 0 register 396 */ 397 #define RL_CFG0_ROM0 0x01 398 #define RL_CFG0_ROM1 0x02 399 #define RL_CFG0_ROM2 0x04 400 #define RL_CFG0_PL0 0x08 401 #define RL_CFG0_PL1 0x10 402 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 403 #define RL_CFG0_PCS 0x40 404 #define RL_CFG0_SCR 0x80 405 406 /* 407 * Config 1 register 408 */ 409 #define RL_CFG1_PWRDWN 0x01 410 #define RL_CFG1_PME 0x01 411 #define RL_CFG1_SLEEP 0x02 412 #define RL_CFG1_VPDEN 0x02 413 #define RL_CFG1_IOMAP 0x04 414 #define RL_CFG1_MEMMAP 0x08 415 #define RL_CFG1_RSVD 0x10 416 #define RL_CFG1_LWACT 0x10 417 #define RL_CFG1_DRVLOAD 0x20 418 #define RL_CFG1_LED0 0x40 419 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 420 #define RL_CFG1_LED1 0x80 421 422 /* 423 * Config 2 register 424 */ 425 #define RL_CFG2_PCI_MASK 0x07 426 #define RL_CFG2_PCI_33MHZ 0x00 427 #define RL_CFG2_PCI_66MHZ 0x01 428 #define RL_CFG2_PCI_64BIT 0x08 429 #define RL_CFG2_AUXPWR 0x10 430 #define RL_CFG2_MSI 0x20 431 432 /* 433 * Config 3 register 434 */ 435 #define RL_CFG3_GRANTSEL 0x80 436 #define RL_CFG3_WOL_MAGIC 0x20 437 #define RL_CFG3_WOL_LINK 0x10 438 #define RL_CFG3_FAST_B2B 0x01 439 440 /* 441 * Config 4 register 442 */ 443 #define RL_CFG4_LWPTN 0x04 444 #define RL_CFG4_LWPME 0x10 445 446 /* 447 * Config 5 register 448 */ 449 #define RL_CFG5_WOL_BCAST 0x40 450 #define RL_CFG5_WOL_MCAST 0x20 451 #define RL_CFG5_WOL_UCAST 0x10 452 #define RL_CFG5_WOL_LANWAKE 0x02 453 #define RL_CFG5_PME_STS 0x01 454 455 /* 456 * 8139C+ register definitions 457 */ 458 459 /* RL_DUMPSTATS_LO register */ 460 461 #define RL_DUMPSTATS_START 0x00000008 462 463 /* Transmit start register */ 464 465 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 466 #define RL_TXSTART_START 0x40 /* start normal queue transmit */ 467 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 468 469 /* 470 * Config 2 register, 8139C+/8169/8169S/8110S only 471 */ 472 #define RL_CFG2_BUSFREQ 0x07 473 #define RL_CFG2_BUSWIDTH 0x08 474 #define RL_CFG2_AUXPWRSTS 0x10 475 476 #define RL_BUSFREQ_33MHZ 0x00 477 #define RL_BUSFREQ_66MHZ 0x01 478 479 #define RL_BUSWIDTH_32BITS 0x00 480 #define RL_BUSWIDTH_64BITS 0x08 481 482 /* C+ mode command register */ 483 484 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 485 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 486 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 487 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 488 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 489 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 490 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 491 #define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 492 #define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 493 #define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 494 #define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 495 #define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 496 #define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 497 #define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 498 #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 499 500 /* C+ early transmit threshold */ 501 502 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 503 504 /* 505 * Gigabit PHY access register (8169 only) 506 */ 507 508 #define RL_PHYAR_PHYDATA 0x0000FFFF 509 #define RL_PHYAR_PHYREG 0x001F0000 510 #define RL_PHYAR_BUSY 0x80000000 511 512 /* 513 * Gigabit media status (8169 only) 514 */ 515 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 516 #define RL_GMEDIASTAT_LINK 0x02 /* link up */ 517 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 518 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 519 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 520 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 521 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 522 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 523 524 /* 525 * The Realtek doesn't use a fragment-based descriptor mechanism. 526 * Instead, there are only four register sets, each of which represents 527 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 528 * packet buffer (32-bit aligned!) and we place the buffer addresses in 529 * the registers so the chip knows where they are. 530 * 531 * We can sort of kludge together the same kind of buffer management 532 * used in previous drivers, but we have to do buffer copies almost all 533 * the time, so it doesn't really buy us much. 534 * 535 * For reception, there's just one large buffer where the chip stores 536 * all received packets. 537 */ 538 539 #define RL_RX_BUF_SZ RL_RXBUF_64 540 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 541 #define RL_TX_LIST_CNT 4 542 #define RL_MIN_FRAMELEN 60 543 #define RL_TXTHRESH(x) ((x) << 11) 544 #define RL_TX_THRESH_INIT 96 545 #define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 546 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 547 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES 548 549 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 550 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 551 552 #define RL_IM_MAGIC 0x5050 553 #define RL_IM_RXTIME(t) ((t) & 0xf) 554 #define RL_IM_TXTIME(t) (((t) & 0xf) << 8) 555 556 struct rl_chain_data { 557 u_int16_t cur_rx; 558 caddr_t rl_rx_buf; 559 caddr_t rl_rx_buf_ptr; 560 bus_addr_t rl_rx_buf_pa; 561 562 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 563 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 564 u_int8_t last_tx; 565 u_int8_t cur_tx; 566 }; 567 568 569 /* 570 * The 8139C+ and 8160 gigE chips support descriptor-based TX 571 * and RX. In fact, they even support TCP large send. Descriptors 572 * must be allocated in contiguous blocks that are aligned on a 573 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 574 */ 575 576 /* 577 * RX/TX descriptor definition. When large send mode is enabled, the 578 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 579 * the checksum offload bits are disabled. The structure layout is 580 * the same for RX and TX descriptors 581 */ 582 583 struct rl_desc { 584 volatile u_int32_t rl_cmdstat; 585 volatile u_int32_t rl_vlanctl; 586 volatile u_int32_t rl_bufaddr_lo; 587 volatile u_int32_t rl_bufaddr_hi; 588 }; 589 590 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 591 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 592 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 593 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 594 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 595 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 596 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 597 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 598 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 599 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 600 601 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 602 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 603 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 604 #define RL_TDESC_CMD_IPCSUMV2 0x20000000 605 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000 606 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000 607 608 /* 609 * Error bits are valid only on the last descriptor of a frame 610 * (i.e. RL_TDESC_CMD_EOF == 1) 611 */ 612 613 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 614 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 615 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 616 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 617 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 618 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 619 #define RL_TDESC_STAT_OWN 0x80000000 620 621 /* 622 * RX descriptor cmd/vlan definitions 623 */ 624 625 #define RL_RDESC_CMD_EOR 0x40000000 626 #define RL_RDESC_CMD_OWN 0x80000000 627 #define RL_RDESC_CMD_BUFLEN 0x00001FFF 628 629 #define RL_RDESC_STAT_OWN 0x80000000 630 #define RL_RDESC_STAT_EOR 0x40000000 631 #define RL_RDESC_STAT_SOF 0x20000000 632 #define RL_RDESC_STAT_EOF 0x10000000 633 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 634 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 635 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 636 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 637 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 638 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 639 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 640 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 641 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 642 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 643 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 644 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 645 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 646 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 647 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 648 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 649 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 650 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 651 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 652 RL_RDESC_STAT_CRCERR) 653 654 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 655 (rl_vlandata valid)*/ 656 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 657 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 658 #define RL_RDESC_IPV6 0x80000000 659 #define RL_RDESC_IPV4 0x40000000 660 661 #define RL_PROTOID_NONIP 0x00000000 662 #define RL_PROTOID_TCPIP 0x00010000 663 #define RL_PROTOID_UDPIP 0x00020000 664 #define RL_PROTOID_IP 0x00030000 665 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 666 RL_PROTOID_TCPIP) 667 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 668 RL_PROTOID_UDPIP) 669 670 /* 671 * Statistics counter structure (8139C+ and 8169 only) 672 */ 673 struct rl_stats { 674 u_int32_t rl_tx_pkts_lo; 675 u_int32_t rl_tx_pkts_hi; 676 u_int32_t rl_tx_errs_lo; 677 u_int32_t rl_tx_errs_hi; 678 u_int32_t rl_tx_errs; 679 u_int16_t rl_missed_pkts; 680 u_int16_t rl_rx_framealign_errs; 681 u_int32_t rl_tx_onecoll; 682 u_int32_t rl_tx_multicolls; 683 u_int32_t rl_rx_ucasts_hi; 684 u_int32_t rl_rx_ucasts_lo; 685 u_int32_t rl_rx_bcasts_lo; 686 u_int32_t rl_rx_bcasts_hi; 687 u_int32_t rl_rx_mcasts; 688 u_int16_t rl_tx_aborts; 689 u_int16_t rl_rx_underruns; 690 }; 691 692 #define RL_RX_DESC_CNT 64 693 #define RL_TX_DESC_CNT_8139 64 694 #define RL_TX_DESC_CNT_8169 512 695 696 #define RL_TX_QLEN 64 697 698 #define RL_NTXSEGS 32 699 700 #define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 701 #define RL_RING_ALIGN 256 702 #define RL_PKTSZ(x) ((x)/* >> 3*/) 703 #ifdef __STRICT_ALIGNMENT 704 #define RE_ETHER_ALIGN 2 705 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 706 #else 707 #define RE_ETHER_ALIGN 0 708 #define RE_RX_DESC_BUFLEN MCLBYTES 709 #endif 710 711 #define RL_TX_DESC_CNT(sc) \ 712 ((sc)->rl_ldata.rl_tx_desc_cnt) 713 #define RL_TX_LIST_SZ(sc) \ 714 (RL_TX_DESC_CNT(sc) * sizeof(struct rl_desc)) 715 #define RL_NEXT_TX_DESC(sc, x) \ 716 (((x) + 1) % RL_TX_DESC_CNT(sc)) 717 #define RL_NEXT_RX_DESC(sc, x) \ 718 (((x) + 1) % RL_RX_DESC_CNT) 719 #define RL_NEXT_TXQ(sc, x) \ 720 (((x) + 1) % RL_TX_QLEN) 721 722 #define RL_TXDESCSYNC(sc, idx, ops) \ 723 bus_dmamap_sync((sc)->sc_dmat, \ 724 (sc)->rl_ldata.rl_tx_list_map, \ 725 sizeof(struct rl_desc) * (idx), \ 726 sizeof(struct rl_desc), \ 727 (ops)) 728 #define RL_RXDESCSYNC(sc, idx, ops) \ 729 bus_dmamap_sync((sc)->sc_dmat, \ 730 (sc)->rl_ldata.rl_rx_list_map, \ 731 sizeof(struct rl_desc) * (idx), \ 732 sizeof(struct rl_desc), \ 733 (ops)) 734 735 #define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 736 #define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 737 738 /* see comment in dev/ic/re.c */ 739 #define RL_JUMBO_FRAMELEN 7440 740 #define RL_JUMBO_MTU_4K \ 741 ((4 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 742 #define RL_JUMBO_MTU_6K \ 743 ((6 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 744 #define RL_JUMBO_MTU_7K \ 745 (RL_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 746 #define RL_JUMBO_MTU_9K \ 747 ((9 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 748 #define RL_MTU ETHERMTU 749 750 #define MAX_NUM_MULTICAST_ADDRESSES 128 751 752 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 753 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 754 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 755 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 756 #define RL_CUR_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 757 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 758 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 759 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 760 #define RL_LAST_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 761 762 struct rl_type { 763 u_int16_t rl_vid; 764 u_int16_t rl_did; 765 }; 766 767 struct rl_mii_frame { 768 u_int8_t mii_stdelim; 769 u_int8_t mii_opcode; 770 u_int8_t mii_phyaddr; 771 u_int8_t mii_regaddr; 772 u_int8_t mii_turnaround; 773 u_int16_t mii_data; 774 }; 775 776 /* 777 * MII constants 778 */ 779 #define RL_MII_STARTDELIM 0x01 780 #define RL_MII_READOP 0x02 781 #define RL_MII_WRITEOP 0x01 782 #define RL_MII_TURNAROUND 0x02 783 784 #define RL_UNKNOWN 0 785 #define RL_8129 1 786 #define RL_8139 2 787 788 struct rl_rxsoft { 789 struct mbuf *rxs_mbuf; 790 bus_dmamap_t rxs_dmamap; 791 }; 792 793 struct rl_txq { 794 struct mbuf *txq_mbuf; 795 bus_dmamap_t txq_dmamap; 796 int txq_descidx; 797 int txq_nsegs; 798 }; 799 800 struct rl_list_data { 801 struct rl_txq rl_txq[RL_TX_QLEN]; 802 int rl_txq_considx; 803 int rl_txq_prodidx; 804 805 bus_dmamap_t rl_tx_list_map; 806 struct rl_desc *rl_tx_list; 807 int rl_tx_free; /* # of free descriptors */ 808 int rl_tx_nextfree; /* next descriptor to use */ 809 int rl_tx_desc_cnt; /* # of descriptors */ 810 bus_dma_segment_t rl_tx_listseg; 811 int rl_tx_listnseg; 812 813 struct rl_rxsoft rl_rxsoft[RL_RX_DESC_CNT]; 814 bus_dmamap_t rl_rx_list_map; 815 struct rl_desc *rl_rx_list; 816 int rl_rx_considx; 817 int rl_rx_prodidx; 818 struct if_rxring rl_rx_ring; 819 bus_dma_segment_t rl_rx_listseg; 820 int rl_rx_listnseg; 821 }; 822 823 struct rl_softc { 824 struct device sc_dev; /* us, as a device */ 825 void * sc_ih; /* interrupt vectoring */ 826 bus_space_handle_t rl_bhandle; /* bus space handle */ 827 bus_space_tag_t rl_btag; /* bus space tag */ 828 bus_dma_tag_t sc_dmat; 829 bus_dma_segment_t sc_rx_seg; 830 bus_dmamap_t sc_rx_dmamap; 831 struct arpcom sc_arpcom; /* interface info */ 832 struct mii_data sc_mii; /* MII information */ 833 u_int8_t rl_type; 834 u_int32_t sc_hwrev; 835 u_int16_t sc_product; 836 int rl_max_mtu; 837 int rl_eecmd_read; 838 int rl_eewidth; 839 int rl_bus_speed; 840 int rl_txthresh; 841 struct rl_chain_data rl_cdata; 842 struct timeout sc_tick_tmo; 843 844 struct rl_list_data rl_ldata; 845 struct mbuf *rl_head; 846 struct mbuf *rl_tail; 847 u_int32_t rl_rxlenmask; 848 struct timeout timer_handle; 849 850 int rl_txstart; 851 u_int32_t rl_flags; 852 #define RL_FLAG_MSI 0x00000001 853 #define RL_FLAG_PCI64 0x00000002 854 #define RL_FLAG_PCIE 0x00000004 855 #define RL_FLAG_PHYWAKE 0x00000008 856 #define RL_FLAG_PAR 0x00000010 857 #define RL_FLAG_DESCV2 0x00000020 858 #define RL_FLAG_MACSTAT 0x00000040 859 #define RL_FLAG_HWIM 0x00000080 860 #define RL_FLAG_TIMERINTR 0x00000100 861 #define RL_FLAG_MACRESET 0x00000200 862 #define RL_FLAG_CMDSTOP 0x00000400 863 #define RL_FLAG_MACSLEEP 0x00000800 864 #define RL_FLAG_AUTOPAD 0x00001000 865 #define RL_FLAG_LINK 0x00002000 866 #define RL_FLAG_PHYWAKE_PM 0x00004000 867 #define RL_FLAG_EARLYOFF 0x00008000 868 #define RL_FLAG_EARLYOFFV2 0x00010000 869 #define RL_FLAG_RXDV_GATED 0x00020000 870 #define RL_FLAG_FASTETHER 0x00040000 871 #define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00080000 872 #define RL_FLAG_JUMBOV2 0x00100000 873 #define RL_FLAG_WOL_MANLINK 0x00200000 874 #define RL_FLAG_WAIT_TXPOLL 0x00400000 875 #define RL_FLAG_WOLRXENB 0x00800000 876 877 u_int16_t rl_intrs; 878 u_int16_t rl_tx_ack; 879 u_int16_t rl_rx_ack; 880 int rl_tx_time; 881 int rl_rx_time; 882 int rl_sim_time; 883 int rl_imtype; 884 #define RL_IMTYPE_NONE 0 885 #define RL_IMTYPE_SIM 1 /* simulated */ 886 #define RL_IMTYPE_HW 2 /* hardware based */ 887 }; 888 889 /* 890 * re(4) hardware ip4csum-tx could be mangled with 28 byte or less IP packets 891 */ 892 #define RL_IP4CSUMTX_MINLEN 28 893 #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 894 /* 895 * XXX 896 * We are allocating pad DMA buffer after RX DMA descs for now 897 * because RL_TX_LIST_SZ(sc) always occupies whole page but 898 * RL_RX_LIST_SZ is less than PAGE_SIZE so there is some unused region. 899 */ 900 #define RL_RX_DMAMEM_SZ (RL_RX_LIST_SZ + RL_IP4CSUMTX_PADLEN) 901 #define RL_TXPADOFF RL_RX_LIST_SZ 902 #define RL_TXPADDADDR(sc) \ 903 ((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF) 904 905 /* 906 * register space access macros 907 */ 908 #define CSR_WRITE_RAW_4(sc, csr, val) \ 909 bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4) 910 #define CSR_WRITE_4(sc, csr, val) \ 911 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) 912 #define CSR_WRITE_2(sc, csr, val) \ 913 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) 914 #define CSR_WRITE_1(sc, csr, val) \ 915 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) 916 917 #define CSR_READ_4(sc, csr) \ 918 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) 919 #define CSR_READ_2(sc, csr) \ 920 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) 921 #define CSR_READ_1(sc, csr) \ 922 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) 923 924 #define CSR_SETBIT_1(sc, offset, val) \ 925 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 926 927 #define CSR_CLRBIT_1(sc, offset, val) \ 928 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 929 930 #define CSR_SETBIT_2(sc, offset, val) \ 931 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 932 933 #define CSR_CLRBIT_2(sc, offset, val) \ 934 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 935 936 #define CSR_SETBIT_4(sc, offset, val) \ 937 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 938 939 #define CSR_CLRBIT_4(sc, offset, val) \ 940 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 941 942 #define RL_TIMEOUT 1000 943 #define RL_PHY_TIMEOUT 20 944 945 /* 946 * General constants that are fun to know. 947 * 948 * Realtek PCI vendor ID 949 */ 950 #define RT_VENDORID 0x10EC 951 952 /* 953 * Realtek chip device IDs. 954 */ 955 #define RT_DEVICEID_8129 0x8129 956 #define RT_DEVICEID_8101E 0x8136 957 #define RT_DEVICEID_8138 0x8138 958 #define RT_DEVICEID_8139 0x8139 959 #define RT_DEVICEID_8169SC 0x8167 960 #define RT_DEVICEID_8168 0x8168 961 #define RT_DEVICEID_8169 0x8169 962 #define RT_DEVICEID_8100 0x8100 963 964 /* 965 * Accton PCI vendor ID 966 */ 967 #define ACCTON_VENDORID 0x1113 968 969 /* 970 * Accton MPX 5030/5038 device ID. 971 */ 972 #define ACCTON_DEVICEID_5030 0x1211 973 974 /* 975 * Delta Electronics Vendor ID. 976 */ 977 #define DELTA_VENDORID 0x1500 978 979 /* 980 * Delta device IDs. 981 */ 982 #define DELTA_DEVICEID_8139 0x1360 983 984 /* 985 * Addtron vendor ID. 986 */ 987 #define ADDTRON_VENDORID 0x4033 988 989 /* 990 * Addtron device IDs. 991 */ 992 #define ADDTRON_DEVICEID_8139 0x1360 993 994 /* D-Link Vendor ID */ 995 #define DLINK_VENDORID 0x1186 996 997 /* D-Link device IDs */ 998 #define DLINK_DEVICEID_8139 0x1300 999 #define DLINK_DEVICEID_8139_2 0x1340 1000 1001 /* Abocom device IDs */ 1002 #define ABOCOM_DEVICEID_8139 0xab06 1003 1004 /* 1005 * PCI low memory base and low I/O base register, and 1006 * other PCI registers. Note: some are only available on 1007 * the 3c905B, in particular those that related to power management. 1008 */ 1009 1010 #define RL_PCI_VENDOR_ID 0x00 1011 #define RL_PCI_DEVICE_ID 0x02 1012 #define RL_PCI_COMMAND 0x04 1013 #define RL_PCI_STATUS 0x06 1014 #define RL_PCI_CLASSCODE 0x09 1015 #define RL_PCI_LATENCY_TIMER 0x0D 1016 #define RL_PCI_HEADER_TYPE 0x0E 1017 #define RL_PCI_LOIO 0x10 1018 #define RL_PCI_LOMEM 0x14 1019 #define RL_PCI_BIOSROM 0x30 1020 #define RL_PCI_INTLINE 0x3C 1021 #define RL_PCI_INTPIN 0x3D 1022 #define RL_PCI_MINGNT 0x3E 1023 #define RL_PCI_MINLAT 0x0F 1024 #define RL_PCI_PMCSR 0x44 1025 #define RL_PCI_RESETOPT 0x48 1026 #define RL_PCI_EEPROM_DATA 0x4C 1027 1028 #define RL_PCI_CAPID 0x50 /* 8 bits */ 1029 #define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 1030 #define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1031 #define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1032 1033 #define RL_PSTATE_MASK 0x0003 1034 #define RL_PSTATE_D0 0x0000 1035 #define RL_PSTATE_D1 0x0001 1036 #define RL_PSTATE_D2 0x0002 1037 #define RL_PSTATE_D3 0x0003 1038 #define RL_PME_EN 0x0100 1039 #define RL_PME_STATUS 0x8000 1040 1041 extern int rl_attach(struct rl_softc *); 1042 extern int rl_intr(void *); 1043 extern void rl_setmulti(struct rl_softc *); 1044 int rl_detach(struct rl_softc *); 1045 int rl_activate(struct device *, int); 1046