1 /* $OpenBSD: rtsxreg.h,v 1.5 2020/08/24 15:06:10 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _RTSXREG_H_ 21 #define _RTSXREG_H_ 22 23 /* Host command buffer control register. */ 24 #define RTSX_HCBAR 0x00 25 #define RTSX_HCBCTLR 0x04 26 #define RTSX_START_CMD (1U << 31) 27 #define RTSX_HW_AUTO_RSP (1U << 30) 28 #define RTSX_STOP_CMD (1U << 28) 29 30 /* Host data buffer control register. */ 31 #define RTSX_HDBAR 0x08 32 #define RTSX_HDBCTLR 0x0C 33 #define RTSX_TRIG_DMA (1U << 31) 34 #define RTSX_DMA_READ (1U << 29) 35 #define RTSX_STOP_DMA (1U << 28) 36 #define RTSX_ADMA_MODE (2U << 26) 37 38 /* Interrupt pending register. */ 39 #define RTSX_BIPR 0x14 40 #define RTSX_CMD_DONE_INT (1U << 31) 41 #define RTSX_DATA_DONE_INT (1U << 30) 42 #define RTSX_TRANS_OK_INT (1U << 29) 43 #define RTSX_TRANS_FAIL_INT (1U << 28) 44 #define RTSX_XD_INT (1U << 27) 45 #define RTSX_MS_INT (1U << 26) 46 #define RTSX_SD_INT (1U << 25) 47 #define RTSX_SD_WRITE_PROTECT (1U << 19) 48 #define RTSX_XD_EXIST (1U << 18) 49 #define RTSX_MS_EXIST (1U << 17) 50 #define RTSX_SD_EXIST (1U << 16) 51 #define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST) 52 #define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT) 53 54 /* Chip register access. */ 55 #define RTSX_HAIMR 0x10 56 #define RTSX_HAIMR_WRITE 0x40000000 57 #define RTSX_HAIMR_BUSY 0x80000000 58 59 /* Interrupt enable register. */ 60 #define RTSX_BIER 0x18 61 #define RTSX_CMD_DONE_INT_EN (1U << 31) 62 #define RTSX_DATA_DONE_INT_EN (1U << 30) 63 #define RTSX_TRANS_OK_INT_EN (1U << 29) 64 #define RTSX_TRANS_FAIL_INT_EN (1U << 28) 65 #define RTSX_XD_INT_EN (1U << 27) 66 #define RTSX_MS_INT_EN (1U << 26) 67 #define RTSX_SD_INT_EN (1U << 25) 68 #define RTSX_GPIO0_INT_EN (1U << 24) 69 #define RTSX_MS_OC_INT_EN (1U << 23) 70 #define RTSX_SD_OC_INT_EN (1U << 22) 71 72 /* Power on/off. */ 73 #define RTSX_FPDCTL 0xFC00 74 #define RTSX_SSC_POWER_DOWN 0x01 75 #define RTSX_SD_OC_POWER_DOWN 0x02 76 #define RTSX_MS_OC_POWER_DOWN 0x04 77 #define RTSX_ALL_POWER_DOWN 0x07 78 #define RTSX_OC_POWER_DOWN 0x06 79 80 /* Card power control register. */ 81 #define RTSX_CARD_PWR_CTL 0xFD50 82 #define RTSX_SD_PWR_ON 0x00 83 #define RTSX_SD_PARTIAL_PWR_ON 0x01 84 #define RTSX_SD_PWR_OFF 0x03 85 #define RTSX_SD_PWR_MASK 0x03 86 #define RTSX_PMOS_STRG_MASK 0x10 87 #define RTSX_PMOS_STRG_400mA 0x00 88 #define RTSX_PMOS_STRG_800mA 0x10 89 90 #define RTSX_MS_PWR_OFF 0x0C 91 #define RTSX_MS_PWR_ON 0x00 92 #define RTSX_MS_PARTIAL_PWR_ON 0x04 93 94 #define RTSX_CARD_SHARE_MODE 0xFD52 95 #define RTSX_CARD_SHARE_48_XD 0x02 96 #define RTSX_CARD_SHARE_48_SD 0x04 97 #define RTSX_CARD_SHARE_48_MS 0x08 98 #define RTSX_CARD_DRIVE_SEL 0xFE53 99 100 /* Card clock. */ 101 #define RTSX_CARD_CLK_EN 0xFD69 102 #define RTSX_XD_CLK_EN 0x02 103 #define RTSX_SD_CLK_EN 0x04 104 #define RTSX_MS_CLK_EN 0x08 105 #define RTSX_SPI_CLK_EN 0x10 106 #define RTSX_CARD_CLK_EN_ALL \ 107 (RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN) 108 109 #define RTSX_SDIO_CTRL 0xFD6B 110 #define RTSX_SDIO_BUS_CTRL 0x01 111 #define RTSX_SDIO_CD_CTRL 0x02 112 113 /* Internal clock. */ 114 #define RTSX_CLK_CTL 0xFC02 115 #define RTSX_CLK_LOW_FREQ 0x01 116 117 /* Internal clock divisor values. */ 118 #define RTSX_CLK_DIV 0xFC03 119 #define RTSX_CLK_DIV_1 0x01 120 #define RTSX_CLK_DIV_2 0x02 121 #define RTSX_CLK_DIV_4 0x03 122 #define RTSX_CLK_DIV_8 0x04 123 124 /* Internal clock selection. */ 125 #define RTSX_CLK_SEL 0xFC04 126 #define RTSX_SSC_80 0 127 #define RTSX_SSC_100 1 128 #define RTSX_SSC_120 2 129 #define RTSX_SSC_150 3 130 #define RTSX_SSC_200 4 131 132 #define RTSX_SSC_DIV_N_0 0xFC0F 133 134 #define RTSX_SSC_CTL1 0xFC11 135 #define RTSX_RSTB 0x80 136 #define RTSX_SSC_8X_EN 0x40 137 #define RTSX_SSC_FIX_FRAC 0x20 138 #define RTSX_SSC_SEL_1M 0x00 139 #define RTSX_SSC_SEL_2M 0x08 140 #define RTSX_SSC_SEL_2M 0x08 141 #define RTSX_SSC_SEL_4M 0x10 142 #define RTSX_SSC_SEL_8M 0x18 143 #define RTSX_SSC_CTL2 0xFC12 144 #define RTSX_SSC_DEPTH_MASK 0x07 145 146 /* RC oscillator, default is 2M */ 147 #define RTSX_RCCTL 0xFC14 148 #define RTSX_RCCTL_F_400K 0x0 149 #define RTSX_RCCTL_F_2M 0x1 150 151 /* RTS5229-only. */ 152 #define RTSX_OLT_LED_CTL 0xFC1E 153 #define RTSX_OLT_LED_PERIOD 0x02 154 #define RTSX_OLT_LED_AUTOBLINK 0x08 155 156 #define RTSX_GPIO_CTL 0xFC1F 157 #define RTSX_GPIO_LED_ON 0x02 158 159 /* Host controller commands. */ 160 #define RTSX_READ_REG_CMD 0 161 #define RTSX_WRITE_REG_CMD 1 162 #define RTSX_CHECK_REG_CMD 2 163 164 165 #define RTSX_OCPCTL 0xFC15 166 #define RTSX_OCPSTAT 0xFC16 167 #define RTSX_OCPGLITCH 0xFC17 168 #define RTSX_OCPPARA1 0xFC18 169 #define RTSX_OCPPARA2 0xFC19 170 171 /* FPGA */ 172 #define RTSX_FPGA_PULL_CTL 0xFC1D 173 #define RTSX_FPGA_MS_PULL_CTL_BIT 0x10 174 #define RTSX_FPGA_SD_PULL_CTL_BIT 0x08 175 176 /* Clock source configuration register. */ 177 #define RTSX_CARD_CLK_SOURCE 0xFC2E 178 #define RTSX_CRC_FIX_CLK (0x00 << 0) 179 #define RTSX_CRC_VAR_CLK0 (0x01 << 0) 180 #define RTSX_CRC_VAR_CLK1 (0x02 << 0) 181 #define RTSX_SD30_FIX_CLK (0x00 << 2) 182 #define RTSX_SD30_VAR_CLK0 (0x01 << 2) 183 #define RTSX_SD30_VAR_CLK1 (0x02 << 2) 184 #define RTSX_SAMPLE_FIX_CLK (0x00 << 4) 185 #define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4) 186 #define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4) 187 188 189 /* ASIC */ 190 #define RTSX_CARD_PULL_CTL1 0xFD60 191 #define RTSX_CARD_PULL_CTL2 0xFD61 192 #define RTSX_CARD_PULL_CTL3 0xFD62 193 194 #define RTSX_PULL_CTL_DISABLE12 0x55 195 #define RTSX_PULL_CTL_DISABLE3 0xD5 196 #define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5 197 #define RTSX_PULL_CTL_ENABLE12 0xAA 198 #define RTSX_PULL_CTL_ENABLE3 0xE9 199 #define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9 200 201 /* SD configuration register 1 (clock divider, bus mode and width). */ 202 #define RTSX_SD_CFG1 0xFDA0 203 #define RTSX_CLK_DIVIDE_0 0x00 204 #define RTSX_CLK_DIVIDE_128 0x80 205 #define RTSX_CLK_DIVIDE_256 0xC0 206 #define RTSX_CLK_DIVIDE_MASK 0xC0 207 #define RTSX_SD20_MODE 0x00 208 #define RTSX_SDDDR_MODE 0x04 209 #define RTSX_SD30_MODE 0x08 210 #define RTSX_SD_MODE_MASK 0x0C 211 #define RTSX_BUS_WIDTH_1 0x00 212 #define RTSX_BUS_WIDTH_4 0x01 213 #define RTSX_BUS_WIDTH_8 0x02 214 #define RTSX_BUS_WIDTH_MASK 0x03 215 216 /* SD configuration register 2 (SD command response flags). */ 217 #define RTSX_SD_CFG2 0xFDA1 218 #define RTSX_SD_CALCULATE_CRC7 0x00 219 #define RTSX_SD_NO_CALCULATE_CRC7 0x80 220 #define RTSX_SD_CHECK_CRC16 0x00 221 #define RTSX_SD_NO_CHECK_CRC16 0x40 222 #define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20 223 #define RTSX_SD_WAIT_BUSY_END 0x08 224 #define RTSX_SD_NO_WAIT_BUSY_END 0x00 225 #define RTSX_SD_CHECK_CRC7 0x00 226 #define RTSX_SD_NO_CHECK_CRC7 0x04 227 #define RTSX_SD_RSP_LEN_0 0x00 228 #define RTSX_SD_RSP_LEN_6 0x01 229 #define RTSX_SD_RSP_LEN_17 0x02 230 /* SD command response types. */ 231 #define RTSX_SD_RSP_TYPE_R0 0x04 232 #define RTSX_SD_RSP_TYPE_R1 0x01 233 #define RTSX_SD_RSP_TYPE_R1B 0x09 234 #define RTSX_SD_RSP_TYPE_R2 0x02 235 #define RTSX_SD_RSP_TYPE_R3 0x05 236 #define RTSX_SD_RSP_TYPE_R4 0x05 237 #define RTSX_SD_RSP_TYPE_R5 0x01 238 #define RTSX_SD_RSP_TYPE_R6 0x01 239 #define RTSX_SD_RSP_TYPE_R7 0x01 240 241 #define RTSX_SD_STAT1 0xFDA3 242 #define RTSX_SD_CRC7_ERR 0x80 243 #define RTSX_SD_CRC16_ERR 0x40 244 #define RTSX_SD_CRC_WRITE_ERR 0x20 245 #define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 246 #define RTSX_GET_CRC_TIME_OUT 0x02 247 #define RTSX_SD_TUNING_COMPARE_ERR 0x01 248 #define RTSX_SD_STAT2 0xFDA4 249 #define RTSX_SD_RSP_80CLK_TIMEOUT 0x01 250 251 #define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR) 252 253 /* SD bus status register. */ 254 #define RTSX_SD_BUS_STAT 0xFDA5 255 #define RTSX_SD_CLK_TOGGLE_EN 0x80 256 #define RTSX_SD_CLK_FORCE_STOP 0x40 257 #define RTSX_SD_DAT3_STATUS 0x10 258 #define RTSX_SD_DAT2_STATUS 0x08 259 #define RTSX_SD_DAT1_STATUS 0x04 260 #define RTSX_SD_DAT0_STATUS 0x02 261 #define RTSX_SD_CMD_STATUS 0x01 262 263 #define RTSX_SD_PAD_CTL 0xFDA6 264 #define RTSX_SD_IO_USING_1V8 0x80 265 266 /* Sample point control register. */ 267 #define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7 268 #define RTSX_DDR_FIX_RX_DAT 0x00 269 #define RTSX_DDR_VAR_RX_DAT 0x80 270 #define RTSX_DDR_FIX_RX_DAT_EDGE 0x00 271 #define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40 272 #define RTSX_DDR_FIX_RX_CMD 0x00 273 #define RTSX_DDR_VAR_RX_CMD 0x20 274 #define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00 275 #define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10 276 #define RTSX_SD20_RX_POS_EDGE 0x00 277 #define RTSX_SD20_RX_14_DELAY 0x08 278 #define RTSX_SD20_RX_SEL_MASK 0x08 279 280 #define RTSX_SD_PUSH_POINT_CTL 0xFDA8 281 #define RTSX_SD20_TX_NEG_EDGE 0x00 282 283 #define RTSX_SD_CMD0 0xFDA9 284 #define RTSX_SD_CMD1 0xFDAA 285 #define RTSX_SD_CMD2 0xFDAB 286 #define RTSX_SD_CMD3 0xFDAC 287 #define RTSX_SD_CMD4 0xFDAD 288 #define RTSX_SD_CMD5 0xFDAE 289 #define RTSX_SD_BYTE_CNT_L 0xFDAF 290 #define RTSX_SD_BYTE_CNT_H 0xFDB0 291 #define RTSX_SD_BLOCK_CNT_L 0xFDB1 292 #define RTSX_SD_BLOCK_CNT_H 0xFDB2 293 294 /* 295 * Transfer modes. 296 */ 297 #define RTSX_SD_TRANSFER 0xFDB3 298 299 /* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */ 300 #define RTSX_TM_NORMAL_WRITE 0x00 301 302 /* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */ 303 #define RTSX_TM_AUTO_WRITE3 0x01 304 305 /* Like AUTO_WRITE3, plus automatically send CMD 12 when done. 306 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 307 #define RTSX_TM_AUTO_WRITE4 0x02 308 309 /* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */ 310 #define RTSX_TM_AUTO_READ3 0x05 311 312 /* Like AUTO_READ3, plus automatically send CMD 12 when done. 313 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 314 #define RTSX_TM_AUTO_READ4 0x06 315 316 /* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put 317 * the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put 318 * into ping-pong buffer 2 instead. */ 319 #define RTSX_TM_CMD_RSP 0x08 320 321 /* Send write command, get response from the card, write data from ring 322 * buffer to card, and send CMD 12 when done. 323 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 324 #define RTSX_TM_AUTO_WRITE1 0x09 325 326 /* Like AUTO_WRITE1 except no CMD 12 is sent. */ 327 #define RTSX_TM_AUTO_WRITE2 0x0A 328 329 /* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT) 330 * from the card into the ring buffer or ping-pong buffer 2. */ 331 #define RTSX_TM_NORMAL_READ 0x0C 332 333 /* Same as WRITE1, except data is read from the card to the ring buffer. */ 334 #define RTSX_TM_AUTO_READ1 0x0D 335 336 /* Same as WRITE2, except data is read from the card to the ring buffer. */ 337 #define RTSX_TM_AUTO_READ2 0x0E 338 339 /* Send CMD 19 and receive response and tuning pattern from card and 340 * report the result. */ 341 #define RTSX_TM_AUTO_TUNING 0x0F 342 343 /* transfer control */ 344 #define RTSX_SD_TRANSFER_START 0x80 345 #define RTSX_SD_TRANSFER_END 0x40 346 #define RTSX_SD_STAT_IDLE 0x20 347 #define RTSX_SD_TRANSFER_ERR 0x10 348 349 #define RTSX_SD_CMD_STATE 0xFDB5 350 #define RTSX_SD_DATA_STATE 0xFDB6 351 352 #define RTSX_CARD_STOP 0xFD54 353 #define RTSX_SPI_STOP 0x01 354 #define RTSX_XD_STOP 0x02 355 #define RTSX_SD_STOP 0x04 356 #define RTSX_MS_STOP 0x08 357 #define RTSX_SPI_CLR_ERR 0x10 358 #define RTSX_XD_CLR_ERR 0x20 359 #define RTSX_SD_CLR_ERR 0x40 360 #define RTSX_MS_CLR_ERR 0x80 361 #define RTSX_ALL_STOP 0x0F 362 #define RTSX_ALL_CLR_ERR 0xF0 363 364 #define RTSX_CARD_OE 0xFD55 365 #define RTSX_XD_OUTPUT_EN 0x02 366 #define RTSX_SD_OUTPUT_EN 0x04 367 #define RTSX_MS_OUTPUT_EN 0x08 368 #define RTSX_SPI_OUTPUT_EN 0x10 369 #define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\ 370 RTSX_MS_OUTPUT_EN) 371 372 #define RTSX_CARD_DATA_SOURCE 0xFD5B 373 #define RTSX_RING_BUFFER 0x00 374 #define RTSX_PINGPONG_BUFFER 0x01 375 #define RTSX_CARD_SELECT 0xFD5C 376 #define RTSX_XD_MOD_SEL 0x01 377 #define RTSX_SD_MOD_SEL 0x02 378 #define RTSX_MS_MOD_SEL 0x03 379 #define RTSX_SPI_MOD_SEL 0x04 380 381 #define RTSX_CARD_GPIO_DIR 0xFD57 382 #define RTSX_CARD_GPIO 0xFD58 383 #define RTSX_CARD_GPIO_LED_OFF 0x01 384 385 /* ping-pong buffer 2 */ 386 #define RTSX_PPBUF_BASE2 0xFA00 387 #define RTSX_PPBUF_SIZE 256 388 389 #define RTSX_SUPPORT_VOLTAGE (MMC_OCR_3_3V_3_4V|MMC_OCR_3_2V_3_3V|\ 390 MMC_OCR_3_1V_3_2V|MMC_OCR_3_0V_3_1V) 391 392 #define RTSX_CFG_PCI 0x1C 393 #define RTSX_CFG_ASIC 0x10 394 395 #define RTSX_IRQEN0 0xFE20 396 #define RTSX_LINK_DOWN_INT_EN 0x10 397 #define RTSX_LINK_READY_INT_EN 0x20 398 #define RTSX_SUSPEND_INT_EN 0x40 399 #define RTSX_DMA_DONE_INT_EN 0x80 400 #define RTSX_IRQSTAT0 0xFE21 401 #define RTSX_LINK_DOWN_INT 0x10 402 #define RTSX_LINK_READY_INT 0x20 403 #define RTSX_SUSPEND_INT 0x40 404 #define RTSX_DMA_DONE_INT 0x80 405 406 #define RTSX_DMATC0 0xFE28 407 #define RTSX_DMATC1 0xFE29 408 #define RTSX_DMATC2 0xFE2A 409 #define RTSX_DMATC3 0xFE2B 410 411 #define RTSX_DMACTL 0xFE2C 412 #define RTSX_DMA_DIR_TO_CARD 0x00 413 #define RTSX_DMA_EN 0x01 414 #define RTSX_DMA_DIR_FROM_CARD 0x02 415 #define RTSX_DMA_BUSY 0x04 416 #define RTSX_DMA_RST 0x80 417 #define RTSX_DMA_128 (0 << 4) 418 #define RTSX_DMA_256 (1 << 4) 419 #define RTSX_DMA_512 (2 << 4) 420 #define RTSX_DMA_1024 (3 << 4) 421 #define RTSX_DMA_PACK_SIZE_MASK 0x30 422 423 #define RTSX_RBCTL 0xFE34 424 #define RTSX_RB_FLUSH 0x80 425 426 #define RTSX_CFGADDR0 0xFE35 427 #define RTSX_CFGADDR1 0xFE36 428 #define RTSX_CFGDATA0 0xFE37 429 #define RTSX_CFGDATA1 0xFE38 430 #define RTSX_CFGDATA2 0xFE39 431 #define RTSX_CFGDATA3 0xFE3A 432 #define RTSX_CFGRWCTL 0xFE3B 433 #define RTSX_CFG_WRITE_DATA0 0x01 434 #define RTSX_CFG_WRITE_DATA1 0x02 435 #define RTSX_CFG_WRITE_DATA2 0x04 436 #define RTSX_CFG_WRITE_DATA3 0x08 437 #define RTSX_CFG_BUSY 0x80 438 439 #define RTSX_SDIOCFG_REG 0x724 440 #define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02 441 #define RTSX_SDIOCFG_HAVE_SDIO 0x04 442 #define RTSX_SDIOCFG_SINGLE_LUN 0x08 443 #define RTSX_SDIOCFG_SDIO_ONLY 0x80 444 445 #define RTSX_HOST_SLEEP_STATE 0xFE60 446 #define RTSX_HOST_ENTER_S1 0x01 447 #define RTSX_HOST_ENTER_S3 0x02 448 449 #define RTSX_SDIO_CFG 0xFE70 450 #define RTSX_SDIO_BUS_AUTO_SWITCH 0x10 451 452 #define RTSX_NFTS_TX_CTRL 0xFE72 453 #define RTSX_INT_READ_CLR 0x02 454 455 #define RTSX_PWR_GATE_CTRL 0xFE75 456 #define RTSX_PWR_GATE_EN 0x01 457 #define RTSX_LDO3318_ON 0x00 458 #define RTSX_LDO3318_SUSPEND 0x04 459 #define RTSX_LDO3318_OFF 0x06 460 #define RTSX_LDO3318_VCC1 0x02 461 #define RTSX_LDO3318_VCC2 0x04 462 #define RTSX_PWD_SUSPEND_EN 0xFE76 463 #define RTSX_LDO_PWR_SEL 0xFE78 464 #define RTSX_LDO_PWR_SEL_3V3 0x01 465 #define RTSX_LDO_PWR_SEL_DV33 0x03 466 467 #define RTSX_PHY_RWCTL 0xFE3C 468 #define RTSX_PHY_READ 0x00 469 #define RTSX_PHY_WRITE 0x01 470 #define RTSX_PHY_BUSY 0x80 471 #define RTSX_PHY_DATA0 0xFE3D 472 #define RTSX_PHY_DATA1 0xFE3E 473 #define RTSX_PHY_ADDR 0xFE3F 474 475 #define RTSX_PHY_VOLTAGE 0x08 476 #define RTSX_PHY_VOLTAGE_MASK 0x3F 477 478 #define RTSX_PETXCFG 0xFE49 479 #define RTSX_PETXCFG_CLKREQ_PIN 0x08 480 481 #define RTSX_CARD_AUTO_BLINK 0xFD56 482 #define RTSX_LED_BLINK_EN 0x08 483 #define RTSX_LED_BLINK_SPEED 0x05 484 485 #define RTSX_WAKE_SEL_CTL 0xFE54 486 #define RTSX_PME_FORCE_CTL 0xFE56 487 488 #define RTSX_CHANGE_LINK_STATE 0xFE5B 489 #define RTSX_CD_RST_CORE_EN 0x01 490 #define RTSX_FORCE_RST_CORE_EN 0x02 491 #define RTSX_NON_STICKY_RST_N_DBG 0x08 492 #define RTSX_MAC_PHY_RST_N_DBG 0x10 493 494 #define RTSX_PERST_GLITCH_WIDTH 0xFE5C 495 496 #define RTSX_SD30_DRIVE_SEL 0xFE5E 497 #define RTSX_SD30_DRIVE_SEL_3V3 0x01 498 #define RTSX_SD30_DRIVE_SEL_1V8 0x03 499 #define RTSX_SD30_DRIVE_SEL_MASK 0x07 500 501 #define RTSX_DUMMY_REG 0xFE90 502 503 #define RTSX_LDO_VCC_CFG1 0xFF73 504 #define RTSX_LDO_VCC_REF_TUNE_MASK 0x30 505 #define RTSX_LDO_VCC_REF_1V2 0x20 506 #define RTSX_LDO_VCC_TUNE_MASK 0x07 507 #define RTSX_LDO_VCC_1V8 0x04 508 #define RTSX_LDO_VCC_3V3 0x07 509 #define RTSX_LDO_VCC_LMT_EN 0x08 510 511 #define RTSX_SG_INT 0x04 512 #define RTSX_SG_END 0x02 513 #define RTSX_SG_VALID 0x01 514 515 #define RTSX_SG_NO_OP 0x00 516 #define RTSX_SG_TRANS_DATA (0x02 << 4) 517 #define RTSX_SG_LINK_DESC (0x03 << 4) 518 519 #define RTSX_IC_VERSION_A 0x00 520 #define RTSX_IC_VERSION_B 0x01 521 #define RTSX_IC_VERSION_C 0x02 522 #define RTSX_IC_VERSION_D 0x03 523 524 #endif 525