1 /* $OpenBSD: rtwn.c,v 1.51 2020/07/10 13:22:20 patrick Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek 802.11b/g/n chipsets. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/task.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_radiotap.h> 54 55 #include <dev/ic/r92creg.h> 56 #include <dev/ic/rtwnvar.h> 57 58 #define RTWN_RIDX_CCK1 0 59 #define RTWN_RIDX_CCK2 1 60 #define RTWN_RIDX_CCK11 3 61 #define RTWN_RIDX_OFDM6 4 62 #define RTWN_RIDX_OFDM54 11 63 #define RTWN_RIDX_MCS0 12 64 #define RTWN_RIDX_MCS8 (RTWN_RIDX_MCS0 + 8) 65 #define RTWN_RIDX_MCS15 27 66 #define RTWN_RIDX_MAX 27 67 68 #define RTWN_POWER_CCK1 0 69 #define RTWN_POWER_CCK2 1 70 #define RTWN_POWER_CCK55 2 71 #define RTWN_POWER_CCK11 3 72 #define RTWN_POWER_OFDM6 4 73 #define RTWN_POWER_OFDM9 5 74 #define RTWN_POWER_OFDM12 6 75 #define RTWN_POWER_OFDM18 7 76 #define RTWN_POWER_OFDM24 8 77 #define RTWN_POWER_OFDM36 9 78 #define RTWN_POWER_OFDM48 10 79 #define RTWN_POWER_OFDM54 11 80 #define RTWN_POWER_MCS(mcs) (12 + (mcs)) 81 #define RTWN_POWER_COUNT 28 82 83 84 #ifdef RTWN_DEBUG 85 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 86 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 87 int rtwn_debug = 0; 88 #else 89 #define DPRINTF(x) 90 #define DPRINTFN(n, x) 91 #endif 92 93 /* Registers to save and restore during IQ calibration. */ 94 struct rtwn_iq_cal_regs { 95 uint32_t adda[16]; 96 uint8_t txpause; 97 uint8_t bcn_ctrl; 98 uint8_t bcn_ctrl1; 99 uint32_t gpio_muxcfg; 100 uint32_t ofdm0_trxpathena; 101 uint32_t ofdm0_trmuxpar; 102 uint32_t fpga0_rfifacesw0; 103 uint32_t fpga0_rfifacesw1; 104 uint32_t fpga0_rfifaceoe0; 105 uint32_t fpga0_rfifaceoe1; 106 uint32_t config_ant_a; 107 uint32_t config_ant_b; 108 uint32_t cck0_afesetting; 109 }; 110 111 void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 void rtwn_cam_write(struct rtwn_softc *, uint32_t, uint32_t); 121 uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 void rtwn_efuse_read(struct rtwn_softc *, uint8_t *, size_t); 123 void rtwn_efuse_switch_power(struct rtwn_softc *); 124 int rtwn_read_chipid(struct rtwn_softc *); 125 void rtwn_read_rom(struct rtwn_softc *); 126 void rtwn_r92c_read_rom(struct rtwn_softc *); 127 void rtwn_r92e_read_rom(struct rtwn_softc *); 128 void rtwn_r88e_read_rom(struct rtwn_softc *); 129 void rtwn_r23a_read_rom(struct rtwn_softc *); 130 int rtwn_media_change(struct ifnet *); 131 int rtwn_ra_init(struct rtwn_softc *); 132 int rtwn_r92c_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 133 int, uint32_t, int); 134 int rtwn_r88e_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 135 int, uint32_t, int); 136 void rtwn_tsf_sync_enable(struct rtwn_softc *); 137 void rtwn_set_led(struct rtwn_softc *, int, int); 138 void rtwn_set_nettype(struct rtwn_softc *, enum ieee80211_opmode); 139 void rtwn_update_short_preamble(struct ieee80211com *); 140 void rtwn_r92c_update_short_preamble(struct rtwn_softc *); 141 void rtwn_r88e_update_short_preamble(struct rtwn_softc *); 142 int8_t rtwn_r88e_get_rssi(struct rtwn_softc *, int, void *); 143 void rtwn_watchdog(struct ifnet *); 144 void rtwn_fw_reset(struct rtwn_softc *); 145 void rtwn_r92c_fw_reset(struct rtwn_softc *); 146 void rtwn_r88e_fw_reset(struct rtwn_softc *); 147 int rtwn_load_firmware(struct rtwn_softc *); 148 void rtwn_rf_init(struct rtwn_softc *); 149 void rtwn_cam_init(struct rtwn_softc *); 150 void rtwn_pa_bias_init(struct rtwn_softc *); 151 void rtwn_rxfilter_init(struct rtwn_softc *); 152 void rtwn_edca_init(struct rtwn_softc *); 153 void rtwn_rate_fallback_init(struct rtwn_softc *); 154 void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 155 void rtwn_get_txpower(struct rtwn_softc *sc, int, 156 struct ieee80211_channel *, struct ieee80211_channel *, 157 uint16_t[]); 158 void rtwn_r92c_get_txpower(struct rtwn_softc *, int, 159 struct ieee80211_channel *, struct ieee80211_channel *, 160 uint16_t[]); 161 void rtwn_r92e_get_txpower(struct rtwn_softc *, int, 162 struct ieee80211_channel *, 163 struct ieee80211_channel *, uint16_t[]); 164 void rtwn_r88e_get_txpower(struct rtwn_softc *, int, 165 struct ieee80211_channel *, 166 struct ieee80211_channel *, uint16_t[]); 167 void rtwn_set_txpower(struct rtwn_softc *, 168 struct ieee80211_channel *, struct ieee80211_channel *); 169 void rtwn_set_chan(struct rtwn_softc *, 170 struct ieee80211_channel *, struct ieee80211_channel *); 171 int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 172 uint16_t[2]); 173 void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 174 uint16_t rx[2][2], struct rtwn_iq_cal_regs *); 175 int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 176 uint16_t[2][2], uint16_t[2][2], int); 177 void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 178 uint16_t[2], int); 179 void rtwn_iq_calib(struct rtwn_softc *); 180 void rtwn_lc_calib(struct rtwn_softc *); 181 void rtwn_temp_calib(struct rtwn_softc *); 182 void rtwn_enable_intr(struct rtwn_softc *); 183 void rtwn_disable_intr(struct rtwn_softc *); 184 int rtwn_init(struct ifnet *); 185 void rtwn_init_task(void *); 186 void rtwn_stop(struct ifnet *); 187 188 /* Aliases. */ 189 #define rtwn_bb_write rtwn_write_4 190 #define rtwn_bb_read rtwn_read_4 191 192 /* 193 * Macro to convert 4-bit signed integer to 8-bit signed integer. 194 */ 195 #define RTWN_SIGN4TO8(val) (((val) & 0x08) ? (val) | 0xf0 : (val)) 196 197 int 198 rtwn_attach(struct device *pdev, struct rtwn_softc *sc) 199 { 200 struct ieee80211com *ic = &sc->sc_ic; 201 struct ifnet *ifp = &ic->ic_if; 202 int i, error; 203 204 sc->sc_pdev = pdev; 205 206 task_set(&sc->init_task, rtwn_init_task, sc); 207 208 error = rtwn_read_chipid(sc); 209 if (error != 0) { 210 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 211 return (ENXIO); 212 } 213 214 /* Determine number of Tx/Rx chains. */ 215 if (sc->chip & RTWN_CHIP_92C) { 216 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 217 sc->nrxchains = 2; 218 } else if (sc->chip & RTWN_CHIP_92E) { 219 sc->ntxchains = 2; 220 sc->nrxchains = 2; 221 } else { 222 sc->ntxchains = 1; 223 sc->nrxchains = 1; 224 } 225 226 rtwn_read_rom(sc); 227 228 if (sc->chip & RTWN_CHIP_PCI) { 229 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 230 sc->sc_pdev->dv_xname, 231 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : 232 (sc->chip & RTWN_CHIP_88E) ? "8188EE" : 233 (sc->chip & RTWN_CHIP_92E) ? "8192EE" : 234 (sc->chip & RTWN_CHIP_23A) ? "8723AE" : 235 (sc->chip & RTWN_CHIP_23B) ? "8723BE" : "8188CE", 236 sc->ntxchains, sc->nrxchains, 237 ether_sprintf(ic->ic_myaddr)); 238 } else if (sc->chip & RTWN_CHIP_USB) { 239 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 240 sc->sc_pdev->dv_xname, 241 (sc->chip & RTWN_CHIP_92C) ? "8192CU" : 242 (sc->chip & RTWN_CHIP_92E) ? "8192EU" : 243 (sc->chip & RTWN_CHIP_88E) ? "8188EU" : 244 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 245 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? 246 "8188CE-VAU" : "8188CUS", 247 sc->ntxchains, sc->nrxchains, 248 ether_sprintf(ic->ic_myaddr)); 249 } else { 250 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 251 return (ENXIO); 252 } 253 254 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 255 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 256 ic->ic_state = IEEE80211_S_INIT; 257 258 /* Set device capabilities. */ 259 ic->ic_caps = 260 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 261 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 262 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 263 IEEE80211_C_WEP | /* WEP. */ 264 IEEE80211_C_RSN; /* WPA/RSN. */ 265 266 /* Set HT capabilities. */ 267 ic->ic_htcaps = 268 IEEE80211_HTCAP_CBW20_40 | 269 IEEE80211_HTCAP_DSSSCCK40; 270 /* Set supported HT rates. */ 271 for (i = 0; i < sc->nrxchains; i++) 272 ic->ic_sup_mcs[i] = 0xff; 273 274 /* Set supported .11b and .11g rates. */ 275 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 276 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 277 278 /* Set supported .11b and .11g channels (1 through 14). */ 279 for (i = 1; i <= 14; i++) { 280 ic->ic_channels[i].ic_freq = 281 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 282 ic->ic_channels[i].ic_flags = 283 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 284 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 285 } 286 287 #ifdef notyet 288 /* 289 * The number of STAs that we can support is limited by the number 290 * of CAM entries used for hardware crypto. 291 */ 292 ic->ic_max_nnodes = R92C_CAM_ENTRY_COUNT - 4; 293 if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE) 294 ic->ic_max_nnodes = IEEE80211_CACHE_SIZE; 295 #endif 296 297 ifp->if_softc = sc; 298 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 299 ifp->if_ioctl = rtwn_ioctl; 300 ifp->if_start = rtwn_start; 301 ifp->if_watchdog = rtwn_watchdog; 302 memcpy(ifp->if_xname, sc->sc_pdev->dv_xname, IFNAMSIZ); 303 304 if_attach(ifp); 305 ieee80211_ifattach(ifp); 306 ic->ic_updateslot = rtwn_updateslot; 307 ic->ic_updateedca = rtwn_updateedca; 308 #ifdef notyet 309 ic->ic_set_key = rtwn_set_key; 310 ic->ic_delete_key = rtwn_delete_key; 311 #endif 312 /* Override state transition machine. */ 313 sc->sc_newstate = ic->ic_newstate; 314 ic->ic_newstate = rtwn_newstate; 315 ieee80211_media_init(ifp, rtwn_media_change, ieee80211_media_status); 316 317 return (0); 318 } 319 320 int 321 rtwn_detach(struct rtwn_softc *sc, int flags) 322 { 323 struct ifnet *ifp = &sc->sc_ic.ic_if; 324 int s; 325 326 s = splnet(); 327 328 task_del(systq, &sc->init_task); 329 330 if (ifp->if_softc != NULL) { 331 ieee80211_ifdetach(ifp); 332 if_detach(ifp); 333 } 334 335 splx(s); 336 337 return (0); 338 } 339 340 int 341 rtwn_activate(struct rtwn_softc *sc, int act) 342 { 343 struct ifnet *ifp = &sc->sc_ic.ic_if; 344 345 switch (act) { 346 case DVACT_QUIESCE: /* rtwn_stop() may sleep */ 347 if (ifp->if_flags & IFF_RUNNING) 348 rtwn_stop(ifp); 349 break; 350 case DVACT_WAKEUP: 351 rtwn_init_task(sc); 352 break; 353 } 354 return (0); 355 } 356 357 void 358 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 359 { 360 sc->sc_ops.write_1(sc->sc_ops.cookie, addr, val); 361 } 362 363 void 364 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 365 { 366 sc->sc_ops.write_2(sc->sc_ops.cookie, addr, val); 367 } 368 369 void 370 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 371 { 372 sc->sc_ops.write_4(sc->sc_ops.cookie, addr, val); 373 } 374 375 uint8_t 376 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 377 { 378 return sc->sc_ops.read_1(sc->sc_ops.cookie, addr); 379 } 380 381 uint16_t 382 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 383 { 384 return sc->sc_ops.read_2(sc->sc_ops.cookie, addr); 385 } 386 387 uint32_t 388 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 389 { 390 return sc->sc_ops.read_4(sc->sc_ops.cookie, addr); 391 } 392 393 int 394 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 395 { 396 struct r92c_fw_cmd cmd; 397 int ntries; 398 399 /* Wait for current FW box to be empty. */ 400 for (ntries = 0; ntries < 100; ntries++) { 401 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 402 break; 403 DELAY(10); 404 } 405 if (ntries == 100) { 406 printf("%s: could not send firmware command %d\n", 407 sc->sc_pdev->dv_xname, id); 408 return (ETIMEDOUT); 409 } 410 memset(&cmd, 0, sizeof(cmd)); 411 cmd.id = id; 412 if (len > 3) 413 cmd.id |= R92C_CMD_FLAG_EXT; 414 KASSERT(len <= sizeof(cmd.msg)); 415 memcpy(cmd.msg, buf, len); 416 417 /* Write the first word last since that will trigger the FW. */ 418 if (sc->chip & RTWN_CHIP_92E) 419 rtwn_write_2(sc, R88E_HMEBOX_EXT(sc->fwcur), 420 *((uint8_t *)&cmd + 4)); 421 else 422 rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), 423 *((uint8_t *)&cmd + 4)); 424 rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 425 426 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 427 428 if (sc->chip & RTWN_CHIP_PCI) { 429 /* Give firmware some time for processing. */ 430 DELAY(2000); 431 } 432 433 return (0); 434 } 435 436 void 437 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 438 { 439 uint32_t param_addr; 440 441 if (sc->chip & RTWN_CHIP_92E) { 442 rtwn_write_4(sc, R92C_FPGA0_POWER_SAVE, 443 rtwn_read_4(sc, R92C_FPGA0_POWER_SAVE) & ~0x20000); 444 } 445 446 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 447 param_addr = SM(R88E_LSSI_PARAM_ADDR, addr); 448 else 449 param_addr = SM(R92C_LSSI_PARAM_ADDR, addr); 450 451 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 452 param_addr | SM(R92C_LSSI_PARAM_DATA, val)); 453 454 DELAY(1); 455 456 if (sc->chip & RTWN_CHIP_92E) { 457 rtwn_write_4(sc, R92C_FPGA0_POWER_SAVE, 458 rtwn_read_4(sc, R92C_FPGA0_POWER_SAVE) | 0x20000); 459 } 460 } 461 462 uint32_t 463 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 464 { 465 uint32_t reg[R92C_MAX_CHAINS], val; 466 467 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 468 if (chain != 0) 469 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 470 471 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 472 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 473 DELAY(1000); 474 475 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 476 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 477 R92C_HSSI_PARAM2_READ_EDGE); 478 DELAY(1000); 479 480 if (!(sc->chip & RTWN_CHIP_88E)) { 481 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 482 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 483 DELAY(1000); 484 } 485 486 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 487 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 488 else 489 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 490 return (MS(val, R92C_LSSI_READBACK_DATA)); 491 } 492 493 void 494 rtwn_cam_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 495 { 496 rtwn_write_4(sc, R92C_CAMWRITE, data); 497 rtwn_write_4(sc, R92C_CAMCMD, 498 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 499 SM(R92C_CAMCMD_ADDR, addr)); 500 } 501 502 uint8_t 503 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 504 { 505 uint32_t reg; 506 int ntries; 507 508 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 509 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 510 reg &= ~R92C_EFUSE_CTRL_VALID; 511 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 512 /* Wait for read operation to complete. */ 513 for (ntries = 0; ntries < 100; ntries++) { 514 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 515 if (reg & R92C_EFUSE_CTRL_VALID) 516 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 517 DELAY(5); 518 } 519 printf("%s: could not read efuse byte at address 0x%x\n", 520 sc->sc_pdev->dv_xname, addr); 521 return (0xff); 522 } 523 524 void 525 rtwn_efuse_read(struct rtwn_softc *sc, uint8_t *rom, size_t size) 526 { 527 uint8_t off, msk, tmp; 528 uint16_t addr = 0; 529 uint32_t reg; 530 int i, len; 531 532 if (!(sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C))) 533 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 534 535 rtwn_efuse_switch_power(sc); 536 537 memset(rom, 0xff, size); 538 len = (sc->chip & RTWN_CHIP_88E) ? 256 : 512; 539 while (addr < len) { 540 reg = rtwn_efuse_read_1(sc, addr); 541 if (reg == 0xff) 542 break; 543 addr++; 544 545 /* Check for extended header. */ 546 if ((sc->sc_flags & RTWN_FLAG_EXT_HDR) && 547 (reg & 0x1f) == 0x0f) { 548 tmp = (reg & 0xe0) >> 5; 549 reg = rtwn_efuse_read_1(sc, addr); 550 addr++; 551 if ((reg & 0x0f) != 0x0f) 552 off = ((reg & 0xf0) >> 1) | tmp; 553 else 554 continue; 555 } else 556 off = reg >> 4; 557 msk = reg & 0xf; 558 for (i = 0; i < 4; i++) { 559 if (msk & (1 << i)) 560 continue; 561 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 562 addr++; 563 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 564 addr++; 565 } 566 } 567 #ifdef RTWN_DEBUG 568 if (rtwn_debug >= 2) { 569 /* Dump ROM content. */ 570 printf("\n"); 571 for (i = 0; i < size; i++) 572 printf("%02x:", rom[i]); 573 printf("\n"); 574 } 575 #endif 576 if (!(sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C))) 577 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 578 } 579 580 void 581 rtwn_efuse_switch_power(struct rtwn_softc *sc) 582 { 583 uint16_t reg; 584 585 if (!(sc->chip & RTWN_CHIP_92E)) { 586 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 587 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 588 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 589 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 590 } 591 } 592 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 593 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 594 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 595 reg | R92C_SYS_FUNC_EN_ELDR); 596 } 597 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 598 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 599 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 600 rtwn_write_2(sc, R92C_SYS_CLKR, 601 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 602 } 603 } 604 605 int 606 rtwn_read_chipid(struct rtwn_softc *sc) 607 { 608 uint32_t reg; 609 610 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) { 611 sc->sc_flags |= RTWN_FLAG_EXT_HDR; 612 return (0); 613 } 614 615 reg = rtwn_read_4(sc, R92C_SYS_CFG); 616 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 617 /* Unsupported test chip. */ 618 return (EIO); 619 620 if ((sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) != 0) { 621 if (reg & R92C_SYS_CFG_TYPE_92C) { 622 sc->chip &= ~RTWN_CHIP_88C; 623 /* Check if it is a castrated 8192C. */ 624 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 625 R92C_HPON_FSM_CHIP_BONDING_ID) == 626 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 627 sc->chip |= RTWN_CHIP_92C_1T2R; 628 } else 629 sc->chip &= ~RTWN_CHIP_92C; 630 631 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 632 sc->chip |= RTWN_CHIP_UMC; 633 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 634 sc->chip |= RTWN_CHIP_UMC_A_CUT; 635 } 636 637 return (0); 638 } else if (sc->chip & RTWN_CHIP_23A) { 639 sc->sc_flags |= RTWN_FLAG_EXT_HDR; 640 641 if ((reg & 0xf000) == 0) 642 sc->chip |= RTWN_CHIP_UMC_A_CUT; 643 return (0); 644 } 645 646 return (ENXIO); /* unsupported chip */ 647 } 648 649 void 650 rtwn_read_rom(struct rtwn_softc *sc) 651 { 652 if (sc->chip & RTWN_CHIP_88E) 653 rtwn_r88e_read_rom(sc); 654 else if (sc->chip & RTWN_CHIP_92E) 655 rtwn_r92e_read_rom(sc); 656 else if (sc->chip & RTWN_CHIP_23A) 657 rtwn_r23a_read_rom(sc); 658 else 659 rtwn_r92c_read_rom(sc); 660 } 661 662 void 663 rtwn_r92c_read_rom(struct rtwn_softc *sc) 664 { 665 struct ieee80211com *ic = &sc->sc_ic; 666 struct r92c_rom *rom = &sc->sc_r92c_rom; 667 668 /* Read full ROM image. */ 669 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r92c_rom, 670 sizeof(sc->sc_r92c_rom)); 671 672 /* XXX Weird but this is what the vendor driver does. */ 673 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 674 DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 675 676 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 677 DPRINTF(("board type=%d\n", sc->board_type)); 678 679 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 680 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 681 682 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 683 } 684 685 void 686 rtwn_r92e_read_rom(struct rtwn_softc *sc) 687 { 688 struct ieee80211com *ic = &sc->sc_ic; 689 struct r92e_rom *rom = &sc->sc_r92e_rom; 690 691 /* Read full ROM image. */ 692 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r92e_rom, 693 sizeof(sc->sc_r92e_rom)); 694 695 sc->crystal_cap = rom->xtal_k; 696 DPRINTF(("crystal cap=0x%x\n", sc->crystal_cap)); 697 698 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 699 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 700 701 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 702 } 703 704 void 705 rtwn_r88e_read_rom(struct rtwn_softc *sc) 706 { 707 struct ieee80211com *ic = &sc->sc_ic; 708 struct r88e_rom *rom = &sc->sc_r88e_rom; 709 710 /* Read full ROM image. */ 711 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r88e_rom, 712 sizeof(sc->sc_r88e_rom)); 713 714 sc->crystal_cap = (sc->chip & RTWN_CHIP_PCI) ? 0x20 : rom->xtal; 715 DPRINTF(("Crystal cap=0x%x\n", sc->crystal_cap)); 716 717 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 718 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 719 720 if (sc->chip & RTWN_CHIP_PCI) 721 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->r88ee_rom.macaddr); 722 else 723 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->r88eu_rom.macaddr); 724 } 725 726 void 727 rtwn_r23a_read_rom(struct rtwn_softc *sc) 728 { 729 struct ieee80211com *ic = &sc->sc_ic; 730 struct r23a_rom *rom = &sc->sc_r23a_rom; 731 732 /* Read full ROM image. */ 733 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r23a_rom, 734 sizeof(sc->sc_r23a_rom)); 735 736 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 737 } 738 739 int 740 rtwn_media_change(struct ifnet *ifp) 741 { 742 int error; 743 744 error = ieee80211_media_change(ifp); 745 if (error != ENETRESET) 746 return (error); 747 748 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 749 (IFF_UP | IFF_RUNNING)) { 750 rtwn_stop(ifp); 751 error = rtwn_init(ifp); 752 } 753 return (error); 754 } 755 756 /* 757 * Initialize rate adaptation. 758 */ 759 int 760 rtwn_ra_init(struct rtwn_softc *sc) 761 { 762 static const uint8_t map[] = 763 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 764 struct ieee80211com *ic = &sc->sc_ic; 765 struct ieee80211_node *ni = ic->ic_bss; 766 struct ieee80211_rateset *rs = &ni->ni_rates; 767 uint32_t rates, basicrates; 768 uint8_t mode; 769 int maxrate, maxbasicrate, i, j; 770 int error = 0; 771 772 /* Get normal and basic rates mask. */ 773 rates = basicrates = 0; 774 maxrate = maxbasicrate = 0; 775 for (i = 0; i < rs->rs_nrates; i++) { 776 /* Convert 802.11 rate to HW rate index. */ 777 for (j = 0; j < nitems(map); j++) 778 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 779 break; 780 if (j == nitems(map)) /* Unknown rate, skip. */ 781 continue; 782 rates |= 1 << j; 783 if (j > maxrate) 784 maxrate = j; 785 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 786 basicrates |= 1 << j; 787 if (j > maxbasicrate) 788 maxbasicrate = j; 789 } 790 } 791 if (ic->ic_curmode == IEEE80211_MODE_11B) 792 mode = R92C_RAID_11B; 793 else 794 mode = R92C_RAID_11BG; 795 DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 796 mode, rates, basicrates)); 797 798 if (sc->chip & RTWN_CHIP_PCI) { 799 /* Configure Automatic Rate Fallback Register. */ 800 if (ic->ic_curmode == IEEE80211_MODE_11B) { 801 if (rates & 0x0c) 802 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x05); 803 else 804 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x07); 805 } else 806 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x07f5); 807 } 808 809 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) { 810 error = rtwn_r88e_ra_init(sc, mode, rates, maxrate, 811 basicrates, maxbasicrate); 812 /* We use AMRR with this chip. Start with the lowest rate. */ 813 ni->ni_txrate = 0; 814 } else { 815 if (sc->chip & RTWN_CHIP_PCI) { 816 ni->ni_txrate = 0; /* AMRR will raise. */ 817 /* Set initial MRR rates. */ 818 rtwn_write_1(sc, 819 R92C_INIDATA_RATE_SEL(R92C_MACID_BC), maxbasicrate); 820 rtwn_write_1(sc, 821 R92C_INIDATA_RATE_SEL(R92C_MACID_BSS), 0); 822 } else { 823 error = rtwn_r92c_ra_init(sc, mode, rates, maxrate, 824 basicrates, maxbasicrate); 825 /* No AMRR support. Indicate highest supported rate. */ 826 ni->ni_txrate = rs->rs_nrates - 1; 827 } 828 } 829 return (error); 830 } 831 832 /* 833 * Initialize rate adaptation in firmware. 834 */ 835 int rtwn_r92c_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 836 int maxrate, uint32_t basicrates, int maxbasicrate) 837 { 838 struct r92c_fw_cmd_macid_cfg cmd; 839 int error; 840 841 /* Set rates mask for group addressed frames. */ 842 cmd.macid = R92C_MACID_BC | R92C_MACID_VALID; 843 cmd.mask = htole32(mode << 28 | basicrates); 844 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 845 if (error != 0) { 846 printf("%s: could not add broadcast station\n", 847 sc->sc_pdev->dv_xname); 848 return (error); 849 } 850 /* Set initial MRR rate. */ 851 DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 852 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BC), 853 maxbasicrate); 854 855 /* Set rates mask for unicast frames. */ 856 cmd.macid = R92C_MACID_BSS | R92C_MACID_VALID; 857 cmd.mask = htole32(mode << 28 | rates); 858 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 859 if (error != 0) { 860 printf("%s: could not add BSS station\n", 861 sc->sc_pdev->dv_xname); 862 return (error); 863 } 864 /* Set initial MRR rate. */ 865 DPRINTF(("maxrate=%d\n", maxrate)); 866 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BSS), 867 maxrate); 868 869 return (0); 870 } 871 872 int 873 rtwn_r88e_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 874 int maxrate, uint32_t basicrates, int maxbasicrate) 875 { 876 u_int32_t reg; 877 878 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, maxbasicrate); 879 880 reg = rtwn_read_4(sc, R92C_RRSR); 881 reg = RW(reg, R92C_RRSR_RATE_BITMAP, rates); 882 rtwn_write_4(sc, R92C_RRSR, reg); 883 884 /* 885 * Workaround for performance problems with firmware rate adaptation: 886 * If the AP only supports 11b rates, disable mixed B/G mode. 887 */ 888 if (mode != R92C_RAID_11B && maxrate <= 3 /* 11M */) 889 sc->sc_flags |= RTWN_FLAG_FORCE_RAID_11B; 890 891 return (0); 892 } 893 894 void 895 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 896 { 897 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 898 uint64_t tsf; 899 900 /* Enable TSF synchronization. */ 901 rtwn_write_1(sc, R92C_BCN_CTRL, 902 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 903 904 rtwn_write_1(sc, R92C_BCN_CTRL, 905 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 906 907 /* Set initial TSF. */ 908 memcpy(&tsf, ni->ni_tstamp, sizeof(tsf)); 909 tsf = letoh64(tsf); 910 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 911 tsf -= IEEE80211_DUR_TU; 912 rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 913 rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 914 915 rtwn_write_1(sc, R92C_BCN_CTRL, 916 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 917 } 918 919 void 920 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 921 { 922 uint8_t reg; 923 924 if (led != RTWN_LED_LINK) 925 return; /* not supported */ 926 927 if (sc->chip & RTWN_CHIP_PCI) { 928 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 929 if (!on) 930 reg |= R92C_LEDCFG2_DIS; 931 else 932 reg |= R92C_LEDCFG2_EN; 933 rtwn_write_1(sc, R92C_LEDCFG2, reg); 934 } else if (sc->chip & RTWN_CHIP_USB) { 935 if (sc->chip & RTWN_CHIP_92E) { 936 rtwn_write_1(sc, 0x64, rtwn_read_1(sc, 0x64) & 0xfe); 937 reg = rtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 938 rtwn_write_1(sc, R92C_LEDCFG1, reg | 939 (R92C_LEDCFG0_DIS << 1)); 940 if (on) { 941 reg = rtwn_read_1(sc, R92C_LEDCFG1) & 942 R92E_LEDSON; 943 rtwn_write_1(sc, R92C_LEDCFG1, reg); 944 } 945 } else if (sc->chip & RTWN_CHIP_88E) { 946 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 947 rtwn_write_1(sc, R92C_LEDCFG2, reg | R92C_LEDCFG2_EN); 948 if (!on) { 949 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 950 rtwn_write_1(sc, R92C_LEDCFG2, 951 reg | R92C_LEDCFG0_DIS); 952 rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 953 rtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 954 0xfe); 955 } 956 } else { 957 reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 958 if (!on) 959 reg |= R92C_LEDCFG0_DIS; 960 rtwn_write_1(sc, R92C_LEDCFG0, reg); 961 } 962 } 963 sc->ledlink = on; /* Save LED state. */ 964 } 965 966 void 967 rtwn_set_nettype(struct rtwn_softc *sc, enum ieee80211_opmode opmode) 968 { 969 uint8_t msr; 970 971 msr = rtwn_read_1(sc, R92C_MSR) & ~R92C_MSR_NETTYPE_MASK; 972 973 switch (opmode) { 974 case IEEE80211_M_MONITOR: 975 msr |= R92C_MSR_NETTYPE_NOLINK; 976 break; 977 case IEEE80211_M_STA: 978 msr |= R92C_MSR_NETTYPE_INFRA; 979 break; 980 default: 981 break; 982 } 983 984 rtwn_write_1(sc, R92C_MSR, msr); 985 } 986 987 void 988 rtwn_calib(struct rtwn_softc *sc) 989 { 990 991 if (sc->avg_pwdb != -1) { 992 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 993 994 /* Indicate Rx signal strength to FW for rate adaptation. */ 995 if (sc->chip & RTWN_CHIP_92E) { 996 struct r92e_fw_cmd_rssi cmd; 997 998 memset(&cmd, 0, sizeof(cmd)); 999 cmd.macid = 0; /* BSS. */ 1000 cmd.pwdb = sc->avg_pwdb; 1001 rtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmd, 1002 sizeof(cmd)); 1003 } else { 1004 struct r92c_fw_cmd_rssi cmd; 1005 1006 memset(&cmd, 0, sizeof(cmd)); 1007 cmd.macid = 0; /* BSS. */ 1008 cmd.pwdb = sc->avg_pwdb; 1009 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1010 sizeof(cmd)); 1011 } 1012 } 1013 1014 /* Do temperature compensation. */ 1015 rtwn_temp_calib(sc); 1016 1017 sc->sc_ops.next_calib(sc->sc_ops.cookie); 1018 } 1019 1020 void 1021 rtwn_next_scan(struct rtwn_softc *sc) 1022 { 1023 struct ieee80211com *ic = &sc->sc_ic; 1024 int s; 1025 1026 s = splnet(); 1027 if (ic->ic_state == IEEE80211_S_SCAN) 1028 ieee80211_next_scan(&ic->ic_if); 1029 splx(s); 1030 } 1031 1032 int 1033 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1034 { 1035 struct rtwn_softc *sc = ic->ic_softc; 1036 struct ieee80211_node *ni; 1037 enum ieee80211_state ostate; 1038 uint32_t reg; 1039 int s, error; 1040 1041 s = splnet(); 1042 ostate = ic->ic_state; 1043 1044 if (nstate != ostate) 1045 DPRINTF(("newstate %s -> %s\n", 1046 ieee80211_state_name[ostate], 1047 ieee80211_state_name[nstate])); 1048 1049 if (ostate == IEEE80211_S_RUN) { 1050 /* Stop calibration. */ 1051 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 1052 1053 /* Turn link LED off. */ 1054 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1055 1056 /* Set media status to 'No Link'. */ 1057 rtwn_set_nettype(sc, IEEE80211_M_MONITOR); 1058 1059 /* Stop Rx of data frames. */ 1060 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1061 1062 /* Rest TSF. */ 1063 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1064 1065 /* Disable TSF synchronization. */ 1066 rtwn_write_1(sc, R92C_BCN_CTRL, 1067 rtwn_read_1(sc, R92C_BCN_CTRL) | 1068 R92C_BCN_CTRL_DIS_TSF_UDT0); 1069 1070 /* Reset EDCA parameters. */ 1071 rtwn_edca_init(sc); 1072 1073 rtwn_updateslot(ic); 1074 rtwn_update_short_preamble(ic); 1075 1076 /* Disable 11b-only AP workaround (see rtwn_r88e_ra_init). */ 1077 sc->sc_flags &= ~RTWN_FLAG_FORCE_RAID_11B; 1078 } 1079 switch (nstate) { 1080 case IEEE80211_S_INIT: 1081 /* Turn link LED off. */ 1082 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1083 break; 1084 case IEEE80211_S_SCAN: 1085 if (ostate != IEEE80211_S_SCAN) { 1086 /* Allow Rx from any BSSID. */ 1087 rtwn_write_4(sc, R92C_RCR, 1088 rtwn_read_4(sc, R92C_RCR) & 1089 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1090 1091 /* Set gain for scanning. */ 1092 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1093 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1094 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1095 1096 if (!(sc->chip & RTWN_CHIP_88E)) { 1097 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1098 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1099 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1100 } 1101 } 1102 1103 /* Make link LED blink during scan. */ 1104 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1105 1106 /* Pause AC Tx queues. */ 1107 rtwn_write_1(sc, R92C_TXPAUSE, 1108 rtwn_read_1(sc, R92C_TXPAUSE) | R92C_TXPAUSE_AC_VO | 1109 R92C_TXPAUSE_AC_VI | R92C_TXPAUSE_AC_BE | 1110 R92C_TXPAUSE_AC_BK); 1111 1112 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 1113 sc->sc_ops.next_scan(sc->sc_ops.cookie); 1114 break; 1115 1116 case IEEE80211_S_AUTH: 1117 /* Set initial gain under link. */ 1118 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1119 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1120 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1121 1122 if (!(sc->chip & RTWN_CHIP_88E)) { 1123 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1124 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1125 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1126 } 1127 1128 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 1129 break; 1130 case IEEE80211_S_ASSOC: 1131 break; 1132 case IEEE80211_S_RUN: 1133 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1134 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 1135 1136 /* Enable Rx of data frames. */ 1137 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1138 1139 /* Enable Rx of control frames. */ 1140 rtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1141 1142 rtwn_write_4(sc, R92C_RCR, 1143 rtwn_read_4(sc, R92C_RCR) | 1144 R92C_RCR_AAP | R92C_RCR_ADF | R92C_RCR_ACF | 1145 R92C_RCR_AMF); 1146 1147 /* Turn link LED on. */ 1148 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1149 break; 1150 } 1151 ni = ic->ic_bss; 1152 1153 /* Set media status to 'Associated'. */ 1154 rtwn_set_nettype(sc, IEEE80211_M_STA); 1155 1156 /* Set BSSID. */ 1157 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1158 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1159 1160 if (ic->ic_curmode == IEEE80211_MODE_11B) 1161 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1162 else /* 802.11b/g */ 1163 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1164 1165 rtwn_updateslot(ic); 1166 rtwn_update_short_preamble(ic); 1167 1168 /* Enable Rx of data frames. */ 1169 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1170 1171 /* Flush all AC queues. */ 1172 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 1173 1174 /* Set beacon interval. */ 1175 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1176 1177 /* Allow Rx from our BSSID only. */ 1178 rtwn_write_4(sc, R92C_RCR, 1179 rtwn_read_4(sc, R92C_RCR) | 1180 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1181 1182 /* Enable TSF synchronization. */ 1183 rtwn_tsf_sync_enable(sc); 1184 1185 /* Intialize rate adaptation. */ 1186 rtwn_ra_init(sc); 1187 1188 /* Turn link LED on. */ 1189 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1190 1191 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1192 /* Reset temperature calibration state machine. */ 1193 sc->thcal_state = 0; 1194 sc->thcal_lctemp = 0; 1195 /* Start periodic calibration. */ 1196 sc->sc_ops.next_calib(sc->sc_ops.cookie); 1197 break; 1198 } 1199 1200 error = sc->sc_newstate(ic, nstate, arg); 1201 splx(s); 1202 1203 return (error); 1204 } 1205 1206 void 1207 rtwn_update_short_preamble(struct ieee80211com *ic) 1208 { 1209 struct rtwn_softc *sc = ic->ic_softc; 1210 1211 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 1212 rtwn_r88e_update_short_preamble(sc); 1213 else 1214 rtwn_r92c_update_short_preamble(sc); 1215 } 1216 1217 void 1218 rtwn_r92c_update_short_preamble(struct rtwn_softc *sc) 1219 { 1220 uint32_t reg; 1221 1222 reg = rtwn_read_4(sc, R92C_RRSR); 1223 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1224 reg |= R92C_RRSR_SHORT; 1225 else 1226 reg &= ~R92C_RRSR_SHORT; 1227 rtwn_write_4(sc, R92C_RRSR, reg); 1228 } 1229 1230 void 1231 rtwn_r88e_update_short_preamble(struct rtwn_softc *sc) 1232 { 1233 uint32_t reg; 1234 1235 reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL); 1236 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1237 reg |= R92C_WMAC_TRXPTCL_CTL_SHORT; 1238 else 1239 reg &= ~R92C_WMAC_TRXPTCL_CTL_SHORT; 1240 rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg); 1241 } 1242 1243 void 1244 rtwn_updateslot(struct ieee80211com *ic) 1245 { 1246 struct rtwn_softc *sc = ic->ic_softc; 1247 int s; 1248 1249 s = splnet(); 1250 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1251 rtwn_write_1(sc, R92C_SLOT, IEEE80211_DUR_DS_SHSLOT); 1252 else 1253 rtwn_write_1(sc, R92C_SLOT, IEEE80211_DUR_DS_SLOT); 1254 splx(s); 1255 } 1256 1257 void 1258 rtwn_updateedca(struct ieee80211com *ic) 1259 { 1260 struct rtwn_softc *sc = ic->ic_softc; 1261 const uint16_t aci2reg[EDCA_NUM_AC] = { 1262 R92C_EDCA_BE_PARAM, 1263 R92C_EDCA_BK_PARAM, 1264 R92C_EDCA_VI_PARAM, 1265 R92C_EDCA_VO_PARAM 1266 }; 1267 struct ieee80211_edca_ac_params *ac; 1268 int s, aci, aifs, slottime; 1269 uint8_t acm = 0; 1270 1271 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1272 slottime = IEEE80211_DUR_DS_SHSLOT; 1273 else 1274 slottime = IEEE80211_DUR_DS_SLOT; 1275 s = splnet(); 1276 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1277 ac = &ic->ic_edca_ac[aci]; 1278 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1279 aifs = ac->ac_aifsn * slottime + IEEE80211_DUR_DS_SIFS; 1280 rtwn_write_4(sc, aci2reg[aci], 1281 SM(R92C_EDCA_PARAM_TXOP, ac->ac_txoplimit) | 1282 SM(R92C_EDCA_PARAM_ECWMIN, ac->ac_ecwmin) | 1283 SM(R92C_EDCA_PARAM_ECWMAX, ac->ac_ecwmax) | 1284 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1285 1286 /* Is admission control mandatory for this queue? */ 1287 if (ac->ac_acm) { 1288 switch (aci) { 1289 case EDCA_AC_BE: 1290 acm |= R92C_ACMHW_BEQEN; 1291 break; 1292 case EDCA_AC_VI: 1293 acm |= R92C_ACMHW_VIQEN; 1294 break; 1295 case EDCA_AC_VO: 1296 acm |= R92C_ACMHW_VOQEN; 1297 break; 1298 default: 1299 break; 1300 } 1301 } 1302 } 1303 splx(s); 1304 1305 /* Enable hardware admission control. */ 1306 rtwn_write_1(sc, R92C_ACMHWCTRL, R92C_ACMHW_HWEN | acm); 1307 } 1308 1309 int 1310 rtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1311 struct ieee80211_key *k) 1312 { 1313 struct rtwn_softc *sc = ic->ic_softc; 1314 static const uint8_t etherzeroaddr[6] = { 0 }; 1315 const uint8_t *macaddr; 1316 uint8_t keybuf[16], algo; 1317 int i, entry; 1318 1319 /* Defer setting of WEP keys until interface is brought up. */ 1320 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1321 (IFF_UP | IFF_RUNNING)) 1322 return (0); 1323 1324 /* Map net80211 cipher to HW crypto algorithm. */ 1325 switch (k->k_cipher) { 1326 case IEEE80211_CIPHER_WEP40: 1327 algo = R92C_CAM_ALGO_WEP40; 1328 break; 1329 case IEEE80211_CIPHER_WEP104: 1330 algo = R92C_CAM_ALGO_WEP104; 1331 break; 1332 case IEEE80211_CIPHER_TKIP: 1333 algo = R92C_CAM_ALGO_TKIP; 1334 break; 1335 case IEEE80211_CIPHER_CCMP: 1336 algo = R92C_CAM_ALGO_AES; 1337 break; 1338 default: 1339 /* Fallback to software crypto for other ciphers. */ 1340 return (ieee80211_set_key(ic, ni, k)); 1341 } 1342 if (k->k_flags & IEEE80211_KEY_GROUP) { 1343 macaddr = etherzeroaddr; 1344 entry = k->k_id; 1345 } else { 1346 macaddr = ic->ic_bss->ni_macaddr; 1347 entry = 4; 1348 } 1349 /* Write key. */ 1350 memset(keybuf, 0, sizeof(keybuf)); 1351 memcpy(keybuf, k->k_key, MIN(k->k_len, sizeof(keybuf))); 1352 for (i = 0; i < 4; i++) { 1353 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 1354 LE_READ_4(&keybuf[i * 4])); 1355 } 1356 /* Write CTL0 last since that will validate the CAM entry. */ 1357 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 1358 LE_READ_4(&macaddr[2])); 1359 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 1360 SM(R92C_CAM_ALGO, algo) | 1361 SM(R92C_CAM_KEYID, k->k_id) | 1362 SM(R92C_CAM_MACLO, LE_READ_2(&macaddr[0])) | 1363 R92C_CAM_VALID); 1364 1365 return (0); 1366 } 1367 1368 void 1369 rtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1370 struct ieee80211_key *k) 1371 { 1372 struct rtwn_softc *sc = ic->ic_softc; 1373 int i, entry; 1374 1375 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1376 ic->ic_state != IEEE80211_S_RUN) 1377 return; /* Nothing to do. */ 1378 1379 if (k->k_flags & IEEE80211_KEY_GROUP) 1380 entry = k->k_id; 1381 else 1382 entry = 4; 1383 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 0); 1384 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 0); 1385 /* Clear key. */ 1386 for (i = 0; i < 4; i++) 1387 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 0); 1388 } 1389 1390 void 1391 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1392 { 1393 int pwdb; 1394 1395 /* Convert antenna signal to percentage. */ 1396 if (rssi <= -100 || rssi >= 20) 1397 pwdb = 0; 1398 else if (rssi >= 0) 1399 pwdb = 100; 1400 else 1401 pwdb = 100 + rssi; 1402 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) { 1403 if (rate <= 3) { 1404 /* CCK gain is smaller than OFDM/MCS gain. */ 1405 pwdb += 6; 1406 if (pwdb > 100) 1407 pwdb = 100; 1408 if (pwdb <= 14) 1409 pwdb -= 4; 1410 else if (pwdb <= 26) 1411 pwdb -= 8; 1412 else if (pwdb <= 34) 1413 pwdb -= 6; 1414 else if (pwdb <= 42) 1415 pwdb -= 2; 1416 } 1417 } 1418 if (sc->avg_pwdb == -1) /* Init. */ 1419 sc->avg_pwdb = pwdb; 1420 else if (sc->avg_pwdb < pwdb) 1421 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1422 else 1423 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1424 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1425 } 1426 1427 int8_t 1428 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1429 { 1430 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1431 struct r92c_rx_phystat *phy; 1432 struct r92c_rx_cck *cck; 1433 uint8_t rpt; 1434 int8_t rssi; 1435 1436 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 1437 return rtwn_r88e_get_rssi(sc, rate, physt); 1438 1439 if (rate <= 3) { 1440 cck = (struct r92c_rx_cck *)physt; 1441 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1442 rpt = (cck->agc_rpt >> 5) & 0x3; 1443 rssi = (cck->agc_rpt & 0x1f) << 1; 1444 } else { 1445 rpt = (cck->agc_rpt >> 6) & 0x3; 1446 rssi = cck->agc_rpt & 0x3e; 1447 } 1448 rssi = cckoff[rpt] - rssi; 1449 } else { /* OFDM/HT. */ 1450 phy = (struct r92c_rx_phystat *)physt; 1451 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 110; 1452 } 1453 return (rssi); 1454 } 1455 1456 int8_t 1457 rtwn_r88e_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1458 { 1459 static const int8_t cckoff[] = { 20, 14, 10, -4, -16, -22, -38, -40 }; 1460 struct r88e_rx_phystat *phy; 1461 uint8_t rpt; 1462 int8_t rssi; 1463 1464 phy = (struct r88e_rx_phystat *)physt; 1465 1466 if (rate <= 3) { 1467 rpt = (phy->agc_rpt >> 5) & 0x7; 1468 rssi = (phy->agc_rpt & 0x1f) << 1; 1469 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1470 if (rpt == 2) 1471 rssi -= 6; 1472 } 1473 rssi = (phy->agc_rpt & 0x1f) > 27 ? -94 : cckoff[rpt] - rssi; 1474 } else { /* OFDM/HT. */ 1475 rssi = ((le32toh(phy->sq_rpt) >> 1) & 0x7f) - 110; 1476 } 1477 return (rssi); 1478 } 1479 1480 void 1481 rtwn_start(struct ifnet *ifp) 1482 { 1483 struct rtwn_softc *sc = ifp->if_softc; 1484 struct ieee80211com *ic = &sc->sc_ic; 1485 struct ieee80211_node *ni; 1486 struct mbuf *m; 1487 1488 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1489 return; 1490 1491 for (;;) { 1492 if (sc->sc_ops.is_oactive(sc->sc_ops.cookie)) { 1493 ifq_set_oactive(&ifp->if_snd); 1494 break; 1495 } 1496 /* Send pending management frames first. */ 1497 m = mq_dequeue(&ic->ic_mgtq); 1498 if (m != NULL) { 1499 ni = m->m_pkthdr.ph_cookie; 1500 goto sendit; 1501 } 1502 if (ic->ic_state != IEEE80211_S_RUN) 1503 break; 1504 1505 /* Encapsulate and send data frames. */ 1506 m = ifq_dequeue(&ifp->if_snd); 1507 if (m == NULL) 1508 break; 1509 #if NBPFILTER > 0 1510 if (ifp->if_bpf != NULL) 1511 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1512 #endif 1513 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1514 continue; 1515 sendit: 1516 #if NBPFILTER > 0 1517 if (ic->ic_rawbpf != NULL) 1518 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1519 #endif 1520 if (sc->sc_ops.tx(sc->sc_ops.cookie, m, ni) != 0) { 1521 ieee80211_release_node(ic, ni); 1522 ifp->if_oerrors++; 1523 continue; 1524 } 1525 1526 sc->sc_tx_timer = 5; 1527 ifp->if_timer = 1; 1528 } 1529 } 1530 1531 void 1532 rtwn_watchdog(struct ifnet *ifp) 1533 { 1534 struct rtwn_softc *sc = ifp->if_softc; 1535 1536 ifp->if_timer = 0; 1537 1538 if (sc->sc_tx_timer > 0) { 1539 if (--sc->sc_tx_timer == 0) { 1540 printf("%s: device timeout\n", sc->sc_pdev->dv_xname); 1541 task_add(systq, &sc->init_task); 1542 ifp->if_oerrors++; 1543 return; 1544 } 1545 ifp->if_timer = 1; 1546 } 1547 ieee80211_watchdog(ifp); 1548 } 1549 1550 int 1551 rtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1552 { 1553 struct rtwn_softc *sc = ifp->if_softc; 1554 struct ieee80211com *ic = &sc->sc_ic; 1555 int s, error = 0; 1556 1557 s = splnet(); 1558 /* 1559 * Prevent processes from entering this function while another 1560 * process is tsleep'ing in it. 1561 */ 1562 while ((sc->sc_flags & RTWN_FLAG_BUSY) && error == 0) 1563 error = tsleep_nsec(&sc->sc_flags, PCATCH, "rtwnioc", INFSLP); 1564 if (error != 0) { 1565 splx(s); 1566 return error; 1567 } 1568 sc->sc_flags |= RTWN_FLAG_BUSY; 1569 1570 switch (cmd) { 1571 case SIOCSIFADDR: 1572 ifp->if_flags |= IFF_UP; 1573 /* FALLTHROUGH */ 1574 case SIOCSIFFLAGS: 1575 if (ifp->if_flags & IFF_UP) { 1576 if (!(ifp->if_flags & IFF_RUNNING)) 1577 rtwn_init(ifp); 1578 } else { 1579 if (ifp->if_flags & IFF_RUNNING) 1580 rtwn_stop(ifp); 1581 } 1582 break; 1583 case SIOCS80211CHANNEL: 1584 error = ieee80211_ioctl(ifp, cmd, data); 1585 if (error == ENETRESET && 1586 ic->ic_opmode == IEEE80211_M_MONITOR) { 1587 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1588 (IFF_UP | IFF_RUNNING)) 1589 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 1590 error = 0; 1591 } 1592 break; 1593 default: 1594 error = ieee80211_ioctl(ifp, cmd, data); 1595 } 1596 1597 if (error == ENETRESET) { 1598 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1599 (IFF_UP | IFF_RUNNING)) { 1600 rtwn_stop(ifp); 1601 rtwn_init(ifp); 1602 } 1603 error = 0; 1604 } 1605 sc->sc_flags &= ~RTWN_FLAG_BUSY; 1606 wakeup(&sc->sc_flags); 1607 splx(s); 1608 1609 return (error); 1610 } 1611 1612 void 1613 rtwn_fw_reset(struct rtwn_softc *sc) 1614 { 1615 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 1616 rtwn_r88e_fw_reset(sc); 1617 else 1618 rtwn_r92c_fw_reset(sc); 1619 } 1620 1621 void 1622 rtwn_r92c_fw_reset(struct rtwn_softc *sc) 1623 { 1624 uint16_t reg; 1625 int ntries; 1626 1627 /* Tell 8051 to reset itself. */ 1628 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 1629 1630 /* Wait until 8051 resets by itself. */ 1631 for (ntries = 0; ntries < 100; ntries++) { 1632 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1633 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 1634 goto sleep; 1635 DELAY(50); 1636 } 1637 /* Force 8051 reset. */ 1638 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 1639 sleep: 1640 if (sc->chip & RTWN_CHIP_PCI) { 1641 /* 1642 * We must sleep for one second to let the firmware settle. 1643 * Accessing registers too early will hang the whole system. 1644 */ 1645 tsleep_nsec(®, 0, "rtwnrst", SEC_TO_NSEC(1)); 1646 } 1647 } 1648 1649 void 1650 rtwn_r88e_fw_reset(struct rtwn_softc *sc) 1651 { 1652 uint16_t reg; 1653 1654 /* Reset MCU IO wrapper. */ 1655 rtwn_write_1(sc, R92C_RSV_CTRL, 1656 rtwn_read_1(sc, R92C_RSV_CTRL) & ~R92C_RSV_CTRL_WLOCK_00); 1657 if (sc->chip & RTWN_CHIP_88E) { 1658 rtwn_write_2(sc, R92C_RSV_CTRL, 1659 rtwn_read_2(sc, R92C_RSV_CTRL) & ~R88E_RSV_CTRL_MCU_RST); 1660 } else { 1661 rtwn_write_2(sc, R92C_RSV_CTRL, 1662 rtwn_read_2(sc, R92C_RSV_CTRL) & ~R88E_RSV_CTRL_MIO_EN); 1663 } 1664 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1665 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 1666 1667 /* Enable MCU IO wrapper. */ 1668 rtwn_write_1(sc, R92C_RSV_CTRL, 1669 rtwn_read_1(sc, R92C_RSV_CTRL) & ~R92C_RSV_CTRL_WLOCK_00); 1670 if (sc->chip & RTWN_CHIP_88E) { 1671 rtwn_write_2(sc, R92C_RSV_CTRL, 1672 rtwn_read_2(sc, R92C_RSV_CTRL) | R88E_RSV_CTRL_MCU_RST); 1673 } else { 1674 rtwn_write_2(sc, R92C_RSV_CTRL, 1675 rtwn_read_2(sc, R92C_RSV_CTRL) | R88E_RSV_CTRL_MIO_EN); 1676 } 1677 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 1678 } 1679 1680 int 1681 rtwn_load_firmware(struct rtwn_softc *sc) 1682 { 1683 const struct r92c_fw_hdr *hdr; 1684 u_char *fw, *ptr; 1685 size_t len0, len; 1686 uint32_t reg; 1687 int mlen, ntries, page, error; 1688 1689 /* Read firmware image from the filesystem. */ 1690 error = sc->sc_ops.load_firmware(sc->sc_ops.cookie, &fw, &len0); 1691 if (error) 1692 return (error); 1693 len = len0; 1694 if (len < sizeof(*hdr)) { 1695 printf("%s: firmware too short\n", sc->sc_pdev->dv_xname); 1696 error = EINVAL; 1697 goto fail; 1698 } 1699 ptr = fw; 1700 hdr = (const struct r92c_fw_hdr *)ptr; 1701 /* Check if there is a valid FW header and skip it. */ 1702 if ((letoh16(hdr->signature) >> 4) == 0x230 || 1703 (letoh16(hdr->signature) >> 4) == 0x88c || 1704 (letoh16(hdr->signature) >> 4) == 0x88e || 1705 (letoh16(hdr->signature) >> 4) == 0x92c || 1706 (letoh16(hdr->signature) >> 4) == 0x92e) { 1707 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 1708 letoh16(hdr->version), letoh16(hdr->subversion), 1709 hdr->month, hdr->date, hdr->hour, hdr->minute)); 1710 ptr += sizeof(*hdr); 1711 len -= sizeof(*hdr); 1712 } 1713 1714 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 1715 rtwn_write_1(sc, R92C_MCUFWDL, 0); 1716 rtwn_fw_reset(sc); 1717 } 1718 1719 if (sc->chip & RTWN_CHIP_PCI) { 1720 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1721 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | R92C_SYS_FUNC_EN_CPUEN); 1722 } 1723 1724 /* Enable FW download. */ 1725 rtwn_write_1(sc, R92C_MCUFWDL, 1726 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 1727 rtwn_write_4(sc, R92C_MCUFWDL, 1728 rtwn_read_4(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_ROM_DLEN); 1729 1730 /* Reset the FWDL checksum. */ 1731 rtwn_write_1(sc, R92C_MCUFWDL, 1732 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 1733 1734 DELAY(50); 1735 for (page = 0; len > 0; page++) { 1736 mlen = MIN(len, R92C_FW_PAGE_SIZE); 1737 error = sc->sc_ops.fw_loadpage(sc->sc_ops.cookie, page, ptr, 1738 mlen); 1739 if (error != 0) { 1740 printf("%s: could not load firmware page %d\n", 1741 sc->sc_pdev->dv_xname, page); 1742 goto fail; 1743 } 1744 ptr += mlen; 1745 len -= mlen; 1746 } 1747 1748 /* Wait for checksum report. */ 1749 for (ntries = 0; ntries < 1000; ntries++) { 1750 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 1751 break; 1752 DELAY(5); 1753 } 1754 if (ntries == 1000) { 1755 printf("%s: timeout waiting for checksum report\n", 1756 sc->sc_pdev->dv_xname); 1757 error = ETIMEDOUT; 1758 goto fail; 1759 } 1760 1761 /* Disable FW download. */ 1762 rtwn_write_1(sc, R92C_MCUFWDL, 1763 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 1764 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 1765 1766 reg = rtwn_read_4(sc, R92C_MCUFWDL); 1767 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 1768 rtwn_write_4(sc, R92C_MCUFWDL, reg); 1769 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C | RTWN_CHIP_23A)) { 1770 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1771 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1772 reg & ~R92C_SYS_FUNC_EN_CPUEN); 1773 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1774 reg | R92C_SYS_FUNC_EN_CPUEN); 1775 } else 1776 rtwn_fw_reset(sc); 1777 /* Wait for firmware readiness. */ 1778 for (ntries = 0; ntries < 1000; ntries++) { 1779 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 1780 break; 1781 DELAY(10); 1782 } 1783 if (ntries == 1000) { 1784 printf("%s: timeout waiting for firmware readiness\n", 1785 sc->sc_pdev->dv_xname); 1786 error = ETIMEDOUT; 1787 goto fail; 1788 } 1789 fail: 1790 free(fw, M_DEVBUF, len0); 1791 return (error); 1792 } 1793 1794 void 1795 rtwn_rf_init(struct rtwn_softc *sc) 1796 { 1797 const struct r92c_rf_prog *prog; 1798 uint32_t reg, type; 1799 int i, j, idx, off; 1800 1801 /* Select RF programming based on board type. */ 1802 if (sc->chip & RTWN_CHIP_88E) 1803 prog = rtl8188eu_rf_prog; 1804 else if (sc->chip & RTWN_CHIP_92E) 1805 prog = rtl8192e_rf_prog; 1806 else if (!(sc->chip & RTWN_CHIP_92C)) { 1807 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 1808 prog = rtl8188ce_rf_prog; 1809 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 1810 prog = rtl8188ru_rf_prog; 1811 else 1812 prog = rtl8188cu_rf_prog; 1813 } else 1814 prog = rtl8192ce_rf_prog; 1815 1816 for (i = 0; i < sc->nrxchains; i++) { 1817 /* Save RF_ENV control type. */ 1818 idx = i / 2; 1819 off = (i % 2) * 16; 1820 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1821 type = (reg >> off) & 0x10; 1822 1823 /* Set RF_ENV enable. */ 1824 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1825 reg |= 0x100000; 1826 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1827 DELAY(50); 1828 /* Set RF_ENV output high. */ 1829 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1830 reg |= 0x10; 1831 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1832 DELAY(50); 1833 /* Set address and data lengths of RF registers. */ 1834 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1835 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 1836 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1837 DELAY(50); 1838 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1839 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 1840 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1841 DELAY(50); 1842 1843 /* Write RF initialization values for this chain. */ 1844 for (j = 0; j < prog[i].count; j++) { 1845 switch (prog[i].regs[j]) { 1846 case 0xfe: 1847 DELAY(50000); 1848 continue; 1849 case 0xfd: 1850 DELAY(5000); 1851 continue; 1852 case 0xfc: 1853 DELAY(1000); 1854 continue; 1855 case 0xfb: 1856 DELAY(50); 1857 continue; 1858 case 0xfa: 1859 DELAY(5); 1860 continue; 1861 case 0xf9: 1862 DELAY(1); 1863 continue; 1864 } 1865 rtwn_rf_write(sc, i, prog[i].regs[j], 1866 prog[i].vals[j]); 1867 DELAY(5); 1868 } 1869 1870 /* Restore RF_ENV control type. */ 1871 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1872 reg &= ~(0x10 << off) | (type << off); 1873 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 1874 1875 /* Cache RF register CHNLBW. */ 1876 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 1877 } 1878 1879 /* magic value for HP 8188EEs */ 1880 if (sc->chip == (RTWN_CHIP_88E | RTWN_CHIP_PCI)) { 1881 struct r88e_rom *rom = &sc->sc_r88e_rom; 1882 if (rom->r88ee_rom.svid == 0x103c && 1883 rom->r88ee_rom.smid == 0x197d) 1884 rtwn_rf_write(sc, 0, 0x52, 0x7e4bd); 1885 } 1886 1887 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1888 RTWN_CHIP_UMC_A_CUT) { 1889 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 1890 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 1891 } else if (sc->chip & RTWN_CHIP_23A) { 1892 rtwn_rf_write(sc, 0, 0x0C, 0x894ae); 1893 rtwn_rf_write(sc, 0, 0x0A, 0x1af31); 1894 rtwn_rf_write(sc, 0, R92C_RF_IPA, 0x8f425); 1895 rtwn_rf_write(sc, 0, R92C_RF_SYN_G(1), 0x4f200); 1896 rtwn_rf_write(sc, 0, R92C_RF_RCK1, 0x44053); 1897 rtwn_rf_write(sc, 0, R92C_RF_RCK2, 0x80201); 1898 } 1899 } 1900 1901 void 1902 rtwn_cam_init(struct rtwn_softc *sc) 1903 { 1904 /* Invalidate all CAM entries. */ 1905 rtwn_write_4(sc, R92C_CAMCMD, 1906 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 1907 } 1908 1909 void 1910 rtwn_pa_bias_init(struct rtwn_softc *sc) 1911 { 1912 uint8_t reg; 1913 int i; 1914 1915 for (i = 0; i < sc->nrxchains; i++) { 1916 if (sc->pa_setting & (1 << i)) 1917 continue; 1918 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 1919 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 1920 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 1921 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 1922 } 1923 if (!(sc->pa_setting & 0x10)) { 1924 reg = rtwn_read_1(sc, 0x16); 1925 reg = (reg & ~0xf0) | 0x90; 1926 rtwn_write_1(sc, 0x16, reg); 1927 } 1928 } 1929 1930 void 1931 rtwn_rxfilter_init(struct rtwn_softc *sc) 1932 { 1933 /* Initialize Rx filter. */ 1934 rtwn_write_4(sc, R92C_RCR, 1935 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 1936 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 1937 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 1938 /* Accept all multicast frames. */ 1939 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 1940 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 1941 /* Accept all management frames. */ 1942 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 1943 /* Reject all control frames. */ 1944 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 1945 /* Accept all data frames. */ 1946 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1947 } 1948 1949 void 1950 rtwn_edca_init(struct rtwn_softc *sc) 1951 { 1952 struct ieee80211com *ic = &sc->sc_ic; 1953 int mode, aci; 1954 1955 /* Set SIFS; 0x10 = 16 usec (SIFS 11g), 0x0a = 10 usec (SIFS 11b) */ 1956 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 1957 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 1958 rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 1959 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 1960 rtwn_write_2(sc, R92C_RESP_SIFS_CCK, 0x100a); 1961 rtwn_write_2(sc, R92C_RESP_SIFS_OFDM, 0x100a); 1962 1963 if (ic->ic_curmode == IEEE80211_MODE_AUTO) 1964 mode = IEEE80211_MODE_11G; /* XXX */ 1965 else 1966 mode = ic->ic_curmode; 1967 for (aci = 0; aci < EDCA_NUM_AC; aci++) 1968 memcpy(&ic->ic_edca_ac[aci], &ieee80211_edca_table[mode][aci], 1969 sizeof(struct ieee80211_edca_ac_params)); 1970 rtwn_updateedca(ic); 1971 1972 if (sc->chip & RTWN_CHIP_PCI) { 1973 /* linux magic */ 1974 rtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x086666); 1975 } 1976 1977 rtwn_write_4(sc, R92C_EDCA_RANDOM_GEN, arc4random()); 1978 } 1979 1980 void 1981 rtwn_rate_fallback_init(struct rtwn_softc *sc) 1982 { 1983 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 1984 if (sc->chip & RTWN_CHIP_PCI) { 1985 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 1986 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 1987 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 1988 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 1989 } else if (sc->chip & RTWN_CHIP_USB) { 1990 rtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 1991 rtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 1992 rtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 1993 rtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 1994 } 1995 } 1996 } 1997 1998 void 1999 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2000 uint16_t power[RTWN_POWER_COUNT]) 2001 { 2002 uint32_t reg; 2003 2004 /* Write per-CCK rate Tx power. */ 2005 if (chain == 0) { 2006 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2007 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_POWER_CCK1]); 2008 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2009 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2010 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_POWER_CCK2]); 2011 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_POWER_CCK55]); 2012 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_POWER_CCK11]); 2013 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2014 } else { 2015 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2016 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_POWER_CCK1]); 2017 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_POWER_CCK2]); 2018 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_POWER_CCK55]); 2019 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2020 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2021 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_POWER_CCK11]); 2022 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2023 } 2024 /* Write per-OFDM rate Tx power. */ 2025 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2026 SM(R92C_TXAGC_RATE06, power[RTWN_POWER_OFDM6]) | 2027 SM(R92C_TXAGC_RATE09, power[RTWN_POWER_OFDM9]) | 2028 SM(R92C_TXAGC_RATE12, power[RTWN_POWER_OFDM12]) | 2029 SM(R92C_TXAGC_RATE18, power[RTWN_POWER_OFDM18])); 2030 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2031 SM(R92C_TXAGC_RATE24, power[RTWN_POWER_OFDM24]) | 2032 SM(R92C_TXAGC_RATE36, power[RTWN_POWER_OFDM36]) | 2033 SM(R92C_TXAGC_RATE48, power[RTWN_POWER_OFDM48]) | 2034 SM(R92C_TXAGC_RATE54, power[RTWN_POWER_OFDM54])); 2035 /* Write per-MCS Tx power. */ 2036 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2037 SM(R92C_TXAGC_MCS00, power[RTWN_POWER_MCS( 0)]) | 2038 SM(R92C_TXAGC_MCS01, power[RTWN_POWER_MCS( 1)]) | 2039 SM(R92C_TXAGC_MCS02, power[RTWN_POWER_MCS( 2)]) | 2040 SM(R92C_TXAGC_MCS03, power[RTWN_POWER_MCS( 3)])); 2041 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2042 SM(R92C_TXAGC_MCS04, power[RTWN_POWER_MCS( 4)]) | 2043 SM(R92C_TXAGC_MCS05, power[RTWN_POWER_MCS( 5)]) | 2044 SM(R92C_TXAGC_MCS06, power[RTWN_POWER_MCS( 6)]) | 2045 SM(R92C_TXAGC_MCS07, power[RTWN_POWER_MCS( 7)])); 2046 if (sc->ntxchains > 1) { 2047 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2048 SM(R92C_TXAGC_MCS08, power[RTWN_POWER_MCS( 8)]) | 2049 SM(R92C_TXAGC_MCS09, power[RTWN_POWER_MCS( 9)]) | 2050 SM(R92C_TXAGC_MCS10, power[RTWN_POWER_MCS(10)]) | 2051 SM(R92C_TXAGC_MCS11, power[RTWN_POWER_MCS(11)])); 2052 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2053 SM(R92C_TXAGC_MCS12, power[RTWN_POWER_MCS(12)]) | 2054 SM(R92C_TXAGC_MCS13, power[RTWN_POWER_MCS(13)]) | 2055 SM(R92C_TXAGC_MCS14, power[RTWN_POWER_MCS(14)]) | 2056 SM(R92C_TXAGC_MCS15, power[RTWN_POWER_MCS(15)])); 2057 } 2058 } 2059 2060 void 2061 rtwn_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c, 2062 struct ieee80211_channel *extc, uint16_t power[RTWN_POWER_COUNT]) 2063 { 2064 if (sc->chip & RTWN_CHIP_88E) 2065 rtwn_r88e_get_txpower(sc, chain, c, extc, power); 2066 else if (sc->chip & RTWN_CHIP_92E) 2067 rtwn_r92e_get_txpower(sc, chain, c, extc, power); 2068 else 2069 rtwn_r92c_get_txpower(sc, chain, c, extc, power); 2070 } 2071 2072 void 2073 rtwn_r92c_get_txpower(struct rtwn_softc *sc, int chain, 2074 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2075 uint16_t power[RTWN_POWER_COUNT]) 2076 { 2077 struct ieee80211com *ic = &sc->sc_ic; 2078 struct r92c_rom *rom = &sc->sc_r92c_rom; 2079 uint16_t cckpow, ofdmpow, htpow, diff, max; 2080 const struct r92c_txpwr *base; 2081 int ridx, chan, group; 2082 2083 /* Determine channel group. */ 2084 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2085 if (chan <= 3) 2086 group = 0; 2087 else if (chan <= 9) 2088 group = 1; 2089 else 2090 group = 2; 2091 2092 /* Get original Tx power based on board type and RF chain. */ 2093 if (!(sc->chip & RTWN_CHIP_92C)) { 2094 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2095 base = &rtl8188ru_txagc[chain]; 2096 else 2097 base = &rtl8192cu_txagc[chain]; 2098 } else 2099 base = &rtl8192cu_txagc[chain]; 2100 2101 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2102 if (sc->regulatory == 0) { 2103 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 2104 power[ridx] = base->pwr[0][ridx]; 2105 } 2106 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_MAX; ridx++) { 2107 if (sc->regulatory == 3) { 2108 power[ridx] = base->pwr[0][ridx]; 2109 /* Apply vendor limits. */ 2110 if (extc != NULL) 2111 max = rom->ht40_max_pwr[group]; 2112 else 2113 max = rom->ht20_max_pwr[group]; 2114 max = (max >> (chain * 4)) & 0xf; 2115 if (power[ridx] > max) 2116 power[ridx] = max; 2117 } else if (sc->regulatory == 1) { 2118 if (extc == NULL) 2119 power[ridx] = base->pwr[group][ridx]; 2120 } else if (sc->regulatory != 2) 2121 power[ridx] = base->pwr[0][ridx]; 2122 } 2123 2124 /* Compute per-CCK rate Tx power. */ 2125 cckpow = rom->cck_tx_pwr[chain][group]; 2126 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2127 power[ridx] += cckpow; 2128 if (power[ridx] > R92C_MAX_TX_PWR) 2129 power[ridx] = R92C_MAX_TX_PWR; 2130 } 2131 2132 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2133 if (sc->ntxchains > 1) { 2134 /* Apply reduction for 2 spatial streams. */ 2135 diff = rom->ht40_2s_tx_pwr_diff[group]; 2136 diff = (diff >> (chain * 4)) & 0xf; 2137 htpow = (htpow > diff) ? htpow - diff : 0; 2138 } 2139 2140 /* Compute per-OFDM rate Tx power. */ 2141 diff = rom->ofdm_tx_pwr_diff[group]; 2142 diff = (diff >> (chain * 4)) & 0xf; 2143 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2144 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2145 power[ridx] += ofdmpow; 2146 if (power[ridx] > R92C_MAX_TX_PWR) 2147 power[ridx] = R92C_MAX_TX_PWR; 2148 } 2149 2150 /* Compute per-MCS Tx power. */ 2151 if (extc == NULL) { 2152 diff = rom->ht20_tx_pwr_diff[group]; 2153 diff = (diff >> (chain * 4)) & 0xf; 2154 htpow += diff; /* HT40->HT20 correction. */ 2155 } 2156 for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) { 2157 power[ridx] += htpow; 2158 if (power[ridx] > R92C_MAX_TX_PWR) 2159 power[ridx] = R92C_MAX_TX_PWR; 2160 } 2161 #ifdef RTWN_DEBUG 2162 if (rtwn_debug >= 4) { 2163 /* Dump per-rate Tx power values. */ 2164 printf("Tx power for chain %d:\n", chain); 2165 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_MAX; ridx++) 2166 printf("Rate %d = %u\n", ridx, power[ridx]); 2167 } 2168 #endif 2169 } 2170 2171 void 2172 rtwn_r92e_get_txpower(struct rtwn_softc *sc, int chain, 2173 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2174 uint16_t power[RTWN_POWER_COUNT]) 2175 { 2176 struct ieee80211com *ic = &sc->sc_ic; 2177 struct r92e_rom *rom = &sc->sc_r92e_rom; 2178 struct r92e_tx_pwr *txpwr; 2179 uint8_t cckpow, htpow, htpow2s = 0, ofdmpow; 2180 int8_t diff; 2181 int ridx, chan, group; 2182 2183 /* Determine channel group. */ 2184 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2185 if (chan <= 2) 2186 group = 0; 2187 else if (chan <= 5) 2188 group = 1; 2189 else if (chan <= 8) 2190 group = 2; 2191 else if (chan <= 11) 2192 group = 3; 2193 else 2194 group = 4; 2195 2196 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2197 2198 if (chain == 0) 2199 txpwr = &rom->txpwr_a; 2200 else 2201 txpwr = &rom->txpwr_b; 2202 2203 /* Compute per-CCK rate Tx power. */ 2204 cckpow = txpwr->cck_tx_pwr[group]; 2205 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2206 power[ridx] = cckpow; 2207 if (power[ridx] > R92C_MAX_TX_PWR) 2208 power[ridx] = R92C_MAX_TX_PWR; 2209 } 2210 2211 htpow = txpwr->ht40_tx_pwr[group]; 2212 2213 /* Compute per-OFDM rate Tx power. */ 2214 diff = RTWN_SIGN4TO8(MS(txpwr->ht20_ofdm_tx_pwr_diff, 2215 R92E_ROM_TXPWR_OFDM_DIFF)); 2216 ofdmpow = htpow + diff; 2217 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2218 power[ridx] = ofdmpow; 2219 if (power[ridx] > R92C_MAX_TX_PWR) 2220 power[ridx] = R92C_MAX_TX_PWR; 2221 } 2222 2223 /* Compute per-MCS Tx power. */ 2224 if (extc == NULL) { 2225 diff = RTWN_SIGN4TO8(MS(txpwr->ht20_ofdm_tx_pwr_diff, 2226 R92E_ROM_TXPWR_HT20_DIFF)); 2227 htpow += diff; 2228 if (sc->ntxchains > 1) { 2229 diff = RTWN_SIGN4TO8(MS( 2230 txpwr->pwr_diff[0].ht40_ht20_tx_pwr_diff, 2231 R92E_ROM_TXPWR_HT20_2S_DIFF)); 2232 htpow2s = htpow + diff; 2233 } 2234 } 2235 2236 for (ridx = RTWN_RIDX_MCS0; ridx < RTWN_RIDX_MCS15; ridx++) { 2237 power[ridx] = (ridx < RTWN_RIDX_MCS8) ? htpow : htpow2s; 2238 if (power[ridx] > R92C_MAX_TX_PWR) 2239 power[ridx] = R92C_MAX_TX_PWR; 2240 } 2241 } 2242 2243 void 2244 rtwn_r88e_get_txpower(struct rtwn_softc *sc, int chain, 2245 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2246 uint16_t power[RTWN_POWER_COUNT]) 2247 { 2248 struct ieee80211com *ic = &sc->sc_ic; 2249 struct r88e_rom *rom = &sc->sc_r88e_rom; 2250 uint8_t cckpow, htpow, ofdmpow; 2251 int8_t diff; 2252 int ridx, chan, group; 2253 2254 /* Determine channel group. */ 2255 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2256 if (chan <= 2) 2257 group = 0; 2258 else if (chan <= 5) 2259 group = 1; 2260 else if (chan <= 8) 2261 group = 2; 2262 else if (chan <= 11) 2263 group = 3; 2264 else if (chan <= 13) 2265 group = 4; 2266 else 2267 group = 5; 2268 2269 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2270 2271 /* Compute per-CCK rate Tx power. */ 2272 cckpow = rom->txpwr.cck_tx_pwr[group]; 2273 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2274 power[ridx] = (ridx == RTWN_RIDX_CCK2) ? cckpow - 9 : cckpow; 2275 if (power[ridx] > R92C_MAX_TX_PWR) 2276 power[ridx] = R92C_MAX_TX_PWR; 2277 } 2278 2279 htpow = (group == 5) ? rom->txpwr.ht40_tx_pwr[group - 1] : 2280 rom->txpwr.ht40_tx_pwr[group]; 2281 2282 /* Compute per-OFDM rate Tx power. */ 2283 diff = RTWN_SIGN4TO8(MS(rom->txpwr.ht20_ofdm_tx_pwr_diff, 2284 R88E_ROM_TXPWR_OFDM_DIFF)); 2285 ofdmpow = htpow + diff; 2286 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2287 power[ridx] = ofdmpow; 2288 if (power[ridx] > R92C_MAX_TX_PWR) 2289 power[ridx] = R92C_MAX_TX_PWR; 2290 } 2291 2292 /* Compute per-MCS Tx power. */ 2293 if (extc == NULL) { 2294 diff = RTWN_SIGN4TO8(MS(rom->txpwr.ht20_ofdm_tx_pwr_diff, 2295 R88E_ROM_TXPWR_HT20_DIFF)); 2296 htpow += diff; 2297 } 2298 for (ridx = RTWN_RIDX_MCS0; ridx < RTWN_RIDX_MCS8; ridx++) { 2299 power[ridx] = htpow; 2300 if (power[ridx] > R92C_MAX_TX_PWR) 2301 power[ridx] = R92C_MAX_TX_PWR; 2302 } 2303 } 2304 2305 void 2306 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 2307 struct ieee80211_channel *extc) 2308 { 2309 uint16_t power[RTWN_POWER_COUNT]; 2310 int i; 2311 2312 for (i = 0; i < sc->ntxchains; i++) { 2313 /* Compute per-rate Tx power values. */ 2314 rtwn_get_txpower(sc, i, c, extc, power); 2315 /* Write per-rate Tx power values to hardware. */ 2316 rtwn_write_txpower(sc, i, power); 2317 } 2318 } 2319 2320 void 2321 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 2322 struct ieee80211_channel *extc) 2323 { 2324 struct ieee80211com *ic = &sc->sc_ic; 2325 u_int chan; 2326 uint32_t reg; 2327 int i; 2328 2329 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2330 2331 /* Set Tx power for this new channel. */ 2332 rtwn_set_txpower(sc, c, extc); 2333 2334 if (extc != NULL) { 2335 uint32_t reg; 2336 2337 /* Is secondary channel below or above primary? */ 2338 int prichlo = c->ic_freq < extc->ic_freq; 2339 2340 if (sc->chip & RTWN_CHIP_92E) { 2341 uint16_t reg; 2342 reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL); 2343 reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK; 2344 reg |= R92C_WMAC_TRXPTCL_CTL_BW_40; 2345 rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg); 2346 rtwn_write_1(sc, R92E_DATA_SC, 0); 2347 } else { 2348 rtwn_write_1(sc, R92C_BWOPMODE, 2349 rtwn_read_1(sc, R92C_BWOPMODE) & 2350 ~R92C_BWOPMODE_20MHZ); 2351 } 2352 2353 reg = rtwn_read_1(sc, R92C_RRSR + 2); 2354 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2355 rtwn_write_1(sc, R92C_RRSR + 2, reg); 2356 2357 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2358 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2359 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2360 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2361 2362 /* Set CCK side band. */ 2363 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2364 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2365 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2366 2367 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 2368 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2369 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2370 2371 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2372 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2373 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2374 ~R92C_FPGA0_ANAPARAM2_CBW20); 2375 } 2376 2377 reg = rtwn_bb_read(sc, 0x818); 2378 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2379 rtwn_bb_write(sc, 0x818, reg); 2380 2381 /* Select 40MHz bandwidth. */ 2382 for (i = 0; i < sc->nrxchains; i++) { 2383 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2384 (sc->rf_chnlbw[i] & ~0xfff) | chan); 2385 } 2386 } else { 2387 if (sc->chip & RTWN_CHIP_92E) { 2388 uint16_t reg; 2389 reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL); 2390 reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK; 2391 rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg); 2392 rtwn_write_1(sc, R92E_DATA_SC, 0); 2393 } else { 2394 rtwn_write_1(sc, R92C_BWOPMODE, 2395 rtwn_read_1(sc, R92C_BWOPMODE) | 2396 R92C_BWOPMODE_20MHZ); 2397 } 2398 2399 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2400 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2401 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2402 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2403 2404 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2405 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2406 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2407 R92C_FPGA0_ANAPARAM2_CBW20); 2408 } else if (sc->chip & RTWN_CHIP_92E) { 2409 reg = rtwn_read_4(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT); 2410 reg &= ~0xc0000000; 2411 rtwn_write_4(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg); 2412 } 2413 2414 /* Select 20MHz bandwidth. */ 2415 for (i = 0; i < sc->nrxchains; i++) { 2416 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2417 (sc->rf_chnlbw[i] & ~0xfff) | chan | 2418 ((sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) ? 2419 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 2420 } 2421 } 2422 2423 if (sc->chip == (RTWN_CHIP_88E | RTWN_CHIP_PCI)) 2424 DELAY(25000); 2425 } 2426 2427 int 2428 rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2429 uint16_t rx[2]) 2430 { 2431 uint32_t status; 2432 int offset = chain * 0x20; 2433 uint32_t iqk_tone_92c[] = { 2434 0x10008c1f, 0x10008c1f, 0x82140102, 0x28160202, 0x10008c22 2435 }; 2436 uint32_t iqk_tone_92e[] = { 2437 0x18008c1c, 0x38008c1c, 0x82140303, 0x68160000, 0x38008c1c 2438 }; 2439 uint32_t *iqk_tone; 2440 2441 if (sc->chip & RTWN_CHIP_92E) 2442 iqk_tone = iqk_tone_92e; 2443 else 2444 iqk_tone = iqk_tone_92c; 2445 2446 if (chain == 0) { /* IQ calibration for chain 0. */ 2447 /* IQ calibration settings for chain 0. */ 2448 rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, iqk_tone[0]); 2449 rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[1]); 2450 rtwn_bb_write(sc, R92C_TX_IQK_PI_A, iqk_tone[2]); 2451 2452 if (sc->ntxchains > 1) { 2453 rtwn_bb_write(sc, R92C_RX_IQK_PI_A, iqk_tone[3]); 2454 /* IQ calibration settings for chain 1. */ 2455 rtwn_bb_write(sc, R92C_TX_IQK_TONE_B, iqk_tone[4]); 2456 rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[4]); 2457 rtwn_bb_write(sc, R92C_TX_IQK_PI_B, 0x82140102); 2458 rtwn_bb_write(sc, R92C_RX_IQK_PI_B, 0x28160202); 2459 } else 2460 rtwn_bb_write(sc, R92C_RX_IQK_PI_A, 0x28160502); 2461 2462 /* LO calibration settings. */ 2463 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 2464 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x00462911); 2465 else 2466 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1); 2467 /* We're doing LO and IQ calibration in one shot. */ 2468 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); 2469 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); 2470 2471 } else { /* IQ calibration for chain 1. */ 2472 /* We're doing LO and IQ calibration in one shot. */ 2473 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000002); 2474 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000000); 2475 } 2476 2477 /* Give LO and IQ calibrations the time to complete. */ 2478 DELAY(1000); 2479 2480 /* Read IQ calibration status. */ 2481 status = rtwn_bb_read(sc, 0xeac); 2482 2483 if (status & (1 << (28 + chain * 3))) 2484 return (0); /* Tx failed. */ 2485 /* Read Tx IQ calibration results. */ 2486 tx[0] = (rtwn_bb_read(sc, R92C_TX_POWER_BEFORE_IQK_A + offset) >> 16) 2487 & 0x3ff; 2488 tx[1] = (rtwn_bb_read(sc, R92C_TX_POWER_AFTER_IQK_A + offset) >> 16) 2489 & 0x3ff; 2490 if (tx[0] == 0x142 || tx[1] == 0x042) 2491 return (0); /* Tx failed. */ 2492 2493 if (status & (1 << (27 + chain * 3))) 2494 return (1); /* Rx failed. */ 2495 /* Read Rx IQ calibration results. */ 2496 rx[0] = (rtwn_bb_read(sc, R92C_RX_POWER_BEFORE_IQK_A_2 + offset) >> 16) 2497 & 0x3ff; 2498 rx[1] = (rtwn_bb_read(sc, R92C_RX_POWER_AFTER_IQK_A_2 + offset) >> 16) 2499 & 0x3ff; 2500 if (rx[0] == 0x132 || rx[1] == 0x036) 2501 return (1); /* Rx failed. */ 2502 2503 return (3); /* Both Tx and Rx succeeded. */ 2504 } 2505 2506 void 2507 rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2508 uint16_t rx[2][2], struct rtwn_iq_cal_regs *iq_cal_regs) 2509 { 2510 static const uint16_t reg_adda[16] = { 2511 0x85c, 0xe6c, 0xe70, 0xe74, 2512 0xe78, 0xe7c, 0xe80, 0xe84, 2513 0xe88, 0xe8c, 0xed0, 0xed4, 2514 0xed8, 0xedc, 0xee0, 0xeec 2515 }; 2516 static const uint32_t adda_92c[] = { 2517 0x0b1b25a0, 0x0bdb25a0, 0x04db25a4, 0x0b1b25a4 2518 }; 2519 static const uint32_t adda_92e[] = { 2520 0x0fc01616, 0x0fc01616, 0x0fc01616, 0x0fc01616 2521 }; 2522 const uint32_t *adda_vals; 2523 2524 int i, chain; 2525 uint32_t hssi_param1, reg; 2526 uint8_t xa_agc, xb_agc; 2527 2528 xa_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)) & 0xff; 2529 xb_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)) & 0xff; 2530 2531 if (sc->chip & RTWN_CHIP_92E) 2532 adda_vals = adda_92e; 2533 else 2534 adda_vals = adda_92c; 2535 2536 if (n == 0) { 2537 for (i = 0; i < nitems(reg_adda); i++) 2538 iq_cal_regs->adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2539 2540 iq_cal_regs->txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2541 iq_cal_regs->bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2542 iq_cal_regs->bcn_ctrl1 = rtwn_read_1(sc, R92C_BCN_CTRL1); 2543 iq_cal_regs->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2544 } 2545 2546 if (sc->ntxchains == 1) { 2547 rtwn_bb_write(sc, reg_adda[0], adda_vals[0]); 2548 for (i = 1; i < nitems(reg_adda); i++) 2549 rtwn_bb_write(sc, reg_adda[i], adda_vals[1]); 2550 } else { 2551 for (i = 0; i < nitems(reg_adda); i++) 2552 rtwn_bb_write(sc, reg_adda[i], adda_vals[2]); 2553 } 2554 2555 if (n == 0) { 2556 iq_cal_regs->ofdm0_trxpathena = 2557 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2558 iq_cal_regs->ofdm0_trmuxpar = 2559 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2560 iq_cal_regs->fpga0_rfifacesw0 = 2561 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)); 2562 iq_cal_regs->fpga0_rfifacesw1 = 2563 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2564 iq_cal_regs->fpga0_rfifaceoe0 = 2565 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 2566 iq_cal_regs->fpga0_rfifaceoe1 = 2567 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1)); 2568 iq_cal_regs->config_ant_a = 2569 rtwn_bb_read(sc, R92C_CONFIG_ANT_A); 2570 iq_cal_regs->config_ant_b = 2571 rtwn_bb_read(sc, R92C_CONFIG_ANT_B); 2572 iq_cal_regs->cck0_afesetting = 2573 rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2574 } 2575 2576 if (sc->chip & RTWN_CHIP_92E) { 2577 rtwn_write_4(sc, R92C_CCK0_AFESETTING, rtwn_read_4(sc, 2578 R92C_CCK0_AFESETTING) | 0x0f000000); 2579 } else { 2580 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2581 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2582 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2583 hssi_param1 | R92C_HSSI_PARAM1_PI); 2584 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2585 hssi_param1 | R92C_HSSI_PARAM1_PI); 2586 } 2587 } 2588 2589 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2590 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2591 2592 if (sc->chip & RTWN_CHIP_92E) { 2593 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22208200); 2594 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), 2595 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)) | (1 << 10) | 2596 (1 << 26)); 2597 2598 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), rtwn_bb_read(sc, 2599 R92C_FPGA0_RFIFACEOE(0)) | (1 << 10)); 2600 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), rtwn_bb_read(sc, 2601 R92C_FPGA0_RFIFACEOE(1)) | (1 << 10)); 2602 } else { 2603 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2604 2605 if (sc->ntxchains > 1) { 2606 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2607 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2608 } 2609 2610 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TXPAUSE_AC_VO | 2611 R92C_TXPAUSE_AC_VI | R92C_TXPAUSE_AC_BE | 2612 R92C_TXPAUSE_AC_BK | R92C_TXPAUSE_MGNT | 2613 R92C_TXPAUSE_HIGH); 2614 } 2615 rtwn_write_1(sc, R92C_BCN_CTRL, 2616 iq_cal_regs->bcn_ctrl & ~(R92C_BCN_CTRL_EN_BCN)); 2617 rtwn_write_1(sc, R92C_BCN_CTRL1, 2618 iq_cal_regs->bcn_ctrl1 & ~(R92C_BCN_CTRL_EN_BCN)); 2619 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2620 iq_cal_regs->gpio_muxcfg & ~(R92C_GPIO_MUXCFG_ENBT)); 2621 2622 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000); 2623 if (sc->ntxchains > 1) 2624 rtwn_bb_write(sc, R92C_CONFIG_ANT_B, 0x00080000); 2625 2626 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 2627 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); 2628 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); 2629 2630 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000); 2631 2632 for (chain = 0; chain < sc->ntxchains; chain++) { 2633 if (chain > 0) { 2634 /* Put chain 0 on standby. */ 2635 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00); 2636 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2637 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 2638 2639 /* Enable chain 1. */ 2640 for (i = 0; i < nitems(reg_adda); i++) 2641 rtwn_bb_write(sc, reg_adda[i], adda_vals[3]); 2642 } 2643 2644 /* Run IQ calibration twice. */ 2645 for (i = 0; i < 2; i++) { 2646 int ret; 2647 2648 ret = rtwn_iq_calib_chain(sc, chain, 2649 tx[chain], rx[chain]); 2650 if (ret == 0) { 2651 DPRINTF(("%s: chain %d: Tx failed.\n", 2652 __func__, chain)); 2653 tx[chain][0] = 0xff; 2654 tx[chain][1] = 0xff; 2655 rx[chain][0] = 0xff; 2656 rx[chain][1] = 0xff; 2657 } else if (ret == 1) { 2658 DPRINTF(("%s: chain %d: Rx failed.\n", 2659 __func__, chain)); 2660 rx[chain][0] = 0xff; 2661 rx[chain][1] = 0xff; 2662 } else if (ret == 3) { 2663 DPRINTF(("%s: chain %d: Both Tx and Rx " 2664 "succeeded.\n", __func__, chain)); 2665 } 2666 } 2667 2668 DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 2669 "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 2670 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 2671 } 2672 2673 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00); 2674 2675 if (!(sc->chip & RTWN_CHIP_92E)) { 2676 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 2677 if (sc->ntxchains > 1) 2678 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 2679 } 2680 2681 if (n != 0) { 2682 if (!(sc->chip & RTWN_CHIP_92E)) { 2683 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2684 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2685 hssi_param1); 2686 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2687 hssi_param1); 2688 } 2689 } 2690 2691 for (i = 0; i < nitems(reg_adda); i++) 2692 rtwn_bb_write(sc, reg_adda[i], iq_cal_regs->adda[i]); 2693 2694 rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs->txpause); 2695 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs->bcn_ctrl); 2696 rtwn_write_1(sc, R92C_BCN_CTRL1, iq_cal_regs->bcn_ctrl1); 2697 rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs->gpio_muxcfg); 2698 2699 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 2700 iq_cal_regs->ofdm0_trxpathena); 2701 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), 2702 iq_cal_regs->fpga0_rfifacesw0); 2703 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 2704 iq_cal_regs->fpga0_rfifacesw1); 2705 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), 2706 iq_cal_regs->fpga0_rfifaceoe0); 2707 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), 2708 iq_cal_regs->fpga0_rfifaceoe1); 2709 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 2710 iq_cal_regs->ofdm0_trmuxpar); 2711 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 2712 iq_cal_regs->config_ant_a); 2713 rtwn_bb_write(sc, R92C_CONFIG_ANT_B, 2714 iq_cal_regs->config_ant_b); 2715 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, 2716 iq_cal_regs->cck0_afesetting); 2717 2718 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2719 reg &= ~0xff; 2720 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | 0x50); 2721 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | xa_agc); 2722 2723 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2724 reg &= ~0xff; 2725 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | 0x50); 2726 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | xb_agc); 2727 2728 rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, 0x01008c00); 2729 rtwn_bb_write(sc, R92C_RX_IQK_TONE_A, 0x01008c00); 2730 } 2731 } 2732 2733 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 2734 int 2735 rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 2736 uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 2737 { 2738 int chain, i, tx_ok[2], rx_ok[2]; 2739 2740 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 2741 for (chain = 0; chain < ntxchains; chain++) { 2742 for (i = 0; i < 2; i++) { 2743 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 2744 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 2745 continue; 2746 2747 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 2748 RTWN_IQ_CAL_MAX_TOLERANCE); 2749 2750 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 2751 RTWN_IQ_CAL_MAX_TOLERANCE); 2752 } 2753 } 2754 2755 if (ntxchains > 1) 2756 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 2757 else 2758 return (tx_ok[0] && rx_ok[0]); 2759 } 2760 #undef RTWN_IQ_CAL_MAX_TOLERANCE 2761 2762 void 2763 rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 2764 uint16_t rx[2], int chain) 2765 { 2766 uint32_t reg, val, x; 2767 long y, tx_c; 2768 2769 if (tx[0] == 0xff || tx[1] == 0xff) 2770 return; 2771 2772 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2773 val = ((reg >> 22) & 0x3ff); 2774 x = tx[0]; 2775 if (x & 0x00000200) 2776 x |= 0xfffffc00; 2777 reg &= ~0x3ff; 2778 reg |= (((x * val) >> 8) & 0x3ff); 2779 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2780 2781 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2782 if (((x * val) >> 7) & 0x01) 2783 reg |= 0x80000000; 2784 else 2785 reg &= ~0x80000000; 2786 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2787 2788 y = tx[1]; 2789 if (y & 0x00000200) 2790 y |= 0xfffffc00; 2791 tx_c = (y * val) >> 8; 2792 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 2793 reg &= ~0xf0000000; 2794 reg |= ((tx_c & 0x3c0) << 22); 2795 rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 2796 2797 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2798 reg &= ~0x003f0000; 2799 reg |= ((tx_c & 0x3f) << 16); 2800 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2801 2802 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2803 if (((y * val) >> 7) & 0x01) 2804 reg |= 0x20000000; 2805 else 2806 reg &= ~0x20000000; 2807 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2808 2809 if (rx[0] == 0xff || rx[1] == 0xff) 2810 return; 2811 2812 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 2813 reg &= ~0x3ff; 2814 reg |= (rx[0] & 0x3ff); 2815 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2816 2817 reg &= ~0xfc00; 2818 reg |= ((rx[1] & 0x03f) << 10); 2819 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2820 2821 if (chain == 0) { 2822 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 2823 reg &= ~0xf0000000; 2824 reg |= ((rx[1] & 0x3c0) << 22); 2825 rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 2826 } else { 2827 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 2828 reg &= ~0xf000; 2829 reg |= ((rx[1] & 0x3c0) << 6); 2830 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 2831 } 2832 } 2833 2834 #define RTWN_IQ_CAL_NRUN 3 2835 void 2836 rtwn_iq_calib(struct rtwn_softc *sc) 2837 { 2838 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 2839 int n, valid; 2840 struct rtwn_iq_cal_regs regs; 2841 2842 valid = 0; 2843 memset(®s, 0, sizeof(regs)); 2844 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 2845 rtwn_iq_calib_run(sc, n, tx[n], rx[n], ®s); 2846 2847 if (n == 0) 2848 continue; 2849 2850 /* Valid results remain stable after consecutive runs. */ 2851 valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 2852 tx[n], rx[n], sc->ntxchains); 2853 if (valid) 2854 break; 2855 } 2856 2857 if (valid) { 2858 rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 2859 if (sc->ntxchains > 1) 2860 rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 2861 } 2862 } 2863 #undef RTWN_IQ_CAL_NRUN 2864 2865 void 2866 rtwn_lc_calib(struct rtwn_softc *sc) 2867 { 2868 uint32_t rf_ac[2]; 2869 uint8_t txmode; 2870 int i; 2871 2872 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 2873 if ((txmode & 0x70) != 0) { 2874 /* Disable all continuous Tx. */ 2875 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 2876 2877 /* Set RF mode to standby mode. */ 2878 for (i = 0; i < sc->nrxchains; i++) { 2879 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 2880 rtwn_rf_write(sc, i, R92C_RF_AC, 2881 RW(rf_ac[i], R92C_RF_AC_MODE, 2882 R92C_RF_AC_MODE_STANDBY)); 2883 } 2884 } else { 2885 /* Block all Tx queues. */ 2886 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TXPAUSE_ALL); 2887 } 2888 /* Start calibration. */ 2889 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2890 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 2891 2892 /* Give calibration the time to complete. */ 2893 DELAY(100); 2894 2895 /* Restore configuration. */ 2896 if ((txmode & 0x70) != 0) { 2897 /* Restore Tx mode. */ 2898 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 2899 /* Restore RF mode. */ 2900 for (i = 0; i < sc->nrxchains; i++) 2901 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 2902 } else { 2903 /* Unblock all Tx queues. */ 2904 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 2905 } 2906 } 2907 2908 void 2909 rtwn_temp_calib(struct rtwn_softc *sc) 2910 { 2911 int temp, t_meter_reg, t_meter_val; 2912 2913 if (sc->chip & RTWN_CHIP_92E) { 2914 t_meter_reg = R92E_RF_T_METER; 2915 t_meter_val = 0x37cf8; 2916 } else { 2917 t_meter_reg = R92C_RF_T_METER; 2918 t_meter_val = 0x60; 2919 } 2920 2921 if (sc->thcal_state == 0) { 2922 /* Start measuring temperature. */ 2923 rtwn_rf_write(sc, 0, t_meter_reg, t_meter_val); 2924 sc->thcal_state = 1; 2925 return; 2926 } 2927 sc->thcal_state = 0; 2928 2929 /* Read measured temperature. */ 2930 temp = rtwn_rf_read(sc, 0, t_meter_reg) & 0x1f; 2931 if (temp == 0) /* Read failed, skip. */ 2932 return; 2933 DPRINTFN(2, ("temperature=%d\n", temp)); 2934 2935 /* 2936 * Redo IQ and LC calibration if temperature changed significantly 2937 * since last calibration. 2938 */ 2939 if (sc->thcal_lctemp == 0) { 2940 /* First calibration is performed in rtwn_init(). */ 2941 sc->thcal_lctemp = temp; 2942 } else if (abs(temp - sc->thcal_lctemp) > 1) { 2943 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 2944 sc->thcal_lctemp, temp)); 2945 rtwn_iq_calib(sc); 2946 rtwn_lc_calib(sc); 2947 /* Record temperature of last calibration. */ 2948 sc->thcal_lctemp = temp; 2949 } 2950 } 2951 2952 void 2953 rtwn_enable_intr(struct rtwn_softc *sc) 2954 { 2955 if (sc->chip & RTWN_CHIP_92E) { 2956 rtwn_write_4(sc, R88E_HIMR, 0); 2957 rtwn_write_4(sc, R88E_HIMRE, 0); 2958 } else if (sc->chip & RTWN_CHIP_88E) { 2959 rtwn_write_4(sc, R88E_HISR, 0xffffffff); 2960 if (sc->chip & RTWN_CHIP_USB) { 2961 rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | 2962 R88E_HIMR_CPWM2 | R88E_HIMR_TBDER | 2963 R88E_HIMR_PSTIMEOUT); 2964 rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 2965 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | 2966 R88E_HIMRE_TXERR); 2967 } else { 2968 rtwn_write_4(sc, R88E_HIMR, 2969 RTWN_88E_INT_ENABLE); 2970 rtwn_write_4(sc, R88E_HIMRE, 2971 R88E_HIMRE_RXFOVW); 2972 rtwn_write_1(sc, R92C_C2HEVT_CLEAR, 0); 2973 rtwn_write_4(sc, R92C_HSIMR, 2974 R88E_HSIMR_PDN_INT_EN | R88E_HSIMR_RON_INT_EN); 2975 } 2976 2977 if (sc->chip & RTWN_CHIP_USB) { 2978 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 2979 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 2980 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 2981 } 2982 } else { 2983 uint32_t imask = 0; 2984 2985 if (sc->chip & RTWN_CHIP_USB) 2986 imask = 0xffffffff; 2987 else if (sc->chip & RTWN_CHIP_PCI) 2988 imask = RTWN_92C_INT_ENABLE; 2989 else 2990 panic("unknown chip type 0x%x", sc->chip); 2991 2992 /* CLear pending interrupts. */ 2993 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 2994 2995 /* Enable interrupts. */ 2996 rtwn_write_4(sc, R92C_HIMR, imask); 2997 } 2998 } 2999 3000 void 3001 rtwn_disable_intr(struct rtwn_softc *sc) 3002 { 3003 if (sc->chip & RTWN_CHIP_88E) { 3004 rtwn_write_4(sc, R88E_HISR, 0x00000000); 3005 rtwn_write_4(sc, R88E_HIMR, 0x00000000); 3006 rtwn_write_4(sc, R88E_HIMRE, 0x00000000); 3007 if (sc->chip & RTWN_CHIP_USB) { 3008 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3009 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3010 ~R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3011 } 3012 } else { 3013 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3014 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3015 } 3016 } 3017 3018 int 3019 rtwn_init(struct ifnet *ifp) 3020 { 3021 struct rtwn_softc *sc = ifp->if_softc; 3022 struct ieee80211com *ic = &sc->sc_ic; 3023 uint32_t reg; 3024 int i, error; 3025 3026 /* Init firmware commands ring. */ 3027 sc->fwcur = 0; 3028 3029 error = sc->sc_ops.alloc_buffers(sc->sc_ops.cookie); 3030 if (error) 3031 goto fail; 3032 3033 /* Power on adapter. */ 3034 error = sc->sc_ops.power_on(sc->sc_ops.cookie); 3035 if (error != 0) { 3036 printf("%s: could not power on adapter\n", 3037 sc->sc_pdev->dv_xname); 3038 goto fail; 3039 } 3040 3041 /* Initialize DMA. */ 3042 error = sc->sc_ops.dma_init(sc->sc_ops.cookie); 3043 if (error != 0) { 3044 printf("%s: could not initialize DMA\n", 3045 sc->sc_pdev->dv_xname); 3046 goto fail; 3047 } 3048 3049 /* Set info size in Rx descriptors (in 64-bit words). */ 3050 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3051 3052 if (sc->chip & RTWN_CHIP_USB) { 3053 /* Init interrupts. */ 3054 rtwn_enable_intr(sc); 3055 } else if (sc->chip & RTWN_CHIP_PCI) { 3056 rtwn_disable_intr(sc); 3057 } 3058 3059 /* Set MAC address. */ 3060 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3061 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3062 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3063 3064 /* Set initial network type. */ 3065 rtwn_set_nettype(sc, IEEE80211_M_MONITOR); 3066 3067 rtwn_rxfilter_init(sc); 3068 3069 reg = rtwn_read_4(sc, R92C_RRSR); 3070 if (sc->chip & RTWN_CHIP_USB) { 3071 reg = RW(reg, R92C_RRSR_RATE_BITMAP, 3072 R92C_RRSR_RATE_CCK_ONLY_1M); 3073 } else { 3074 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3075 } 3076 rtwn_write_4(sc, R92C_RRSR, reg); 3077 3078 /* Set short/long retry limits. */ 3079 if (sc->chip & RTWN_CHIP_USB) { 3080 rtwn_write_2(sc, R92C_RL, 3081 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3082 } else { 3083 rtwn_write_2(sc, R92C_RL, 3084 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3085 } 3086 3087 /* Initialize EDCA parameters. */ 3088 rtwn_edca_init(sc); 3089 3090 /* Set data and response automatic rate fallback retry counts. */ 3091 rtwn_rate_fallback_init(sc); 3092 3093 if (sc->chip & RTWN_CHIP_USB) { 3094 rtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3095 rtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3096 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3097 } else { 3098 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3099 } 3100 3101 /* Set ACK timeout. */ 3102 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3103 3104 /* Setup USB aggregation. */ 3105 if (sc->chip & RTWN_CHIP_USB) 3106 sc->sc_ops.aggr_init(sc->sc_ops.cookie); 3107 3108 /* Initialize beacon parameters. */ 3109 rtwn_write_2(sc, R92C_BCN_CTRL, 3110 (R92C_BCN_CTRL_DIS_TSF_UDT0 << 8) | R92C_BCN_CTRL_DIS_TSF_UDT0); 3111 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3112 rtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 3113 rtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 3114 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3115 3116 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 3117 /* Setup AMPDU aggregation. */ 3118 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3119 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3120 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3121 3122 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3123 } 3124 3125 if (sc->chip & RTWN_CHIP_PCI) { 3126 /* Reset H2C protection register. */ 3127 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3128 } 3129 3130 /* Load 8051 microcode. */ 3131 error = rtwn_load_firmware(sc); 3132 if (error != 0) 3133 goto fail; 3134 3135 /* Initialize MAC/BB/RF blocks. */ 3136 sc->sc_ops.mac_init(sc->sc_ops.cookie); 3137 sc->sc_ops.bb_init(sc->sc_ops.cookie); 3138 rtwn_rf_init(sc); 3139 3140 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) { 3141 rtwn_write_2(sc, R92C_CR, 3142 rtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3143 R92C_CR_MACRXEN); 3144 } 3145 3146 /* Turn CCK and OFDM blocks on. */ 3147 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3148 reg |= R92C_RFMOD_CCK_EN; 3149 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3150 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3151 reg |= R92C_RFMOD_OFDM_EN; 3152 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3153 3154 /* Clear per-station keys table. */ 3155 rtwn_cam_init(sc); 3156 3157 /* Enable decryption / encryption. */ 3158 if (sc->chip & RTWN_CHIP_USB) { 3159 rtwn_write_2(sc, R92C_SECCFG, 3160 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 3161 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXENC_ENA | 3162 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 3163 } 3164 3165 /* Enable hardware sequence numbering. */ 3166 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3167 3168 if (sc->chip & RTWN_CHIP_92E) { 3169 rtwn_write_4(sc, R92C_BAR_MODE_CTRL, 0x0201ffff); 3170 rtwn_write_1(sc, R92C_NAV_UPPER, 0); 3171 3172 rtwn_write_1(sc, R92C_QUEUE_CTRL, 3173 rtwn_read_1(sc, R92C_QUEUE_CTRL) & ~0x08); 3174 } 3175 3176 /* Perform LO and IQ calibrations. */ 3177 rtwn_iq_calib(sc); 3178 /* Perform LC calibration. */ 3179 rtwn_lc_calib(sc); 3180 3181 /* Fix USB interference issue. */ 3182 if (sc->chip & RTWN_CHIP_USB) { 3183 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 3184 rtwn_write_1(sc, 0xfe40, 0xe0); 3185 rtwn_write_1(sc, 0xfe41, 0x8d); 3186 rtwn_write_1(sc, 0xfe42, 0x80); 3187 3188 rtwn_pa_bias_init(sc); 3189 } 3190 } 3191 3192 /* Initialize GPIO setting. */ 3193 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3194 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3195 3196 /* Fix for lower temperature. */ 3197 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 3198 rtwn_write_1(sc, 0x15, 0xe9); 3199 3200 /* Set default channel. */ 3201 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3202 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 3203 3204 if (sc->chip & RTWN_CHIP_PCI) 3205 rtwn_enable_intr(sc); 3206 3207 error = sc->sc_ops.init(sc->sc_ops.cookie); 3208 if (error) 3209 goto fail; 3210 3211 /* We're ready to go. */ 3212 ifq_clr_oactive(&ifp->if_snd); 3213 ifp->if_flags |= IFF_RUNNING; 3214 3215 if ((ic->ic_flags & IEEE80211_F_WEPON) && 3216 (sc->chip & RTWN_CHIP_USB)) { 3217 /* Install WEP keys. */ 3218 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3219 ic->ic_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3220 sc->sc_ops.wait_async(sc->sc_ops.cookie); 3221 } 3222 3223 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3224 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3225 else 3226 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3227 return (0); 3228 fail: 3229 rtwn_stop(ifp); 3230 return (error); 3231 } 3232 3233 void 3234 rtwn_init_task(void *arg1) 3235 { 3236 struct rtwn_softc *sc = arg1; 3237 struct ifnet *ifp = &sc->sc_ic.ic_if; 3238 int s; 3239 3240 s = splnet(); 3241 while (sc->sc_flags & RTWN_FLAG_BUSY) 3242 tsleep_nsec(&sc->sc_flags, 0, "rtwnpwr", INFSLP); 3243 sc->sc_flags |= RTWN_FLAG_BUSY; 3244 3245 rtwn_stop(ifp); 3246 3247 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3248 rtwn_init(ifp); 3249 3250 sc->sc_flags &= ~RTWN_FLAG_BUSY; 3251 wakeup(&sc->sc_flags); 3252 splx(s); 3253 } 3254 3255 void 3256 rtwn_stop(struct ifnet *ifp) 3257 { 3258 struct rtwn_softc *sc = ifp->if_softc; 3259 struct ieee80211com *ic = &sc->sc_ic; 3260 int s; 3261 3262 sc->sc_tx_timer = 0; 3263 ifp->if_timer = 0; 3264 ifp->if_flags &= ~IFF_RUNNING; 3265 ifq_clr_oactive(&ifp->if_snd); 3266 3267 s = splnet(); 3268 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3269 splx(s); 3270 3271 sc->sc_ops.wait_async(sc->sc_ops.cookie); 3272 3273 s = splnet(); 3274 3275 sc->sc_ops.cancel_scan(sc->sc_ops.cookie); 3276 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 3277 3278 task_del(systq, &sc->init_task); 3279 3280 splx(s); 3281 3282 sc->sc_ops.stop(sc->sc_ops.cookie); 3283 } 3284