1 /* $OpenBSD: siopreg.h,v 1.11 2007/08/05 19:05:09 kettenis Exp $ */ 2 /* $NetBSD: siopreg.h,v 1.16 2005/02/27 00:27:02 perry Exp $ */ 3 4 /* 5 * Copyright (c) 2000 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Devices definitions for Symbios/NCR M53c8xx PCI-SCSI I/O Processors 36 * Docs available from http://www.symbios.com/ 37 */ 38 39 #define SIOP_SCNTL0 0x00 /* SCSI control 0, R/W */ 40 #define SCNTL0_ARB_MASK 0xc0 41 #define SCNTL0_SARB 0x00 42 #define SCNTL0_FARB 0xc0 43 #define SCNTL0_START 0x20 44 #define SCNTL0_WATM 0x10 45 #define SCNTL0_EPC 0x08 46 #define SCNTL0_AAP 0x02 47 #define SCNTL0_TRG 0x01 48 49 #define SIOP_SCNTL1 0x01 /* SCSI control 1, R/W */ 50 #define SCNTL1_EXC 0x80 51 #define SCNTL1_ADB 0x40 52 #define SCNTL1_DHP 0x20 53 #define SCNTL1_CON 0x10 54 #define SCNTL1_RST 0x08 55 #define SCNTL1_AESP 0x04 56 #define SCNTL1_IARB 0x02 57 #define SCNTL1_SST 0x01 58 59 #define SIOP_SCNTL2 0x02 /* SCSI control 2, R/W */ 60 #define SCNTL2_SDU 0x80 61 #define SCNTL2_CHM 0x40 /* 875 only */ 62 #define SCNTL2_SLPMD 0x20 /* 875 only */ 63 #define SCNTL2_SLPHBEN 0x10 /* 875 only */ 64 #define SCNTL2_WSS 0x08 /* 875 only */ 65 #define SCNTL2_VUE0 0x04 /* 875 only */ 66 #define SCNTL2_VUE1 0x02 /* 875 only */ 67 #define SCNTL2_WSR 0x01 /* 875 only */ 68 69 #define SIOP_SCNTL3 0x03 /* SCSI control 3, R/W */ 70 #define SCNTL3_ULTRA 0x80 /* 875 only */ 71 #define SCNTL3_SCF_SHIFT 4 72 #define SCNTL3_SCF_MASK 0x70 73 #define SCNTL3_EWS 0x08 /* 875 only */ 74 #define SCNTL3_CCF_SHIFT 0 75 #define SCNTL3_CCF_MASK 0x07 76 77 /* periods for various SCF values, assume transfer period of 4 */ 78 struct scf_period { 79 int clock; /* clock period (ns * 10) */ 80 int period; /* scsi period, as set in the SDTR message */ 81 int scf; /* scf value to use */ 82 }; 83 84 #ifdef SIOP_NEEDS_PERIOD_TABLES 85 static const struct scf_period scf_period[] = { 86 {250, 25, 1}, /* 10.0 MHz */ 87 {250, 37, 2}, /* 6.67 MHz */ 88 {250, 50, 3}, /* 5.00 MHz */ 89 {250, 75, 4}, /* 3.33 MHz */ 90 {125, 12, 1}, /* 20.0 MHz */ 91 {125, 18, 2}, /* 13.3 MHz */ 92 {125, 25, 3}, /* 10.0 MHz */ 93 {125, 37, 4}, /* 6.67 MHz */ 94 {125, 50, 5}, /* 5.0 MHz */ 95 { 62, 10, 1}, /* 40.0 MHz */ 96 { 62, 12, 3}, /* 20.0 MHz */ 97 { 62, 18, 4}, /* 13.3 MHz */ 98 { 62, 25, 5}, /* 10.0 MHz */ 99 }; 100 101 static const struct scf_period dt_scf_period[] = { 102 { 62, 9, 1}, /* 80.0 MHz */ 103 { 62, 10, 3}, /* 40.0 MHz */ 104 { 62, 12, 5}, /* 20.0 MHz */ 105 { 62, 18, 6}, /* 13.3 MHz */ 106 { 62, 25, 7}, /* 10.0 MHz */ 107 }; 108 #endif 109 110 #define SIOP_SCID 0x04 /* SCSI chip ID R/W */ 111 #define SCID_RRE 0x40 112 #define SCID_SRE 0x20 113 #define SCID_ENCID_SHIFT 0 114 #define SCID_ENCID_MASK 0x07 115 116 #define SIOP_SXFER 0x05 /* SCSI transfer, R/W */ 117 #define SXFER_TP_SHIFT 5 118 #define SXFER_TP_MASK 0xe0 119 #define SXFER_MO_SHIFT 0 120 #define SXFER_MO_MASK 0x3f 121 122 #define SIOP_SDID 0x06 /* SCSI destination ID, R/W */ 123 #define SDID_ENCID_SHIFT 0 124 #define SDID_ENCID_MASK 0x07 125 126 #define SIOP_GPREG 0x07 /* General purpose, R/W */ 127 #define GPREG_GPIO4 0x10 /* 875 only */ 128 #define GPREG_GPIO3 0x08 /* 875 only */ 129 #define GPREG_GPIO2 0x04 /* 875 only */ 130 #define GPREG_GPIO1 0x02 131 #define GPREG_GPIO0 0x01 132 133 #define SIOP_SFBR 0x08 /* SCSI first byte received, R/W */ 134 135 #define SIOP_SOCL 0x09 /* SCSI output control latch, RW */ 136 137 #define SIOP_SSID 0x0A /* SCSI selector ID, RO */ 138 #define SSID_VAL 0x80 139 #define SSID_ENCID_SHIFT 0 140 #define SSID_ENCID_MASK 0x0f 141 142 #define SIOP_SBCL 0x0B /* SCSI control line, RO */ 143 144 #define SIOP_DSTAT 0x0C /* DMA status, RO */ 145 #define DSTAT_DFE 0x80 146 #define DSTAT_MDPE 0x40 147 #define DSTAT_BF 0x20 148 #define DSTAT_ABRT 0x10 149 #define DSTAT_SSI 0x08 150 #define DSTAT_SIR 0x04 151 #define DSTAT_IID 0x01 152 153 #define SIOP_SSTAT0 0x0D /* STSI status 0, RO */ 154 #define SSTAT0_ILF 0x80 155 #define SSTAT0_ORF 0x40 156 #define SSTAT0_OLF 0x20 157 #define SSTAT0_AIP 0x10 158 #define SSTAT0_LOA 0x08 159 #define SSTAT0_WOA 0x04 160 #define SSTAT0_RST 0x02 161 #define SSTAT0_SDP 0x01 162 163 #define SIOP_SSTAT1 0x0E /* STSI status 1, RO */ 164 #define SSTAT1_FFO_SHIFT 4 165 #define SSTAT1_FFO_MASK 0x80 166 #define SSTAT1_SDPL 0x08 167 #define SSTAT1_MSG 0x04 168 #define SSTAT1_CD 0x02 169 #define SSTAT1_IO 0x01 170 #define SSTAT1_PHASE_MASK (SSTAT1_IO | SSTAT1_CD | SSTAT1_MSG) 171 #define SSTAT1_PHASE_DATAOUT 0 172 #define SSTAT1_PHASE_DATAIN SSTAT1_IO 173 #define SSTAT1_PHASE_CMD SSTAT1_CD 174 #define SSTAT1_PHASE_STATUS (SSTAT1_CD | SSTAT1_IO) 175 #define SSTAT1_PHASE_MSGOUT (SSTAT1_MSG | SSTAT1_CD) 176 #define SSTAT1_PHASE_MSGIN (SSTAT1_MSG | SSTAT1_CD | SSTAT1_IO) 177 178 #define SIOP_SSTAT2 0x0F /* STSI status 2, RO */ 179 #define SSTAT2_ILF1 0x80 /* 875 only */ 180 #define SSTAT2_ORF1 0x40 /* 875 only */ 181 #define SSTAT2_OLF1 0x20 /* 875 only */ 182 #define SSTAT2_FF4 0x10 /* 875 only */ 183 #define SSTAT2_SPL1 0x08 /* 875 only */ 184 #define SSTAT2_DF 0x04 /* 875 only */ 185 #define SSTAT2_LDSC 0x02 186 #define SSTAT2_SDP1 0x01 /* 875 only */ 187 188 #define SIOP_DSA 0x10 /* data struct addr, R/W */ 189 190 #define SIOP_ISTAT 0x14 /* IRQ status, R/W */ 191 #define ISTAT_ABRT 0x80 192 #define ISTAT_SRST 0x40 193 #define ISTAT_SIGP 0x20 194 #define ISTAT_SEM 0x10 195 #define ISTAT_CON 0x08 196 #define ISTAT_INTF 0x04 197 #define ISTAT_SIP 0x02 198 #define ISTAT_DIP 0x01 199 200 #define SIOP_CTEST0 0x18 /* Chip test 0, R/W */ 201 #define CTEST0_EHP 0x04 /* 720/770 */ 202 203 #define SIOP_CTEST1 0x19 /* Chip test 1, R/W */ 204 205 #define SIOP_CTEST2 0x1A /* Chip test 2, R/W */ 206 #define CTEST2_SRTCH 0x04 /* 875 only */ 207 208 #define SIOP_CTEST3 0x1B /* Chip test 3, R/W */ 209 #define CTEST3_FLF 0x08 210 #define CTEST3_CLF 0x04 211 #define CTEST3_FM 0x02 212 #define CTEST3_WRIE 0x01 213 214 #define SIOP_TEMP 0x1C /* Temp register (used by CALL/RET), R/W */ 215 216 #define SIOP_DFIFO 0x20 /* DMA FIFO */ 217 218 #define SIOP_CTEST4 0x21 /* Chip test 4, R/W */ 219 #define CTEST4_MUX 0x80 /* 720/770 */ 220 #define CTEST4_BDIS 0x80 221 #define CTEST_ZMOD 0x40 222 #define CTEST_ZSD 0x20 223 #define CTEST_SRTM 0x10 224 #define CTEST_MPEE 0x08 225 226 #define SIOP_CTEST5 0x22 /* Chip test 5, R/W */ 227 #define CTEST5_ADCK 0x80 228 #define CTEST5_BBCK 0x40 229 #define CTEST5_DFS 0x20 230 #define CTEST5_MASR 0x10 231 #define CTEST5_DDIR 0x08 232 #define CTEST5_BOMASK 0x03 233 234 #define SIOP_CTEST6 0x23 /* Chip test 6, R/W */ 235 236 #define SIOP_DBC 0x24 /* DMA byte counter, R/W */ 237 238 #define SIOP_DCMD 0x27 /* DMA command, R/W */ 239 240 #define SIOP_DNAD 0x28 /* DMA next addr, R/W */ 241 242 #define SIOP_DSP 0x2C /* DMA scripts pointer, R/W */ 243 244 #define SIOP_DSPS 0x30 /* DMA scripts pointer save, R/W */ 245 246 #define SIOP_SCRATCHA 0x34 /* scratch register A. R/W */ 247 248 #define SIOP_DMODE 0x38 /* DMA mode, R/W */ 249 #define DMODE_BL_SHIFT 6 250 #define DMODE_BL_MASK 0xC0 251 #define DMODE_SIOM 0x20 252 #define DMODE_DIOM 0x10 253 #define DMODE_ERL 0x08 254 #define DMODE_ERMP 0x04 255 #define DMODE_BOF 0x02 256 #define DMODE_MAN 0x01 257 258 #define SIOP_DIEN 0x39 /* DMA interrupt enable, R/W */ 259 #define DIEN_MDPE 0x40 260 #define DIEN_BF 0x20 261 #define DIEN_AVRT 0x10 262 #define DIEN_SSI 0x08 263 #define DIEN_SIR 0x04 264 #define DIEN_IID 0x01 265 266 #define SIOP_SBR 0x3A /* scratch byte register, R/W */ 267 268 #define SIOP_DCNTL 0x3B /* DMA control, R/W */ 269 #define DCNTL_CLSE 0x80 270 #define DCNTL_PFF 0x40 271 #define DCNTL_EA 0x20 /* 720/770 */ 272 #define DCNTL_PFEN 0x20 /* 8xx */ 273 #define DCNTL_SSM 0x10 274 #define DCNTL_IRQM 0x08 275 #define DCNTL_STD 0x04 276 #define DCNTL_IRQD 0x02 277 #define DCNTL_COM 0x01 278 279 #define SIOP_ADDER 0x3C /* adder output sum, RO */ 280 281 #define SIOP_SIEN0 0x40 /* SCSI interrupt enable 0, R/W */ 282 #define SIEN0_MA 0x80 283 #define SIEN0_CMP 0x40 284 #define SIEN0_SEL 0x20 285 #define SIEN0_RSL 0x10 286 #define SIEN0_SGE 0x08 287 #define SIEN0_UDC 0x04 288 #define SIEN0_SRT 0x02 289 #define SIEN0_PAR 0x01 290 291 #define SIOP_SIEN1 0x41 /* SCSI interrupt enable 1, R/W */ 292 #define SIEN1_SBMC 0x10 /* 895 only */ 293 #define SIEN1_STO 0x04 294 #define SIEN1_GEN 0x02 295 #define SIEN1_HTH 0x01 296 297 #define SIOP_SIST0 0x42 /* SCSI interrupt status 0, RO */ 298 #define SIST0_MA 0x80 299 #define SIST0_CMP 0x40 300 #define SIST0_SEL 0x20 301 #define SIST0_RSL 0x10 302 #define SIST0_SGE 0x08 303 #define SIST0_UDC 0x04 304 #define SIST0_RST 0x02 305 #define SIST0_PAR 0x01 306 307 #define SIOP_SIST1 0x43 /* SCSI interrupt status 1, RO */ 308 #define SIST1_SBMC 0x10 /* 895 only */ 309 #define SIST1_STO 0x04 310 #define SIST1_GEN 0x02 311 #define SIST1_HTH 0x01 312 313 #define SIOP_SLPAR 0x44 /* scsi longitudinal parity, R/W */ 314 315 #define SIOP_SWIDE 0x45 /* scsi wide residue, RW, 875 only */ 316 317 #define SIOP_MACNTL 0x46 /* memory access control, R/W */ 318 319 #define SIOP_GPCNTL 0x47 /* General Purpose Pin control, R/W */ 320 #define GPCNTL_ME 0x80 /* 875 only */ 321 #define GPCNTL_FE 0x40 /* 875 only */ 322 #define GPCNTL_IN4 0x10 /* 875 only */ 323 #define GPCNTL_IN3 0x08 /* 875 only */ 324 #define GPCNTL_IN2 0x04 /* 875 only */ 325 #define GPCNTL_IN1 0x02 326 #define GPCNTL_IN0 0x01 327 328 #define SIOP_STIME0 0x48 /* SCSI timer 0, R/W */ 329 #define STIME0_HTH_SHIFT 4 330 #define STIME0_HTH_MASK 0xf0 331 #define STIME0_SEL_SHIFT 0 332 #define STIME0_SEL_MASK 0x0f 333 334 #define SIOP_STIME1 0x49 /* SCSI timer 1, R/W */ 335 #define STIME1_HTHBA 0x40 /* 875 only */ 336 #define STIME1_GENSF 0x20 /* 875 only */ 337 #define STIME1_HTHSF 0x10 /* 875 only */ 338 #define STIME1_GEN_SHIFT 0 339 #define STIME1_GEN_MASK 0x0f 340 341 #define SIOP_RESPID0 0x4A /* response ID, R/W */ 342 343 #define SIOP_RESPID1 0x4B /* response ID, R/W, 875-only */ 344 345 #define SIOP_STEST0 0x4C /* SCSI test 0, RO */ 346 347 #define SIOP_STEST1 0x4D /* SCSI test 1, RO, RW on 875 */ 348 #define STEST1_DOGE 0x20 /* 1010 only */ 349 #define STEST1_DIGE 0x10 /* 1010 only */ 350 #define STEST1_DBLEN 0x08 /* 875-only */ 351 #define STEST1_DBLSEL 0x04 /* 875-only */ 352 353 #define SIOP_STEST2 0x4E /* SCSI test 2, RO, R/W on 875 */ 354 #define STEST2_DIF 0x20 /* 875 only */ 355 #define STEST2_EXT 0x02 356 357 #define SIOP_STEST3 0x4F /* SCSI test 3, RO, RW on 875 */ 358 #define STEST3_TE 0x80 359 #define STEST3_HSC 0x20 360 361 #define SIOP_STEST4 0x52 /* SCSI test 4, 895 only */ 362 #define STEST4_MODE_MASK 0xc0 363 #define STEST4_MODE_DIF 0x40 364 #define STEST4_MODE_SE 0x80 365 #define STEST4_MODE_LVD 0xc0 366 #define STEST4_LOCK 0x20 367 #define STEST4_ 368 369 #define SIOP_SIDL 0x50 /* SCSI input data latch, RO */ 370 371 #define SIOP_SODL 0x54 /* SCSI output data latch, R/W */ 372 373 #define SIOP_SBDL 0x58 /* SCSI bus data lines, RO */ 374 375 #define SIOP_SCRATCHB 0x5C /* Scratch register B, R/W */ 376 377 #define SIOP_SCRATCHC 0x60 /* Scratch register C, R/W, 875 only */ 378 379 #define SIOP_SCRATCHD 0x64 /* Scratch register D, R/W, 875-only */ 380 381 #define SIOP_SCRATCHE 0x68 /* Scratch register E, R/W, 875-only */ 382 383 #define SIOP_SCRATCHF 0x6c /* Scratch register F, R/W, 875-only */ 384 385 #define SIOP_SCRATCHG 0x70 /* Scratch register G, R/W, 875-only */ 386 387 #define SIOP_SCRATCHH 0x74 /* Scratch register H, R/W, 875-only */ 388 389 #define SIOP_SCRATCHI 0x78 /* Scratch register I, R/W, 875-only */ 390 391 #define SIOP_SCRATCHJ 0x7c /* Scratch register J, R/W, 875-only */ 392 393 #define SIOP_SCNTL4 0xBC /* SCSI control 4, R/W, 1010-only */ 394 #define SCNTL4_XCLKS_ST 0x01 395 #define SCNTL4_XCLKS_DT 0x02 396 #define SCNTL4_XCLKH_ST 0x04 397 #define SCNTL4_XCLKH_DT 0x08 398 #define SCNTL4_AIPEN 0x40 399 #define SCNTL4_U3EN 0x80 400 401 #define SIOP_DFBC 0xf0 /* DMA fifo byte count, RO */ 402 403 #define SIOP_AIPCNTL0 0xbe /* AIP Control 0, 1010-only */ 404 #define AIPCNTL0_ERRLIVE 0x04 /* AIP error status, live */ 405 #define AIPCNTL0_ERR 0x02 /* AIP error status, latched */ 406 #define AIPCNTL0_PARITYERRs 0x01 /* Parity error */ 407 408 #define SIOP_AIPCNTL1 0xbf /* AIP Control 1, 1010-only */ 409 #define AIPCNTL1_DIS 0x08 /* disable AIP generation, 1010-66 only */ 410 #define AIPCNTL1_RSETERR 0x04 /* reset AIP error 1010-66 only */ 411 #define AIPCNTL1_FB 0x02 /* force bad AIP value 1010-66 only */ 412 #define AIPCNTL1_RSET 0x01 /* reset AIP sequence value 1010-66 only */ 413 414 /* 415 * Non-volatile configuration settings stored in the EEPROM. There 416 * are at least two known formats: Symbios Logic format and Tekram format. 417 */ 418 419 #define SIOP_NVRAM_SYM_SIZE 368 420 #define SIOP_NVRAM_SYM_ADDRESS 0x100 421 422 struct nvram_symbios { 423 /* Header (6 bytes) */ 424 u_int16_t type; /* 0x0000 */ 425 u_int16_t byte_count; /* excluding header/trailer */ 426 u_int16_t checksum; 427 428 /* Adapter configuration (20 bytes) */ 429 u_int8_t v_major; 430 u_int8_t v_minor; 431 u_int32_t boot_crc; 432 u_int16_t flags; 433 #define NVRAM_SYM_F_SCAM_ENABLE 0x0001 434 #define NVRAM_SYM_F_PARITY_ENABLE 0x0002 435 #define NVRAM_SYM_F_VERBOSE_MESSAGES 0x0004 436 #define NVRAM_SYM_F_CHS_MAPPING 0x0008 437 u_int16_t flags1; 438 #define NVRAM_SYM_F1_SCAN_HI_LO 0x0001 439 u_int16_t term_state; 440 #define NVRAM_SYM_TERM_CANT_PROGRAM 0 441 #define NVRAM_SYM_TERM_ENABLED 1 442 #define NVRAM_SYM_TERM_DISABLED 2 443 u_int16_t rmvbl_flags; 444 #define NVRAM_SYM_RMVBL_NO_SUPPORT 0 445 #define NVRAM_SYM_RMVBL_BOOT_DEVICE 1 446 #define NVRAM_SYM_RMVBL_MEDIA_INSTALLED 2 447 u_int8_t host_id; 448 u_int8_t num_hba; 449 u_int8_t num_devices; 450 u_int8_t max_scam_devices; 451 u_int8_t num_valid_scam_devices; 452 u_int8_t rsvd; 453 454 /* Boot order (14 bytes x 4) */ 455 struct nvram_symbios_host { 456 u_int16_t type; /* 4 - 8xx */ 457 u_int16_t device_id; /* PCI device ID */ 458 u_int16_t vendor_id; /* PCI vendor ID */ 459 u_int8_t bus_nr; /* PCI bus number */ 460 u_int8_t device_fn; /* PCI device/func # << 3 */ 461 u_int16_t word8; 462 u_int16_t flags; 463 #define NVRAM_SYM_HOST_F_SCAN_AT_BOOT 0x0001 464 u_int16_t io_port; /* PCI I/O address */ 465 } __packed host[4]; 466 467 /* Targets (8 bytes x 16) */ 468 struct nvram_symbios_target { 469 u_int8_t flags; 470 #define NVRAM_SYM_TARG_F_DISCONNECT_EN 0x0001 471 #define NVRAM_SYM_TARG_F_SCAN_AT_BOOT 0x0002 472 #define NVRAM_SYM_TARG_F_SCAN_LUNS 0x0004 473 #define NVRAM_SYM_TARG_F_TQ_EN 0x0008 474 u_int8_t rsvd; 475 u_int8_t bus_width; 476 u_int8_t sync_offset; /* 8, 16, etc. */ 477 u_int16_t sync_period; /* 4 * factor */ 478 u_int16_t timeout; 479 } __packed target[16]; 480 481 /* SCAM table (8 bytes x 4) */ 482 struct nvram_symbios_scam { 483 u_int16_t id; 484 u_int16_t method; 485 #define NVRAM_SYM_SCAM_DEFAULT_METHOD 0 486 #define NVRAM_SYM_SCAM_DONT_ASSIGN 1 487 #define NVRAM_SYM_SCAM_SET_SPECIFIC_ID 2 488 #define NVRAM_SYM_SCAM_USE_ORDER_GIVEN 3 489 u_int16_t status; 490 #define NVRAM_SYM_SCAM_UNKNOWN 0 491 #define NVRAM_SYM_SCAM_DEVICE_NOT_FOUND 1 492 #define NVRAM_SYM_SCAM_ID_NOT_SET 2 493 #define NVRAM_SYM_SCAM_ID_VALID 3 494 u_int8_t target_id; 495 u_int8_t rsvd; 496 } __packed scam[4]; 497 498 u_int8_t spare_devices[15 * 8]; 499 u_int8_t trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */ 500 } __packed; 501 502 #define SIOP_NVRAM_TEK_SIZE 64 503 #define SIOP_NVRAM_TEK_93c46_ADDRESS 0 504 #define SIOP_NVRAM_TEK_24c16_ADDRESS 0x40 505 506 #if 0 507 static const u_int8_t tekram_sync_table[16] __attribute__((__unused__)) = { 508 25, 31, 37, 43, 509 50, 62, 75, 125, 510 12, 15, 18, 21, 511 6, 7, 9, 10, 512 }; 513 514 struct nvram_tekram { 515 struct nvram_tekram_target { 516 u_int8_t flags; 517 #define NVRAM_TEK_TARG_F_PARITY_CHECK 0x01 518 #define NVRAM_TEK_TARG_F_SYNC_NEGO 0x02 519 #define NVRAM_TEK_TARG_F_DISCONNECT_EN 0x04 520 #define NVRAM_TEK_TARG_F_START_CMD 0x08 521 #define NVRAM_TEK_TARG_F_TQ_EN 0x10 522 #define NVRAM_TEK_TARG_F_WIDE_NEGO 0x20 523 u_int8_t sync_index; 524 u_int16_t word2; 525 } __packed target[16]; 526 u_int8_t host_id; 527 u_int8_t flags; 528 #define NVRAM_TEK_F_MORE_THAN_2_DRIVES 0x01 529 #define NVRAM_TEK_F_DRIVES_SUP_1G 0x02 530 #define NVRAM_TEK_F_RESET_ON_POWER_ON 0x04 531 #define NVRAM_TEK_F_ACTIVE_NEGATION 0x08 532 #define NVRAM_TEK_F_IMMEDIATE_SEEK 0x10 533 #define NVRAM_TEK_F_SCAN_LUNS 0x20 534 #define NVRAM_TEK_F_REMOVABLE_FLAGS 0xc0 /* 0 dis, 1 boot, 2 all */ 535 u_int8_t boot_delay_index; 536 u_int8_t max_tags_index; 537 u_int16_t flags1; 538 #define NVRAM_TEK_F_F2_F6_ENABLED 0x0001 539 u_int16_t spare[29]; 540 } __packed; 541 #endif 542