1 /* $OpenBSD: smc91cxx.c,v 1.32 2009/10/13 19:33:16 pirofti Exp $ */ 2 /* $NetBSD: smc91cxx.c,v 1.11 1998/08/08 23:51:41 mycroft Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Gardner Buchanan. 49 * 4. The name of Gardner Buchanan may not be used to endorse or promote 50 * products derived from this software without specific prior written 51 * permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 57 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 58 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 62 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 65 */ 66 67 /* 68 * Core driver for the SMC 91Cxx family of Ethernet chips. 69 * 70 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 71 * written for NetBSD/amiga by Michael Hitch. 72 */ 73 74 #include "bpfilter.h" 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/mbuf.h> 79 #include <sys/syslog.h> 80 #include <sys/socket.h> 81 #include <sys/device.h> 82 #include <sys/timeout.h> 83 #include <sys/kernel.h> 84 #include <sys/malloc.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_ether.h> 98 #include <netinet/in_systm.h> 99 #include <netinet/in_var.h> 100 #include <netinet/ip.h> 101 #endif 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include <dev/mii/mii_bitbang.h> 110 111 #include <dev/ic/smc91cxxreg.h> 112 #include <dev/ic/smc91cxxvar.h> 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 116 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 117 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 118 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 119 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 120 121 /* XXX Hardware padding doesn't work yet(?) */ 122 #define SMC91CXX_SW_PAD 123 124 const char *smc91cxx_idstrs[] = { 125 NULL, /* 0 */ 126 NULL, /* 1 */ 127 NULL, /* 2 */ 128 "SMC91C90/91C92", /* 3 */ 129 "SMC91C94/91C96", /* 4 */ 130 "SMC91C95", /* 5 */ 131 NULL, /* 6 */ 132 "SMC91C100", /* 7 */ 133 "SMC91C100FD", /* 8 */ 134 NULL, /* 9 */ 135 NULL, /* 10 */ 136 NULL, /* 11 */ 137 NULL, /* 12 */ 138 NULL, /* 13 */ 139 NULL, /* 14 */ 140 NULL, /* 15 */ 141 }; 142 143 /* Supported media types. */ 144 const int smc91cxx_media[] = { 145 IFM_ETHER|IFM_10_T, 146 IFM_ETHER|IFM_10_5, 147 }; 148 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 149 150 /* 151 * MII bit-bang glue. 152 */ 153 u_int32_t smc91cxx_mii_bitbang_read(struct device *); 154 void smc91cxx_mii_bitbang_write(struct device *, u_int32_t); 155 156 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 157 smc91cxx_mii_bitbang_read, 158 smc91cxx_mii_bitbang_write, 159 { 160 MR_MDO, /* MII_BIT_MDO */ 161 MR_MDI, /* MII_BIT_MDI */ 162 MR_MCLK, /* MII_BIT_MDC */ 163 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 164 0, /* MII_BIT_DIR_PHY_HOST */ 165 } 166 }; 167 168 struct cfdriver sm_cd = { 169 NULL, "sm", DV_IFNET 170 }; 171 172 /* MII callbacks */ 173 int smc91cxx_mii_readreg(struct device *, int, int); 174 void smc91cxx_mii_writereg(struct device *, int, int, int); 175 void smc91cxx_statchg(struct device *); 176 void smc91cxx_tick(void *); 177 178 int smc91cxx_mediachange(struct ifnet *); 179 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 180 181 int smc91cxx_set_media(struct smc91cxx_softc *, int); 182 183 void smc91cxx_read(struct smc91cxx_softc *); 184 void smc91cxx_reset(struct smc91cxx_softc *); 185 void smc91cxx_start(struct ifnet *); 186 void smc91cxx_resume(struct smc91cxx_softc *); 187 void smc91cxx_watchdog(struct ifnet *); 188 int smc91cxx_ioctl(struct ifnet *, u_long, caddr_t); 189 190 static __inline int ether_cmp(void *, void *); 191 static __inline int 192 ether_cmp(va, vb) 193 void *va, *vb; 194 { 195 u_int8_t *a = va; 196 u_int8_t *b = vb; 197 198 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 199 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 200 } 201 202 void 203 smc91cxx_attach(sc, myea) 204 struct smc91cxx_softc *sc; 205 u_int8_t *myea; 206 { 207 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 208 bus_space_tag_t bst = sc->sc_bst; 209 bus_space_handle_t bsh = sc->sc_bsh; 210 struct ifmedia *ifm = &sc->sc_mii.mii_media; 211 u_int32_t miicapabilities; 212 u_int16_t tmp; 213 int i, aui; 214 const char *idstr; 215 216 /* Make sure the chip is stopped. */ 217 smc91cxx_stop(sc); 218 219 SMC_SELECT_BANK(sc, 3); 220 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 221 sc->sc_chipid = RR_ID(tmp); 222 /* check magic number */ 223 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 224 idstr = NULL; 225 printf("%s: invalid BSR 0x%04x\n", sc->sc_dev.dv_xname, tmp); 226 } else 227 idstr = smc91cxx_idstrs[RR_ID(tmp)]; 228 #ifdef SMC_DEBUG 229 printf("\n%s: ", sc->sc_dev.dv_xname); 230 if (idstr != NULL) 231 printf("%s, ", idstr); 232 else 233 printf("unknown chip id %d, ", sc->sc_chipid); 234 printf("revision %d", RR_REV(tmp)); 235 #endif 236 237 /* Read the station address from the chip. */ 238 SMC_SELECT_BANK(sc, 1); 239 if (myea == NULL) { 240 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 241 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 242 sc->sc_arpcom.ac_enaddr[i + 1] = (tmp >>8) & 0xff; 243 sc->sc_arpcom.ac_enaddr[i] = tmp & 0xff; 244 } 245 } else { 246 bcopy(myea, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 247 } 248 249 printf(": address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 250 251 /* Initialize the ifnet structure. */ 252 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 253 ifp->if_softc = sc; 254 ifp->if_start = smc91cxx_start; 255 ifp->if_ioctl = smc91cxx_ioctl; 256 ifp->if_watchdog = smc91cxx_watchdog; 257 ifp->if_flags = 258 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 259 IFQ_SET_READY(&ifp->if_snd); 260 261 /* Attach the interface. */ 262 if_attach(ifp); 263 ether_ifattach(ifp); 264 265 /* 266 * Initialize our media structures and MII info. We will 267 * probe the MII if we are on the SMC91Cxx 268 */ 269 sc->sc_mii.mii_ifp = ifp; 270 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 271 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 272 sc->sc_mii.mii_statchg = smc91cxx_statchg; 273 ifmedia_init(ifm, 0, smc91cxx_mediachange, smc91cxx_mediastatus); 274 275 SMC_SELECT_BANK(sc, 1); 276 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 277 278 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 279 switch (sc->sc_chipid) { 280 case CHIP_91100: 281 /* 282 * The 91100 does not have full-duplex capabilities, 283 * even if the PHY does. 284 */ 285 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 286 /* FALLTHROUGH */ 287 case CHIP_91100FD: 288 if (tmp & CR_MII_SELECT) { 289 #ifdef SMC_DEBUG 290 printf("%s: default media MII\n", 291 sc->sc_dev.dv_xname); 292 #endif 293 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 294 MII_PHY_ANY, MII_OFFSET_ANY, 0); 295 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 296 ifmedia_add(&sc->sc_mii.mii_media, 297 IFM_ETHER|IFM_NONE, 0, NULL); 298 ifmedia_set(&sc->sc_mii.mii_media, 299 IFM_ETHER|IFM_NONE); 300 } else { 301 ifmedia_set(&sc->sc_mii.mii_media, 302 IFM_ETHER|IFM_AUTO); 303 } 304 sc->sc_flags |= SMC_FLAGS_HAS_MII; 305 break; 306 } 307 /* FALLTHROUGH */ 308 default: 309 aui = tmp & CR_AUI_SELECT; 310 #ifdef SMC_DEBUG 311 printf("%s: default media %s\n", sc->sc_dev.dv_xname, 312 aui ? "AUI" : "UTP"); 313 #endif 314 for (i = 0; i < NSMC91CxxMEDIA; i++) 315 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 316 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 317 break; 318 } 319 320 /* The attach is successful. */ 321 sc->sc_flags |= SMC_FLAGS_ATTACHED; 322 } 323 324 /* 325 * Change media according to request. 326 */ 327 int 328 smc91cxx_mediachange(ifp) 329 struct ifnet *ifp; 330 { 331 struct smc91cxx_softc *sc = ifp->if_softc; 332 333 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 334 } 335 336 int 337 smc91cxx_set_media(sc, media) 338 struct smc91cxx_softc *sc; 339 int media; 340 { 341 bus_space_tag_t bst = sc->sc_bst; 342 bus_space_handle_t bsh = sc->sc_bsh; 343 u_int16_t tmp; 344 345 /* 346 * If the interface is not currently powered on, just return. 347 * When it is enabled later, smc91cxx_init() will properly set 348 * up the media for us. 349 */ 350 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 351 return (0); 352 353 if (IFM_TYPE(media) != IFM_ETHER) 354 return (EINVAL); 355 356 if (sc->sc_flags & SMC_FLAGS_HAS_MII) 357 return (mii_mediachg(&sc->sc_mii)); 358 359 switch (IFM_SUBTYPE(media)) { 360 case IFM_10_T: 361 case IFM_10_5: 362 SMC_SELECT_BANK(sc, 1); 363 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 364 if (IFM_SUBTYPE(media) == IFM_10_5) 365 tmp |= CR_AUI_SELECT; 366 else 367 tmp &= ~CR_AUI_SELECT; 368 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 369 delay(20000); /* XXX is this needed? */ 370 break; 371 372 default: 373 return (EINVAL); 374 } 375 376 return (0); 377 } 378 379 /* 380 * Notify the world which media we're using. 381 */ 382 void 383 smc91cxx_mediastatus(ifp, ifmr) 384 struct ifnet *ifp; 385 struct ifmediareq *ifmr; 386 { 387 struct smc91cxx_softc *sc = ifp->if_softc; 388 bus_space_tag_t bst = sc->sc_bst; 389 bus_space_handle_t bsh = sc->sc_bsh; 390 u_int16_t tmp; 391 392 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 393 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 394 ifmr->ifm_status = 0; 395 return; 396 } 397 398 /* 399 * If we have MII, go ask the PHY what's going on. 400 */ 401 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 402 mii_pollstat(&sc->sc_mii); 403 ifmr->ifm_active = sc->sc_mii.mii_media_active; 404 ifmr->ifm_status = sc->sc_mii.mii_media_status; 405 return; 406 } 407 408 SMC_SELECT_BANK(sc, 1); 409 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 410 ifmr->ifm_active = 411 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 412 } 413 414 /* 415 * Reset and initialize the chip. 416 */ 417 void 418 smc91cxx_init(sc) 419 struct smc91cxx_softc *sc; 420 { 421 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 422 bus_space_tag_t bst = sc->sc_bst; 423 bus_space_handle_t bsh = sc->sc_bsh; 424 u_int16_t tmp; 425 int s, i; 426 427 s = splnet(); 428 429 /* 430 * This resets the registers mostly to defaults, but doesn't 431 * affect the EEPROM. After the reset cycle, we pause briefly 432 * for the chip to recover. 433 * 434 * XXX how long are we really supposed to delay? --thorpej 435 */ 436 SMC_SELECT_BANK(sc, 0); 437 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 438 delay(100); 439 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 440 delay(200); 441 442 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 443 444 /* Set the Ethernet address. */ 445 SMC_SELECT_BANK(sc, 1); 446 for (i = 0; i < ETHER_ADDR_LEN; i++ ) 447 bus_space_write_1(bst, bsh, IAR_ADDR0_REG_W + i, 448 sc->sc_arpcom.ac_enaddr[i]); 449 450 /* 451 * Set the control register to automatically release successfully 452 * transmitted packets (making the best use of our limited memory) 453 * and enable the EPH interrupt on certain TX errors. 454 */ 455 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 456 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 457 458 /* 459 * Reset the MMU and wait for it to be un-busy. 460 */ 461 SMC_SELECT_BANK(sc, 2); 462 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 463 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 464 /* XXX bound this loop! */ ; 465 466 /* 467 * Disable all interrupts. 468 */ 469 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 470 471 /* 472 * Set current media. 473 */ 474 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 475 476 /* 477 * Set the receive filter. We want receive enable and auto 478 * strip of CRC from received packet. If we are in promisc. mode, 479 * then set that bit as well. 480 * 481 * XXX Initialize multicast filter. For now, we just accept 482 * XXX all multicast. 483 */ 484 SMC_SELECT_BANK(sc, 0); 485 486 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 487 if (ifp->if_flags & IFF_PROMISC) 488 tmp |= RCR_PROMISC; 489 490 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 491 492 /* 493 * Set transmitter control to "enabled". 494 */ 495 tmp = TCR_ENABLE; 496 497 #ifndef SMC91CXX_SW_PAD 498 /* 499 * Enable hardware padding of transmitted packets. 500 * XXX doesn't work? 501 */ 502 tmp |= TCR_PAD_ENABLE; 503 #endif 504 505 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 506 507 /* 508 * Now, enable interrupts. 509 */ 510 SMC_SELECT_BANK(sc, 2); 511 512 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 513 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 514 515 /* Interface is now running, with no output active. */ 516 ifp->if_flags |= IFF_RUNNING; 517 ifp->if_flags &= ~IFF_OACTIVE; 518 519 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 520 /* Start the one second clock. */ 521 timeout_set(&sc->sc_mii_timeout, smc91cxx_tick, sc); 522 timeout_add_sec(&sc->sc_mii_timeout, 1); 523 } 524 525 /* 526 * Attempt to start any pending transmission. 527 */ 528 smc91cxx_start(ifp); 529 530 splx(s); 531 } 532 533 /* 534 * Start output on an interface. 535 * Must be called at splnet or interrupt level. 536 */ 537 void 538 smc91cxx_start(ifp) 539 struct ifnet *ifp; 540 { 541 struct smc91cxx_softc *sc = ifp->if_softc; 542 bus_space_tag_t bst = sc->sc_bst; 543 bus_space_handle_t bsh = sc->sc_bsh; 544 u_int len; 545 struct mbuf *m, *top; 546 u_int16_t length, npages; 547 u_int8_t packetno; 548 int timo, pad; 549 550 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 551 return; 552 553 again: 554 /* 555 * Peek at the next packet. 556 */ 557 IFQ_POLL(&ifp->if_snd, m); 558 if (m == NULL) 559 return; 560 561 /* 562 * Compute the frame length and set pad to give an overall even 563 * number of bytes. Below, we assume that the packet length 564 * is even. 565 */ 566 for (len = 0, top = m; m != NULL; m = m->m_next) 567 len += m->m_len; 568 pad = (len & 1); 569 570 /* 571 * We drop packets that are too large. Perhaps we should 572 * truncate them instead? 573 */ 574 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 575 printf("%s: large packet discarded\n", sc->sc_dev.dv_xname); 576 ifp->if_oerrors++; 577 IFQ_DEQUEUE(&ifp->if_snd, m); 578 m_freem(m); 579 goto readcheck; 580 } 581 582 #ifdef SMC91CXX_SW_PAD 583 /* 584 * Not using hardware padding; pad to ETHER_MIN_LEN. 585 */ 586 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 587 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 588 #endif 589 590 length = pad + len; 591 592 /* 593 * The MMU has a 256 byte page size. The MMU expects us to 594 * ask for "npages - 1". We include space for the status word, 595 * byte count, and control bytes in the allocation request. 596 */ 597 npages = (length + 6) >> 8; 598 599 /* 600 * Now allocate the memory. 601 */ 602 SMC_SELECT_BANK(sc, 2); 603 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 604 605 timo = MEMORY_WAIT_TIME; 606 do { 607 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 608 break; 609 delay(1); 610 } while (--timo); 611 612 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 613 614 if (packetno & ARR_FAILED || timo == 0) { 615 /* 616 * No transmit memory is available. Record the number 617 * of requestd pages and enable the allocation completion 618 * interrupt. Set up the watchdog timer in case we miss 619 * the interrupt. Mark the interface as active so that 620 * no one else attempts to transmit while we're allocating 621 * memory. 622 */ 623 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 624 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 625 626 ifp->if_timer = 5; 627 ifp->if_flags |= IFF_OACTIVE; 628 629 return; 630 } 631 632 /* 633 * We have a packet number - set the data window. 634 */ 635 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 636 637 /* 638 * Point to the beginning of the packet. 639 */ 640 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 641 642 /* 643 * Send the packet length (+6 for stats, length, and control bytes) 644 * and the status word (set to zeros). 645 */ 646 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 647 bus_space_write_1(bst, bsh, DATA_REG_B, (length + 6) & 0xff); 648 bus_space_write_1(bst, bsh, DATA_REG_B, ((length + 6) >> 8) & 0xff); 649 650 /* 651 * Get the packet from the kernel. This will include the Ethernet 652 * frame header, MAC address, etc. 653 */ 654 IFQ_DEQUEUE(&ifp->if_snd, m); 655 656 /* 657 * Push the packet out to the card. 658 */ 659 for (top = m; m != NULL; m = m->m_next) { 660 /* Words... */ 661 if (m->m_len > 1) 662 bus_space_write_multi_stream_2(bst, bsh, DATA_REG_W, 663 mtod(m, u_int16_t *), m->m_len >> 1); 664 665 /* ...and the remaining byte, if any. */ 666 if (m->m_len & 1) 667 bus_space_write_1(bst, bsh, DATA_REG_B, 668 *(u_int8_t *)(mtod(m, u_int8_t *) + (m->m_len - 1))); 669 } 670 671 #ifdef SMC91CXX_SW_PAD 672 /* 673 * Push out padding. 674 */ 675 while (pad > 1) { 676 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 677 pad -= 2; 678 } 679 if (pad) 680 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 681 #endif 682 683 /* 684 * Push out control byte and unused packet byte. The control byte 685 * is 0, meaning the packet is even lengthed and no special 686 * CRC handling is necessary. 687 */ 688 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 689 690 /* 691 * Enable transmit interrupts and let the chip go. Set a watchdog 692 * in case we miss the interrupt. 693 */ 694 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 695 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 696 IM_TX_INT | IM_TX_EMPTY_INT); 697 698 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 699 700 ifp->if_timer = 5; 701 702 #if NBPFILTER > 0 703 /* Hand off a copy to the bpf. */ 704 if (ifp->if_bpf) 705 bpf_mtap(ifp->if_bpf, top, BPF_DIRECTION_OUT); 706 #endif 707 708 ifp->if_opackets++; 709 m_freem(top); 710 711 readcheck: 712 /* 713 * Check for incoming pcakets. We don't want to overflow the small 714 * RX FIFO. If nothing has arrived, attempt to queue another 715 * transmit packet. 716 */ 717 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 718 goto again; 719 } 720 721 /* 722 * Interrupt service routine. 723 */ 724 int 725 smc91cxx_intr(arg) 726 void *arg; 727 { 728 struct smc91cxx_softc *sc = arg; 729 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 730 bus_space_tag_t bst = sc->sc_bst; 731 bus_space_handle_t bsh = sc->sc_bsh; 732 u_int8_t mask, interrupts, status; 733 u_int16_t packetno, tx_status, card_stats; 734 735 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 736 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 737 return (0); 738 739 SMC_SELECT_BANK(sc, 2); 740 741 /* 742 * Obtain the current interrupt mask. 743 */ 744 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 745 746 /* 747 * Get the set of interrupt which occurred and eliminate any 748 * which are not enabled. 749 */ 750 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 751 status = interrupts & mask; 752 753 /* Ours? */ 754 if (status == 0) 755 return (0); 756 757 /* 758 * It's ours; disable all interrupts while we process them. 759 */ 760 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 761 762 /* 763 * Receive overrun interrupts. 764 */ 765 if (status & IM_RX_OVRN_INT) { 766 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 767 ifp->if_ierrors++; 768 } 769 770 /* 771 * Receive interrupts. 772 */ 773 if (status & IM_RCV_INT) { 774 #if 1 /* DIAGNOSTIC */ 775 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 776 if (packetno & FIFO_REMPTY) { 777 printf("%s: receive interrupt on empty fifo\n", 778 sc->sc_dev.dv_xname); 779 goto out; 780 } else 781 #endif 782 smc91cxx_read(sc); 783 } 784 785 /* 786 * Memory allocation interrupts. 787 */ 788 if (status & IM_ALLOC_INT) { 789 /* Disable this interrupt. */ 790 mask &= ~IM_ALLOC_INT; 791 792 /* 793 * Release the just-allocated memory. We will reallocate 794 * it through the normal start logic. 795 */ 796 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 797 /* XXX bound this loop! */ ; 798 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 799 800 ifp->if_flags &= ~IFF_OACTIVE; 801 ifp->if_timer = 0; 802 } 803 804 /* 805 * Transmit complete interrupt. Handle transmission error messages. 806 * This will only be called on error condition because of AUTO RELEASE 807 * mode. 808 */ 809 if (status & IM_TX_INT) { 810 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 811 812 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 813 FIFO_TX_MASK; 814 815 /* 816 * Select this as the packet to read from. 817 */ 818 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 819 820 /* 821 * Position the pointer to the beginning of the packet. 822 */ 823 bus_space_write_2(bst, bsh, POINTER_REG_W, 824 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 825 826 /* 827 * Fetch the TX status word. This will be a copy of 828 * the EPH_STATUS_REG_W at the time of the transmission 829 * failure. 830 */ 831 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 832 833 if (tx_status & EPHSR_TX_SUC) 834 printf("%s: successful packet caused TX interrupt?!\n", 835 sc->sc_dev.dv_xname); 836 else 837 ifp->if_oerrors++; 838 839 if (tx_status & EPHSR_LATCOL) 840 ifp->if_collisions++; 841 842 /* 843 * Some of these errors disable the transmitter; reenable it. 844 */ 845 SMC_SELECT_BANK(sc, 0); 846 #ifdef SMC91CXX_SW_PAD 847 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 848 #else 849 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 850 TCR_ENABLE | TCR_PAD_ENABLE); 851 #endif 852 853 /* 854 * Kill the failed packet and wait for the MMU to unbusy. 855 */ 856 SMC_SELECT_BANK(sc, 2); 857 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 858 /* XXX bound this loop! */ ; 859 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 860 861 ifp->if_timer = 0; 862 } 863 864 /* 865 * Transmit underrun interrupts. We use this opportunity to 866 * update transmit statistics from the card. 867 */ 868 if (status & IM_TX_EMPTY_INT) { 869 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 870 871 /* Disable this interrupt. */ 872 mask &= ~IM_TX_EMPTY_INT; 873 874 SMC_SELECT_BANK(sc, 0); 875 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 876 877 /* Single collisions. */ 878 ifp->if_collisions += card_stats & ECR_COLN_MASK; 879 880 /* Multiple collisions. */ 881 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 882 883 SMC_SELECT_BANK(sc, 2); 884 885 ifp->if_timer = 0; 886 } 887 888 /* 889 * Other errors. Reset the interface. 890 */ 891 if (status & IM_EPH_INT) { 892 smc91cxx_stop(sc); 893 smc91cxx_init(sc); 894 } 895 896 /* 897 * Attempt to queue more packets for transmission. 898 */ 899 smc91cxx_start(ifp); 900 901 out: 902 /* 903 * Reenable the interrupts we wish to receive now that processing 904 * is complete. 905 */ 906 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 907 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 908 909 return (1); 910 } 911 912 /* 913 * Read a packet from the card and pass it up to the kernel. 914 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 915 */ 916 void 917 smc91cxx_read(sc) 918 struct smc91cxx_softc *sc; 919 { 920 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 921 bus_space_tag_t bst = sc->sc_bst; 922 bus_space_handle_t bsh = sc->sc_bsh; 923 struct mbuf *m; 924 u_int16_t status, packetno, packetlen; 925 u_int8_t *data; 926 927 again: 928 /* 929 * Set data pointer to the beginning of the packet. Since 930 * PTR_RCV is set, the packet number will be found automatically 931 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 932 */ 933 bus_space_write_2(bst, bsh, POINTER_REG_W, 934 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 935 936 /* 937 * First two words are status and packet length. 938 */ 939 status = bus_space_read_2(bst, bsh, DATA_REG_W); 940 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 941 942 /* 943 * The packet length includes 3 extra words: status, length, 944 * and an extra word that includes the control byte. 945 */ 946 packetlen -= 6; 947 948 /* 949 * Account for receive errors and discard. 950 */ 951 if (status & RS_ERRORS) { 952 ifp->if_ierrors++; 953 goto out; 954 } 955 956 /* 957 * Adjust for odd-length packet. 958 */ 959 if (status & RS_ODDFRAME) 960 packetlen++; 961 962 /* 963 * Allocate a header mbuf. 964 */ 965 MGETHDR(m, M_DONTWAIT, MT_DATA); 966 if (m == NULL) 967 goto out; 968 m->m_pkthdr.rcvif = ifp; 969 m->m_pkthdr.len = packetlen; 970 971 /* 972 * Always put the packet in a cluster. 973 * XXX should chain small mbufs if less than threshold. 974 */ 975 MCLGET(m, M_DONTWAIT); 976 if ((m->m_flags & M_EXT) == 0) { 977 m_freem(m); 978 ifp->if_ierrors++; 979 printf("%s: can't allocate cluster for incoming packet\n", 980 sc->sc_dev.dv_xname); 981 goto out; 982 } 983 984 /* 985 * Pull the packet off the interface. Make sure the payload 986 * is aligned. 987 */ 988 m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t) + 989 sizeof(struct ether_header)) - sizeof(struct ether_header); 990 991 data = mtod(m, u_int8_t *); 992 if (packetlen > 1) 993 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 994 (u_int16_t *)data, packetlen >> 1); 995 if (packetlen & 1) { 996 data += packetlen & ~1; 997 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 998 } 999 1000 ifp->if_ipackets++; 1001 1002 #if NBPFILTER > 0 1003 /* 1004 * Hand the packet off to bpf listeners. If there's a bpf listener, 1005 * we need to check if the packet is ours. 1006 */ 1007 if (ifp->if_bpf) 1008 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1009 #endif 1010 1011 m->m_pkthdr.len = m->m_len = packetlen; 1012 ether_input_mbuf(ifp, m); 1013 1014 out: 1015 /* 1016 * Tell the card to free the memory occupied by this packet. 1017 */ 1018 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1019 /* XXX bound this loop! */ ; 1020 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1021 1022 /* 1023 * Check for another packet. 1024 */ 1025 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1026 if (packetno & FIFO_REMPTY) 1027 return; 1028 goto again; 1029 } 1030 1031 /* 1032 * Process an ioctl request. 1033 */ 1034 int 1035 smc91cxx_ioctl(ifp, cmd, data) 1036 struct ifnet *ifp; 1037 u_long cmd; 1038 caddr_t data; 1039 { 1040 struct smc91cxx_softc *sc = ifp->if_softc; 1041 struct ifaddr *ifa = (struct ifaddr *)data; 1042 struct ifreq *ifr = (struct ifreq *)data; 1043 int s, error = 0; 1044 1045 s = splnet(); 1046 1047 switch (cmd) { 1048 case SIOCSIFADDR: 1049 if ((error = smc91cxx_enable(sc)) != 0) 1050 break; 1051 ifp->if_flags |= IFF_UP; 1052 switch (ifa->ifa_addr->sa_family) { 1053 #ifdef INET 1054 case AF_INET: 1055 smc91cxx_init(sc); 1056 arp_ifinit(&sc->sc_arpcom, ifa); 1057 break; 1058 #endif 1059 default: 1060 smc91cxx_init(sc); 1061 break; 1062 } 1063 break; 1064 1065 case SIOCSIFFLAGS: 1066 if ((ifp->if_flags & IFF_UP) == 0 && 1067 (ifp->if_flags & IFF_RUNNING) != 0) { 1068 /* 1069 * If interface is marked down and it is running, 1070 * stop it. 1071 */ 1072 smc91cxx_stop(sc); 1073 ifp->if_flags &= ~IFF_RUNNING; 1074 smc91cxx_disable(sc); 1075 } else if ((ifp->if_flags & IFF_UP) != 0 && 1076 (ifp->if_flags & IFF_RUNNING) == 0) { 1077 /* 1078 * If interface is marked up and it is stopped, 1079 * start it. 1080 */ 1081 if ((error = smc91cxx_enable(sc)) != 0) 1082 break; 1083 smc91cxx_init(sc); 1084 } else if ((ifp->if_flags & IFF_UP) != 0) { 1085 /* 1086 * Reset the interface to pick up changes in any 1087 * other flags that affect hardware registers. 1088 */ 1089 smc91cxx_reset(sc); 1090 } 1091 break; 1092 1093 case SIOCGIFMEDIA: 1094 case SIOCSIFMEDIA: 1095 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1096 break; 1097 1098 default: 1099 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1100 } 1101 1102 if (error == ENETRESET) { 1103 if (ifp->if_flags & IFF_RUNNING) 1104 smc91cxx_reset(sc); 1105 error = 0; 1106 } 1107 1108 splx(s); 1109 return (error); 1110 } 1111 1112 /* 1113 * Reset the interface. 1114 */ 1115 void 1116 smc91cxx_reset(sc) 1117 struct smc91cxx_softc *sc; 1118 { 1119 int s; 1120 1121 s = splnet(); 1122 smc91cxx_stop(sc); 1123 smc91cxx_init(sc); 1124 splx(s); 1125 } 1126 1127 /* 1128 * Watchdog timer. 1129 */ 1130 void 1131 smc91cxx_watchdog(ifp) 1132 struct ifnet *ifp; 1133 { 1134 struct smc91cxx_softc *sc = ifp->if_softc; 1135 1136 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1137 ++sc->sc_arpcom.ac_if.if_oerrors; 1138 1139 smc91cxx_reset(sc); 1140 } 1141 1142 /* 1143 * Stop output on the interface. 1144 */ 1145 void 1146 smc91cxx_stop(sc) 1147 struct smc91cxx_softc *sc; 1148 { 1149 bus_space_tag_t bst = sc->sc_bst; 1150 bus_space_handle_t bsh = sc->sc_bsh; 1151 1152 /* 1153 * Clear interrupt mask; disable all interrupts. 1154 */ 1155 SMC_SELECT_BANK(sc, 2); 1156 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1157 1158 /* 1159 * Disable transmitter and receiver. 1160 */ 1161 SMC_SELECT_BANK(sc, 0); 1162 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1163 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1164 1165 /* 1166 * Cancel watchdog timer. 1167 */ 1168 sc->sc_arpcom.ac_if.if_timer = 0; 1169 } 1170 1171 /* 1172 * Enable power on the interface. 1173 */ 1174 int 1175 smc91cxx_enable(sc) 1176 struct smc91cxx_softc *sc; 1177 { 1178 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1179 if ((*sc->sc_enable)(sc) != 0) { 1180 printf("%s: device enable failed\n", 1181 sc->sc_dev.dv_xname); 1182 return (EIO); 1183 } 1184 } 1185 1186 sc->sc_flags |= SMC_FLAGS_ENABLED; 1187 return (0); 1188 } 1189 1190 /* 1191 * Disable power on the interface. 1192 */ 1193 void 1194 smc91cxx_disable(sc) 1195 struct smc91cxx_softc *sc; 1196 { 1197 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1198 (*sc->sc_disable)(sc); 1199 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1200 } 1201 } 1202 1203 int 1204 smc91cxx_activate(self, act) 1205 struct device *self; 1206 int act; 1207 { 1208 #if 0 1209 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1210 #endif 1211 int rv = 0, s; 1212 1213 s = splnet(); 1214 switch (act) { 1215 case DVACT_ACTIVATE: 1216 break; 1217 1218 case DVACT_DEACTIVATE: 1219 #if 0 1220 if_deactivate(&sc->sc_ic.ic_if); 1221 #endif 1222 break; 1223 } 1224 splx(s); 1225 return(rv); 1226 } 1227 1228 int 1229 smc91cxx_detach(self, flags) 1230 struct device *self; 1231 int flags; 1232 { 1233 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1234 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1235 1236 /* Succeed now if there's no work to do. */ 1237 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1238 return(0); 1239 1240 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1241 smc91cxx_disable(sc); 1242 1243 /* smc91cxx_attach() never fails */ 1244 1245 /* Delete all media. */ 1246 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1247 1248 #if NBPFILTER > 0 1249 bpfdetach(ifp); 1250 #endif 1251 ether_ifdetach(ifp); 1252 if_detach(ifp); 1253 1254 return (0); 1255 } 1256 1257 u_int32_t 1258 smc91cxx_mii_bitbang_read(self) 1259 struct device *self; 1260 { 1261 struct smc91cxx_softc *sc = (void *) self; 1262 1263 /* We're already in bank 3. */ 1264 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1265 } 1266 1267 void 1268 smc91cxx_mii_bitbang_write(self, val) 1269 struct device *self; 1270 u_int32_t val; 1271 { 1272 struct smc91cxx_softc *sc = (void *) self; 1273 1274 /* We're already in bank 3. */ 1275 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1276 } 1277 1278 int 1279 smc91cxx_mii_readreg(self, phy, reg) 1280 struct device *self; 1281 int phy, reg; 1282 { 1283 struct smc91cxx_softc *sc = (void *) self; 1284 int val; 1285 1286 SMC_SELECT_BANK(sc, 3); 1287 1288 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1289 1290 SMC_SELECT_BANK(sc, 2); 1291 1292 return (val); 1293 } 1294 1295 void 1296 smc91cxx_mii_writereg(self, phy, reg, val) 1297 struct device *self; 1298 int phy, reg, val; 1299 { 1300 struct smc91cxx_softc *sc = (void *) self; 1301 1302 SMC_SELECT_BANK(sc, 3); 1303 1304 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1305 1306 SMC_SELECT_BANK(sc, 2); 1307 } 1308 1309 void 1310 smc91cxx_statchg(self) 1311 struct device *self; 1312 { 1313 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1314 bus_space_tag_t bst = sc->sc_bst; 1315 bus_space_handle_t bsh = sc->sc_bsh; 1316 int mctl; 1317 1318 SMC_SELECT_BANK(sc, 0); 1319 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1320 if (sc->sc_mii.mii_media_active & IFM_FDX) 1321 mctl |= TCR_SWFDUP; 1322 else 1323 mctl &= ~TCR_SWFDUP; 1324 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1325 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1326 } 1327 1328 /* 1329 * One second timer, used to tick the MII. 1330 */ 1331 void 1332 smc91cxx_tick(arg) 1333 void *arg; 1334 { 1335 struct smc91cxx_softc *sc = arg; 1336 int s; 1337 1338 #ifdef DIAGNOSTIC 1339 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1340 panic("smc91cxx_tick"); 1341 #endif 1342 1343 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1344 return; 1345 1346 s = splnet(); 1347 mii_tick(&sc->sc_mii); 1348 splx(s); 1349 1350 timeout_add_sec(&sc->sc_mii_timeout, 1); 1351 } 1352