1 /* $OpenBSD: tcic2.c,v 1.11 2014/07/12 18:48:17 tedu Exp $ */ 2 /* $NetBSD: tcic2.c,v 1.3 2000/01/13 09:38:17 joda Exp $ */ 3 4 #undef TCICDEBUG 5 6 /* 7 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 8 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Marc Horowitz. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/extent.h> 41 #include <sys/malloc.h> 42 #include <sys/kthread.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 50 #include <dev/ic/tcic2reg.h> 51 #include <dev/ic/tcic2var.h> 52 53 #ifdef TCICDEBUG 54 int tcic_debug = 1; 55 #define DPRINTF(arg) if (tcic_debug) printf arg; 56 #else 57 #define DPRINTF(arg) 58 #endif 59 60 /* 61 * Individual drivers will allocate their own memory and io regions. Memory 62 * regions must be a multiple of 4k, aligned on a 4k boundary. 63 */ 64 65 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 66 67 void tcic_attach_socket(struct tcic_handle *); 68 void tcic_init_socket(struct tcic_handle *); 69 70 int tcic_submatch(struct device *, void *, void *); 71 int tcic_print(void *arg, const char *pnp); 72 int tcic_intr_socket(struct tcic_handle *); 73 74 void tcic_attach_card(struct tcic_handle *); 75 void tcic_detach_card(struct tcic_handle *, int); 76 void tcic_deactivate_card(struct tcic_handle *); 77 78 void tcic_chip_do_mem_map(struct tcic_handle *, int); 79 void tcic_chip_do_io_map(struct tcic_handle *, int); 80 81 void tcic_create_event_thread(void *); 82 void tcic_event_thread(void *); 83 84 void tcic_queue_event(struct tcic_handle *, int); 85 86 struct cfdriver tcic_cd = { 87 NULL, "tcic", DV_DULL 88 }; 89 90 /* Map between irq numbers and internal representation */ 91 #if 1 92 int tcic_irqmap[] = 93 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 94 int tcic_valid_irqs = 0x4cf8; 95 #else 96 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 97 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 98 int tcic_valid_irqs = 0x4eb8; 99 #endif 100 101 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 102 int tcic_io_speed = 165; /* io access time in nanoseconds */ 103 104 /* 105 * Check various reserved and otherwise in their value restricted bits. 106 */ 107 int 108 tcic_check_reserved_bits(iot, ioh) 109 bus_space_tag_t iot; 110 bus_space_handle_t ioh; 111 { 112 int val, auxreg; 113 114 DPRINTF(("tcic: chkrsvd 1\n")); 115 /* R_ADDR bit 30:28 have a restricted range. */ 116 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 117 >> TCIC_SS_SHIFT; 118 if (val > 1) 119 return 0; 120 121 DPRINTF(("tcic: chkrsvd 2\n")); 122 /* R_SCTRL bits 6,2,1 are reserved. */ 123 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 124 if (val & TCIC_SCTRL_RSVD) 125 return 0; 126 127 DPRINTF(("tcic: chkrsvd 3\n")); 128 /* R_ICSR bit 2 must be same as bit 3. */ 129 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 130 if (((val >> 1) & 1) != ((val >> 2) & 1)) 131 return 0; 132 133 DPRINTF(("tcic: chkrsvd 4\n")); 134 /* R_IENA bits 7,2 are reserved. */ 135 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 136 if (val & TCIC_IENA_RSVD) 137 return 0; 138 139 DPRINTF(("tcic: chkrsvd 5\n")); 140 /* Some aux registers have reserved bits. */ 141 /* Which are we looking at? */ 142 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 143 & TCIC_AR_MASK; 144 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 145 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 146 switch (auxreg) { 147 case TCIC_AR_SYSCFG: 148 if (INVALID_AR_SYSCFG(val)) 149 return 0; 150 break; 151 case TCIC_AR_ILOCK: 152 if (INVALID_AR_ILOCK(val)) 153 return 0; 154 break; 155 case TCIC_AR_TEST: 156 if (INVALID_AR_TEST(val)) 157 return 0; 158 break; 159 } 160 161 DPRINTF(("tcic: chkrsvd 6\n")); 162 /* XXX fails if pcmcia bios is enabled. */ 163 /* Various bits set or not depending if in RESET mode. */ 164 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 165 if (val & TCIC_SCTRL_RESET) { 166 DPRINTF(("tcic: chkrsvd 7\n")); 167 /* Address bits must be 0 */ 168 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 169 if (val != 0) 170 return 0; 171 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 172 if (val != 0) 173 return 0; 174 DPRINTF(("tcic: chkrsvd 8\n")); 175 /* EDC bits must be 0 */ 176 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 177 if (val != 0) 178 return 0; 179 /* We're OK, so take it out of reset. XXX -chb */ 180 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 181 } 182 else { /* not in RESET mode */ 183 int omode; 184 int val1, val2; 185 DPRINTF(("tcic: chkrsvd 9\n")); 186 /* Programming timers must have expired. */ 187 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 188 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 189 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 190 return 0; 191 DPRINTF(("tcic: chkrsvd 10\n")); 192 /* 193 * EDC bits should change on read from data space 194 * as long as either EDC or the data are nonzero. 195 */ 196 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 197 & TCIC_ADDR2_INDREG) != 0) { 198 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 199 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 200 if (val1 | val2) { 201 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 202 if (val1 == val2) 203 return 0; 204 } 205 } 206 DPRINTF(("tcic: chkrsvd 11\n")); 207 /* XXX what does this check? -chb */ 208 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 209 val1 = omode ^ TCIC_AR_MASK; 210 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 211 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 212 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 213 if ( val1 != val2) 214 return 0; 215 } 216 /* All tests passed */ 217 return 1; 218 } 219 220 /* 221 * Read chip ID from AR_ILOCK in test mode. 222 */ 223 int 224 tcic_chipid(iot, ioh) 225 bus_space_tag_t iot; 226 bus_space_handle_t ioh; 227 { 228 unsigned id, otest; 229 230 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 231 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 232 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 233 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 234 id &= TCIC_ILOCKTEST_ID_MASK; 235 id >>= TCIC_ILOCKTEST_ID_SHFT; 236 237 /* clear up IRQs inside tcic. XXX -chb */ 238 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 239 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 240 241 return id; 242 } 243 /* 244 * Indicate whether the driver can handle the chip. 245 */ 246 int 247 tcic_chipid_known(id) 248 int id; 249 { 250 /* XXX only know how to handle DB86082 -chb */ 251 switch (id) { 252 case TCIC_CHIPID_DB86082_1: 253 case TCIC_CHIPID_DB86082A: 254 case TCIC_CHIPID_DB86082B_ES: 255 case TCIC_CHIPID_DB86082B: 256 case TCIC_CHIPID_DB86084_1: 257 case TCIC_CHIPID_DB86084A: 258 case TCIC_CHIPID_DB86184_1: 259 case TCIC_CHIPID_DB86072_1_ES: 260 case TCIC_CHIPID_DB86072_1: 261 return 1; 262 } 263 264 return 0; 265 } 266 267 char * 268 tcic_chipid_to_string(id) 269 int id; 270 { 271 switch (id) { 272 case TCIC_CHIPID_DB86082_1: 273 return ("Databook DB86082"); 274 case TCIC_CHIPID_DB86082A: 275 return ("Databook DB86082A"); 276 case TCIC_CHIPID_DB86082B_ES: 277 return ("Databook DB86082B-es"); 278 case TCIC_CHIPID_DB86082B: 279 return ("Databook DB86082B"); 280 case TCIC_CHIPID_DB86084_1: 281 return ("Databook DB86084"); 282 case TCIC_CHIPID_DB86084A: 283 return ("Databook DB86084A"); 284 case TCIC_CHIPID_DB86184_1: 285 return ("Databook DB86184"); 286 case TCIC_CHIPID_DB86072_1_ES: 287 return ("Databook DB86072-es"); 288 case TCIC_CHIPID_DB86072_1: 289 return ("Databook DB86072"); 290 } 291 292 return ("Unknown controller"); 293 } 294 /* 295 * Return bitmask of IRQs that the chip can handle. 296 * XXX should be table driven. 297 */ 298 int 299 tcic_validirqs(chipid) 300 int chipid; 301 { 302 switch (chipid) { 303 case TCIC_CHIPID_DB86082_1: 304 case TCIC_CHIPID_DB86082A: 305 case TCIC_CHIPID_DB86082B_ES: 306 case TCIC_CHIPID_DB86082B: 307 case TCIC_CHIPID_DB86084_1: 308 case TCIC_CHIPID_DB86084A: 309 case TCIC_CHIPID_DB86184_1: 310 case TCIC_CHIPID_DB86072_1_ES: 311 case TCIC_CHIPID_DB86072_1: 312 return tcic_valid_irqs; 313 } 314 return 0; 315 } 316 317 void 318 tcic_attach(sc) 319 struct tcic_softc *sc; 320 { 321 int i, reg; 322 323 /* set more chipset-dependent parameters in the softc. */ 324 switch (sc->chipid) { 325 case TCIC_CHIPID_DB86084_1: 326 case TCIC_CHIPID_DB86084A: 327 case TCIC_CHIPID_DB86184_1: 328 sc->pwrena = TCIC_PWR_ENA; 329 break; 330 default: 331 sc->pwrena = 0; 332 break; 333 } 334 335 /* set up global config registers */ 336 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 337 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 338 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 339 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 340 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 341 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 342 reg |= TCIC_ILOCK_HOLD_CCLK; 343 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 344 345 /* the TCIC has two sockets */ 346 /* XXX should i check for actual presence of sockets? -chb */ 347 for (i = 0; i < TCIC_NSLOTS; i++) { 348 sc->handle[i].sc = sc; 349 sc->handle[i].sock = i; 350 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 351 sc->handle[i].memwins 352 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 353 } 354 355 /* establish the interrupt */ 356 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 357 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 358 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 359 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 360 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 361 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 362 363 /* XXX block interrupts? */ 364 365 for (i = 0; i < TCIC_NSLOTS; i++) { 366 /* XXX make more clear what happens here -chb */ 367 tcic_sel_sock(&sc->handle[i]); 368 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 369 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 370 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 371 #if 1 /* XXX explain byte routing issue */ 372 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 373 #else 374 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 375 #endif 376 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 377 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 378 reg &= ~TCIC_SYSCFG_AUTOBUSY; 379 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 380 SIMPLEQ_INIT(&sc->handle[i].events); 381 } 382 383 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 384 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 385 printf("%s: %s has ", sc->dev.dv_xname, 386 tcic_chipid_to_string(sc->chipid)); 387 388 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 389 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 390 printf("sockets A and B\n"); 391 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 392 printf("socket A only\n"); 393 else 394 printf("socket B only\n"); 395 396 } 397 } 398 399 void 400 tcic_attach_sockets(sc) 401 struct tcic_softc *sc; 402 { 403 int i; 404 405 for (i = 0; i < TCIC_NSLOTS; i++) 406 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 407 tcic_attach_socket(&sc->handle[i]); 408 } 409 410 void 411 tcic_attach_socket(h) 412 struct tcic_handle *h; 413 { 414 struct pcmciabus_attach_args paa; 415 416 /* initialize the rest of the handle */ 417 418 h->shutdown = 0; 419 h->memalloc = 0; 420 h->ioalloc = 0; 421 h->ih_irq = 0; 422 423 /* now, config one pcmcia device per socket */ 424 425 paa.paa_busname = "pcmcia"; 426 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 427 paa.pch = (pcmcia_chipset_handle_t) h; 428 paa.iobase = h->sc->iobase; 429 paa.iosize = h->sc->iosize; 430 431 h->pcmcia = config_found_sm(&h->sc->dev, &paa, tcic_print, 432 tcic_submatch); 433 434 /* if there's actually a pcmcia device attached, initialize the slot */ 435 436 if (h->pcmcia) 437 tcic_init_socket(h); 438 else 439 h->flags &= ~TCIC_FLAG_SOCKETP; 440 } 441 442 void 443 tcic_create_event_thread(arg) 444 void *arg; 445 { 446 struct tcic_handle *h = arg; 447 char name[MAXCOMLEN+1]; 448 const char *cs; 449 450 switch (h->sock) { 451 case 0: 452 cs = "0"; 453 break; 454 case 1: 455 cs = "1"; 456 break; 457 default: 458 panic("tcic_create_event_thread: unknown tcic socket"); 459 } 460 461 snprintf(name, sizeof name, "%s,%s", h->sc->dev.dv_xname, cs); 462 if (kthread_create(tcic_event_thread, h, &h->event_thread, name)) { 463 printf("%s: unable to create event thread for sock 0x%02x\n", 464 h->sc->dev.dv_xname, h->sock); 465 panic("tcic_create_event_thread"); 466 } 467 } 468 469 void 470 tcic_event_thread(arg) 471 void *arg; 472 { 473 struct tcic_handle *h = arg; 474 struct tcic_event *pe; 475 int s; 476 477 while (h->shutdown == 0) { 478 s = splhigh(); 479 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 480 splx(s); 481 (void) tsleep(&h->events, PWAIT, "tcicev", 0); 482 continue; 483 } 484 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 485 splx(s); 486 487 switch (pe->pe_type) { 488 case TCIC_EVENT_INSERTION: 489 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 490 tcic_attach_card(h); 491 break; 492 493 case TCIC_EVENT_REMOVAL: 494 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 495 tcic_detach_card(h, DETACH_FORCE); 496 break; 497 498 default: 499 panic("tcic_event_thread: unknown event %d", 500 pe->pe_type); 501 } 502 free(pe, M_TEMP, 0); 503 } 504 505 h->event_thread = NULL; 506 507 /* In case parent is waiting for us to exit. */ 508 wakeup(h->sc); 509 510 kthread_exit(0); 511 } 512 513 514 void 515 tcic_init_socket(h) 516 struct tcic_handle *h; 517 { 518 int reg; 519 520 /* select this socket's config registers */ 521 tcic_sel_sock(h); 522 523 /* set up the socket to interrupt on card detect */ 524 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 525 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 526 527 /* enable CD irq in R_IENA */ 528 reg = tcic_read_2(h, TCIC_R_IENA); 529 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 530 531 /* if there's a card there, then attach it. also save sstat */ 532 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 533 if (reg & TCIC_SSTAT_CD) 534 tcic_attach_card(h); 535 } 536 537 int 538 tcic_submatch(parent, match, aux) 539 struct device *parent; 540 void *match; 541 void *aux; 542 { 543 struct cfdata *cf = match; 544 545 struct pcmciabus_attach_args *paa = aux; 546 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 547 548 switch (h->sock) { 549 case 0: 550 if (cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 551 -1 /* PCMCIABUSCF_CONTROLLER_DEFAULT */ && 552 cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 0) 553 return 0; 554 if (cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 555 -1 /* PCMCIABUSCF_SOCKET_DEFAULT */ && 556 cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 0) 557 return 0; 558 559 break; 560 case 1: 561 if (cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 562 -1 /* PCMCIABUSCF_CONTROLLER_DEFAULT */ && 563 cf->cf_loc[0 /* PCMCIABUSCF_CONTROLLER */] != 0) 564 return 0; 565 if (cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 566 -1 /* PCMCIABUSCF_SOCKET_DEFAULT */ && 567 cf->cf_loc[1 /* PCMCIABUSCF_SOCKET */] != 1) 568 return 0; 569 570 break; 571 default: 572 panic("unknown tcic socket"); 573 } 574 575 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 576 } 577 578 int 579 tcic_print(arg, pnp) 580 void *arg; 581 const char *pnp; 582 { 583 struct pcmciabus_attach_args *paa = arg; 584 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 585 586 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 587 if (pnp) 588 printf("pcmcia at %s", pnp); 589 590 switch (h->sock) { 591 case 0: 592 printf(" socket 0"); 593 break; 594 case 1: 595 printf(" socket 1"); 596 break; 597 default: 598 panic("unknown tcic socket"); 599 } 600 return (UNCONF); 601 } 602 603 int 604 tcic_intr(arg) 605 void *arg; 606 { 607 struct tcic_softc *sc = arg; 608 int i, ret = 0; 609 610 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 611 612 for (i = 0; i < TCIC_NSLOTS; i++) 613 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 614 ret += tcic_intr_socket(&sc->handle[i]); 615 616 return (ret ? 1 : 0); 617 } 618 619 int 620 tcic_intr_socket(h) 621 struct tcic_handle *h; 622 { 623 int icsr, rv; 624 625 rv = 0; 626 tcic_sel_sock(h); 627 icsr = tcic_read_1(h, TCIC_R_ICSR); 628 629 DPRINTF(("%s: %d icsr: 0x%02x \n", h->sc->dev.dv_xname, h->sock, icsr)); 630 631 /* XXX or should the next three be handled in tcic_intr? -chb */ 632 if (icsr & TCIC_ICSR_PROGTIME) { 633 DPRINTF(("%s: %02x PROGTIME\n", h->sc->dev.dv_xname, h->sock)); 634 rv = 1; 635 } 636 if (icsr & TCIC_ICSR_ILOCK) { 637 DPRINTF(("%s: %02x ILOCK\n", h->sc->dev.dv_xname, h->sock)); 638 rv = 1; 639 } 640 if (icsr & TCIC_ICSR_ERR) { 641 DPRINTF(("%s: %02x ERR\n", h->sc->dev.dv_xname, h->sock)); 642 rv = 1; 643 } 644 if (icsr & TCIC_ICSR_CDCHG) { 645 int sstat, delta; 646 647 /* compute what changed since last interrupt */ 648 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 649 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 650 delta = h->sstat ^ sstat; 651 h->sstat = sstat; 652 653 if (delta) 654 rv = 1; 655 656 DPRINTF(("%s: %02x CDCHG %x\n", h->sc->dev.dv_xname, h->sock, 657 delta)); 658 659 /* 660 * XXX This should probably schedule something to happen 661 * after the interrupt handler completes 662 */ 663 664 if (delta & TCIC_SSTAT_CD) { 665 if (sstat & TCIC_SSTAT_CD) { 666 if (!(h->flags & TCIC_FLAG_CARDP)) { 667 DPRINTF(("%s: enqueuing INSERTION event\n", 668 h->sc->dev.dv_xname)); 669 tcic_queue_event(h, TCIC_EVENT_INSERTION); 670 } 671 } else { 672 if (h->flags & TCIC_FLAG_CARDP) { 673 /* Deactivate the card now. */ 674 DPRINTF(("%s: deactivating card\n", 675 h->sc->dev.dv_xname)); 676 tcic_deactivate_card(h); 677 678 DPRINTF(("%s: enqueuing REMOVAL event\n", 679 h->sc->dev.dv_xname)); 680 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 681 } 682 } 683 } 684 if (delta & TCIC_SSTAT_RDY) { 685 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 686 /* shouldn't happen */ 687 } 688 if (delta & TCIC_SSTAT_LBAT1) { 689 DPRINTF(("%s: %02x LBAT1\n", h->sc->dev.dv_xname, h->sock)); 690 } 691 if (delta & TCIC_SSTAT_LBAT2) { 692 DPRINTF(("%s: %02x LBAT2\n", h->sc->dev.dv_xname, h->sock)); 693 } 694 if (delta & TCIC_SSTAT_WP) { 695 DPRINTF(("%s: %02x WP\n", h->sc->dev.dv_xname, h->sock)); 696 } 697 } 698 return rv; 699 } 700 701 void 702 tcic_queue_event(h, event) 703 struct tcic_handle *h; 704 int event; 705 { 706 struct tcic_event *pe; 707 int s; 708 709 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 710 if (pe == NULL) 711 panic("tcic_queue_event: can't allocate event"); 712 713 pe->pe_type = event; 714 s = splhigh(); 715 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 716 splx(s); 717 wakeup(&h->events); 718 } 719 void 720 tcic_attach_card(h) 721 struct tcic_handle *h; 722 { 723 DPRINTF(("tcic_attach_card\n")); 724 725 if (h->flags & TCIC_FLAG_CARDP) 726 panic("tcic_attach_card: already attached"); 727 728 /* call the MI attach function */ 729 730 pcmcia_card_attach(h->pcmcia); 731 732 h->flags |= TCIC_FLAG_CARDP; 733 } 734 735 void 736 tcic_detach_card(h, flags) 737 struct tcic_handle *h; 738 int flags; /* DETACH_* */ 739 { 740 DPRINTF(("tcic_detach_card\n")); 741 742 if (!(h->flags & TCIC_FLAG_CARDP)) 743 panic("tcic_detach_card: already detached"); 744 745 h->flags &= ~TCIC_FLAG_CARDP; 746 747 /* call the MI detach function */ 748 749 pcmcia_card_detach(h->pcmcia, flags); 750 751 } 752 753 void 754 tcic_deactivate_card(h) 755 struct tcic_handle *h; 756 { 757 int val, reg; 758 759 if (!(h->flags & TCIC_FLAG_CARDP)) 760 panic("tcic_deactivate_card: already detached"); 761 762 /* call the MI deactivate function */ 763 pcmcia_card_deactivate(h->pcmcia); 764 765 tcic_sel_sock(h); 766 767 /* XXX disable card detect resume and configuration reset??? */ 768 769 /* power down the socket */ 770 tcic_write_1(h, TCIC_R_PWR, 0); 771 772 /* reset the card XXX ? -chb */ 773 774 /* turn off irq's for this socket */ 775 reg = TCIC_IR_SCF1_N(h->sock); 776 val = tcic_read_ind_2(h, reg); 777 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 778 reg = TCIC_IR_SCF2_N(h->sock); 779 val = tcic_read_ind_2(h, reg); 780 tcic_write_ind_2(h, reg, 781 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 782 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 783 } 784 785 /* XXX the following routine may need to be rewritten. -chb */ 786 int 787 tcic_chip_mem_alloc(pch, size, pcmhp) 788 pcmcia_chipset_handle_t pch; 789 bus_size_t size; 790 struct pcmcia_mem_handle *pcmhp; 791 { 792 struct tcic_handle *h = (struct tcic_handle *) pch; 793 bus_space_handle_t memh; 794 bus_addr_t addr; 795 bus_size_t sizepg; 796 int i, mask, mhandle; 797 798 /* out of sc->memh, allocate as many pages as necessary */ 799 800 /* 801 * The TCIC can map memory only in sizes that are 802 * powers of two, aligned at the natural boundary for the size. 803 */ 804 i = tcic_log2((u_int)size); 805 if ((1<<i) < size) 806 i++; 807 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 808 809 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", size, sizepg)); 810 811 /* can't allocate that much anyway */ 812 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 813 return 1; 814 815 mask = (1 << sizepg) - 1; 816 817 addr = 0; /* XXX gcc -Wuninitialized */ 818 mhandle = 0; /* XXX gcc -Wuninitialized */ 819 820 /* XXX i should be initialised to always lay on boundary. -chb */ 821 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 822 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 823 if (bus_space_subregion(h->sc->memt, h->sc->memh, 824 i * TCIC_MEM_PAGESIZE, 825 sizepg * TCIC_MEM_PAGESIZE, &memh)) 826 return (1); 827 mhandle = mask << i; 828 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 829 h->sc->subregionmask &= ~(mhandle); 830 break; 831 } 832 } 833 834 if (i == (TCIC_MEM_PAGES + 1 - sizepg)) 835 return (1); 836 837 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 838 (u_long) size)); 839 840 pcmhp->memt = h->sc->memt; 841 pcmhp->memh = memh; 842 pcmhp->addr = addr; 843 pcmhp->size = size; 844 pcmhp->mhandle = mhandle; 845 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 846 847 return (0); 848 } 849 850 /* XXX the following routine may need to be rewritten. -chb */ 851 void 852 tcic_chip_mem_free(pch, pcmhp) 853 pcmcia_chipset_handle_t pch; 854 struct pcmcia_mem_handle *pcmhp; 855 { 856 struct tcic_handle *h = (struct tcic_handle *) pch; 857 858 h->sc->subregionmask |= pcmhp->mhandle; 859 } 860 861 void 862 tcic_chip_do_mem_map(h, win) 863 struct tcic_handle *h; 864 int win; 865 { 866 int reg, hwwin, wscnt; 867 868 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 869 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 870 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 871 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 872 (u_long)h->mem[win].offset)); 873 /* 874 * the even windows are used for socket 0, 875 * the odd ones for socket 1. 876 */ 877 hwwin = (win << 1) + h->sock; 878 879 /* the WR_MEXT register is MBZ */ 880 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 881 882 /* set the host base address and window size */ 883 if (h->mem[win].size2 <= 1) { 884 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 885 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 886 } else { 887 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 888 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 889 } 890 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 891 892 /* set the card address and address space */ 893 reg = 0; 894 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 895 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 896 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 897 win, hwwin, reg)); 898 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 899 900 /* set the MCTL register */ 901 /* must save WSCNT field in case this is a DB86082 rev 0 */ 902 /* XXX why can't I do the following two in one statement? */ 903 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 904 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 905 reg |= mem8 ? TCIC_MCTL_B8 : 0; 906 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 907 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 908 wscnt = tcic_ns2wscnt(h->mem[win].speed); 909 #else 910 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 911 #endif 912 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 913 /* 914 * this chip has the wait state count in window 915 * register 7 - hwwin. 916 */ 917 int reg2; 918 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 919 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 920 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 921 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 922 } else { 923 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 924 } 925 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 926 927 #ifdef TCICDEBUG 928 { 929 int r1, r2, r3; 930 931 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 932 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 933 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 934 935 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 936 win, hwwin, r1, r2, r3)); 937 } 938 #endif 939 } 940 941 /* XXX needs work */ 942 int 943 tcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 944 pcmcia_chipset_handle_t pch; 945 int kind; 946 bus_addr_t card_addr; 947 bus_size_t size; 948 struct pcmcia_mem_handle *pcmhp; 949 bus_size_t *offsetp; 950 int *windowp; 951 { 952 struct tcic_handle *h = (struct tcic_handle *) pch; 953 bus_addr_t busaddr; 954 long card_offset; 955 int i, win; 956 957 win = -1; 958 for (i = 0; i < h->memwins; i++) { 959 if ((h->memalloc & (1 << i)) == 0) { 960 win = i; 961 h->memalloc |= (1 << i); 962 break; 963 } 964 } 965 966 if (win == -1) 967 return (1); 968 969 *windowp = win; 970 971 /* XXX this is pretty gross */ 972 973 if (h->sc->memt != pcmhp->memt) 974 panic("tcic_chip_mem_map memt is bogus"); 975 976 busaddr = pcmhp->addr; 977 978 /* 979 * compute the address offset to the pcmcia address space for the 980 * tcic. this is intentionally signed. The masks and shifts below 981 * will cause TRT to happen in the tcic registers. Deal with making 982 * sure the address is aligned, and return the alignment offset. 983 */ 984 985 *offsetp = card_addr % TCIC_MEM_ALIGN; 986 card_addr -= *offsetp; 987 988 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 989 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 990 (u_long) card_addr)); 991 992 /* XXX we can't use size. -chb */ 993 /* 994 * include the offset in the size, and decrement size by one, since 995 * the hw wants start/stop 996 */ 997 size += *offsetp - 1; 998 999 card_offset = (((long) card_addr) - ((long) busaddr)); 1000 1001 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 1002 win, (u_long)card_offset)); 1003 1004 h->mem[win].addr = busaddr; 1005 h->mem[win].size = size; 1006 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 1007 h->mem[win].offset = card_offset; 1008 h->mem[win].kind = kind; 1009 1010 tcic_chip_do_mem_map(h, win); 1011 1012 return (0); 1013 } 1014 1015 void 1016 tcic_chip_mem_unmap(pch, window) 1017 pcmcia_chipset_handle_t pch; 1018 int window; 1019 { 1020 struct tcic_handle *h = (struct tcic_handle *) pch; 1021 int reg, hwwin; 1022 1023 if (window >= h->memwins) 1024 panic("tcic_chip_mem_unmap: window out of range"); 1025 1026 hwwin = (window << 1) + h->sock; 1027 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 1028 reg &= ~TCIC_MCTL_ENA; 1029 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 1030 1031 h->memalloc &= ~(1 << window); 1032 } 1033 1034 int 1035 tcic_chip_io_alloc(pch, start, size, align, pcihp) 1036 pcmcia_chipset_handle_t pch; 1037 bus_addr_t start; 1038 bus_size_t size; 1039 bus_size_t align; 1040 struct pcmcia_io_handle *pcihp; 1041 { 1042 struct tcic_handle *h = (struct tcic_handle *) pch; 1043 bus_space_tag_t iot; 1044 bus_space_handle_t ioh; 1045 bus_addr_t ioaddr; 1046 int size2, flags = 0; 1047 1048 /* 1049 * Allocate some arbitrary I/O space. 1050 */ 1051 1052 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 1053 (u_long) start, (u_long) size, (u_long) align)); 1054 /* 1055 * The TCIC can map I/O space only in sizes that are 1056 * powers of two, aligned at the natural boundary for the size. 1057 */ 1058 size2 = tcic_log2((u_int)size); 1059 if ((1 << size2) < size) 1060 size2++; 1061 /* can't allocate that much anyway */ 1062 if (size2 > 16) /* XXX 64K -chb */ 1063 return 1; 1064 if (align) { 1065 if ((1 << size2) != align) 1066 return 1; /* not suitably aligned */ 1067 } else { 1068 align = 1 << size2; /* no alignment given, make it natural */ 1069 } 1070 if (start & (align - 1)) 1071 return 1; /* not suitably aligned */ 1072 1073 iot = h->sc->iot; 1074 1075 if (start) { 1076 ioaddr = start; 1077 if (bus_space_map(iot, start, size, 0, &ioh)) 1078 return (1); 1079 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 1080 (u_long) ioaddr, (u_long) size)); 1081 } else { 1082 flags |= PCMCIA_IO_ALLOCATED; 1083 if (bus_space_alloc(iot, h->sc->iobase, 1084 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 1085 &ioaddr, &ioh)) 1086 return (1); 1087 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 1088 (u_long) ioaddr, (u_long) size)); 1089 } 1090 1091 pcihp->iot = iot; 1092 pcihp->ioh = ioh; 1093 pcihp->addr = ioaddr; 1094 pcihp->size = size; 1095 pcihp->flags = flags; 1096 1097 return (0); 1098 } 1099 1100 void 1101 tcic_chip_io_free(pch, pcihp) 1102 pcmcia_chipset_handle_t pch; 1103 struct pcmcia_io_handle *pcihp; 1104 { 1105 bus_space_tag_t iot = pcihp->iot; 1106 bus_space_handle_t ioh = pcihp->ioh; 1107 bus_size_t size = pcihp->size; 1108 1109 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1110 bus_space_free(iot, ioh, size); 1111 else 1112 bus_space_unmap(iot, ioh, size); 1113 } 1114 1115 static int tcic_iowidth_map[] = 1116 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1117 1118 void 1119 tcic_chip_do_io_map(h, win) 1120 struct tcic_handle *h; 1121 int win; 1122 { 1123 int reg, size2, iotiny, wbase, hwwin, wscnt; 1124 1125 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1126 win, (long) h->io[win].addr, (long) h->io[win].size, 1127 h->io[win].width * 8)); 1128 1129 /* 1130 * the even windows are used for socket 0, 1131 * the odd ones for socket 1. 1132 */ 1133 hwwin = (win << 1) + h->sock; 1134 1135 /* set the WR_BASE register */ 1136 /* XXX what if size isn't power of 2? -chb */ 1137 size2 = tcic_log2((u_int)h->io[win].size); 1138 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1139 if (size2 < 1) { 1140 iotiny = TCIC_ICTL_TINY; 1141 wbase = h->io[win].addr; 1142 } else { 1143 iotiny = 0; 1144 /* XXX we should do better -chb */ 1145 wbase = h->io[win].addr | (1 << (size2 - 1)); 1146 } 1147 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1148 1149 /* set the WR_ICTL register */ 1150 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1151 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1152 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1153 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1154 reg |= TCIC_ICTL_PASS16; 1155 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1156 wscnt = tcic_ns2wscnt(h->io[win].speed); 1157 #else 1158 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1159 #endif 1160 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1161 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1162 1163 #ifdef TCICDEBUG 1164 { 1165 int r1, r2; 1166 1167 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1168 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1169 1170 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1171 win, hwwin, r1, r2)); 1172 } 1173 #endif 1174 } 1175 1176 int 1177 tcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1178 pcmcia_chipset_handle_t pch; 1179 int width; 1180 bus_addr_t offset; 1181 bus_size_t size; 1182 struct pcmcia_io_handle *pcihp; 1183 int *windowp; 1184 { 1185 struct tcic_handle *h = (struct tcic_handle *) pch; 1186 bus_addr_t ioaddr = pcihp->addr + offset; 1187 int i, win; 1188 #ifdef TCICDEBUG 1189 static char *width_names[] = { "auto", "io8", "io16" }; 1190 #endif 1191 1192 /* XXX Sanity check offset/size. */ 1193 1194 win = -1; 1195 for (i = 0; i < TCIC_IO_WINS; i++) { 1196 if ((h->ioalloc & (1 << i)) == 0) { 1197 win = i; 1198 h->ioalloc |= (1 << i); 1199 break; 1200 } 1201 } 1202 1203 if (win == -1) 1204 return (1); 1205 1206 *windowp = win; 1207 1208 /* XXX this is pretty gross */ 1209 1210 if (h->sc->iot != pcihp->iot) 1211 panic("tcic_chip_io_map iot is bogus"); 1212 1213 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1214 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1215 1216 /* XXX wtf is this doing here? */ 1217 1218 printf(" port 0x%lx", (u_long) ioaddr); 1219 if (size > 1) 1220 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1221 1222 h->io[win].addr = ioaddr; 1223 h->io[win].size = size; 1224 h->io[win].width = width; 1225 1226 tcic_chip_do_io_map(h, win); 1227 1228 return (0); 1229 } 1230 1231 void 1232 tcic_chip_io_unmap(pch, window) 1233 pcmcia_chipset_handle_t pch; 1234 int window; 1235 { 1236 struct tcic_handle *h = (struct tcic_handle *) pch; 1237 int reg, hwwin; 1238 1239 if (window >= TCIC_IO_WINS) 1240 panic("tcic_chip_io_unmap: window out of range"); 1241 1242 hwwin = (window << 1) + h->sock; 1243 reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1244 reg &= ~TCIC_ICTL_ENA; 1245 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1246 1247 h->ioalloc &= ~(1 << window); 1248 } 1249 1250 void 1251 tcic_chip_socket_enable(pch) 1252 pcmcia_chipset_handle_t pch; 1253 { 1254 struct tcic_handle *h = (struct tcic_handle *) pch; 1255 int cardtype, reg, win; 1256 1257 tcic_sel_sock(h); 1258 1259 /* 1260 * power down the socket to reset it. 1261 * put card reset into high-z, put chip outputs to card into high-z 1262 */ 1263 1264 tcic_write_1(h, TCIC_R_PWR, 0); 1265 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1266 reg |= TCIC_ILOCK_CWAIT; 1267 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1268 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1269 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1270 1271 /* power up the socket */ 1272 1273 /* turn on VCC, turn of VPP */ 1274 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1275 if (h->sc->pwrena) /* this is a '84 type chip */ 1276 reg |= TCIC_PWR_VCC5V; 1277 tcic_write_1(h, TCIC_R_PWR, reg); 1278 delay(10000); 1279 1280 /* enable reset and wiggle it to reset the card */ 1281 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1282 reg |= TCIC_ILOCK_CRESENA; 1283 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1284 /* XXX need bus_space_barrier here */ 1285 reg |= TCIC_ILOCK_CRESET; 1286 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1287 /* enable card signals */ 1288 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1289 delay(10); /* wait 10 us */ 1290 1291 /* clear the reset flag */ 1292 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1293 reg &= ~(TCIC_ILOCK_CRESET); 1294 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1295 1296 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1297 delay(20000); 1298 1299 /* wait for the chip to finish initializing */ 1300 tcic_wait_ready(h); 1301 1302 /* WWW */ 1303 /* zero out the address windows */ 1304 1305 /* writing to WR_MBASE_N disables the window */ 1306 for (win = 0; win < h->memwins; win++) { 1307 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win<<1)+h->sock), 0); 1308 } 1309 /* writing to WR_IBASE_N disables the window */ 1310 for (win = 0; win < TCIC_IO_WINS; win++) { 1311 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win<<1)+h->sock), 0); 1312 } 1313 1314 /* set the card type */ 1315 1316 cardtype = pcmcia_card_gettype(h->pcmcia); 1317 1318 #if 0 1319 reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1320 reg &= ~TCIC_SCF1_IRQ_MASK; 1321 #else 1322 reg = 0; 1323 #endif 1324 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1325 TCIC_SCF1_IOSTS : 0); 1326 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1327 reg &= ~TCIC_SCF1_IRQOD; 1328 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1329 1330 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1331 h->sc->dev.dv_xname, h->sock, 1332 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1333 1334 /* reinstall all the memory and io mappings */ 1335 1336 for (win = 0; win < h->memwins; win++) 1337 if (h->memalloc & (1 << win)) 1338 tcic_chip_do_mem_map(h, win); 1339 1340 for (win = 0; win < TCIC_IO_WINS; win++) 1341 if (h->ioalloc & (1 << win)) 1342 tcic_chip_do_io_map(h, win); 1343 } 1344 1345 void 1346 tcic_chip_socket_disable(pch) 1347 pcmcia_chipset_handle_t pch; 1348 { 1349 struct tcic_handle *h = (struct tcic_handle *) pch; 1350 int val; 1351 1352 DPRINTF(("tcic_chip_socket_disable\n")); 1353 1354 tcic_sel_sock(h); 1355 1356 /* disable interrupts */ 1357 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1358 val &= TCIC_SCF1_IRQ_MASK; 1359 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1360 1361 /* disable the output signals */ 1362 tcic_write_1(h, TCIC_R_SCTRL, 0); 1363 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1364 val &= ~TCIC_ILOCK_CRESENA; 1365 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1366 1367 /* power down the socket */ 1368 tcic_write_1(h, TCIC_R_PWR, 0); 1369 } 1370 1371 /* 1372 * XXX The following is Linux driver but doesn't match the table 1373 * in the manual. 1374 */ 1375 int 1376 tcic_ns2wscnt(ns) 1377 int ns; 1378 { 1379 if (ns < 14) { 1380 return 0; 1381 } else { 1382 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1383 } 1384 } 1385 1386 int 1387 tcic_log2(val) 1388 u_int val; 1389 { 1390 int i, l2; 1391 1392 l2 = i = 0; 1393 while (val) { 1394 if (val & 1) 1395 l2 = i; 1396 i++; 1397 val >>= 1; 1398 } 1399 return l2; 1400 } 1401