1 /* $OpenBSD: trm.c,v 1.33 2015/05/07 01:09:56 jsg Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.c 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * HISTORY: 13 * 14 * REV# DATE NAME DESCRIPTION 15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x 16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8 17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting 18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic 19 * ------------------------------------------------------------ 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions 23 * are met: 24 * 1. Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * 2. Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * 3. The name of the author may not be used to endorse or promote products 30 * derived from this software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * ------------------------------------------------------------ 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/buf.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 55 #include <scsi/scsi_all.h> 56 #include <scsi/scsiconf.h> 57 #include <scsi/scsi_message.h> 58 59 #include <dev/pci/pcidevs.h> 60 #include <dev/ic/trm.h> 61 62 /* #define TRM_DEBUG0 */ 63 64 void trm_minphys(struct buf *, struct scsi_link *); 65 66 void trm_initSRB(struct trm_scsi_req_q *); 67 68 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 69 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 70 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 71 72 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 73 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 74 75 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t); 76 77 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t); 78 79 void trm_scsi_cmd(struct scsi_xfer *); 80 81 void *trm_srb_alloc(void *); 82 83 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 84 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 85 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 86 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 87 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 88 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 89 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 90 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 91 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 92 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 93 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 94 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 95 96 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int); 97 98 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t); 99 100 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *); 101 void trm_srb_reinit (struct trm_softc *, struct trm_scsi_req_q *); 102 void trm_srb_free (void *, void *); 103 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *); 104 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *); 105 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *); 106 107 void trm_initAdapter (struct trm_softc *); 108 void trm_Disconnect (struct trm_softc *); 109 void trm_Reselect (struct trm_softc *); 110 void trm_GoingSRB_Done (struct trm_softc *, struct trm_dcb *); 111 void trm_ScsiRstDetect (struct trm_softc *); 112 void trm_ResetSCSIBus (struct trm_softc *); 113 void trm_reset (struct trm_softc *); 114 void trm_StartWaitingSRB (struct trm_softc *); 115 void trm_ResetAllDevParam(struct trm_softc *); 116 void trm_RecoverSRB (struct trm_softc *); 117 void trm_linkSRB (struct trm_softc *); 118 119 void trm_initACB(struct trm_softc *, int); 120 121 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t); 122 123 void trm_EnableMsgOut(struct trm_softc *, u_int8_t); 124 125 void trm_timeout(void *); 126 127 void trm_print_info(struct trm_softc *, struct trm_dcb *); 128 129 /* 130 * Define structures 131 */ 132 struct cfdriver trm_cd = { 133 NULL, "trm", DV_DULL 134 }; 135 136 struct scsi_adapter trm_switch = { 137 trm_scsi_cmd, 138 trm_minphys, 139 NULL, 140 NULL 141 }; 142 143 /* 144 * ------------------------------------------------------------ 145 * 146 * stateV = (void *) trm_SCSI_phase0[phase] 147 * 148 * ------------------------------------------------------------ 149 */ 150 static void *trm_SCSI_phase0[8] = { 151 trm_DataOutPhase0, /* phase:0 */ 152 trm_DataInPhase0, /* phase:1 */ 153 trm_Nop, /* phase:2 */ 154 trm_StatusPhase0, /* phase:3 */ 155 trm_Nop, /* phase:4 */ 156 trm_Nop, /* phase:5 */ 157 trm_MsgOutPhase0, /* phase:6 */ 158 trm_MsgInPhase0, /* phase:7 */ 159 }; 160 161 /* 162 * ------------------------------------------------------------ 163 * 164 * stateV = (void *) trm_SCSI_phase1[phase] 165 * 166 * ------------------------------------------------------------ 167 */ 168 static void *trm_SCSI_phase1[8] = { 169 trm_DataOutPhase1, /* phase:0 */ 170 trm_DataInPhase1, /* phase:1 */ 171 trm_CommandPhase1, /* phase:2 */ 172 trm_StatusPhase1, /* phase:3 */ 173 trm_Nop, /* phase:4 */ 174 trm_Nop, /* phase:5 */ 175 trm_MsgOutPhase1, /* phase:6 */ 176 trm_MsgInPhase1, /* phase:7 */ 177 }; 178 179 180 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 181 /* 182 *Fast20: 000 50ns, 20.0 Mbytes/s 183 * 001 75ns, 13.3 Mbytes/s 184 * 010 100ns, 10.0 Mbytes/s 185 * 011 125ns, 8.0 Mbytes/s 186 * 100 150ns, 6.6 Mbytes/s 187 * 101 175ns, 5.7 Mbytes/s 188 * 110 200ns, 5.0 Mbytes/s 189 * 111 250ns, 4.0 Mbytes/s 190 * 191 *Fast40: 000 25ns, 40.0 Mbytes/s 192 * 001 50ns, 20.0 Mbytes/s 193 * 010 75ns, 13.3 Mbytes/s 194 * 011 100ns, 10.0 Mbytes/s 195 * 100 125ns, 8.0 Mbytes/s 196 * 101 150ns, 6.6 Mbytes/s 197 * 110 175ns, 5.7 Mbytes/s 198 * 111 200ns, 5.0 Mbytes/s 199 */ 200 201 /* 202 * real period: 203 */ 204 u_int8_t trm_clock_period[8] = { 205 /* nanosecond divided by 4 */ 206 12, /* 48 ns 20 MB/sec */ 207 18, /* 72 ns 13.3 MB/sec */ 208 25, /* 100 ns 10.0 MB/sec */ 209 31, /* 124 ns 8.0 MB/sec */ 210 37, /* 148 ns 6.6 MB/sec */ 211 43, /* 172 ns 5.7 MB/sec */ 212 50, /* 200 ns 5.0 MB/sec */ 213 62 /* 248 ns 4.0 MB/sec */ 214 }; 215 216 /* 217 * ------------------------------------------------------------ 218 * Function : trm_srb_alloc 219 * Purpose : Get the first free SRB 220 * Inputs : 221 * Return : NULL or a free SCSI Request block 222 * ------------------------------------------------------------ 223 */ 224 void * 225 trm_srb_alloc(void *xsc) 226 { 227 struct trm_softc *sc = xsc; 228 struct trm_scsi_req_q *pSRB; 229 230 mtx_enter(&sc->sc_srb_mtx); 231 pSRB = TAILQ_FIRST(&sc->freeSRB); 232 if (pSRB != NULL) 233 TAILQ_REMOVE(&sc->freeSRB, pSRB, link); 234 mtx_leave(&sc->sc_srb_mtx); 235 236 #ifdef TRM_DEBUG0 237 printf("%s: trm_srb_alloc. pSRB = %p, next pSRB = %p\n", 238 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB)); 239 #endif 240 241 return pSRB; 242 } 243 244 /* 245 * ------------------------------------------------------------ 246 * Function : trm_RewaitSRB 247 * Purpose : Q back to pending Q 248 * Inputs : struct trm_dcb * - 249 * struct trm_scsi_req_q * - 250 * ------------------------------------------------------------ 251 */ 252 void 253 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 254 { 255 int intflag; 256 257 intflag = splbio(); 258 259 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 260 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 261 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 262 } 263 264 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 265 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 266 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 267 } 268 269 pSRB->SRBState = TRM_READY; 270 pSRB->TargetStatus = SCSI_OK; 271 pSRB->AdaptStatus = TRM_STATUS_GOOD; 272 273 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 274 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 275 276 splx(intflag); 277 } 278 279 /* 280 * ------------------------------------------------------------ 281 * Function : trm_StartWaitingSRB 282 * Purpose : If there is no active DCB then run robin through 283 * the DCB's to find the next waiting SRB 284 * and move it to the going list. 285 * Inputs : struct trm_softc * - 286 * ------------------------------------------------------------ 287 */ 288 void 289 trm_StartWaitingSRB(struct trm_softc *sc) 290 { 291 struct trm_scsi_req_q *pSRB, *next; 292 int intflag; 293 294 intflag = splbio(); 295 296 if ((sc->pActiveDCB != NULL) || 297 (TAILQ_EMPTY(&sc->waitingSRB)) || 298 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0) 299 goto out; 300 301 for (pSRB = TAILQ_FIRST(&sc->waitingSRB); pSRB != NULL; pSRB = next) { 302 next = TAILQ_NEXT(pSRB, link); 303 if (trm_StartSRB(sc, pSRB) == 0) { 304 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 305 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 306 pSRB->SRBFlag |= TRM_ON_GOING_SRB; 307 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link); 308 break; 309 } 310 } 311 312 out: 313 splx(intflag); 314 } 315 316 /* 317 * ------------------------------------------------------------ 318 * Function : trm_scsi_cmd 319 * Purpose : enqueues a SCSI command 320 * Inputs : 321 * Call By : GENERIC SCSI driver 322 * ------------------------------------------------------------ 323 */ 324 void 325 trm_scsi_cmd(struct scsi_xfer *xs) 326 { 327 struct trm_scsi_req_q *pSRB; 328 bus_space_handle_t ioh; 329 struct trm_softc *sc; 330 bus_space_tag_t iot; 331 struct trm_dcb *pDCB; 332 u_int8_t target, lun; 333 int i, error, intflag, timeout, xferflags; 334 335 target = xs->sc_link->target; 336 lun = xs->sc_link->lun; 337 338 sc = (struct trm_softc *)xs->sc_link->adapter_softc; 339 ioh = sc->sc_iohandle; 340 iot = sc->sc_iotag; 341 342 #ifdef TRM_DEBUG0 343 if ((xs->flags & SCSI_POLL) != 0) { 344 sc_print_addr(xs->sc_link); 345 printf("trm_scsi_cmd. sc = %p, xs = %p, opcode = 0x%02x\n", 346 sc, xs, lun, xs->cmd->opcode); 347 } 348 #endif 349 350 if (target >= TRM_MAX_TARGETS) { 351 sc_print_addr(xs->sc_link); 352 printf("target >= %d\n", TRM_MAX_TARGETS); 353 xs->error = XS_DRIVER_STUFFUP; 354 scsi_done(xs); 355 return; 356 } 357 if (lun >= TRM_MAX_LUNS) { 358 sc_print_addr(xs->sc_link); 359 printf("lun >= %d\n", TRM_MAX_LUNS); 360 xs->error = XS_DRIVER_STUFFUP; 361 scsi_done(xs); 362 return; 363 } 364 365 pDCB = sc->pDCB[target][lun]; 366 if (pDCB == NULL) { 367 /* Removed as a result of INQUIRY proving no device present */ 368 xs->error = XS_DRIVER_STUFFUP; 369 scsi_done(xs); 370 return; 371 } 372 373 xferflags = xs->flags; 374 if (xferflags & SCSI_RESET) { 375 #ifdef TRM_DEBUG0 376 sc_print_addr(xs->sc_link); 377 printf("trm_reset via SCSI_RESET\n"); 378 #endif 379 trm_reset(sc); 380 xs->error = XS_NOERROR; 381 scsi_done(xs); 382 return; 383 } 384 385 pSRB = xs->io; 386 trm_srb_reinit(sc, pSRB); 387 388 xs->error = XS_NOERROR; 389 xs->status = SCSI_OK; 390 xs->resid = 0; 391 392 intflag = splbio(); 393 394 /* 395 * BuildSRB(pSRB,pDCB); 396 */ 397 if (xs->datalen != 0) { 398 #ifdef TRM_DEBUG0 399 sc_print_addr(xs->sc_link); 400 printf("xs->datalen=%x\n", (u_int32_t)xs->datalen); 401 sc_print_addr(xs->sc_link); 402 printf("sc->sc_dmatag=0x%x\n", (u_int32_t)sc->sc_dmatag); 403 sc_print_addr(xs->sc_link); 404 printf("pSRB->dmamapxfer=0x%x\n", (u_int32_t)pSRB->dmamapxfer); 405 sc_print_addr(xs->sc_link); 406 printf("xs->data=0x%x\n", (u_int32_t)xs->data); 407 #endif 408 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer, 409 xs->data, xs->datalen, NULL, 410 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : 411 BUS_DMA_WAITOK)) != 0) { 412 sc_print_addr(xs->sc_link); 413 printf("DMA transfer map unable to load, error = %d\n", 414 error); 415 xs->error = XS_DRIVER_STUFFUP; 416 splx(intflag); 417 scsi_done(xs); 418 return; 419 } 420 421 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 422 0, pSRB->dmamapxfer->dm_mapsize, 423 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 424 425 /* 426 * Set up the scatter gather list 427 */ 428 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) { 429 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr; 430 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len; 431 } 432 pSRB->SRBTotalXferLength = xs->datalen; 433 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs; 434 } 435 436 pSRB->pSRBDCB = pDCB; 437 pSRB->xs = xs; 438 pSRB->ScsiCmdLen = xs->cmdlen; 439 440 memcpy(pSRB->CmdBlock, xs->cmd, xs->cmdlen); 441 442 timeout_set(&xs->stimeout, trm_timeout, pSRB); 443 444 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 445 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link); 446 trm_StartWaitingSRB(sc); 447 448 if ((xferflags & SCSI_POLL) == 0) { 449 timeout_add_msec(&xs->stimeout, xs->timeout); 450 splx(intflag); 451 return; 452 } 453 454 splx(intflag); 455 for (timeout = xs->timeout; timeout > 0; timeout--) { 456 intflag = splbio(); 457 trm_Interrupt(sc); 458 splx(intflag); 459 if (ISSET(xs->flags, ITSDONE)) 460 break; 461 DELAY(1000); 462 } 463 464 if (!ISSET(xs->flags, ITSDONE) && timeout == 0) 465 trm_timeout(pSRB); 466 467 scsi_done(xs); 468 } 469 470 /* 471 * ------------------------------------------------------------ 472 * Function : trm_ResetAllDevParam 473 * Purpose : 474 * Inputs : struct trm_softc * 475 * ------------------------------------------------------------ 476 */ 477 void 478 trm_ResetAllDevParam(struct trm_softc *sc) 479 { 480 struct trm_adapter_nvram *pEEpromBuf; 481 int target, quirks; 482 483 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 484 485 for (target = 0; target < TRM_MAX_TARGETS; target++) { 486 if (target == sc->sc_AdaptSCSIID || sc->pDCB[target][0] == NULL) 487 continue; 488 489 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0) 490 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS; 491 else if (sc->pDCB[target][0]->sc_link != NULL) 492 quirks = sc->pDCB[target][0]->sc_link->quirks; 493 494 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks); 495 } 496 } 497 498 /* 499 * ------------------------------------------------------------ 500 * Function : trm_ResetDevParam 501 * Purpose : 502 * Inputs : 503 * ------------------------------------------------------------ 504 */ 505 void 506 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks) 507 { 508 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 509 u_int8_t PeriodIndex; 510 const int target = pDCB->target; 511 512 pDCB->DCBFlag &= TRM_QUIRKS_VALID; 513 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE); 514 515 pDCB->SyncPeriod = 0; 516 pDCB->SyncOffset = 0; 517 pDCB->MaxNegoPeriod = 0; 518 519 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0; 520 521 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0)); 522 523 if (((quirks & SDEV_NOWIDE) == 0) && 524 (pDCB->DevMode & TRM_WIDE) && 525 ((sc->sc_config & HCC_WIDE_CARD) != 0)) 526 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT; 527 528 if (((quirks & SDEV_NOSYNC) == 0) && 529 ((pDCB->DevMode & TRM_SYNC) != 0)) { 530 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07; 531 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex]; 532 } 533 534 if (((quirks & SDEV_NOTAGS) == 0) && 535 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) && 536 ((pDCB->DevMode & TRM_DISCONNECT) != 0)) 537 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */ 538 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING; 539 540 trm_SetXferParams(sc, pDCB, 0); 541 } 542 543 /* 544 * ------------------------------------------------------------ 545 * Function : trm_RecoverSRB 546 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs 547 * Inputs : struct trm_softc * - 548 * ------------------------------------------------------------ 549 */ 550 void 551 trm_RecoverSRB(struct trm_softc *sc) 552 { 553 struct trm_scsi_req_q *pSRB; 554 555 /* ASSUME we are inside splbio()/splx() */ 556 557 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) { 558 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 559 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 560 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 561 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 562 } 563 } 564 565 /* 566 * ------------------------------------------------------------ 567 * Function : trm_reset 568 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip). 569 * Inputs : 570 * ------------------------------------------------------------ 571 */ 572 void 573 trm_reset (struct trm_softc *sc) 574 { 575 const bus_space_handle_t ioh = sc->sc_iohandle; 576 const bus_space_tag_t iot = sc->sc_iotag; 577 int i, intflag; 578 579 intflag = splbio(); 580 581 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 582 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 583 584 trm_ResetSCSIBus(sc); 585 for (i = 0; i < 500; i++) 586 DELAY(1000); 587 588 /* 589 * Enable all SCSI interrupts except EN_SCAM 590 */ 591 bus_space_write_1(iot, ioh, 592 TRM_S1040_SCSI_INTEN, 593 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 594 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 595 /* 596 * Enable DMA interrupt 597 */ 598 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 599 /* 600 * Clear DMA FIFO 601 */ 602 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO); 603 /* 604 * Clear SCSI FIFO 605 */ 606 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 607 608 trm_ResetAllDevParam(sc); 609 trm_GoingSRB_Done(sc, NULL); 610 sc->pActiveDCB = NULL; 611 612 /* 613 * RESET_DETECT, RESET_DONE, RESET_DEV 614 */ 615 sc->sc_Flag = 0; 616 trm_StartWaitingSRB(sc); 617 618 splx(intflag); 619 } 620 621 /* 622 * ------------------------------------------------------------ 623 * Function : trm_timeout 624 * Purpose : Prints a timeout message and aborts the timed out SCSI request 625 * Inputs : void * - A struct trm_scsi_req_q * structure pointer 626 * ------------------------------------------------------------ 627 */ 628 void 629 trm_timeout(void *arg1) 630 { 631 struct trm_scsi_req_q *pSRB; 632 struct scsi_xfer *xs; 633 struct trm_softc *sc; 634 635 pSRB = (struct trm_scsi_req_q *)arg1; 636 xs = pSRB->xs; 637 638 if (xs != NULL) { 639 sc = xs->sc_link->adapter_softc; 640 sc_print_addr(xs->sc_link); 641 printf("SCSI OpCode 0x%02x ", xs->cmd->opcode); 642 if (pSRB->SRBFlag & TRM_AUTO_REQSENSE) 643 printf("REQUEST SENSE "); 644 printf("timed out\n"); 645 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 646 trm_FinishSRB(sc, pSRB); 647 #ifdef TRM_DEBUG0 648 sc_print_addr(xs->sc_link); 649 printf("trm_reset via trm_timeout()\n"); 650 #endif 651 trm_reset(sc); 652 trm_StartWaitingSRB(sc); 653 } 654 } 655 656 /* 657 * ------------------------------------------------------------ 658 * Function : trm_StartSRB 659 * Purpose : Send the commands in the SRB to the device 660 * Inputs : struct trm_softc * - 661 * struct trm_scsi_req_q * - 662 * Return : 0 - SCSI processor is unoccupied 663 * 1 - SCSI processor is occupied with an SRB 664 * ------------------------------------------------------------ 665 */ 666 int 667 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 668 { 669 const bus_space_handle_t ioh = sc->sc_iohandle; 670 const bus_space_tag_t iot = sc->sc_iotag; 671 struct trm_dcb *pDCB = pSRB->pSRBDCB; 672 u_int32_t tag_mask; 673 u_int8_t tag_id, scsicommand; 674 675 #ifdef TRM_DEBUG0 676 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n", 677 sc->sc_device.dv_xname, sc, pDCB, pSRB); 678 #endif 679 /* 680 * If the queue is full or the SCSI processor has a pending interrupt 681 * then try again later. 682 */ 683 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) || (bus_space_read_2(iot, ioh, 684 TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT)) 685 return (1); 686 687 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 688 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target); 689 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 690 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 691 692 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) && 693 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) { 694 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID; 695 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks); 696 } 697 698 /* 699 * Flush FIFO 700 */ 701 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 702 703 sc->MsgCnt = 1; 704 sc->MsgBuf[0] = pDCB->IdentifyMsg; 705 if (((pSRB->xs->flags & SCSI_POLL) != 0) || 706 (pSRB->CmdBlock[0] == INQUIRY) || 707 (pSRB->CmdBlock[0] == REQUEST_SENSE)) 708 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG; 709 710 scsicommand = SCMD_SEL_ATN; 711 712 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) { 713 scsicommand = SCMD_SEL_ATNSTOP; 714 pSRB->SRBState = TRM_MSGOUT; 715 716 } else if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) == 0) { 717 pDCB->DCBFlag |= TRM_QUEUE_FULL; 718 719 } else if ((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) { 720 if (pSRB->TagNumber == TRM_NO_TAG) { 721 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1) 722 if ((tag_mask & pDCB->TagMask) == 0) { 723 pDCB->TagMask |= tag_mask; 724 pSRB->TagNumber = tag_id; 725 break; 726 } 727 728 if (tag_id >= 32) { 729 pDCB->DCBFlag |= TRM_QUEUE_FULL; 730 sc->MsgCnt = 0; 731 return 1; 732 } 733 } 734 735 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */ 736 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG; 737 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber; 738 739 scsicommand = SCMD_SEL_ATN3; 740 } 741 742 pSRB->SRBState = TRM_START; 743 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 744 sc->pActiveDCB = pDCB; 745 pDCB->pActiveSRB = pSRB; 746 747 if (sc->MsgCnt > 0) { 748 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]); 749 if (sc->MsgCnt > 1) { 750 DELAY(30); 751 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1); 752 } 753 sc->MsgCnt = 0; 754 } 755 756 /* 757 * it's important for atn stop 758 */ 759 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT); 760 /* 761 * SCSI command 762 */ 763 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand); 764 765 return 0; 766 } 767 768 /* 769 * ------------------------------------------------------------ 770 * Function : trm_Interrupt 771 * Purpose : Catch an interrupt from the adapter 772 * Process pending device interrupts. 773 * Inputs : void * - struct trm_softc * structure pointer 774 * ------------------------------------------------------------ 775 */ 776 int 777 trm_Interrupt(void *vsc) 778 { 779 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 780 struct trm_scsi_req_q *pSRB; 781 bus_space_handle_t ioh; 782 struct trm_softc *sc = (struct trm_softc *)vsc; 783 bus_space_tag_t iot; 784 u_int16_t phase; 785 u_int8_t scsi_status, scsi_intstatus; 786 787 if (sc == NULL) 788 return 0; 789 790 ioh = sc->sc_iohandle; 791 iot = sc->sc_iotag; 792 793 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS); 794 if (!(scsi_status & SCSIINTERRUPT)) 795 return 0; 796 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 797 798 #ifdef TRM_DEBUG0 799 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n", 800 sc->sc_device.dv_xname, scsi_status, scsi_intstatus); 801 #endif 802 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0) 803 trm_Disconnect(sc); 804 805 else if ((scsi_intstatus & INT_RESELECTED) != 0) 806 trm_Reselect(sc); 807 808 else if ((scsi_intstatus & INT_SCSIRESET) != 0) 809 trm_ScsiRstDetect(sc); 810 811 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) { 812 pSRB = sc->pActiveDCB->pActiveSRB; 813 /* 814 * software sequential machine 815 */ 816 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 817 /* 818 * 62037 or 62137 819 * call trm_SCSI_phase0[]... "phase entry" 820 * handle every phase before start transfer 821 */ 822 stateV = trm_SCSI_phase0[phase]; 823 stateV(sc, pSRB, &scsi_status); 824 /* 825 * if any exception occurred 826 * scsi_status will be modified to bus free phase 827 * new scsi_status transfer out from previous stateV 828 */ 829 /* 830 * phase:0,1,2,3,4,5,6,7 831 */ 832 pSRB->ScsiPhase = scsi_status & PHASEMASK; 833 phase = (u_int16_t) scsi_status & PHASEMASK; 834 /* 835 * call trm_SCSI_phase1[]... "phase entry" 836 * handle every phase do transfer 837 */ 838 stateV = trm_SCSI_phase1[phase]; 839 stateV(sc, pSRB, &scsi_status); 840 841 } else { 842 return 0; 843 } 844 845 return 1; 846 } 847 848 /* 849 * ------------------------------------------------------------ 850 * Function : trm_MsgOutPhase0 851 * Purpose : Check the state machine before sending a message out 852 * Inputs : struct trm_softc * - 853 * struct trm_scsi_req_q * - 854 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready 855 * ------------------------------------------------------------ 856 */ 857 void 858 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 859 { 860 switch (pSRB->SRBState) { 861 case TRM_UNEXPECT_RESEL: 862 case TRM_ABORT_SENT: 863 *pscsi_status = PH_BUS_FREE; /* initial phase */ 864 break; 865 866 default: 867 break; 868 } 869 } 870 871 /* 872 * ------------------------------------------------------------ 873 * Function : trm_MsgOutPhase1 874 * Purpose : Write the message out to the bus 875 * Inputs : struct trm_softc * - 876 * struct trm_scsi_req_q * - 877 * u_int8_t * - unused 878 * ------------------------------------------------------------ 879 */ 880 void 881 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 882 { 883 const bus_space_handle_t ioh = sc->sc_iohandle; 884 const bus_space_tag_t iot = sc->sc_iotag; 885 struct trm_dcb *pDCB = sc->pActiveDCB; 886 887 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 888 889 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) { 890 /* 891 * WIDE DATA TRANSFER REQUEST code (03h) 892 */ 893 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 894 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO; 895 896 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 897 sc->MsgBuf[1] = MSG_EXTENDED; 898 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN; 899 sc->MsgBuf[3] = MSG_EXT_WDTR; 900 901 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 902 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT; 903 else 904 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 905 906 sc->MsgCnt = 5; 907 908 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 909 910 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE; 911 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO; 912 913 sc->MsgCnt = 0; 914 915 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0) 916 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 917 918 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED; 919 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN; 920 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR; 921 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod; 922 923 if (pDCB->MaxNegoPeriod > 0) 924 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET; 925 else 926 sc->MsgBuf[sc->MsgCnt++] = 0; 927 } 928 929 if (sc->MsgCnt > 0) { 930 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt); 931 if (sc->MsgBuf[0] == MSG_ABORT) 932 pSRB->SRBState = TRM_ABORT_SENT; 933 sc->MsgCnt = 0; 934 } 935 /* 936 * it's important for atn stop 937 */ 938 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 939 /* 940 * Transfer information out 941 */ 942 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 943 } 944 945 /* 946 * ------------------------------------------------------------ 947 * Function : trm_CommandPhase1 948 * Purpose : Send commands to bus 949 * Inputs : 950 * ------------------------------------------------------------ 951 */ 952 void 953 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 954 { 955 const bus_space_handle_t ioh = sc->sc_iohandle; 956 const bus_space_tag_t iot = sc->sc_iotag; 957 958 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 959 960 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen); 961 962 pSRB->SRBState = TRM_COMMAND; 963 /* 964 * it's important for atn stop 965 */ 966 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 967 /* 968 * Transfer information out 969 */ 970 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 971 } 972 973 /* 974 * ------------------------------------------------------------ 975 * Function : trm_DataOutPhase0 976 * Purpose : Ready for Data Out, clear FIFO 977 * Inputs : u_int8_t * - SCSI status, used but not set 978 * ------------------------------------------------------------ 979 */ 980 void 981 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 982 { 983 const bus_space_handle_t ioh = sc->sc_iohandle; 984 const bus_space_tag_t iot = sc->sc_iotag; 985 struct SGentry *pseg; 986 struct trm_dcb *pDCB; 987 u_int32_t dLeftCounter, TempSRBXferredLength; 988 u_int16_t scsi_status; 989 u_int8_t TempDMAstatus, SGIndexTemp; 990 991 dLeftCounter = 0; 992 993 pDCB = pSRB->pSRBDCB; 994 scsi_status = *pscsi_status; 995 996 if (pSRB->SRBState != TRM_XFERPAD) { 997 if ((scsi_status & PARITYERROR) != 0) 998 pSRB->SRBFlag |= TRM_PARITY_ERROR; 999 if ((scsi_status & SCSIXFERDONE) == 0) { 1000 /* 1001 * when data transfer from DMA FIFO to SCSI FIFO 1002 * if there was some data left in SCSI FIFO 1003 */ 1004 dLeftCounter = (u_int32_t)(bus_space_read_1( 1005 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F); 1006 if (pDCB->SyncPeriod & WIDE_SYNC) { 1007 /* 1008 * if WIDE scsi SCSI FIFOCNT unit is word 1009 * so need to * 2 1010 */ 1011 dLeftCounter <<= 1; 1012 } 1013 } 1014 /* 1015 * calculate all the residue data that not yet transferred 1016 * SCSI transfer counter + left in SCSI FIFO data 1017 * 1018 * .....TRM_S1040_SCSI_COUNTER (24bits) 1019 * The counter always decrement by one for every SCSI byte 1020 * transfer. 1021 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits) 1022 * The counter is SCSI FIFO offset counter 1023 */ 1024 dLeftCounter += bus_space_read_4(iot, ioh, 1025 TRM_S1040_SCSI_COUNTER); 1026 if (dLeftCounter == 1) { 1027 dLeftCounter = 0; 1028 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1029 DO_CLRFIFO); 1030 } 1031 if (dLeftCounter == 0 || 1032 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1033 TempDMAstatus = bus_space_read_1(iot, 1034 ioh, TRM_S1040_DMA_STATUS); 1035 while ((TempDMAstatus & DMAXFERCOMP) == 0) { 1036 TempDMAstatus = bus_space_read_1(iot, 1037 ioh, TRM_S1040_DMA_STATUS); 1038 } 1039 pSRB->SRBTotalXferLength = 0; 1040 } else { 1041 /* 1042 * Update SG list 1043 */ 1044 /* 1045 * if transfer not yet complete 1046 * there were some data residue in SCSI FIFO or 1047 * SCSI transfer counter not empty 1048 */ 1049 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1050 /* 1051 * data that had transferred length 1052 */ 1053 TempSRBXferredLength = pSRB->SRBTotalXferLength 1054 - dLeftCounter; 1055 /* 1056 * next time to be transferred length 1057 */ 1058 pSRB->SRBTotalXferLength = dLeftCounter; 1059 /* 1060 * parsing from last time disconnect SRBSGIndex 1061 */ 1062 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1063 for (SGIndexTemp = pSRB->SRBSGIndex; 1064 SGIndexTemp < pSRB->SRBSGCount; 1065 SGIndexTemp++) { 1066 /* 1067 * find last time which SG transfer be 1068 * disconnect 1069 */ 1070 if (TempSRBXferredLength >= pseg->length) 1071 TempSRBXferredLength -= pseg->length; 1072 else { 1073 /* 1074 * update last time disconnected 1075 * SG list 1076 */ 1077 /* 1078 * residue data length 1079 */ 1080 pseg->length -= 1081 TempSRBXferredLength; 1082 /* 1083 * residue data pointer 1084 */ 1085 pseg->address += 1086 TempSRBXferredLength; 1087 pSRB->SRBSGIndex = SGIndexTemp; 1088 break; 1089 } 1090 pseg++; 1091 } 1092 } 1093 } 1094 } 1095 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 1096 } 1097 1098 /* 1099 * ------------------------------------------------------------ 1100 * Function : trm_DataOutPhase1 1101 * Purpose : Transfers data out, calls trm_DataIO_transfer 1102 * Inputs : 1103 * ------------------------------------------------------------ 1104 */ 1105 void 1106 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1107 { 1108 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT); 1109 } 1110 1111 /* 1112 * ------------------------------------------------------------ 1113 * Function : trm_DataInPhase0 1114 * Purpose : Prepare for reading data in from bus 1115 * Inputs : 1116 * ------------------------------------------------------------ 1117 */ 1118 void 1119 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1120 { 1121 const bus_space_handle_t ioh = sc->sc_iohandle; 1122 const bus_space_tag_t iot = sc->sc_iotag; 1123 struct SGentry *pseg; 1124 u_int32_t TempSRBXferredLength, dLeftCounter; 1125 u_int16_t scsi_status; 1126 u_int8_t SGIndexTemp; 1127 1128 dLeftCounter = 0; 1129 1130 scsi_status = *pscsi_status; 1131 if (pSRB->SRBState != TRM_XFERPAD) { 1132 if ((scsi_status & PARITYERROR) != 0) 1133 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1134 dLeftCounter += bus_space_read_4(iot, ioh, 1135 TRM_S1040_SCSI_COUNTER); 1136 if (dLeftCounter == 0 || 1137 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1138 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0) 1139 ; 1140 pSRB->SRBTotalXferLength = 0; 1141 } else { 1142 /* 1143 * phase changed 1144 * 1145 * parsing the case: 1146 * when a transfer not yet complete 1147 * but be disconnected by uper layer 1148 * if transfer not yet complete 1149 * there were some data residue in SCSI FIFO or 1150 * SCSI transfer counter not empty 1151 */ 1152 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1153 /* 1154 * data that had transferred length 1155 */ 1156 TempSRBXferredLength = pSRB->SRBTotalXferLength 1157 - dLeftCounter; 1158 /* 1159 * next time to be transferred length 1160 */ 1161 pSRB->SRBTotalXferLength = dLeftCounter; 1162 /* 1163 * parsing from last time disconnect SRBSGIndex 1164 */ 1165 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1166 for (SGIndexTemp = pSRB->SRBSGIndex; 1167 SGIndexTemp < pSRB->SRBSGCount; 1168 SGIndexTemp++) { 1169 /* 1170 * find last time which SG transfer be 1171 * disconnect 1172 */ 1173 if (TempSRBXferredLength >= 1174 pseg->length) { 1175 TempSRBXferredLength -= pseg->length; 1176 } else { 1177 /* 1178 * update last time disconnected 1179 * SG list 1180 * 1181 * residue data length 1182 */ 1183 pseg->length -= TempSRBXferredLength; 1184 /* 1185 * residue data pointer 1186 */ 1187 pseg->address += TempSRBXferredLength; 1188 pSRB->SRBSGIndex = SGIndexTemp; 1189 break; 1190 } 1191 pseg++; 1192 } 1193 } 1194 } 1195 } 1196 } 1197 1198 /* 1199 * ------------------------------------------------------------ 1200 * Function : trm_DataInPhase1 1201 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer 1202 * Inputs : 1203 * ------------------------------------------------------------ 1204 */ 1205 void 1206 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1207 { 1208 trm_DataIO_transfer(sc, pSRB, XFERDATAIN); 1209 } 1210 1211 /* 1212 * ------------------------------------------------------------ 1213 * Function : trm_DataIO_transfer 1214 * Purpose : 1215 * Inputs : 1216 * ------------------------------------------------------------ 1217 */ 1218 void 1219 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir) 1220 { 1221 const bus_space_handle_t ioh = sc->sc_iohandle; 1222 const bus_space_tag_t iot = sc->sc_iotag; 1223 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1224 u_int8_t bval; 1225 1226 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1227 if (pSRB->SRBTotalXferLength != 0) { 1228 /* 1229 * load what physical address of Scatter/Gather list 1230 * table want to be transfer 1231 */ 1232 pSRB->SRBState = TRM_DATA_XFER; 1233 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0); 1234 bus_space_write_4(iot, ioh, 1235 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr + 1236 ((u_int32_t)pSRB->SRBSGIndex << 3))); 1237 /* 1238 * load how many bytes in the Scatter/Gather list table 1239 */ 1240 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT, 1241 ((u_int32_t)(pSRB->SRBSGCount - 1242 pSRB->SRBSGIndex) << 3)); 1243 /* 1244 * load total transfer length (24bits, 1245 * pSRB->SRBTotalXferLength) max value 16Mbyte 1246 */ 1247 bus_space_write_4(iot, ioh, 1248 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength); 1249 /* 1250 * Start DMA transfer 1251 */ 1252 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir); 1253 /* bus_space_write_2(iot, ioh, 1254 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/ 1255 /* 1256 * Set the transfer bus and direction 1257 */ 1258 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN; 1259 } else { 1260 /* 1261 * xfer pad 1262 */ 1263 if (pSRB->SRBSGCount) 1264 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN; 1265 1266 if (pDCB->SyncPeriod & WIDE_SYNC) { 1267 bus_space_write_4(iot, ioh, 1268 TRM_S1040_SCSI_COUNTER, 2); 1269 } else { 1270 bus_space_write_4(iot, ioh, 1271 TRM_S1040_SCSI_COUNTER, 1); 1272 } 1273 1274 if (ioDir == XFERDATAOUT) { 1275 bus_space_write_2(iot, 1276 ioh, TRM_S1040_SCSI_FIFO, 0); 1277 } else { 1278 bus_space_read_2(iot, 1279 ioh, TRM_S1040_SCSI_FIFO); 1280 } 1281 pSRB->SRBState = TRM_XFERPAD; 1282 /* 1283 * Set the transfer bus and direction 1284 */ 1285 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN; 1286 } 1287 /* 1288 * it's important for atn stop 1289 */ 1290 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1291 /* 1292 * Tell the bus to do the transfer 1293 */ 1294 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval); 1295 } 1296 } 1297 1298 /* 1299 * ------------------------------------------------------------ 1300 * Function : trm_StatusPhase0 1301 * Purpose : Update Target Status with data from SCSI FIFO 1302 * Inputs : u_int8_t * - Set to PH_BUS_FREE 1303 * ------------------------------------------------------------ 1304 */ 1305 void 1306 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1307 { 1308 const bus_space_handle_t ioh = sc->sc_iohandle; 1309 const bus_space_tag_t iot = sc->sc_iotag; 1310 1311 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1312 1313 pSRB->SRBState = TRM_COMPLETED; 1314 /* 1315 * initial phase 1316 */ 1317 *pscsi_status = PH_BUS_FREE; 1318 /* 1319 * it's important for atn stop 1320 */ 1321 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1322 /* 1323 * Tell bus that the message was accepted 1324 */ 1325 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1326 } 1327 1328 /* 1329 * ------------------------------------------------------------ 1330 * Function : trm_StatusPhase1 1331 * Purpose : Clear FIFO of DMA and SCSI 1332 * Inputs : 1333 * ------------------------------------------------------------ 1334 */ 1335 void 1336 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1337 { 1338 const bus_space_handle_t ioh = sc->sc_iohandle; 1339 const bus_space_tag_t iot = sc->sc_iotag; 1340 1341 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) { 1342 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40) 1343 == 0) { 1344 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1345 DO_CLRFIFO); 1346 } 1347 if ((bus_space_read_2(iot, ioh, 1348 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1349 bus_space_write_1(iot, ioh, 1350 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1351 } 1352 } else { 1353 if ((bus_space_read_2(iot, ioh, 1354 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1355 bus_space_write_1(iot, ioh, 1356 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1357 } 1358 if ((bus_space_read_1(iot, ioh, 1359 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) { 1360 bus_space_write_2(iot, ioh, 1361 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1362 } 1363 } 1364 pSRB->SRBState = TRM_STATUS; 1365 /* 1366 * it's important for atn stop 1367 */ 1368 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1369 /* 1370 * Tell the bus that the command is complete 1371 */ 1372 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP); 1373 } 1374 1375 /* 1376 * ------------------------------------------------------------ 1377 * Function : trm_MsgInPhase0 1378 * Purpose : 1379 * Inputs : 1380 * 1381 * extended message codes: 1382 * code description 1383 * ---- ----------- 1384 * 02h Reserved 1385 * 00h MODIFY DATA POINTER 1386 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1387 * 03h WIDE DATA TRANSFER REQUEST 1388 * 04h - 7Fh Reserved 1389 * 80h - FFh Vendor specific 1390 * 1391 * ------------------------------------------------------------ 1392 */ 1393 void 1394 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1395 { 1396 const bus_space_handle_t ioh = sc->sc_iohandle; 1397 const bus_space_tag_t iot = sc->sc_iotag; 1398 struct trm_dcb *pDCB; 1399 u_int8_t message_in_code, bIndex, message_in_tag_id; 1400 1401 pDCB = sc->pActiveDCB; 1402 1403 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1404 1405 if (pSRB->SRBState != TRM_EXTEND_MSGIN) { 1406 switch (message_in_code) { 1407 case MSG_DISCONNECT: 1408 pSRB->SRBState = TRM_DISCONNECTED; 1409 break; 1410 1411 case MSG_EXTENDED: 1412 case MSG_SIMPLE_Q_TAG: 1413 case MSG_HEAD_OF_Q_TAG: 1414 case MSG_ORDERED_Q_TAG: 1415 pSRB->SRBState = TRM_EXTEND_MSGIN; 1416 /* 1417 * extended message (01h) 1418 */ 1419 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf)); 1420 sc->MsgBuf[0] = message_in_code; 1421 sc->MsgCnt = 1; 1422 /* 1423 * extended message length (n) 1424 */ 1425 break; 1426 1427 case MSG_MESSAGE_REJECT: 1428 /* 1429 * Reject message 1430 */ 1431 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) { 1432 /* 1433 * do wide nego reject 1434 */ 1435 pDCB = pSRB->pSRBDCB; 1436 1437 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO; 1438 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1439 1440 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 1441 /* 1442 * Set ATN, in case ATN was clear 1443 */ 1444 pSRB->SRBState = TRM_MSGOUT; 1445 bus_space_write_2(iot, ioh, 1446 TRM_S1040_SCSI_CONTROL, DO_SETATN); 1447 } else { 1448 /* 1449 * Clear ATN 1450 */ 1451 bus_space_write_2(iot, ioh, 1452 TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1453 } 1454 1455 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) { 1456 /* 1457 * do sync nego reject 1458 */ 1459 pDCB = pSRB->pSRBDCB; 1460 1461 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO; 1462 1463 pDCB->SyncPeriod = 0; 1464 pDCB->SyncOffset = 0; 1465 1466 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1467 goto re_prog; 1468 } 1469 break; 1470 1471 case MSG_IGN_WIDE_RESIDUE: 1472 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1473 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1474 break; 1475 1476 default: 1477 break; 1478 } 1479 1480 } else { 1481 1482 /* 1483 * We are collecting an extended message. Save the latest byte and then 1484 * check to see if the message is complete. If so, process it. 1485 */ 1486 sc->MsgBuf[sc->MsgCnt++] = message_in_code; 1487 #ifdef TRM_DEBUG0 1488 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", 1489 sc->sc_device.dv_xname, 1490 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] ); 1491 #endif 1492 switch (sc->MsgBuf[0]) { 1493 case MSG_SIMPLE_Q_TAG: 1494 case MSG_HEAD_OF_Q_TAG: 1495 case MSG_ORDERED_Q_TAG: 1496 if (sc->MsgCnt == 2) { 1497 pSRB->SRBState = TRM_FREE; 1498 message_in_tag_id = sc->MsgBuf[1]; 1499 sc->MsgCnt = 0; 1500 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) { 1501 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id)) 1502 break; 1503 } 1504 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) { 1505 pDCB->pActiveSRB = pSRB; 1506 pSRB->SRBState = TRM_DATA_XFER; 1507 } else { 1508 #ifdef TRM_DEBUG0 1509 printf("%s: TRM_UNEXPECT_RESEL!\n", 1510 sc->sc_device.dv_xname); 1511 #endif 1512 pSRB = &sc->SRB[0]; 1513 trm_srb_reinit(sc, pSRB); 1514 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1515 pDCB->pActiveSRB = pSRB; 1516 trm_EnableMsgOut(sc, MSG_ABORT_TAG); 1517 } 1518 } 1519 break; 1520 1521 case MSG_EXTENDED: 1522 /* TODO XXXX: Correctly handling target initiated negotiations? */ 1523 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) { 1524 /* 1525 * ====================================== 1526 * WIDE DATA TRANSFER REQUEST 1527 * ====================================== 1528 * byte 0 : Extended message (01h) 1529 * byte 1 : Extended message length (02h) 1530 * byte 2 : WIDE DATA TRANSFER code (03h) 1531 * byte 3 : Transfer width exponent 1532 */ 1533 1534 pSRB->SRBState = TRM_FREE; 1535 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO); 1536 1537 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN) 1538 goto reject_offer; 1539 1540 switch (sc->MsgBuf[3]) { 1541 case MSG_EXT_WDTR_BUS_32_BIT: 1542 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 1543 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1544 else 1545 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT; 1546 break; 1547 1548 case MSG_EXT_WDTR_BUS_16_BIT: 1549 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) { 1550 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1551 break; 1552 } 1553 pDCB->SyncPeriod |= WIDE_SYNC; 1554 /* FALL THROUGH == ACCEPT OFFER */ 1555 1556 case MSG_EXT_WDTR_BUS_8_BIT: 1557 pSRB->SRBState = TRM_MSGOUT; 1558 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE); 1559 1560 if (pDCB->MaxNegoPeriod == 0) { 1561 pDCB->SyncPeriod = 0; 1562 pDCB->SyncOffset = 0; 1563 goto re_prog; 1564 } 1565 break; 1566 1567 default: 1568 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 1569 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1570 reject_offer: 1571 sc->MsgCnt = 1; 1572 sc->MsgBuf[0] = MSG_MESSAGE_REJECT; 1573 break; 1574 } 1575 1576 /* Echo accepted offer, or send revised offer */ 1577 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN); 1578 1579 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) { 1580 /* 1581 * ================================= 1582 * SYNCHRONOUS DATA TRANSFER REQUEST 1583 * ================================= 1584 * byte 0 : Extended message (01h) 1585 * byte 1 : Extended message length (03) 1586 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1587 * byte 3 : Transfer period factor 1588 * byte 4 : REQ/ACK offset 1589 */ 1590 1591 pSRB->SRBState = TRM_FREE; 1592 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO); 1593 1594 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN) 1595 goto reject_offer; 1596 1597 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) { 1598 /* 1599 * Asynchronous transfers 1600 */ 1601 pDCB->SyncPeriod = 0; 1602 pDCB->SyncOffset = 0; 1603 1604 } else { 1605 /* 1606 * Synchronous transfers 1607 */ 1608 /* 1609 * REQ/ACK offset 1610 */ 1611 pDCB->SyncOffset = sc->MsgBuf[4]; 1612 1613 for (bIndex = 0; bIndex < 7; bIndex++) 1614 if (sc->MsgBuf[3] <= trm_clock_period[bIndex]) 1615 break; 1616 1617 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 1618 } 1619 1620 re_prog: /* 1621 * program SCSI control register 1622 */ 1623 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1624 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1625 1626 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID)); 1627 } 1628 break; 1629 1630 default: 1631 break; 1632 } 1633 } 1634 1635 /* 1636 * initial phase 1637 */ 1638 *pscsi_status = PH_BUS_FREE; 1639 /* 1640 * it's important for atn stop 1641 */ 1642 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1643 /* 1644 * Tell bus that the message was accepted 1645 */ 1646 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1647 } 1648 1649 /* 1650 * ------------------------------------------------------------ 1651 * Function : trm_MsgInPhase1 1652 * Purpose : Clear the FIFO 1653 * Inputs : 1654 * ------------------------------------------------------------ 1655 */ 1656 void 1657 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1658 { 1659 const bus_space_handle_t ioh = sc->sc_iohandle; 1660 const bus_space_tag_t iot = sc->sc_iotag; 1661 1662 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1663 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1664 1665 /* 1666 * it's important for atn stop 1667 */ 1668 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1669 /* 1670 * SCSI command 1671 */ 1672 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN); 1673 } 1674 1675 /* 1676 * ------------------------------------------------------------ 1677 * Function : trm_Nop 1678 * Purpose : EMPTY 1679 * Inputs : 1680 * ------------------------------------------------------------ 1681 */ 1682 void 1683 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1684 { 1685 } 1686 1687 /* 1688 * ------------------------------------------------------------ 1689 * Function : trm_SetXferParams 1690 * Purpose : Set the Sync period, offset and mode for each device that has 1691 * the same target as the given one (struct trm_dcb *) 1692 * Inputs : 1693 * ------------------------------------------------------------ 1694 */ 1695 void 1696 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info) 1697 { 1698 struct trm_dcb *pDCBTemp; 1699 int lun, target; 1700 1701 /* 1702 * set all lun device's period, offset 1703 */ 1704 #ifdef TRM_DEBUG0 1705 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname); 1706 #endif 1707 1708 target = pDCB->target; 1709 for(lun = 0; lun < TRM_MAX_LUNS; lun++) { 1710 pDCBTemp = sc->pDCB[target][lun]; 1711 if (pDCBTemp != NULL) { 1712 pDCBTemp->DevMode = pDCB->DevMode; 1713 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod; 1714 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 1715 pDCBTemp->SyncOffset = pDCB->SyncOffset; 1716 pDCBTemp->DCBFlag = pDCB->DCBFlag; 1717 } 1718 } 1719 1720 if (print_info) 1721 trm_print_info(sc, pDCB); 1722 } 1723 1724 /* 1725 * ------------------------------------------------------------ 1726 * Function : trm_Disconnect 1727 * Purpose : 1728 * Inputs : 1729 * 1730 * ---SCSI bus phase 1731 * PH_DATA_OUT 0x00 Data out phase 1732 * PH_DATA_IN 0x01 Data in phase 1733 * PH_COMMAND 0x02 Command phase 1734 * PH_STATUS 0x03 Status phase 1735 * PH_BUS_FREE 0x04 Invalid phase used as bus free 1736 * PH_BUS_FREE 0x05 Invalid phase used as bus free 1737 * PH_MSG_OUT 0x06 Message out phase 1738 * PH_MSG_IN 0x07 Message in phase 1739 * ------------------------------------------------------------ 1740 */ 1741 void 1742 trm_Disconnect(struct trm_softc *sc) 1743 { 1744 const bus_space_handle_t ioh = sc->sc_iohandle; 1745 struct trm_scsi_req_q *pSRB; 1746 const bus_space_tag_t iot = sc->sc_iotag; 1747 struct trm_dcb *pDCB; 1748 int j; 1749 1750 #ifdef TRM_DEBUG0 1751 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname); 1752 #endif 1753 1754 pDCB = sc->pActiveDCB; 1755 if (pDCB == NULL) { 1756 /* TODO: Why use a loop? Why not use DELAY(400)? */ 1757 for(j = 400; j > 0; --j) 1758 DELAY(1); /* 1 msec */ 1759 bus_space_write_2(iot, ioh, 1760 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1761 return; 1762 } 1763 1764 pSRB = pDCB->pActiveSRB; 1765 sc->pActiveDCB = NULL; 1766 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1767 bus_space_write_2(iot, ioh, 1768 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1769 DELAY(100); 1770 1771 switch (pSRB->SRBState) { 1772 case TRM_UNEXPECT_RESEL: 1773 pSRB->SRBState = TRM_FREE; 1774 break; 1775 1776 case TRM_ABORT_SENT: 1777 trm_GoingSRB_Done(sc, pDCB); 1778 break; 1779 1780 case TRM_START: 1781 case TRM_MSGOUT: 1782 /* 1783 * Selection time out 1784 */ 1785 /* If not polling just keep trying until xs->stimeout expires */ 1786 if ((pSRB->xs->flags & SCSI_POLL) == 0) { 1787 trm_RewaitSRB(sc, pSRB); 1788 } else { 1789 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT; 1790 goto disc1; 1791 } 1792 break; 1793 1794 case TRM_COMPLETED: 1795 disc1: 1796 /* 1797 * TRM_COMPLETED - remove id from mask of active tags 1798 */ 1799 pDCB->pActiveSRB = NULL; 1800 trm_FinishSRB(sc, pSRB); 1801 break; 1802 1803 default: 1804 break; 1805 } 1806 1807 trm_StartWaitingSRB(sc); 1808 } 1809 1810 /* 1811 * ------------------------------------------------------------ 1812 * Function : trm_Reselect 1813 * Purpose : 1814 * Inputs : 1815 * ------------------------------------------------------------ 1816 */ 1817 void 1818 trm_Reselect(struct trm_softc *sc) 1819 { 1820 const bus_space_handle_t ioh = sc->sc_iohandle; 1821 const bus_space_tag_t iot = sc->sc_iotag; 1822 struct trm_scsi_req_q *pSRB; 1823 struct trm_dcb *pDCB; 1824 u_int16_t RselTarLunId; 1825 u_int8_t target, lun; 1826 1827 #ifdef TRM_DEBUG0 1828 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname); 1829 #endif 1830 1831 pDCB = sc->pActiveDCB; 1832 if (pDCB != NULL) { 1833 /* 1834 * Arbitration lost but Reselection win 1835 */ 1836 pSRB = pDCB->pActiveSRB; 1837 trm_RewaitSRB(sc, pSRB); 1838 } 1839 1840 /* 1841 * Read Reselected Target Id and LUN 1842 */ 1843 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF; 1844 /* TODO XXXX: Make endian independent! */ 1845 target = RselTarLunId & 0xff; 1846 lun = (RselTarLunId >> 8) & 0xff; 1847 1848 #ifdef TRM_DEBUG0 1849 printf("%s: reselect - target = %d, lun = %d\n", 1850 sc->sc_device.dv_xname, target, lun); 1851 #endif 1852 1853 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS)) 1854 pDCB = sc->pDCB[target][lun]; 1855 else 1856 pDCB = NULL; 1857 1858 if (pDCB == NULL) 1859 printf("%s: reselect - target = %d, lun = %d not found\n", 1860 sc->sc_device.dv_xname, target, lun); 1861 1862 sc->pActiveDCB = pDCB; 1863 1864 /* TODO XXXX: This will crash if pDCB is ever NULL */ 1865 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) { 1866 pSRB = &sc->SRB[0]; 1867 pDCB->pActiveSRB = pSRB; 1868 } else { 1869 pSRB = pDCB->pActiveSRB; 1870 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) { 1871 /* 1872 * abort command 1873 */ 1874 pSRB = &sc->SRB[0]; 1875 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1876 pDCB->pActiveSRB = pSRB; 1877 trm_EnableMsgOut(sc, MSG_ABORT); 1878 } else 1879 pSRB->SRBState = TRM_DATA_XFER; 1880 } 1881 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1882 1883 /* 1884 * Program HA ID, target ID, period and offset 1885 */ 1886 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target); 1887 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 1888 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1889 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1890 1891 /* 1892 * it's important for atn stop 1893 */ 1894 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1895 DELAY(30); 1896 1897 /* 1898 * SCSI command 1899 * to rls the /ACK signal 1900 */ 1901 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1902 } 1903 1904 /* 1905 * ------------------------------------------------------------ 1906 * Function : trm_FinishSRB 1907 * Purpose : Complete execution of a SCSI command 1908 * Inputs : 1909 * ------------------------------------------------------------ 1910 */ 1911 void 1912 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 1913 { 1914 struct scsi_inquiry_data *ptr; 1915 struct scsi_sense_data *s1, *s2; 1916 struct scsi_xfer *xs = pSRB->xs; 1917 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1918 int target, lun, intflag; 1919 1920 #ifdef TRM_DEBUG0 1921 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n", 1922 sc->sc_device.dv_xname, sc, pSRB); 1923 #endif 1924 pDCB->DCBFlag &= ~TRM_QUEUE_FULL; 1925 1926 intflag = splbio(); 1927 if (pSRB->TagNumber != TRM_NO_TAG) { 1928 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber); 1929 pSRB->TagNumber = TRM_NO_TAG; 1930 } 1931 /* SRB may have started & finished, or be waiting and timed out */ 1932 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 1933 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 1934 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 1935 } 1936 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 1937 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 1938 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 1939 } 1940 splx(intflag); 1941 1942 if (xs == NULL) { 1943 return; 1944 } 1945 1946 timeout_del(&xs->stimeout); 1947 1948 xs->status = pSRB->TargetStatus; 1949 if (xs->datalen != 0) { 1950 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 1951 0, pSRB->dmamapxfer->dm_mapsize, 1952 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1953 BUS_DMASYNC_POSTWRITE); 1954 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer); 1955 } 1956 1957 switch (xs->status) { 1958 case SCSI_INTERM_COND_MET: 1959 case SCSI_COND_MET: 1960 case SCSI_INTERM: 1961 case SCSI_OK: 1962 switch (pSRB->AdaptStatus) { 1963 case TRM_STATUS_GOOD: 1964 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) { 1965 #ifdef TRM_DEBUG0 1966 sc_print_addr(xs->sc_link); 1967 printf(" trm_FinishSRB. TRM_PARITY_ERROR\n"); 1968 #endif 1969 xs->error = XS_DRIVER_STUFFUP; 1970 1971 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) { 1972 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) == 0) 1973 xs->error = XS_TIMEOUT; 1974 else { 1975 bzero(&xs->sense, sizeof(xs->sense)); 1976 xs->status = SCSI_CHECK; 1977 xs->error = XS_SENSE; 1978 } 1979 1980 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) { 1981 s1 = &pSRB->scsisense; 1982 s2 = &xs->sense; 1983 1984 *s2 = *s1; 1985 1986 xs->status = SCSI_CHECK; 1987 xs->error = XS_SENSE; 1988 1989 } else 1990 xs->error = XS_NOERROR; 1991 break; 1992 1993 case TRM_OVER_UNDER_RUN: 1994 #ifdef TRM_DEBUG0 1995 sc_print_addr(xs->sc_link); 1996 printf("trm_FinishSRB. TRM_OVER_UNDER_RUN\n"); 1997 #endif 1998 xs->error = XS_DRIVER_STUFFUP; 1999 break; 2000 2001 default: 2002 #ifdef TRM_DEBUG0 2003 sc_print_addr(xs->sc_link); 2004 printf("trm_FinishSRB. AdaptStatus Error = 0x%02x\n", 2005 pSRB->AdaptStatus); 2006 #endif 2007 xs->error = XS_DRIVER_STUFFUP; 2008 break; 2009 } 2010 break; 2011 2012 case SCSI_TERMINATED: 2013 case SCSI_ACA_ACTIVE: 2014 case SCSI_CHECK: 2015 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) 2016 xs->error = XS_DRIVER_STUFFUP; 2017 else { 2018 trm_RequestSense(sc, pSRB); 2019 return; 2020 } 2021 break; 2022 2023 case SCSI_QUEUE_FULL: 2024 /* this says no more until someone completes */ 2025 pDCB->DCBFlag |= TRM_QUEUE_FULL; 2026 trm_RewaitSRB(sc, pSRB); 2027 return; 2028 2029 case SCSI_RESV_CONFLICT: 2030 case SCSI_BUSY: 2031 xs->error = XS_BUSY; 2032 break; 2033 2034 case TRM_SCSI_UNEXP_BUS_FREE: 2035 xs->status = SCSI_OK; 2036 xs->error = XS_DRIVER_STUFFUP; 2037 break; 2038 2039 case TRM_SCSI_BUS_RST_DETECTED: 2040 xs->status = SCSI_OK; 2041 xs->error = XS_RESET; 2042 break; 2043 2044 case TRM_SCSI_SELECT_TIMEOUT: 2045 xs->status = SCSI_OK; 2046 xs->error = XS_SELTIMEOUT; 2047 break; 2048 2049 default: 2050 xs->error = XS_DRIVER_STUFFUP; 2051 break; 2052 } 2053 2054 target = xs->sc_link->target; 2055 lun = xs->sc_link->lun; 2056 2057 if ((xs->flags & SCSI_POLL) != 0) { 2058 2059 if (xs->cmd->opcode == INQUIRY && pDCB->sc_link == NULL) { 2060 2061 ptr = (struct scsi_inquiry_data *) xs->data; 2062 2063 if ((xs->error != XS_NOERROR) || 2064 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) { 2065 #ifdef TRM_DEBUG0 2066 sc_print_addr(xs->sc_link); 2067 printf("trm_FinishSRB NO Device\n"); 2068 #endif 2069 free(pDCB, M_DEVBUF, 0); 2070 sc->pDCB[target][lun] = NULL; 2071 pDCB = NULL; 2072 2073 } else 2074 pDCB->sc_link = xs->sc_link; 2075 } 2076 } 2077 2078 /* 2079 * Notify cmd done 2080 */ 2081 #ifdef TRM_DEBUG0 2082 if ((xs->error != 0) || (xs->status != 0) || 2083 ((xs->flags & SCSI_POLL) != 0)) { 2084 sc_print_addr(xs->sc_link); 2085 printf("trm_FinishSRB. xs->cmd->opcode = 0x%02x, xs->error = %d, xs->status = %d\n", 2086 xs->cmd->opcode, xs->error, xs->status); 2087 } 2088 #endif 2089 2090 if (ISSET(xs->flags, SCSI_POLL)) 2091 SET(xs->flags, ITSDONE); 2092 else 2093 scsi_done(xs); 2094 } 2095 2096 /* 2097 * ------------------------------------------------------------ 2098 * Function : trm_srb_reinit 2099 * Purpose : 2100 * Inputs : 2101 * ------------------------------------------------------------ 2102 */ 2103 void 2104 trm_srb_reinit(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2105 { 2106 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX)); 2107 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2108 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense)); 2109 2110 pSRB->SRBTotalXferLength = 0; 2111 pSRB->SRBSGCount = 0; 2112 pSRB->SRBSGIndex = 0; 2113 pSRB->SRBFlag = 0; 2114 2115 pSRB->SRBState = TRM_FREE; 2116 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2117 pSRB->TargetStatus = SCSI_OK; 2118 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 2119 2120 pSRB->xs = NULL; 2121 pSRB->pSRBDCB = NULL; 2122 } 2123 2124 /* 2125 * ------------------------------------------------------------ 2126 * Function : trm_srb_free 2127 * Purpose : 2128 * Inputs : 2129 * ------------------------------------------------------------ 2130 */ 2131 void 2132 trm_srb_free(void *xsc, void *xpSRB) 2133 { 2134 struct trm_softc *sc = xsc; 2135 struct trm_scsi_req_q *pSRB = xpSRB; 2136 2137 trm_srb_reinit(sc, pSRB); 2138 2139 if (pSRB != &sc->SRB[0]) { 2140 mtx_enter(&sc->sc_srb_mtx); 2141 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2142 mtx_leave(&sc->sc_srb_mtx); 2143 } 2144 } 2145 2146 /* 2147 * ------------------------------------------------------------ 2148 * Function : trm_GoingSRB_Done 2149 * Purpose : 2150 * Inputs : 2151 * ------------------------------------------------------------ 2152 */ 2153 void 2154 trm_GoingSRB_Done(struct trm_softc *sc, struct trm_dcb *pDCB) 2155 { 2156 struct trm_scsi_req_q *pSRB, *pNextSRB; 2157 2158 /* ASSUME we are inside a splbio()/splx() pair */ 2159 2160 pSRB = TAILQ_FIRST(&sc->goingSRB); 2161 while (pSRB != NULL) { 2162 /* 2163 * Need to save pNextSRB because trm_FinishSRB() puts 2164 * pSRB in freeSRB queue, and thus its links no longer 2165 * point to members of the goingSRB queue. This is why 2166 * TAILQ_FOREACH() will not work for this traversal. 2167 */ 2168 pNextSRB = TAILQ_NEXT(pSRB, link); 2169 if (pDCB == NULL || pSRB->pSRBDCB == pDCB) { 2170 /* TODO XXXX: Is TIMED_OUT the best state to report? */ 2171 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 2172 trm_FinishSRB(sc, pSRB); 2173 } 2174 pSRB = pNextSRB; 2175 } 2176 } 2177 2178 /* 2179 * ------------------------------------------------------------ 2180 * Function : trm_ResetSCSIBus 2181 * Purpose : Reset the SCSI bus 2182 * Inputs : struct trm_softc * - 2183 * ------------------------------------------------------------ 2184 */ 2185 void 2186 trm_ResetSCSIBus(struct trm_softc *sc) 2187 { 2188 const bus_space_handle_t ioh = sc->sc_iohandle; 2189 const bus_space_tag_t iot = sc->sc_iotag; 2190 int intflag; 2191 2192 intflag = splbio(); 2193 2194 sc->sc_Flag |= RESET_DEV; 2195 2196 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI); 2197 while ((bus_space_read_2(iot, ioh, 2198 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0); 2199 2200 splx(intflag); 2201 } 2202 2203 /* 2204 * ------------------------------------------------------------ 2205 * Function : trm_ScsiRstDetect 2206 * Purpose : 2207 * Inputs : 2208 * ------------------------------------------------------------ 2209 */ 2210 void 2211 trm_ScsiRstDetect(struct trm_softc *sc) 2212 { 2213 const bus_space_handle_t ioh = sc->sc_iohandle; 2214 const bus_space_tag_t iot = sc->sc_iotag; 2215 int wlval; 2216 2217 #ifdef TRM_DEBUG0 2218 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname); 2219 #endif 2220 2221 wlval = 1000; 2222 /* 2223 * delay 1 sec 2224 */ 2225 while (--wlval != 0) 2226 DELAY(1000); 2227 2228 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 2229 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 2230 2231 if ((sc->sc_Flag & RESET_DEV) != 0) 2232 sc->sc_Flag |= RESET_DONE; 2233 else { 2234 sc->sc_Flag |= RESET_DETECT; 2235 trm_ResetAllDevParam(sc); 2236 trm_RecoverSRB(sc); 2237 sc->pActiveDCB = NULL; 2238 sc->sc_Flag = 0; 2239 trm_StartWaitingSRB(sc); 2240 } 2241 } 2242 2243 /* 2244 * ------------------------------------------------------------ 2245 * Function : trm_RequestSense 2246 * Purpose : 2247 * Inputs : 2248 * ------------------------------------------------------------ 2249 */ 2250 void 2251 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2252 { 2253 pSRB->SRBFlag |= TRM_AUTO_REQSENSE; 2254 2255 /* 2256 * Status of initiator/target 2257 */ 2258 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2259 pSRB->TargetStatus = SCSI_OK; 2260 /* 2261 * Status of initiator/target 2262 */ 2263 2264 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr; 2265 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data); 2266 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data); 2267 pSRB->SRBSGCount = 1; 2268 pSRB->SRBSGIndex = 0; 2269 2270 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2271 2272 pSRB->CmdBlock[0] = REQUEST_SENSE; 2273 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5; 2274 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data); 2275 2276 pSRB->ScsiCmdLen = 6; 2277 2278 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0)) 2279 timeout_add_msec(&pSRB->xs->stimeout, pSRB->xs->timeout); 2280 2281 if (trm_StartSRB(sc, pSRB) != 0) 2282 trm_RewaitSRB(sc, pSRB); 2283 } 2284 2285 /* 2286 * ------------------------------------------------------------ 2287 * Function : trm_EnableMsgOut 2288 * Purpose : set up MsgBuf to send out a single byte message 2289 * Inputs : 2290 * ------------------------------------------------------------ 2291 */ 2292 void 2293 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg) 2294 { 2295 sc->MsgBuf[0] = msg; 2296 sc->MsgCnt = 1; 2297 2298 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN); 2299 } 2300 2301 /* 2302 * ------------------------------------------------------------ 2303 * Function : trm_linkSRB 2304 * Purpose : 2305 * Inputs : 2306 * ------------------------------------------------------------ 2307 */ 2308 void 2309 trm_linkSRB(struct trm_softc *sc) 2310 { 2311 struct trm_scsi_req_q *pSRB; 2312 int i, intflag; 2313 2314 intflag = splbio(); 2315 2316 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2317 pSRB = &sc->SRB[i]; 2318 2319 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr 2320 + i * sizeof(struct trm_scsi_req_q); 2321 2322 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2323 + i * sizeof(struct trm_scsi_req_q) 2324 + offsetof(struct trm_scsi_req_q, SegmentX); 2325 2326 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2327 + i * sizeof(struct trm_scsi_req_q) 2328 + offsetof(struct trm_scsi_req_q, scsisense); 2329 2330 /* 2331 * map all SRB space 2332 */ 2333 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE, 2334 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0, 2335 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2336 &pSRB->dmamapxfer) != 0) { 2337 printf("%s: unable to create DMA transfer map\n", 2338 sc->sc_device.dv_xname); 2339 splx(intflag); 2340 return; 2341 } 2342 2343 if (i > 0) 2344 /* We use sc->SRB[0] directly, so *don't* link it */ 2345 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2346 #ifdef TRM_DEBUG0 2347 printf("pSRB = %p ", pSRB); 2348 #endif 2349 } 2350 #ifdef TRM_DEBUG0 2351 printf("\n "); 2352 #endif 2353 splx(intflag); 2354 } 2355 2356 /* 2357 * ------------------------------------------------------------ 2358 * Function : trm_minphys 2359 * Purpose : limited by the number of segments in the dma segment list 2360 * Inputs : *buf 2361 * ------------------------------------------------------------ 2362 */ 2363 void 2364 trm_minphys(struct buf *bp, struct scsi_link *sl) 2365 { 2366 if (bp->b_bcount > (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG) { 2367 bp->b_bcount = (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG; 2368 } 2369 minphys(bp); 2370 } 2371 2372 /* 2373 * ------------------------------------------------------------ 2374 * Function : trm_initACB 2375 * Purpose : initialize the internal structures for a given SCSI host 2376 * Inputs : 2377 * ------------------------------------------------------------ 2378 */ 2379 void 2380 trm_initACB(struct trm_softc *sc, int unit) 2381 { 2382 const bus_space_handle_t ioh = sc->sc_iohandle; 2383 const bus_space_tag_t iot = sc->sc_iotag; 2384 struct trm_adapter_nvram *pEEpromBuf; 2385 struct trm_dcb *pDCB; 2386 int target, lun; 2387 2388 pEEpromBuf = &trm_eepromBuf[unit]; 2389 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2390 2391 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0) 2392 sc->sc_config |= HCC_WIDE_CARD; 2393 2394 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0) 2395 sc->sc_config |= HCC_SCSI_RESET; 2396 2397 TAILQ_INIT(&sc->freeSRB); 2398 TAILQ_INIT(&sc->waitingSRB); 2399 TAILQ_INIT(&sc->goingSRB); 2400 2401 mtx_init(&sc->sc_srb_mtx, IPL_BIO); 2402 scsi_iopool_init(&sc->sc_iopool, sc, trm_srb_alloc, trm_srb_free); 2403 2404 sc->pActiveDCB = NULL; 2405 sc->sc_AdapterUnit = unit; 2406 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId; 2407 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 2408 sc->sc_Flag = 0; 2409 2410 /* 2411 * put all SRB's (except [0]) onto the freeSRB list 2412 */ 2413 trm_linkSRB(sc); 2414 2415 /* 2416 * allocate DCB array 2417 */ 2418 for (target = 0; target < TRM_MAX_TARGETS; target++) { 2419 if (target == sc->sc_AdaptSCSIID) 2420 continue; 2421 2422 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2423 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb), 2424 M_DEVBUF, M_NOWAIT | M_ZERO); 2425 sc->pDCB[target][lun] = pDCB; 2426 2427 if (pDCB == NULL) 2428 continue; 2429 2430 pDCB->target = target; 2431 pDCB->lun = lun; 2432 pDCB->pActiveSRB = NULL; 2433 } 2434 } 2435 2436 sc->sc_adapter.scsi_cmd = trm_scsi_cmd; 2437 sc->sc_adapter.scsi_minphys = trm_minphys; 2438 2439 sc->sc_link.adapter_softc = sc; 2440 sc->sc_link.adapter_target = sc->sc_AdaptSCSIID; 2441 sc->sc_link.openings = 30; /* So TagMask (32 bit integer) always has space */ 2442 sc->sc_link.adapter = &sc->sc_adapter; 2443 sc->sc_link.adapter_buswidth = ((sc->sc_config & HCC_WIDE_CARD) == 0) ? 8:16; 2444 sc->sc_link.pool = &sc->sc_iopool; 2445 2446 trm_reset(sc); 2447 } 2448 2449 /* 2450 * ------------------------------------------------------------ 2451 * Function : trm_write_all 2452 * Description : write pEEpromBuf 128 bytes to seeprom 2453 * Input : iot, ioh - chip's base address 2454 * Output : none 2455 * ------------------------------------------------------------ 2456 */ 2457 void 2458 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2459 bus_space_handle_t ioh) 2460 { 2461 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2462 u_int8_t bAddr; 2463 2464 /* 2465 * Enable SEEPROM 2466 */ 2467 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2468 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2469 /* 2470 * Write enable 2471 */ 2472 trm_write_cmd(iot, ioh, 0x04, 0xFF); 2473 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2474 trm_wait_30us(iot, ioh); 2475 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2476 trm_set_data(iot, ioh, bAddr, *bpEeprom); 2477 /* 2478 * Write disable 2479 */ 2480 trm_write_cmd(iot, ioh, 0x04, 0x00); 2481 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2482 trm_wait_30us(iot, ioh); 2483 /* 2484 * Disable SEEPROM 2485 */ 2486 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2487 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2488 } 2489 2490 /* 2491 * ------------------------------------------------------------ 2492 * Function : trm_set_data 2493 * Description : write one byte to seeprom 2494 * Input : iot, ioh - chip's base address 2495 * bAddr - address of SEEPROM 2496 * bData - data of SEEPROM 2497 * Output : none 2498 * ------------------------------------------------------------ 2499 */ 2500 void 2501 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr, 2502 u_int8_t bData) 2503 { 2504 u_int8_t bSendData; 2505 int i; 2506 2507 /* 2508 * Send write command & address 2509 */ 2510 trm_write_cmd(iot, ioh, 0x05, bAddr); 2511 /* 2512 * Write data 2513 */ 2514 for (i = 0; i < 8; i++, bData <<= 1) { 2515 bSendData = NVR_SELECT; 2516 if ((bData & 0x80) != 0) { /* Start from bit 7 */ 2517 bSendData |= NVR_BITOUT; 2518 } 2519 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2520 trm_wait_30us(iot, ioh); 2521 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2522 (bSendData | NVR_CLOCK)); 2523 trm_wait_30us(iot, ioh); 2524 } 2525 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2526 trm_wait_30us(iot, ioh); 2527 /* 2528 * Disable chip select 2529 */ 2530 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2531 trm_wait_30us(iot, ioh); 2532 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2533 trm_wait_30us(iot, ioh); 2534 /* 2535 * Wait for write ready 2536 */ 2537 for (;;) { 2538 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2539 (NVR_SELECT | NVR_CLOCK)); 2540 trm_wait_30us(iot, ioh); 2541 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2542 trm_wait_30us(iot, ioh); 2543 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN) 2544 break; 2545 } 2546 /* 2547 * Disable chip select 2548 */ 2549 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2550 } 2551 2552 /* 2553 * ------------------------------------------------------------ 2554 * Function : trm_read_all 2555 * Description : read seeprom 128 bytes to pEEpromBuf 2556 * Input : pEEpromBuf, iot, ioh - chip's base address 2557 * Output : none 2558 * ------------------------------------------------------------ 2559 */ 2560 void 2561 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2562 bus_space_handle_t ioh) 2563 { 2564 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2565 u_int8_t bAddr; 2566 2567 /* 2568 * Enable SEEPROM 2569 */ 2570 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2571 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2572 2573 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2574 *bpEeprom = trm_get_data(iot, ioh, bAddr); 2575 2576 /* 2577 * Disable SEEPROM 2578 */ 2579 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2580 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2581 } 2582 2583 /* 2584 * ------------------------------------------------------------ 2585 * Function : trm_get_data 2586 * Description : read one byte from seeprom 2587 * Input : iot, ioh - chip's base address 2588 * bAddr - address of SEEPROM 2589 * Output : bData - data of SEEPROM 2590 * ------------------------------------------------------------ 2591 */ 2592 u_int8_t 2593 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr) 2594 { 2595 u_int8_t bReadData, bData; 2596 int i; 2597 2598 bData = 0; 2599 2600 /* 2601 * Send read command & address 2602 */ 2603 trm_write_cmd(iot, ioh, 0x06, bAddr); 2604 2605 for (i = 0; i < 8; i++) { 2606 /* 2607 * Read data 2608 */ 2609 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2610 (NVR_SELECT | NVR_CLOCK)); 2611 trm_wait_30us(iot, ioh); 2612 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2613 /* 2614 * Get data bit while falling edge 2615 */ 2616 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM); 2617 bData <<= 1; 2618 if ((bReadData & NVR_BITIN) != 0) 2619 bData |= 1; 2620 trm_wait_30us(iot, ioh); 2621 } 2622 /* 2623 * Disable chip select 2624 */ 2625 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2626 2627 return bData; 2628 } 2629 2630 /* 2631 * ------------------------------------------------------------ 2632 * Function : trm_wait_30us 2633 * Description : wait 30 us 2634 * Input : iot, ioh - chip's base address 2635 * Output : none 2636 * ------------------------------------------------------------ 2637 */ 2638 void 2639 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh) 2640 { 2641 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5); 2642 2643 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT) 2644 == 0); 2645 } 2646 2647 /* 2648 * ------------------------------------------------------------ 2649 * Function : trm_write_cmd 2650 * Description : write SB and Op Code into seeprom 2651 * Input : iot, ioh - chip's base address 2652 * bCmd - SB + Op Code 2653 * bAddr - address of SEEPROM 2654 * Output : none 2655 * ------------------------------------------------------------ 2656 */ 2657 void 2658 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd, 2659 u_int8_t bAddr) 2660 { 2661 u_int8_t bSendData; 2662 int i; 2663 2664 for (i = 0; i < 3; i++, bCmd <<= 1) { 2665 /* 2666 * Program SB + OP code 2667 */ 2668 bSendData = NVR_SELECT; 2669 if (bCmd & 0x04) /* Start from bit 2 */ 2670 bSendData |= NVR_BITOUT; 2671 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2672 trm_wait_30us(iot, ioh); 2673 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2674 (bSendData | NVR_CLOCK)); 2675 trm_wait_30us(iot, ioh); 2676 } 2677 2678 for (i = 0; i < 7; i++, bAddr <<= 1) { 2679 /* 2680 * Program address 2681 */ 2682 bSendData = NVR_SELECT; 2683 if (bAddr & 0x40) { /* Start from bit 6 */ 2684 bSendData |= NVR_BITOUT; 2685 } 2686 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2687 trm_wait_30us(iot, ioh); 2688 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2689 (bSendData | NVR_CLOCK)); 2690 trm_wait_30us(iot, ioh); 2691 } 2692 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2693 trm_wait_30us(iot, ioh); 2694 } 2695 2696 /* 2697 * ------------------------------------------------------------ 2698 * Function : trm_check_eeprom 2699 * Description : read eeprom 128 bytes to pEEpromBuf and check 2700 * checksum. If it is wrong, updated with default value. 2701 * Input : eeprom, iot, ioh - chip's base address 2702 * Output : none 2703 * ------------------------------------------------------------ 2704 */ 2705 void 2706 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2707 bus_space_handle_t ioh) 2708 { 2709 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget; 2710 u_int32_t dAddr; 2711 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf; 2712 u_int16_t wAddr, wCheckSum; 2713 2714 #ifdef TRM_DEBUG0 2715 printf("\ntrm_check_eeprom\n"); 2716 #endif 2717 trm_read_all(pEEpromBuf, iot, ioh); 2718 wCheckSum = 0; 2719 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++) 2720 wCheckSum += *wpEeprom; 2721 2722 if (wCheckSum != 0x1234) { 2723 #ifdef TRM_DEBUG0 2724 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n"); 2725 #endif 2726 /* 2727 * Checksum error, load default 2728 */ 2729 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2730 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2731 >> 8); 2732 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) 2733 PCI_PRODUCT_TEKRAM2_DC3X5U; 2734 pEEpromBuf->NvramSubSysID[1] = (u_int8_t) 2735 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2736 pEEpromBuf->NvramSubClass = 0; 2737 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2738 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2739 >> 8); 2740 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) 2741 PCI_PRODUCT_TEKRAM2_DC3X5U; 2742 pEEpromBuf->NvramDeviceID[1] = (u_int8_t) 2743 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2744 pEEpromBuf->NvramReserved = 0; 2745 2746 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++) 2747 /* 2748 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 2749 */ 2750 *dpEeprom = 0x00000077; 2751 2752 /* 2753 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId 2754 */ 2755 *dpEeprom++ = 0x04000F07; 2756 2757 /* 2758 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 2759 */ 2760 *dpEeprom++ = 0x00000015; 2761 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 2762 *dpEeprom = 0; 2763 2764 pEEpromBuf->NvramCheckSum = 0; 2765 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++) 2766 wCheckSum += *wpEeprom; 2767 2768 *wpEeprom = 0x1234 - wCheckSum; 2769 trm_write_all(pEEpromBuf, iot, ioh); 2770 } 2771 } 2772 2773 /* 2774 * ------------------------------------------------------------ 2775 * Function : trm_initAdapter 2776 * Purpose : initialize the SCSI chip ctrl registers 2777 * Inputs : psh - pointer to this host adapter's structure 2778 * ------------------------------------------------------------ 2779 */ 2780 void 2781 trm_initAdapter(struct trm_softc *sc) 2782 { 2783 const bus_space_handle_t ioh = sc->sc_iohandle; 2784 const bus_space_tag_t iot = sc->sc_iotag; 2785 u_int16_t wval; 2786 u_int8_t bval; 2787 2788 /* 2789 * program configuration 0 2790 */ 2791 if ((sc->sc_config & HCC_PARITY) != 0) { 2792 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 2793 } else { 2794 bval = PHASELATCH | INITIATOR | BLOCKRST; 2795 } 2796 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval); 2797 /* 2798 * program configuration 1 2799 */ 2800 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13); 2801 /* 2802 * 250ms selection timeout 2803 */ 2804 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT); 2805 /* 2806 * Mask all the interrupt 2807 */ 2808 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 2809 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 2810 /* 2811 * Reset SCSI module 2812 */ 2813 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE); 2814 /* 2815 * program Host ID 2816 */ 2817 bval = sc->sc_AdaptSCSIID; 2818 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval); 2819 /* 2820 * set ansynchronous transfer 2821 */ 2822 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0); 2823 /* 2824 * Turn LED control off 2825 */ 2826 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F; 2827 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval); 2828 /* 2829 * DMA config 2830 */ 2831 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE; 2832 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval); 2833 /* 2834 * Clear pending interrupt status 2835 */ 2836 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 2837 /* 2838 * Enable SCSI interrupts 2839 */ 2840 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 2841 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 2842 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 2843 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 2844 } 2845 2846 /* 2847 * ------------------------------------------------------------ 2848 * Function : trm_init 2849 * Purpose : initialize the internal structures for a given SCSI host 2850 * Inputs : host - pointer to this host adapter's structure 2851 * Preconditions : when this function is called, the chip_type field of 2852 * the ACB structure MUST have been set. 2853 * ------------------------------------------------------------ 2854 */ 2855 int 2856 trm_init(struct trm_softc *sc, int unit) 2857 { 2858 const bus_space_handle_t ioh = sc->sc_iohandle; 2859 const bus_space_tag_t iot = sc->sc_iotag; 2860 bus_dma_segment_t seg; 2861 int error, rseg, all_srbs_size; 2862 2863 /* 2864 * EEPROM CHECKSUM 2865 */ 2866 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh); 2867 2868 /* 2869 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 2870 */ 2871 /* 2872 * allocate the space for all SCSI control blocks (SRB) for DMA memory. 2873 */ 2874 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q); 2875 2876 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg, 2877 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 2878 if (error != 0) { 2879 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n", 2880 sc->sc_device.dv_xname, error); 2881 /*errx(error, "%s: unable to allocate SCSI request blocks", 2882 sc->sc_device.dv_xname);*/ 2883 return -1; 2884 } 2885 2886 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size, 2887 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 2888 if (error != 0) { 2889 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n", 2890 sc->sc_device.dv_xname, error); 2891 /*errx(error, "unable to map SCSI request blocks");*/ 2892 return -1; 2893 } 2894 2895 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1, 2896 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control); 2897 if (error != 0) { 2898 printf("%s: unable to create SRB DMA maps, error = %d\n", 2899 sc->sc_device.dv_xname, error); 2900 /*errx(error, "unable to create SRB DMA maps");*/ 2901 return -1; 2902 } 2903 2904 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control, 2905 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT); 2906 if (error != 0) { 2907 printf("%s: unable to load SRB DMA maps, error = %d\n", 2908 sc->sc_device.dv_xname, error); 2909 /*errx(error, "unable to load SRB DMA maps");*/ 2910 return -1; 2911 } 2912 #ifdef TRM_DEBUG0 2913 printf("\n\n%s: all_srbs_size=%x\n", 2914 sc->sc_device.dv_xname, all_srbs_size); 2915 #endif 2916 trm_initACB(sc, unit); 2917 trm_initAdapter(sc); 2918 2919 return 0; 2920 } 2921 2922 /* ------------------------------------------------------------ 2923 * Function : trm_print_info 2924 * Purpose : Print the DCB negotiation information 2925 * Inputs : 2926 * ------------------------------------------------------------ 2927 */ 2928 void 2929 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB) 2930 { 2931 int syncXfer, index; 2932 2933 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC); 2934 2935 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target); 2936 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0) 2937 printf("16 bit "); 2938 else 2939 printf("8 bit "); 2940 2941 if (pDCB->SyncOffset == 0) 2942 printf("Asynchronous "); 2943 else { 2944 syncXfer = 100000 / (trm_clock_period[index] * 4); 2945 printf("%d.%01d MHz, Offset %d ", 2946 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset); 2947 } 2948 printf("data transfers "); 2949 2950 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) 2951 printf("with Tag Queuing"); 2952 2953 printf("\n"); 2954 } 2955