1 /* $OpenBSD: wdc.c,v 1.119 2011/06/10 01:38:46 deraadt Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/conf.h> 60 #include <sys/buf.h> 61 #include <sys/device.h> 62 #include <sys/malloc.h> 63 #include <sys/syslog.h> 64 #include <sys/proc.h> 65 #include <sys/disk.h> 66 #include <sys/pool.h> 67 #include <uvm/uvm_extern.h> 68 69 #include <machine/intr.h> 70 #include <machine/bus.h> 71 72 #include <dev/ata/atavar.h> 73 #include <dev/ata/atareg.h> 74 #include <dev/ic/wdcreg.h> 75 #include <dev/ic/wdcvar.h> 76 #include <dev/ic/wdcevent.h> 77 78 #define WDCDELAY 100 /* 100 microseconds */ 79 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 80 #if 0 81 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 82 #define WDCNDELAY_DEBUG 50 83 #endif /* 0 */ 84 85 struct pool wdc_xfer_pool; 86 87 void __wdcerror(struct channel_softc *, char *); 88 int __wdcwait_reset(struct channel_softc *, int); 89 void __wdccommand_done(struct channel_softc *, struct wdc_xfer *); 90 void __wdccommand_start(struct channel_softc *, struct wdc_xfer *); 91 int __wdccommand_intr(struct channel_softc *, struct wdc_xfer *, int); 92 int wdprint(void *, const char *); 93 void wdc_kill_pending(struct channel_softc *); 94 95 #define DEBUG_INTR 0x01 96 #define DEBUG_XFERS 0x02 97 #define DEBUG_STATUS 0x04 98 #define DEBUG_FUNCS 0x08 99 #define DEBUG_PROBE 0x10 100 #define DEBUG_STATUSX 0x20 101 #define DEBUG_SDRIVE 0x40 102 #define DEBUG_DETACH 0x80 103 104 #ifdef WDCDEBUG 105 #ifndef WDCDEBUG_MASK 106 #define WDCDEBUG_MASK 0x00 107 #endif 108 int wdcdebug_mask = WDCDEBUG_MASK; 109 int wdc_nxfer = 0; 110 #define WDCDEBUG_PRINT(args, level) do { \ 111 if ((wdcdebug_mask & (level)) != 0) \ 112 printf args; \ 113 } while (0) 114 #else 115 #define WDCDEBUG_PRINT(args, level) 116 #endif /* WDCDEBUG */ 117 118 int at_poll = AT_POLL; 119 120 int wdc_floating_bus(struct channel_softc *, int); 121 int wdc_preata_drive(struct channel_softc *, int); 122 int wdc_ata_present(struct channel_softc *, int); 123 124 struct cfdriver wdc_cd = { 125 NULL, "wdc", DV_DULL 126 }; 127 128 struct channel_softc_vtbl wdc_default_vtbl = { 129 wdc_default_read_reg, 130 wdc_default_write_reg, 131 wdc_default_lba48_write_reg, 132 wdc_default_read_raw_multi_2, 133 wdc_default_write_raw_multi_2, 134 wdc_default_read_raw_multi_4, 135 wdc_default_write_raw_multi_4 136 }; 137 138 #ifdef WDCDEBUG 139 static char *wdc_log_buf = NULL; 140 static unsigned int wdc_tail = 0; 141 static unsigned int wdc_head = 0; 142 static unsigned int wdc_log_cap = 16 * 1024; 143 static int chp_idx = 1; 144 145 void 146 wdc_log(struct channel_softc *chp, enum wdcevent_type type, 147 unsigned int size, char val[]) 148 { 149 unsigned int request_size; 150 char *ptr; 151 int log_size; 152 unsigned int head = wdc_head; 153 unsigned int tail = wdc_tail; 154 155 #ifdef DIAGNOSTIC 156 if (head < 0 || head > wdc_log_cap || 157 tail < 0 || tail > wdc_log_cap) { 158 printf ("wdc_log: head %x wdc_tail %x\n", head, 159 tail); 160 return; 161 } 162 163 if (size > wdc_log_cap / 2) { 164 printf ("wdc_log: type %d size %x\n", type, size); 165 return; 166 } 167 #endif 168 169 if (wdc_log_buf == NULL) { 170 wdc_log_buf = malloc(wdc_log_cap, M_DEVBUF, M_NOWAIT); 171 if (wdc_log_buf == NULL) 172 return; 173 } 174 if (chp->ch_log_idx == 0) 175 chp->ch_log_idx = chp_idx++; 176 177 request_size = size + 2; 178 179 /* Check how many bytes are left */ 180 log_size = head - tail; 181 if (log_size < 0) log_size += wdc_log_cap; 182 183 if (log_size + request_size >= wdc_log_cap) { 184 int nb = 0; 185 int rec_size; 186 187 while (nb <= (request_size * 2)) { 188 if (wdc_log_buf[tail] == 0) 189 rec_size = 1; 190 else 191 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 192 tail = (tail + rec_size) % wdc_log_cap; 193 nb += rec_size; 194 } 195 } 196 197 /* Avoid wrapping in the middle of a request */ 198 if (head + request_size >= wdc_log_cap) { 199 memset(&wdc_log_buf[head], 0, wdc_log_cap - head); 200 head = 0; 201 } 202 203 ptr = &wdc_log_buf[head]; 204 *ptr++ = type & 0xff; 205 *ptr++ = ((chp->ch_log_idx & 0x7) << 5) | (size & 0x1f); 206 memcpy(ptr, val, size); 207 208 wdc_head = (head + request_size) % wdc_log_cap; 209 wdc_tail = tail; 210 } 211 212 char *wdc_get_log(unsigned int *, unsigned int *); 213 214 char * 215 wdc_get_log(unsigned int * size, unsigned int *left) 216 { 217 int log_size; 218 char *retbuf = NULL; 219 int nb, tocopy; 220 int s; 221 unsigned int head = wdc_head; 222 unsigned int tail = wdc_tail; 223 224 s = splbio(); 225 226 log_size = (head - tail); 227 if (left != NULL) 228 *left = 0; 229 230 if (log_size < 0) 231 log_size += wdc_log_cap; 232 233 tocopy = log_size; 234 if ((u_int)tocopy > *size) 235 tocopy = *size; 236 237 if (wdc_log_buf == NULL) { 238 *size = 0; 239 *left = 0; 240 goto out; 241 } 242 243 #ifdef DIAGNOSTIC 244 if (head < 0 || head > wdc_log_cap || 245 tail < 0 || tail > wdc_log_cap) { 246 printf ("wdc_log: head %x tail %x\n", head, 247 tail); 248 *size = 0; 249 *left = 0; 250 goto out; 251 } 252 #endif 253 254 retbuf = malloc(tocopy, M_TEMP, M_NOWAIT); 255 if (retbuf == NULL) { 256 *size = 0; 257 *left = log_size; 258 goto out; 259 } 260 261 nb = 0; 262 for (;;) { 263 int rec_size; 264 265 if (wdc_log_buf[tail] == 0) 266 rec_size = 1; 267 else 268 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 269 270 if ((nb + rec_size) >= tocopy) 271 break; 272 273 memcpy(&retbuf[nb], &wdc_log_buf[tail], rec_size); 274 tail = (tail + rec_size) % wdc_log_cap; 275 nb += rec_size; 276 } 277 278 wdc_tail = tail; 279 *size = nb; 280 *left = log_size - nb; 281 282 out: 283 splx(s); 284 return (retbuf); 285 } 286 #endif /* WDCDEBUG */ 287 288 u_int8_t 289 wdc_default_read_reg(struct channel_softc *chp, enum wdc_regs reg) 290 { 291 #ifdef DIAGNOSTIC 292 if (reg & _WDC_WRONLY) { 293 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 294 } 295 #endif /* DIAGNOSTIC */ 296 297 if (reg & _WDC_AUX) 298 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 299 reg & _WDC_REGMASK)); 300 else 301 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 302 reg & _WDC_REGMASK)); 303 } 304 305 void 306 wdc_default_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 307 { 308 #ifdef DIAGNOSTIC 309 if (reg & _WDC_RDONLY) { 310 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 311 } 312 #endif /* DIAGNOSTIC */ 313 314 if (reg & _WDC_AUX) 315 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 316 reg & _WDC_REGMASK, val); 317 else 318 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 319 reg & _WDC_REGMASK, val); 320 } 321 322 void 323 wdc_default_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, 324 u_int16_t val) 325 { 326 /* All registers are two byte deep FIFOs. */ 327 CHP_WRITE_REG(chp, reg, val >> 8); 328 CHP_WRITE_REG(chp, reg, val); 329 } 330 331 void 332 wdc_default_read_raw_multi_2(struct channel_softc *chp, void *data, 333 unsigned int nbytes) 334 { 335 if (data == NULL) { 336 unsigned int i; 337 338 for (i = 0; i < nbytes; i += 2) { 339 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 340 } 341 342 return; 343 } 344 345 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 346 data, nbytes); 347 } 348 349 350 void 351 wdc_default_write_raw_multi_2(struct channel_softc *chp, void *data, 352 unsigned int nbytes) 353 { 354 if (data == NULL) { 355 unsigned int i; 356 357 for (i = 0; i < nbytes; i += 2) { 358 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 359 } 360 361 return; 362 } 363 364 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 365 data, nbytes); 366 } 367 368 369 void 370 wdc_default_write_raw_multi_4(struct channel_softc *chp, void *data, 371 unsigned int nbytes) 372 { 373 if (data == NULL) { 374 unsigned int i; 375 376 for (i = 0; i < nbytes; i += 4) { 377 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 378 } 379 380 return; 381 } 382 383 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 384 data, nbytes); 385 } 386 387 388 void 389 wdc_default_read_raw_multi_4(struct channel_softc *chp, void *data, 390 unsigned int nbytes) 391 { 392 if (data == NULL) { 393 unsigned int i; 394 395 for (i = 0; i < nbytes; i += 4) { 396 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 397 } 398 399 return; 400 } 401 402 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 403 data, nbytes); 404 } 405 406 int 407 wdprint(void *aux, const char *pnp) 408 { 409 struct ata_atapi_attach *aa_link = aux; 410 if (pnp) 411 printf("drive at %s", pnp); 412 printf(" channel %d drive %d", aa_link->aa_channel, 413 aa_link->aa_drv_data->drive); 414 return (UNCONF); 415 } 416 417 void 418 wdc_disable_intr(struct channel_softc *chp) 419 { 420 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 421 } 422 423 void 424 wdc_enable_intr(struct channel_softc *chp) 425 { 426 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 427 } 428 429 void 430 wdc_set_drive(struct channel_softc *chp, int drive) 431 { 432 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_IBM); 433 WDC_LOG_SET_DRIVE(chp, drive); 434 } 435 436 int 437 wdc_floating_bus(struct channel_softc *chp, int drive) 438 { 439 u_int8_t cumulative_status, status; 440 int iter; 441 442 wdc_set_drive(chp, drive); 443 delay(10); 444 445 /* Stolen from Phoenix BIOS Drive Autotyping document */ 446 cumulative_status = 0; 447 for (iter = 0; iter < 100; iter++) { 448 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 449 delay (1); 450 451 status = CHP_READ_REG(chp, wdr_status); 452 453 /* The other bits are meaningless if BSY is set */ 454 if (status & WDCS_BSY) 455 continue; 456 457 cumulative_status |= status; 458 459 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 460 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 461 return 1; 462 } 463 464 465 return 0; 466 } 467 468 int 469 wdc_preata_drive(struct channel_softc *chp, int drive) 470 { 471 if (wdc_floating_bus(chp, drive)) { 472 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 473 chp->wdc->sc_dev.dv_xname, 474 chp->channel, drive), DEBUG_PROBE); 475 return 0; 476 } 477 478 wdc_set_drive(chp, drive); 479 delay(100); 480 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 481 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 482 chp->wdc->sc_dev.dv_xname, 483 chp->channel, drive), DEBUG_PROBE); 484 return 0; 485 } 486 487 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 488 WDC_LOG_ATA_CMDSHORT(chp, WDCC_RECAL); 489 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 490 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 491 chp->wdc->sc_dev.dv_xname, 492 chp->channel, drive), DEBUG_PROBE); 493 return 0; 494 } 495 496 return 1; 497 } 498 499 int 500 wdc_ata_present(struct channel_softc *chp, int drive) 501 { 502 int time_to_done; 503 int retry_cnt = 0; 504 505 wdc_set_drive(chp, drive); 506 delay(10); 507 508 retry: 509 /* 510 You're actually supposed to wait up to 10 seconds 511 for DRDY. However, as a practical matter, most 512 drives assert DRDY very quickly after dropping BSY. 513 514 The 10 seconds wait is sub-optimal because, according 515 to the ATA standard, the master should reply with 00 516 for any reads to a non-existent slave. 517 */ 518 time_to_done = wdc_wait_for_status(chp, 519 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 520 (WDCS_DRDY | WDCS_DSC), 1000); 521 if (time_to_done == -1) { 522 if (retry_cnt == 0 && chp->ch_status == 0x00) { 523 /* At least one flash card needs to be kicked */ 524 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 525 retry_cnt++; 526 goto retry; 527 } 528 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 529 " %02x\n", 530 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 531 chp->channel, drive, chp->ch_status), 532 DEBUG_PROBE); 533 return 0; 534 } 535 536 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 537 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 538 " %02x\n", 539 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 540 chp->channel, drive, chp->ch_status), 541 DEBUG_PROBE); 542 543 return 0; 544 } 545 546 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 547 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 548 chp->channel, drive, time_to_done), DEBUG_PROBE); 549 550 /* 551 * Test register writability 552 */ 553 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 554 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 555 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 556 DELAY(10); 557 558 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 559 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 560 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 561 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 562 chp->channel, drive), DEBUG_PROBE); 563 return 0; 564 } 565 566 return 1; 567 } 568 569 570 /* 571 * Test to see controller with at least one attached drive is there. 572 * Returns a bit for each possible drive found (0x01 for drive 0, 573 * 0x02 for drive 1). 574 * Logic: 575 * - If a status register is at 0x7f or 0xff, assume there is no drive here 576 * (ISA has pull-up resistors). Similarly if the status register has 577 * the value we last wrote to the bus (for IDE interfaces without pullups). 578 * If no drive at all -> return. 579 * - reset the controller, wait for it to complete (may take up to 31s !). 580 * If timeout -> return. 581 * - test ATA/ATAPI signatures. If at last one drive found -> return. 582 * - try an ATA command on the master. 583 */ 584 585 int 586 wdcprobe(struct channel_softc *chp) 587 { 588 u_int8_t st0, st1, sc, sn, cl, ch; 589 u_int8_t ret_value = 0x03; 590 u_int8_t drive; 591 #ifdef WDCDEBUG 592 int savedmask = wdcdebug_mask; 593 #endif 594 595 if (chp->_vtbl == 0) { 596 int s = splbio(); 597 chp->_vtbl = &wdc_default_vtbl; 598 splx(s); 599 } 600 601 #ifdef WDCDEBUG 602 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 603 (chp->wdc && 604 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 605 wdcdebug_mask |= DEBUG_PROBE; 606 #endif /* WDCDEBUG */ 607 608 if (chp->wdc == NULL || 609 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 610 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 611 wdc_set_drive(chp, 0); 612 delay(10); 613 st0 = CHP_READ_REG(chp, wdr_status); 614 WDC_LOG_STATUS(chp, st0); 615 wdc_set_drive(chp, 1); 616 delay(10); 617 st1 = CHP_READ_REG(chp, wdr_status); 618 WDC_LOG_STATUS(chp, st1); 619 620 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%b, st1=0x%b\n", 621 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 622 chp->channel, st0, WDCS_BITS, st1, WDCS_BITS), 623 DEBUG_PROBE); 624 625 if (st0 == 0xff || st0 == WDSD_IBM) 626 ret_value &= ~0x01; 627 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 628 ret_value &= ~0x02; 629 if (ret_value == 0) 630 return 0; 631 } 632 633 /* reset the channel */ 634 wdc_do_reset(chp); 635 636 ret_value = __wdcwait_reset(chp, ret_value); 637 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 638 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 639 ret_value), DEBUG_PROBE); 640 641 if (ret_value == 0) 642 return 0; 643 644 /* 645 * Use signatures to find potential ATAPI drives 646 */ 647 for (drive = 0; drive < 2; drive++) { 648 if ((ret_value & (0x01 << drive)) == 0) 649 continue; 650 wdc_set_drive(chp, drive); 651 delay(10); 652 /* Save registers contents */ 653 st0 = CHP_READ_REG(chp, wdr_status); 654 sc = CHP_READ_REG(chp, wdr_seccnt); 655 sn = CHP_READ_REG(chp, wdr_sector); 656 cl = CHP_READ_REG(chp, wdr_cyl_lo); 657 ch = CHP_READ_REG(chp, wdr_cyl_hi); 658 WDC_LOG_REG(chp, wdr_cyl_lo, (ch << 8) | cl); 659 660 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%b, sc=0x%x" 661 " sn=0x%x cl=0x%x ch=0x%x\n", 662 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 663 chp->channel, drive, st0, WDCS_BITS, sc, sn, cl, ch), 664 DEBUG_PROBE); 665 /* 666 * This is a simplification of the test in the ATAPI 667 * spec since not all drives seem to set the other regs 668 * correctly. 669 */ 670 if (cl == 0x14 && ch == 0xeb) 671 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 672 } 673 674 /* 675 * Detect ATA drives by poking around the registers 676 */ 677 for (drive = 0; drive < 2; drive++) { 678 if ((ret_value & (0x01 << drive)) == 0) 679 continue; 680 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 681 continue; 682 683 wdc_disable_intr(chp); 684 /* ATA detect */ 685 if (wdc_ata_present(chp, drive)) { 686 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 687 if (chp->wdc == NULL || 688 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 689 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 690 } else { 691 ret_value &= ~(1 << drive); 692 } 693 wdc_enable_intr(chp); 694 } 695 696 #ifdef WDCDEBUG 697 wdcdebug_mask = savedmask; 698 #endif 699 return (ret_value); 700 } 701 702 struct channel_queue * 703 wdc_alloc_queue(void) 704 { 705 static int inited = 0; 706 struct channel_queue *queue; 707 708 /* Initialize global data. */ 709 if (inited == 0) { 710 /* Initialize the wdc_xfer pool. */ 711 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 712 0, 0, "wdcspl", NULL); 713 inited = 1; 714 } 715 716 queue = malloc(sizeof(*queue), M_DEVBUF, M_NOWAIT); 717 if (queue != NULL) { 718 TAILQ_INIT(&queue->sc_xfer); 719 } 720 return (queue); 721 } 722 723 void 724 wdc_free_queue(struct channel_queue *queue) 725 { 726 free(queue, M_DEVBUF); 727 } 728 729 void 730 wdcattach(struct channel_softc *chp) 731 { 732 int i; 733 struct ata_atapi_attach aa_link; 734 #ifdef WDCDEBUG 735 int savedmask = wdcdebug_mask; 736 #endif 737 738 if (!cold) 739 at_poll = AT_WAIT; 740 741 if (chp->wdc->reset == NULL) 742 chp->wdc->reset = wdc_do_reset; 743 744 timeout_set(&chp->ch_timo, wdctimeout, chp); 745 746 if (!chp->_vtbl) 747 chp->_vtbl = &wdc_default_vtbl; 748 749 for (i = 0; i < 2; i++) { 750 chp->ch_drive[i].chnl_softc = chp; 751 chp->ch_drive[i].drive = i; 752 } 753 754 if (chp->wdc->drv_probe != NULL) { 755 chp->wdc->drv_probe(chp); 756 } else { 757 if (wdcprobe(chp) == 0) 758 /* If no drives, abort attach here. */ 759 return; 760 } 761 762 /* ATAPI drives need settling time. Give them 250ms */ 763 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 764 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 765 delay(250 * 1000); 766 } 767 768 #ifdef WDCDEBUG 769 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 770 wdcdebug_mask |= DEBUG_PROBE; 771 772 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 773 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 774 wdcdebug_mask = DEBUG_PROBE; 775 } 776 #endif /* WDCDEBUG */ 777 778 for (i = 0; i < 2; i++) { 779 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 780 781 /* If controller can't do 16bit flag the drives as 32bit */ 782 if ((chp->wdc->cap & 783 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 784 WDC_CAPABILITY_DATA32) 785 drvp->drive_flags |= DRIVE_CAP32; 786 787 if ((drvp->drive_flags & DRIVE) == 0) 788 continue; 789 790 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 791 chp->ch_flags |= WDCF_ONESLAVE; 792 /* 793 * Wait a bit, some devices are weird just after a reset. 794 * Then issue a IDENTIFY command, to try to detect slave ghost. 795 */ 796 delay(5000); 797 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 798 CMD_OK) { 799 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 800 drvp->drive_flags &= ~DRIVE_OLD; 801 } else { 802 bzero(&drvp->id, sizeof(struct ataparams)); 803 drvp->drive_flags &= 804 ~(DRIVE_ATA | DRIVE_ATAPI); 805 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 806 chp->wdc->sc_dev.dv_xname, 807 chp->channel, i), DEBUG_PROBE); 808 809 if ((drvp->drive_flags & DRIVE_OLD) && 810 !wdc_preata_drive(chp, i)) 811 drvp->drive_flags &= ~DRIVE_OLD; 812 } 813 } 814 815 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 816 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 817 DEBUG_PROBE); 818 819 /* If no drives, abort here */ 820 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 821 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 822 goto exit; 823 824 for (i = 0; i < 2; i++) { 825 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 826 continue; 827 } 828 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 829 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 830 aa_link.aa_type = T_ATAPI; 831 else 832 aa_link.aa_type = T_ATA; 833 aa_link.aa_channel = chp->channel; 834 aa_link.aa_openings = 1; 835 aa_link.aa_drv_data = &chp->ch_drive[i]; 836 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 837 } 838 839 /* 840 * reset drive_flags for unattached devices, reset state for attached 841 * ones 842 */ 843 for (i = 0; i < 2; i++) { 844 if (chp->ch_drive[i].drive_name[0] == 0) 845 chp->ch_drive[i].drive_flags = 0; 846 } 847 848 exit: 849 #ifdef WDCDEBUG 850 wdcdebug_mask = savedmask; 851 #endif 852 return; /* for the ``exit'' label above */ 853 } 854 855 /* 856 * Start I/O on a controller, for the given channel. 857 * The first xfer may be not for our channel if the channel queues 858 * are shared. 859 */ 860 void 861 wdcstart(struct channel_softc *chp) 862 { 863 struct wdc_xfer *xfer; 864 865 splassert(IPL_BIO); 866 867 /* is there a xfer ? */ 868 if ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) == NULL) { 869 return; 870 } 871 872 /* adjust chp, in case we have a shared queue */ 873 chp = xfer->chp; 874 875 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 876 return; /* channel already active */ 877 } 878 #ifdef DIAGNOSTIC 879 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 880 panic("wdcstart: channel waiting for irq"); 881 #endif /* DIAGNOSTIC */ 882 883 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 884 chp->channel, xfer->drive), DEBUG_XFERS); 885 chp->ch_flags |= WDCF_ACTIVE; 886 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 887 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 888 chp->ch_drive[xfer->drive].state = 0; 889 } 890 xfer->c_start(chp, xfer); 891 } 892 893 int 894 wdcdetach(struct channel_softc *chp, int flags) 895 { 896 int s, rv; 897 898 s = splbio(); 899 chp->dying = 1; 900 901 wdc_kill_pending(chp); 902 timeout_del(&chp->ch_timo); 903 904 rv = config_detach_children((struct device *)chp->wdc, flags); 905 splx(s); 906 907 return (rv); 908 } 909 910 /* 911 * Interrupt routine for the controller. Acknowledge the interrupt, check for 912 * errors on the current operation, mark it done if necessary, and start the 913 * next request. Also check for a partially done transfer, and continue with 914 * the next chunk if so. 915 */ 916 int 917 wdcintr(void *arg) 918 { 919 struct channel_softc *chp = arg; 920 struct wdc_xfer *xfer; 921 u_int8_t st = 0; 922 int ret = 0; 923 924 /* Acknowledge interrupt by reading status */ 925 if (chp->_vtbl == 0) 926 st = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 927 wdr_status & _WDC_REGMASK); 928 else 929 st = CHP_READ_REG(chp, wdr_status); 930 if (st == 0xff) 931 return (-1); 932 933 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 934 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 935 return ret; 936 } 937 938 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 939 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 940 if (chp->ch_flags & WDCF_DMA_WAIT) { 941 chp->wdc->dma_status = 942 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 943 xfer->drive, 0); 944 if (chp->wdc->dma_status == 0xff) 945 return (-1); 946 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 947 /* IRQ not for us, not detected by DMA engine */ 948 return 0; 949 } 950 chp->ch_flags &= ~WDCF_DMA_WAIT; 951 } 952 953 chp->ch_flags &= ~WDCF_IRQ_WAIT; 954 ret = xfer->c_intr(chp, xfer, 1); 955 if (ret == 0) /* irq was not for us, still waiting for irq */ 956 chp->ch_flags |= WDCF_IRQ_WAIT; 957 return (ret); 958 } 959 960 /* Put all disk in RESET state */ 961 void 962 wdc_reset_channel(struct ata_drive_datas *drvp, int nowait) 963 { 964 struct channel_softc *chp = drvp->chnl_softc; 965 int drive; 966 967 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 968 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 969 DEBUG_FUNCS); 970 (void) wdcreset(chp, nowait ? NOWAIT : VERBOSE); 971 for (drive = 0; drive < 2; drive++) { 972 chp->ch_drive[drive].state = 0; 973 } 974 } 975 976 int 977 wdcreset(struct channel_softc *chp, int flags) 978 { 979 int drv_mask1, drv_mask2; 980 981 if (!chp->_vtbl) 982 chp->_vtbl = &wdc_default_vtbl; 983 984 chp->wdc->reset(chp); 985 986 if (flags & NOWAIT) 987 return 0; 988 989 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 990 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 991 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 992 993 if ((flags & VERBOSE) && drv_mask2 != drv_mask1) { 994 printf("%s channel %d: reset failed for", 995 chp->wdc->sc_dev.dv_xname, chp->channel); 996 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 997 printf(" drive 0"); 998 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 999 printf(" drive 1"); 1000 printf("\n"); 1001 } 1002 1003 return (drv_mask1 != drv_mask2) ? 1 : 0; 1004 } 1005 1006 void 1007 wdc_do_reset(struct channel_softc *chp) 1008 { 1009 wdc_set_drive(chp, 0); 1010 DELAY(10); 1011 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT | WDCTL_RST); 1012 delay(10000); 1013 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 1014 delay(10000); 1015 } 1016 1017 int 1018 __wdcwait_reset(struct channel_softc *chp, int drv_mask) 1019 { 1020 int timeout; 1021 u_int8_t st0, er0, st1, er1; 1022 1023 /* wait for BSY to deassert */ 1024 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 1025 wdc_set_drive(chp, 0); 1026 delay(10); 1027 st0 = CHP_READ_REG(chp, wdr_status); 1028 er0 = CHP_READ_REG(chp, wdr_error); 1029 wdc_set_drive(chp, 1); 1030 delay(10); 1031 st1 = CHP_READ_REG(chp, wdr_status); 1032 er1 = CHP_READ_REG(chp, wdr_error); 1033 1034 if ((drv_mask & 0x01) == 0) { 1035 /* no master */ 1036 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1037 /* No master, slave is ready, it's done */ 1038 goto end; 1039 } 1040 } else if ((drv_mask & 0x02) == 0) { 1041 /* no slave */ 1042 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1043 /* No slave, master is ready, it's done */ 1044 goto end; 1045 } 1046 } else { 1047 /* Wait for both master and slave to be ready */ 1048 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1049 goto end; 1050 } 1051 } 1052 delay(WDCDELAY); 1053 } 1054 /* Reset timed out. Maybe it's because drv_mask was not right */ 1055 if (st0 & WDCS_BSY) 1056 drv_mask &= ~0x01; 1057 if (st1 & WDCS_BSY) 1058 drv_mask &= ~0x02; 1059 end: 1060 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%b, er0=0x%x, " 1061 "st1=0x%b, er1=0x%x, reset time=%d msec\n", 1062 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1063 st0, WDCS_BITS, er0, st1, WDCS_BITS, er1, 1064 timeout * WDCDELAY / 1000), DEBUG_PROBE); 1065 1066 return drv_mask; 1067 } 1068 1069 /* 1070 * Wait for a drive to be !BSY, and have mask in its status register. 1071 * return -1 for a timeout after "timeout" ms. 1072 */ 1073 int 1074 wdc_wait_for_status(struct channel_softc *chp, int mask, int bits, int timeout) 1075 { 1076 u_char status; 1077 int time = 0; 1078 1079 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1080 :"none", chp->channel), DEBUG_STATUS); 1081 chp->ch_error = 0; 1082 1083 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1084 1085 for (;;) { 1086 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 1087 WDC_LOG_STATUS(chp, chp->ch_status); 1088 1089 if (status == 0xff) { 1090 if ((chp->ch_flags & WDCF_ONESLAVE)) { 1091 wdc_set_drive(chp, 1); 1092 chp->ch_status = status = 1093 CHP_READ_REG(chp, wdr_status); 1094 WDC_LOG_STATUS(chp, chp->ch_status); 1095 } 1096 } 1097 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 1098 break; 1099 if (++time > timeout) { 1100 WDCDEBUG_PRINT(("wdcwait: timeout, status 0x%b " 1101 "error 0x%x\n", status, WDCS_BITS, 1102 CHP_READ_REG(chp, wdr_error)), 1103 DEBUG_STATUSX | DEBUG_STATUS); 1104 return -1; 1105 } 1106 delay(WDCDELAY); 1107 } 1108 if (status & WDCS_ERR) { 1109 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1110 WDC_LOG_ERROR(chp, chp->ch_error); 1111 1112 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1113 DEBUG_STATUSX | DEBUG_STATUS); 1114 } 1115 1116 #ifdef WDCNDELAY_DEBUG 1117 /* After autoconfig, there should be no long delays. */ 1118 if (!cold && time > WDCNDELAY_DEBUG) { 1119 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1120 if (xfer == NULL) 1121 printf("%s channel %d: warning: busy-wait took %dus\n", 1122 chp->wdc->sc_dev.dv_xname, chp->channel, 1123 WDCDELAY * time); 1124 else 1125 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1126 chp->wdc->sc_dev.dv_xname, chp->channel, 1127 xfer->drive, 1128 WDCDELAY * time); 1129 } 1130 #endif /* WDCNDELAY_DEBUG */ 1131 return time; 1132 } 1133 1134 /* 1135 * Busy-wait for DMA to complete 1136 */ 1137 int 1138 wdc_dmawait(struct channel_softc *chp, struct wdc_xfer *xfer, int timeout) 1139 { 1140 int time; 1141 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1142 chp->wdc->dma_status = 1143 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1144 chp->channel, xfer->drive, 0); 1145 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1146 return 0; 1147 if (chp->wdc->dma_status == 0xff) { 1148 chp->dying = 1; 1149 return -1; 1150 } 1151 delay(WDCDELAY); 1152 } 1153 /* timeout, force a DMA halt */ 1154 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1155 chp->channel, xfer->drive, 1); 1156 return 1; 1157 } 1158 1159 void 1160 wdctimeout(void *arg) 1161 { 1162 struct channel_softc *chp = (struct channel_softc *)arg; 1163 struct wdc_xfer *xfer; 1164 int s; 1165 1166 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1167 1168 s = splbio(); 1169 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1170 1171 /* Did we lose a race with the interrupt? */ 1172 if (xfer == NULL || 1173 !timeout_triggered(&chp->ch_timo)) { 1174 splx(s); 1175 return; 1176 } 1177 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1178 __wdcerror(chp, "timeout"); 1179 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1180 "atapi":"ata"); 1181 printf("\tc_bcount: %d\n", xfer->c_bcount); 1182 printf("\tc_skip: %d\n", xfer->c_skip); 1183 if (chp->ch_flags & WDCF_DMA_WAIT) { 1184 chp->wdc->dma_status = 1185 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1186 chp->channel, xfer->drive, 1); 1187 chp->ch_flags &= ~WDCF_DMA_WAIT; 1188 } 1189 /* 1190 * Call the interrupt routine. If we just missed and interrupt, 1191 * it will do what's needed. Else, it will take the needed 1192 * action (reset the device). 1193 */ 1194 xfer->c_flags |= C_TIMEOU; 1195 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1196 xfer->c_intr(chp, xfer, 1); 1197 } else 1198 __wdcerror(chp, "missing untimeout"); 1199 splx(s); 1200 } 1201 1202 /* 1203 * Probe drive's capabilities, for use by the controller later. 1204 * Assumes drvp points to an existing drive. 1205 * XXX this should be a controller-indep function 1206 */ 1207 void 1208 wdc_probe_caps(struct ata_drive_datas *drvp, struct ataparams *params) 1209 { 1210 struct channel_softc *chp = drvp->chnl_softc; 1211 struct wdc_softc *wdc = chp->wdc; 1212 int i, valid_mode_found; 1213 int cf_flags = drvp->cf_flags; 1214 1215 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1216 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1217 struct ataparams params2; 1218 1219 /* 1220 * Controller claims 16 and 32 bit transfers. 1221 * Re-do an IDENTIFY with 32-bit transfers, 1222 * and compare results. 1223 */ 1224 drvp->drive_flags |= DRIVE_CAP32; 1225 ata_get_params(drvp, at_poll, ¶ms2); 1226 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1227 /* Not good. fall back to 16bits */ 1228 drvp->drive_flags &= ~DRIVE_CAP32; 1229 } 1230 } 1231 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1232 if (params->atap_ata_major > 0x01 && 1233 params->atap_ata_major != 0xffff) { 1234 for (i = 14; i > 0; i--) { 1235 if (params->atap_ata_major & (1 << i)) { 1236 printf("%sATA version %d\n", sep, i); 1237 drvp->ata_vers = i; 1238 break; 1239 } 1240 } 1241 } else 1242 #endif /* 0 */ 1243 /* Use PIO mode 3 as a default value for ATAPI devices */ 1244 if (drvp->drive_flags & DRIVE_ATAPI) 1245 drvp->PIO_mode = 3; 1246 1247 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap 0x%x cf_flags 0x%x\n", 1248 wdc->cap, cf_flags), DEBUG_PROBE); 1249 1250 valid_mode_found = 0; 1251 1252 WDCDEBUG_PRINT(("%s: atap_oldpiotiming=%d\n", __func__, 1253 params->atap_oldpiotiming), DEBUG_PROBE); 1254 /* 1255 * ATA-4 compliant devices contain PIO mode 1256 * number in atap_oldpiotiming. 1257 */ 1258 if (params->atap_oldpiotiming <= 2) { 1259 drvp->PIO_cap = params->atap_oldpiotiming; 1260 valid_mode_found = 1; 1261 drvp->drive_flags |= DRIVE_MODE; 1262 } else if (params->atap_oldpiotiming > 180) { 1263 /* 1264 * ATA-2 compliant devices contain cycle 1265 * time in atap_oldpiotiming. 1266 * A device with a cycle time of 180ns 1267 * or less is at least PIO mode 3 and 1268 * should be reporting that in 1269 * atap_piomode_supp, so ignore it here. 1270 */ 1271 if (params->atap_oldpiotiming <= 240) { 1272 drvp->PIO_cap = 2; 1273 } else { 1274 drvp->PIO_cap = 1; 1275 } 1276 valid_mode_found = 1; 1277 drvp->drive_flags |= DRIVE_MODE; 1278 } 1279 if (valid_mode_found) 1280 drvp->PIO_mode = drvp->PIO_cap; 1281 1282 WDCDEBUG_PRINT(("%s: atap_extensions=0x%x, atap_piomode_supp=0x%x, " 1283 "atap_dmamode_supp=0x%x, atap_udmamode_supp=0x%x\n", 1284 __func__, params->atap_extensions, params->atap_piomode_supp, 1285 params->atap_dmamode_supp, params->atap_udmamode_supp), 1286 DEBUG_PROBE); 1287 1288 /* 1289 * It's not in the specs, but it seems that some drive 1290 * returns 0xffff in atap_extensions when this field is invalid 1291 */ 1292 if (params->atap_extensions != 0xffff && 1293 (params->atap_extensions & WDC_EXT_MODES)) { 1294 /* 1295 * XXX some drives report something wrong here (they claim to 1296 * support PIO mode 8 !). As mode is coded on 3 bits in 1297 * SET FEATURE, limit it to 7 (so limit i to 4). 1298 * If higher mode than 7 is found, abort. 1299 */ 1300 for (i = 7; i >= 0; i--) { 1301 if ((params->atap_piomode_supp & (1 << i)) == 0) 1302 continue; 1303 if (i > 4) 1304 return; 1305 1306 valid_mode_found = 1; 1307 1308 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1309 drvp->PIO_cap = i + 3; 1310 continue; 1311 } 1312 1313 /* 1314 * See if mode is accepted. 1315 * If the controller can't set its PIO mode, 1316 * assume the BIOS set it up correctly 1317 */ 1318 if (ata_set_mode(drvp, 0x08 | (i + 3), 1319 at_poll) != CMD_OK) 1320 continue; 1321 1322 /* 1323 * If controller's driver can't set its PIO mode, 1324 * set the highest one the controller supports 1325 */ 1326 if (wdc->PIO_cap >= i + 3) { 1327 drvp->PIO_mode = i + 3; 1328 drvp->PIO_cap = i + 3; 1329 break; 1330 } 1331 } 1332 if (!valid_mode_found) { 1333 /* 1334 * We didn't find a valid PIO mode. 1335 * Assume the values returned for DMA are buggy too 1336 */ 1337 return; 1338 } 1339 drvp->drive_flags |= DRIVE_MODE; 1340 1341 /* Some controllers don't support ATAPI DMA */ 1342 if ((drvp->drive_flags & DRIVE_ATAPI) && 1343 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1344 return; 1345 1346 valid_mode_found = 0; 1347 for (i = 7; i >= 0; i--) { 1348 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1349 continue; 1350 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1351 (wdc->cap & WDC_CAPABILITY_MODE)) 1352 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1353 != CMD_OK) 1354 continue; 1355 1356 valid_mode_found = 1; 1357 1358 if (wdc->cap & WDC_CAPABILITY_DMA) { 1359 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1360 wdc->DMA_cap < i) 1361 continue; 1362 drvp->DMA_mode = i; 1363 drvp->DMA_cap = i; 1364 drvp->drive_flags |= DRIVE_DMA; 1365 } 1366 break; 1367 } 1368 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1369 for (i = 7; i >= 0; i--) { 1370 if ((params->atap_udmamode_supp & (1 << i)) 1371 == 0) 1372 continue; 1373 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1374 (wdc->cap & WDC_CAPABILITY_UDMA)) 1375 if (ata_set_mode(drvp, 0x40 | i, 1376 at_poll) != CMD_OK) 1377 continue; 1378 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1379 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1380 wdc->UDMA_cap < i) 1381 continue; 1382 drvp->UDMA_mode = i; 1383 drvp->UDMA_cap = i; 1384 drvp->drive_flags |= DRIVE_UDMA; 1385 } 1386 break; 1387 } 1388 } 1389 } 1390 1391 /* Try to guess ATA version here, if it didn't get reported */ 1392 if (drvp->ata_vers == 0) { 1393 if (drvp->drive_flags & DRIVE_UDMA) 1394 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1395 else if (drvp->PIO_cap > 2) 1396 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1397 } 1398 if (cf_flags & ATA_CONFIG_PIO_SET) { 1399 drvp->PIO_mode = 1400 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1401 drvp->drive_flags |= DRIVE_MODE; 1402 } 1403 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1404 /* don't care about DMA modes */ 1405 return; 1406 } 1407 if (cf_flags & ATA_CONFIG_DMA_SET) { 1408 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1409 ATA_CONFIG_DMA_DISABLE) { 1410 drvp->drive_flags &= ~DRIVE_DMA; 1411 } else { 1412 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1413 ATA_CONFIG_DMA_OFF; 1414 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1415 } 1416 } 1417 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1418 /* don't care about UDMA modes */ 1419 return; 1420 } 1421 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1422 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1423 ATA_CONFIG_UDMA_DISABLE) { 1424 drvp->drive_flags &= ~DRIVE_UDMA; 1425 } else { 1426 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1427 ATA_CONFIG_UDMA_OFF; 1428 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1429 } 1430 } 1431 } 1432 1433 void 1434 wdc_output_bytes(struct ata_drive_datas *drvp, void *bytes, unsigned int buflen) 1435 { 1436 struct channel_softc *chp = drvp->chnl_softc; 1437 unsigned int off = 0; 1438 unsigned int len = buflen, roundlen; 1439 1440 if (drvp->drive_flags & DRIVE_CAP32) { 1441 roundlen = len & ~3; 1442 1443 CHP_WRITE_RAW_MULTI_4(chp, 1444 (void *)((u_int8_t *)bytes + off), roundlen); 1445 1446 off += roundlen; 1447 len -= roundlen; 1448 } 1449 1450 if (len > 0) { 1451 roundlen = (len + 1) & ~0x1; 1452 1453 CHP_WRITE_RAW_MULTI_2(chp, 1454 (void *)((u_int8_t *)bytes + off), roundlen); 1455 } 1456 } 1457 1458 void 1459 wdc_input_bytes(struct ata_drive_datas *drvp, void *bytes, unsigned int buflen) 1460 { 1461 struct channel_softc *chp = drvp->chnl_softc; 1462 unsigned int off = 0; 1463 unsigned int len = buflen, roundlen; 1464 1465 if (drvp->drive_flags & DRIVE_CAP32) { 1466 roundlen = len & ~3; 1467 1468 CHP_READ_RAW_MULTI_4(chp, 1469 (void *)((u_int8_t *)bytes + off), roundlen); 1470 1471 off += roundlen; 1472 len -= roundlen; 1473 } 1474 1475 if (len > 0) { 1476 roundlen = (len + 1) & ~0x1; 1477 1478 CHP_READ_RAW_MULTI_2(chp, 1479 (void *)((u_int8_t *)bytes + off), roundlen); 1480 } 1481 } 1482 1483 void 1484 wdc_print_caps(struct ata_drive_datas *drvp) 1485 { 1486 /* This is actually a lie until we fix the _probe_caps 1487 algorithm. Don't print out lies */ 1488 #if 0 1489 printf("%s: can use ", drvp->drive_name); 1490 1491 if (drvp->drive_flags & DRIVE_CAP32) { 1492 printf("32-bit"); 1493 } else 1494 printf("16-bit"); 1495 1496 printf(", PIO mode %d", drvp->PIO_cap); 1497 1498 if (drvp->drive_flags & DRIVE_DMA) { 1499 printf(", DMA mode %d", drvp->DMA_cap); 1500 } 1501 1502 if (drvp->drive_flags & DRIVE_UDMA) { 1503 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1504 } 1505 1506 printf("\n"); 1507 #endif /* 0 */ 1508 } 1509 1510 void 1511 wdc_print_current_modes(struct channel_softc *chp) 1512 { 1513 int drive; 1514 struct ata_drive_datas *drvp; 1515 1516 for (drive = 0; drive < 2; drive++) { 1517 drvp = &chp->ch_drive[drive]; 1518 if ((drvp->drive_flags & DRIVE) == 0) 1519 continue; 1520 1521 printf("%s(%s:%d:%d):", 1522 drvp->drive_name, 1523 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1524 1525 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1526 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1527 printf(" using BIOS timings"); 1528 else 1529 printf(" using PIO mode %d", drvp->PIO_mode); 1530 if (drvp->drive_flags & DRIVE_DMA) 1531 printf(", DMA mode %d", drvp->DMA_mode); 1532 if (drvp->drive_flags & DRIVE_UDMA) 1533 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1534 printf("\n"); 1535 } 1536 } 1537 1538 /* 1539 * downgrade the transfer mode of a drive after an error. return 1 if 1540 * downgrade was possible, 0 otherwise. 1541 */ 1542 int 1543 wdc_downgrade_mode(struct ata_drive_datas *drvp) 1544 { 1545 struct channel_softc *chp = drvp->chnl_softc; 1546 struct wdc_softc *wdc = chp->wdc; 1547 int cf_flags = drvp->cf_flags; 1548 1549 /* if drive or controller don't know its mode, we can't do much */ 1550 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1551 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1552 return 0; 1553 /* current drive mode was set by a config flag, let it this way */ 1554 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1555 (cf_flags & ATA_CONFIG_DMA_SET) || 1556 (cf_flags & ATA_CONFIG_UDMA_SET)) 1557 return 0; 1558 1559 /* 1560 * We'd ideally like to use an Ultra DMA mode since they have the 1561 * protection of a CRC. So we try each Ultra DMA mode and see if 1562 * we can find any working combo 1563 */ 1564 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1565 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1566 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1567 drvp->drive_name, drvp->UDMA_mode); 1568 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1569 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1570 /* 1571 * If we were using ultra-DMA, don't downgrade to 1572 * multiword DMA if we noticed a CRC error. It has 1573 * been noticed that CRC errors in ultra-DMA lead to 1574 * silent data corruption in multiword DMA. Data 1575 * corruption is less likely to occur in PIO mode. 1576 */ 1577 drvp->drive_flags &= ~DRIVE_UDMA; 1578 drvp->drive_flags |= DRIVE_DMA; 1579 drvp->DMA_mode = drvp->DMA_cap; 1580 printf("%s: transfer error, downgrading to DMA mode %d\n", 1581 drvp->drive_name, drvp->DMA_mode); 1582 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1583 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1584 drvp->PIO_mode = drvp->PIO_cap; 1585 printf("%s: transfer error, downgrading to PIO mode %d\n", 1586 drvp->drive_name, drvp->PIO_mode); 1587 } else /* already using PIO, can't downgrade */ 1588 return 0; 1589 1590 wdc->set_modes(chp); 1591 /* reset the channel, which will schedule all drives for setup */ 1592 wdc_reset_channel(drvp, 0); 1593 return 1; 1594 } 1595 1596 int 1597 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1598 { 1599 struct channel_softc *chp = drvp->chnl_softc; 1600 struct wdc_xfer *xfer; 1601 int s, ret; 1602 1603 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1604 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1605 DEBUG_FUNCS); 1606 1607 /* set up an xfer and queue. Wait for completion */ 1608 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1609 WDC_NOSLEEP); 1610 if (xfer == NULL) { 1611 return WDC_TRY_AGAIN; 1612 } 1613 1614 if (wdc_c->flags & AT_POLL) 1615 xfer->c_flags |= C_POLL; 1616 xfer->drive = drvp->drive; 1617 xfer->databuf = wdc_c->data; 1618 xfer->c_bcount = wdc_c->bcount; 1619 xfer->cmd = wdc_c; 1620 xfer->c_start = __wdccommand_start; 1621 xfer->c_intr = __wdccommand_intr; 1622 xfer->c_kill_xfer = __wdccommand_done; 1623 1624 s = splbio(); 1625 wdc_exec_xfer(chp, xfer); 1626 #ifdef DIAGNOSTIC 1627 if ((wdc_c->flags & AT_POLL) != 0 && 1628 (wdc_c->flags & AT_DONE) == 0) 1629 panic("wdc_exec_command: polled command not done"); 1630 #endif /* DIAGNOSTIC */ 1631 if (wdc_c->flags & AT_DONE) { 1632 ret = WDC_COMPLETE; 1633 } else { 1634 if (wdc_c->flags & AT_WAIT) { 1635 WDCDEBUG_PRINT(("wdc_exec_command sleeping\n"), 1636 DEBUG_FUNCS); 1637 1638 while ((wdc_c->flags & AT_DONE) == 0) { 1639 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1640 } 1641 ret = WDC_COMPLETE; 1642 } else { 1643 ret = WDC_QUEUED; 1644 } 1645 } 1646 splx(s); 1647 return ret; 1648 } 1649 1650 void 1651 __wdccommand_start(struct channel_softc *chp, struct wdc_xfer *xfer) 1652 { 1653 int drive = xfer->drive; 1654 struct wdc_command *wdc_c = xfer->cmd; 1655 1656 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1657 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1658 DEBUG_FUNCS); 1659 1660 /* 1661 * Disable interrupts if we're polling 1662 */ 1663 if (xfer->c_flags & C_POLL) { 1664 wdc_disable_intr(chp); 1665 } 1666 1667 wdc_set_drive(chp, drive); 1668 DELAY(1); 1669 1670 /* 1671 * For resets, we don't really care to make sure that 1672 * the bus is free 1673 */ 1674 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1675 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1676 wdc_c->r_st_bmask, wdc_c->timeout) != 0) { 1677 goto timeout; 1678 } 1679 } else 1680 DELAY(10); 1681 1682 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1683 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1684 1685 if ((wdc_c->flags & AT_WRITE) == AT_WRITE) { 1686 /* wait at least 400ns before reading status register */ 1687 DELAY(10); 1688 if (wait_for_unbusy(chp, wdc_c->timeout) != 0) 1689 goto timeout; 1690 1691 if ((chp->ch_status & (WDCS_DRQ | WDCS_ERR)) == WDCS_ERR) { 1692 __wdccommand_done(chp, xfer); 1693 return; 1694 } 1695 1696 if (wait_for_drq(chp, wdc_c->timeout) != 0) 1697 goto timeout; 1698 1699 wdc_output_bytes(&chp->ch_drive[drive], 1700 wdc_c->data, wdc_c->bcount); 1701 } 1702 1703 if ((wdc_c->flags & AT_POLL) == 0) { 1704 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1705 timeout_add_msec(&chp->ch_timo, wdc_c->timeout); 1706 return; 1707 } 1708 1709 /* 1710 * Polled command. Wait for drive ready or drq. Done in intr(). 1711 * Wait for at last 400ns for status bit to be valid. 1712 */ 1713 delay(10); 1714 __wdccommand_intr(chp, xfer, 0); 1715 return; 1716 1717 timeout: 1718 wdc_c->flags |= AT_TIMEOU; 1719 __wdccommand_done(chp, xfer); 1720 } 1721 1722 int 1723 __wdccommand_intr(struct channel_softc *chp, struct wdc_xfer *xfer, int irq) 1724 { 1725 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1726 struct wdc_command *wdc_c = xfer->cmd; 1727 int bcount = wdc_c->bcount; 1728 char *data = wdc_c->data; 1729 1730 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1731 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1732 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1733 (irq == 0) ? wdc_c->timeout : 0)) { 1734 if (chp->dying) { 1735 __wdccommand_done(chp, xfer); 1736 return -1; 1737 } 1738 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1739 return 0; /* IRQ was not for us */ 1740 wdc_c->flags |= AT_TIMEOU; 1741 goto out; 1742 } 1743 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1744 chp->wdc->irqack(chp); 1745 if (wdc_c->flags & AT_READ) { 1746 if ((chp->ch_status & WDCS_DRQ) == 0) { 1747 wdc_c->flags |= AT_TIMEOU; 1748 goto out; 1749 } 1750 wdc_input_bytes(drvp, data, bcount); 1751 /* Should we wait for device to indicate idle? */ 1752 } 1753 out: 1754 __wdccommand_done(chp, xfer); 1755 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1756 return 1; 1757 } 1758 1759 void 1760 __wdccommand_done(struct channel_softc *chp, struct wdc_xfer *xfer) 1761 { 1762 struct wdc_command *wdc_c = xfer->cmd; 1763 1764 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1765 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 1766 chp->ch_status), DEBUG_FUNCS); 1767 if (chp->dying) 1768 goto killit; 1769 if (chp->ch_status & WDCS_DWF) 1770 wdc_c->flags |= AT_DF; 1771 if (chp->ch_status & WDCS_ERR) { 1772 wdc_c->flags |= AT_ERROR; 1773 wdc_c->r_error = chp->ch_error; 1774 } 1775 wdc_c->flags |= AT_DONE; 1776 if ((wdc_c->flags & AT_READREG) != 0 && 1777 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1778 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1779 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1780 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1781 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1782 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1783 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1784 wdc_c->r_precomp = wdc_c->r_error; 1785 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp 1786 isn't a readable register */ 1787 } 1788 1789 killit: 1790 if (xfer->c_flags & C_POLL) { 1791 wdc_enable_intr(chp); 1792 } else 1793 timeout_del(&chp->ch_timo); 1794 1795 wdc_free_xfer(chp, xfer); 1796 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1797 1798 if (chp->dying) 1799 return; 1800 1801 if (wdc_c->flags & AT_WAIT) 1802 wakeup(wdc_c); 1803 else 1804 if (wdc_c->callback) 1805 wdc_c->callback(wdc_c->callback_arg); 1806 wdcstart(chp); 1807 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1808 } 1809 1810 /* 1811 * Send a command. The drive should be ready. 1812 * Assumes interrupts are blocked. 1813 */ 1814 void 1815 wdccommand(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1816 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1817 u_int8_t precomp) 1818 { 1819 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1820 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1821 chp->channel, drive, command, cylin, head, sector, count, precomp), 1822 DEBUG_FUNCS); 1823 WDC_LOG_ATA_CMDLONG(chp, head, precomp, cylin, cylin >> 8, sector, 1824 count, command); 1825 1826 /* Select drive, head, and addressing mode. */ 1827 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1828 1829 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */ 1830 CHP_WRITE_REG(chp, wdr_precomp, precomp); 1831 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1832 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1833 CHP_WRITE_REG(chp, wdr_sector, sector); 1834 CHP_WRITE_REG(chp, wdr_seccnt, count); 1835 1836 /* Send command. */ 1837 CHP_WRITE_REG(chp, wdr_command, command); 1838 } 1839 1840 /* 1841 * Send a 48-bit addressing command. The drive should be ready. 1842 * Assumes interrupts are blocked. 1843 */ 1844 void 1845 wdccommandext(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1846 u_int64_t blkno, u_int16_t count) 1847 { 1848 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%llu " 1849 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1850 chp->channel, drive, command, blkno, count), 1851 DEBUG_FUNCS); 1852 WDC_LOG_ATA_CMDEXT(chp, blkno >> 40, blkno >> 16, blkno >> 32, 1853 blkno >> 8, blkno >> 24, blkno, count >> 8, count, command); 1854 1855 /* Select drive and LBA mode. */ 1856 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_LBA); 1857 1858 /* Load parameters. */ 1859 CHP_LBA48_WRITE_REG(chp, wdr_lba_hi, 1860 ((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0xff)); 1861 CHP_LBA48_WRITE_REG(chp, wdr_lba_mi, 1862 ((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0xff)); 1863 CHP_LBA48_WRITE_REG(chp, wdr_lba_lo, 1864 ((blkno >> 16) & 0xff00) | (blkno & 0xff)); 1865 CHP_LBA48_WRITE_REG(chp, wdr_seccnt, count); 1866 1867 /* Send command. */ 1868 CHP_WRITE_REG(chp, wdr_command, command); 1869 } 1870 1871 /* 1872 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1873 * tested by the caller. 1874 */ 1875 void 1876 wdccommandshort(struct channel_softc *chp, int drive, int command) 1877 { 1878 1879 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1880 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1881 DEBUG_FUNCS); 1882 WDC_LOG_ATA_CMDSHORT(chp, command); 1883 1884 /* Select drive. */ 1885 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1886 CHP_WRITE_REG(chp, wdr_command, command); 1887 } 1888 1889 /* Add a command to the queue and start controller. Must be called at splbio */ 1890 1891 void 1892 wdc_exec_xfer(struct channel_softc *chp, struct wdc_xfer *xfer) 1893 { 1894 WDCDEBUG_PRINT(("wdc_exec_xfer %p flags 0x%x channel %d drive %d\n", 1895 xfer, xfer->c_flags, chp->channel, xfer->drive), DEBUG_XFERS); 1896 1897 /* complete xfer setup */ 1898 xfer->chp = chp; 1899 1900 /* 1901 * If we are a polled command, and the list is not empty, 1902 * we are doing a dump. Drop the list to allow the polled command 1903 * to complete, we're going to reboot soon anyway. 1904 */ 1905 if ((xfer->c_flags & C_POLL) != 0 && 1906 !TAILQ_EMPTY(&chp->ch_queue->sc_xfer)) { 1907 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1908 } 1909 /* insert at the end of command list */ 1910 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1911 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1912 chp->ch_flags), DEBUG_XFERS); 1913 wdcstart(chp); 1914 } 1915 1916 struct wdc_xfer * 1917 wdc_get_xfer(int flags) 1918 { 1919 struct wdc_xfer *xfer; 1920 int s; 1921 1922 s = splbio(); 1923 xfer = pool_get(&wdc_xfer_pool, 1924 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1925 splx(s); 1926 if (xfer != NULL) 1927 memset(xfer, 0, sizeof(struct wdc_xfer)); 1928 return xfer; 1929 } 1930 1931 void 1932 wdc_free_xfer(struct channel_softc *chp, struct wdc_xfer *xfer) 1933 { 1934 int s; 1935 1936 if (xfer->c_flags & C_PRIVATEXFER) { 1937 chp->ch_flags &= ~WDCF_ACTIVE; 1938 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1939 return; 1940 } 1941 1942 s = splbio(); 1943 chp->ch_flags &= ~WDCF_ACTIVE; 1944 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1945 pool_put(&wdc_xfer_pool, xfer); 1946 splx(s); 1947 } 1948 1949 1950 /* 1951 * Kill off all pending xfers for a channel_softc. 1952 * 1953 * Must be called at splbio(). 1954 */ 1955 void 1956 wdc_kill_pending(struct channel_softc *chp) 1957 { 1958 struct wdc_xfer *xfer; 1959 1960 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1961 chp = xfer->chp; 1962 (*xfer->c_kill_xfer)(chp, xfer); 1963 } 1964 } 1965 1966 void 1967 __wdcerror(struct channel_softc *chp, char *msg) 1968 { 1969 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1970 if (xfer == NULL) 1971 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1972 msg); 1973 else 1974 printf("%s(%s:%d:%d): %s\n", 1975 chp->ch_drive[xfer->drive].drive_name, 1976 chp->wdc->sc_dev.dv_xname, 1977 chp->channel, xfer->drive, msg); 1978 } 1979 1980 /* 1981 * the bit bucket 1982 */ 1983 void 1984 wdcbit_bucket(struct channel_softc *chp, int size) 1985 { 1986 CHP_READ_RAW_MULTI_2(chp, NULL, size); 1987 } 1988 1989 1990 #include <sys/ataio.h> 1991 #include <sys/file.h> 1992 1993 int wdc_ioc_ata_cmd(struct ata_drive_datas *, atareq_t *); 1994 1995 int 1996 wdc_ioc_ata_cmd(struct ata_drive_datas *drvp, atareq_t *atareq) 1997 { 1998 struct wdc_command wdc_c; 1999 int err = 0; 2000 2001 /* 2002 * Make sure a timeout was supplied in the ioctl request 2003 */ 2004 if (atareq->timeout == 0) 2005 return (EINVAL); 2006 2007 if (atareq->datalen > MAXPHYS) 2008 return (EINVAL); 2009 2010 bzero(&wdc_c, sizeof(wdc_c)); 2011 2012 if (atareq->datalen > 0) { 2013 wdc_c.data = dma_alloc(atareq->datalen, PR_NOWAIT | PR_ZERO); 2014 if (wdc_c.data == NULL) { 2015 err = ENOMEM; 2016 goto err; 2017 } 2018 wdc_c.bcount = atareq->datalen; 2019 } 2020 2021 wdc_c.flags = AT_WAIT; 2022 if (atareq->flags & ATACMD_READ) 2023 wdc_c.flags |= AT_READ; 2024 if (atareq->flags & ATACMD_WRITE) { 2025 if (atareq->datalen > 0) { 2026 err = copyin(atareq->databuf, wdc_c.data, 2027 atareq->datalen); 2028 if (err != 0) 2029 goto err; 2030 } 2031 wdc_c.flags |= AT_WRITE; 2032 } 2033 if (atareq->flags & ATACMD_READREG) 2034 wdc_c.flags |= AT_READREG; 2035 2036 wdc_c.timeout = atareq->timeout; 2037 wdc_c.r_command = atareq->command; 2038 wdc_c.r_head = atareq->head & 0x0f; 2039 wdc_c.r_cyl = atareq->cylinder; 2040 wdc_c.r_sector = atareq->sec_num; 2041 wdc_c.r_count = atareq->sec_count; 2042 wdc_c.r_precomp = atareq->features; 2043 if (drvp->drive_flags & DRIVE_ATAPI) { 2044 if (wdc_c.r_command == WDCC_IDENTIFY) 2045 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 2046 } else { 2047 wdc_c.r_st_bmask = WDCS_DRDY; 2048 wdc_c.r_st_pmask = WDCS_DRDY; 2049 } 2050 2051 if (wdc_exec_command(drvp, &wdc_c) != WDC_COMPLETE) { 2052 atareq->retsts = ATACMD_ERROR; 2053 goto copyout; 2054 } 2055 2056 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 2057 if (wdc_c.flags & AT_ERROR) { 2058 atareq->retsts = ATACMD_ERROR; 2059 atareq->error = wdc_c.r_error; 2060 } else if (wdc_c.flags & AT_DF) 2061 atareq->retsts = ATACMD_DF; 2062 else 2063 atareq->retsts = ATACMD_TIMEOUT; 2064 } else { 2065 atareq->retsts = ATACMD_OK; 2066 if (atareq->flags & ATACMD_READREG) { 2067 atareq->head = wdc_c.r_head; 2068 atareq->cylinder = wdc_c.r_cyl; 2069 atareq->sec_num = wdc_c.r_sector; 2070 atareq->sec_count = wdc_c.r_count; 2071 atareq->features = wdc_c.r_precomp; 2072 atareq->error = wdc_c.r_error; 2073 } 2074 } 2075 2076 copyout: 2077 if (atareq->datalen > 0 && atareq->flags & ATACMD_READ) { 2078 err = copyout(wdc_c.data, atareq->databuf, atareq->datalen); 2079 if (err != 0) 2080 goto err; 2081 } 2082 2083 err: 2084 if (wdc_c.data) 2085 dma_free(wdc_c.data, atareq->datalen); 2086 return (err); 2087 } 2088 2089 int 2090 wdc_ioctl(struct ata_drive_datas *drvp, u_long xfer, caddr_t addr, int flag, 2091 struct proc *p) 2092 { 2093 int error = 0; 2094 2095 switch (xfer) { 2096 #ifdef WDCDEBUG 2097 case ATAIOGETTRACE: { 2098 atagettrace_t *agt = (atagettrace_t *)addr; 2099 unsigned int size = 0; 2100 char *log_to_copy; 2101 2102 size = agt->buf_size; 2103 if (size > 65536) { 2104 size = 65536; 2105 } 2106 2107 log_to_copy = wdc_get_log(&size, &agt->bytes_left); 2108 2109 if (log_to_copy != NULL) { 2110 error = copyout(log_to_copy, agt->buf, size); 2111 free(log_to_copy, M_TEMP); 2112 } 2113 2114 agt->bytes_copied = size; 2115 break; 2116 } 2117 #endif /* WDCDEBUG */ 2118 2119 case ATAIOCCOMMAND: { 2120 atareq_t *atareq = (atareq_t *)addr; 2121 2122 /* 2123 * Make sure this command is (relatively) safe first 2124 */ 2125 if ((flag & FWRITE) == 0 && atareq->flags & ATACMD_WRITE) 2126 error = EPERM; 2127 else 2128 error = wdc_ioc_ata_cmd(drvp, atareq); 2129 break; 2130 } 2131 2132 default: 2133 error = ENOTTY; 2134 goto exit; 2135 } 2136 2137 exit: 2138 return (error); 2139 } 2140