xref: /openbsd/sys/dev/isa/itvar.h (revision d954485d)
1*d954485dSbrynet /*	$OpenBSD: itvar.h,v 1.15 2013/03/21 18:20:00 brynet Exp $	*/
2e3a5c547Sgrange 
3e3a5c547Sgrange /*
448bf708fSform  * Copyright (c) 2007-2008 Oleg Safiullin <form@pdp-11.org.ru>
5c582b5c0Sform  * Copyright (c) 2006-2007 Juan Romero Pardines <juan@xtrarom.org>
6c582b5c0Sform  * Copyright (c) 2003 Julien Bordet <zejames@greyhats.org>
7e3a5c547Sgrange  * All rights reserved.
8e3a5c547Sgrange  *
9e3a5c547Sgrange  * Redistribution and use in source and binary forms, with or without
10e3a5c547Sgrange  * modification, are permitted provided that the following conditions
11e3a5c547Sgrange  * are met:
12e3a5c547Sgrange  * 1. Redistributions of source code must retain the above copyright
13e3a5c547Sgrange  *    notice, this list of conditions and the following disclaimer.
14e3a5c547Sgrange  * 2. Redistributions in binary form must reproduce the above copyright
15e3a5c547Sgrange  *    notice, this list of conditions and the following disclaimer in the
16e3a5c547Sgrange  *    documentation and/or other materials provided with the distribution.
17e3a5c547Sgrange  *
18e3a5c547Sgrange  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19e3a5c547Sgrange  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20e3a5c547Sgrange  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21e3a5c547Sgrange  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22e3a5c547Sgrange  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23e3a5c547Sgrange  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24e3a5c547Sgrange  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25e3a5c547Sgrange  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26e3a5c547Sgrange  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27e3a5c547Sgrange  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28e3a5c547Sgrange  */
29e3a5c547Sgrange 
30a1f930f2Sform #ifndef _DEV_ISA_ITVAR_H_
31a1f930f2Sform #define _DEV_ISA_ITVAR_H_
32e3a5c547Sgrange 
33a1f930f2Sform #define IT_EC_INTERVAL		5
341e5c1a87Sform #define IT_EC_NUMSENSORS	17
35a1f930f2Sform #define IT_EC_VREF		4096
36e3a5c547Sgrange 
3748bf708fSform #define IO_IT1			0x2e
3848bf708fSform #define IO_IT2			0x4e
39e3a5c547Sgrange 
40a1f930f2Sform #define IT_IO_ADDR		0x00
41a1f930f2Sform #define IT_IO_DATA		0x01
42e3a5c547Sgrange 
43a1f930f2Sform #define IT_ID_8705		0x8705
44a1f930f2Sform #define IT_ID_8712		0x8712
45a1f930f2Sform #define IT_ID_8716		0x8716
46a1f930f2Sform #define IT_ID_8718		0x8718
479cab3a99Sform #define IT_ID_8720		0x8720
487a7d733bSform #define IT_ID_8721		0x8721
49a1f930f2Sform #define IT_ID_8726		0x8726
50*d954485dSbrynet #define IT_ID_8728		0x8728
51d78b6a36Smikeb #define IT_ID_8772		0x8772
52e3a5c547Sgrange 
53a1f930f2Sform #define IT_CCR			0x02
54a1f930f2Sform #define IT_LDN			0x07
55a1f930f2Sform #define IT_CHIPID1		0x20
56a1f930f2Sform #define IT_CHIPID2		0x21
57a1f930f2Sform #define IT_CHIPREV		0x22
58e3a5c547Sgrange 
59a1f930f2Sform #define IT_EC_LDN		0x04
60a1f930f2Sform #define IT_EC_MSB		0x60
61a1f930f2Sform #define IT_EC_LSB		0x61
62e3a5c547Sgrange 
63a1f930f2Sform #define IT_EC_ADDR		0x05
64a1f930f2Sform #define IT_EC_DATA		0x06
65e3a5c547Sgrange 
66a1f930f2Sform #define IT_EC_CFG		0x00
67a1f930f2Sform #define IT_EC_FAN_DIV		0x0b
681e5c1a87Sform #define IT_EC_FAN_ECER		0x0c
691e5c1a87Sform #define IT_EC_FAN_TAC1		0x0d
701e5c1a87Sform #define IT_EC_FAN_TAC2		0x0e
711e5c1a87Sform #define IT_EC_FAN_TAC3		0x0f
721e5c1a87Sform #define IT_EC_FAN_MCR		0x13
731e5c1a87Sform #define IT_EC_FAN_EXT_TAC1	0x18
741e5c1a87Sform #define IT_EC_FAN_EXT_TAC2	0x19
751e5c1a87Sform #define IT_EC_FAN_EXT_TAC3	0x1a
76a1f930f2Sform #define IT_EC_VOLTBASE		0x20
77a1f930f2Sform #define IT_EC_TEMPBASE		0x29
781e5c1a87Sform #define IT_EC_ADC_VINER		0x50
791e5c1a87Sform #define IT_EC_ADC_TEMPER	0x51
801e5c1a87Sform #define IT_EC_FAN_TAC4_LSB	0x80
811e5c1a87Sform #define IT_EC_FAN_TAC4_MSB	0x81
821e5c1a87Sform #define IT_EC_FAN_TAC5_LSB	0x82
831e5c1a87Sform #define IT_EC_FAN_TAC5_MSB	0x83
84e3a5c547Sgrange 
853ecd7674Sform #define IT_EC_CFG_START		0x01
861e5c1a87Sform #define IT_EC_CFG_INTCLR	0x08
873ecd7674Sform #define IT_EC_CFG_UPDVBAT	0x40
883ecd7674Sform 
89a1f930f2Sform #define IT_WDT_LDN		0x07
90e3a5c547Sgrange 
91a1f930f2Sform #define IT_WDT_CSR		0x71
92a1f930f2Sform #define IT_WDT_TCR		0x72
936888f60cSform #define IT_WDT_TMO_LSB		0x73
946888f60cSform #define IT_WDT_TMO_MSB		0x74
956888f60cSform 
966888f60cSform #define IT_WDT_TCR_SECS		0x80
976888f60cSform #define IT_WDT_TCR_KRST		0x40
986888f60cSform #define IT_WDT_TCR_PWROK	0x10
99e3a5c547Sgrange 
100e3a5c547Sgrange 
101e3a5c547Sgrange struct it_softc {
102e3a5c547Sgrange 	struct device		sc_dev;
103e3a5c547Sgrange 
104a1f930f2Sform 	bus_space_tag_t		sc_iot;
105a1f930f2Sform 	bus_space_handle_t	sc_ioh;
10648bf708fSform 	int			sc_iobase;
10748bf708fSform 	int			sc_ec_iobase;
108a1f930f2Sform 	u_int16_t		sc_chipid;
109a1f930f2Sform 	u_int8_t		sc_chiprev;
110e3a5c547Sgrange 
111a1f930f2Sform 	bus_space_tag_t		sc_ec_iot;
112a1f930f2Sform 	bus_space_handle_t	sc_ec_ioh;
113e3a5c547Sgrange 
114a1f930f2Sform 	struct ksensor		sc_sensors[IT_EC_NUMSENSORS];
115a1f930f2Sform 	struct ksensordev	sc_sensordev;
11648bf708fSform 
11748bf708fSform 	LIST_ENTRY(it_softc)	sc_list;
118e3a5c547Sgrange };
119e3a5c547Sgrange 
120a1f930f2Sform #endif	/* _DEV_ISA_ITVAR_H_ */
121