1/* $OpenBSD: aic79xx.reg,v 1.9 2007/11/26 09:28:33 martynas Exp $ */ 2/* 3 * Aic79xx register and scratch ram definitions. 4 * 5 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.reg,v 1.18 2004/08/04 17:55:34 gibbs Exp $ 42 */ 43VERSION = "$Id: aic79xx.reg,v 1.9 2007/11/26 09:28:33 martynas Exp $" 44 45/* 46 * This file is processed by the aic7xxx_asm utility for use in assembling 47 * firmware for the aic79xx family of SCSI host adapters as well as to generate 48 * a C header file for use in the kernel portion of the Aic79xx driver. 49 */ 50 51/* Register window Modes */ 52#define M_DFF0 0 53#define M_DFF1 1 54#define M_CCHAN 2 55#define M_SCSI 3 56#define M_CFG 4 57#define M_DST_SHIFT 4 58 59#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 60#define SET_MODE(src, dst) \ 61 SET_SRC_MODE src; \ 62 SET_DST_MODE dst; \ 63 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 64 mvi MK_MODE(src, dst) call set_mode_work_around; \ 65 } else { \ 66 mvi MODE_PTR, MK_MODE(src, dst); \ 67 } 68 69#define RESTORE_MODE(mode) \ 70 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 71 mov mode call set_mode_work_around; \ 72 } else { \ 73 mov MODE_PTR, mode; \ 74 } 75 76#define SET_SEQINTCODE(code) \ 77 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 78 mvi code call set_seqint_work_around; \ 79 } else { \ 80 mvi SEQINTCODE, code; \ 81 } 82 83/* 84 * Mode Pointer 85 * Controls which of the 5, 512byte, address spaces should be used 86 * as the source and destination of any register accesses in our 87 * register window. 88 */ 89register MODE_PTR { 90 address 0x000 91 access_mode RW 92 field DST_MODE 0x70 93 field SRC_MODE 0x07 94 mode_pointer 95} 96 97const SRC_MODE_SHIFT 0 98const DST_MODE_SHIFT 4 99 100/* 101 * Host Interrupt Status 102 */ 103register INTSTAT { 104 address 0x001 105 access_mode RW 106 field HWERRINT 0x80 107 field BRKADRINT 0x40 108 field SWTMINT 0x20 109 field PCIINT 0x10 110 field SCSIINT 0x08 111 field SEQINT 0x04 112 field CMDCMPLT 0x02 113 field SPLTINT 0x01 114 mask INT_PEND 0xFF 115} 116 117/* 118 * Sequencer Interrupt Code 119 */ 120register SEQINTCODE { 121 address 0x002 122 access_mode RW 123 field { 124 NO_SEQINT, /* No seqint pending. */ 125 BAD_PHASE, /* unknown scsi bus phase */ 126 SEND_REJECT, /* sending a message reject */ 127 PROTO_VIOLATION, /* Protocol Violation */ 128 NO_MATCH, /* no cmd match for reconnect */ 129 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 130 PDATA_REINIT, /* 131 * Returned to data phase 132 * that requires data 133 * transfer pointers to be 134 * recalculated from the 135 * transfer residual. 136 */ 137 HOST_MSG_LOOP, /* 138 * The bus is ready for the 139 * host to perform another 140 * message transaction. This 141 * mechanism is used for things 142 * like sync/wide negotiation 143 * that require a kernel based 144 * message state engine. 145 */ 146 BAD_STATUS, /* Bad status from target */ 147 DATA_OVERRUN, /* 148 * Target attempted to write 149 * beyond the bounds of its 150 * command. 151 */ 152 MKMSG_FAILED, /* 153 * Target completed command 154 * without honoring our ATN 155 * request to issue a message. 156 */ 157 MISSED_BUSFREE, /* 158 * The sequencer never saw 159 * the bus go free after 160 * either a command complete 161 * or disconnect message. 162 */ 163 DUMP_CARD_STATE, 164 ILLEGAL_PHASE, 165 INVALID_SEQINT, 166 CFG4ISTAT_INTR, 167 STATUS_OVERRUN, 168 CFG4OVERRUN, 169 ENTERING_NONPACK, 170 TASKMGMT_FUNC_COMPLETE, /* 171 * Task management function 172 * request completed with 173 * an expected busfree. 174 */ 175 TASKMGMT_CMD_CMPLT_OKAY, /* 176 * A command with a non-zero 177 * task management function 178 * has completed via the normal 179 * command completion method 180 * for commands with a zero 181 * task management function. 182 * This happens when an attempt 183 * to abort a command loses 184 * the race for the command to 185 * complete normally. 186 */ 187 TRACEPOINT0, 188 TRACEPOINT1, 189 TRACEPOINT2, 190 TRACEPOINT3, 191 SAW_HWERR, 192 BAD_SCB_STATUS 193 } 194} 195 196/* 197 * Clear Host Interrupt 198 */ 199register CLRINT { 200 address 0x003 201 access_mode WO 202 field CLRHWERRINT 0x80 /* Rev B or greater */ 203 field CLRBRKADRINT 0x40 204 field CLRSWTMINT 0x20 205 field CLRPCIINT 0x10 206 field CLRSCSIINT 0x08 207 field CLRSEQINT 0x04 208 field CLRCMDINT 0x02 209 field CLRSPLTINT 0x01 210} 211 212/* 213 * Error Register 214 */ 215register ERROR { 216 address 0x004 217 access_mode RO 218 field CIOPARERR 0x80 219 field CIOACCESFAIL 0x40 /* Rev B or greater */ 220 field MPARERR 0x20 221 field DPARERR 0x10 222 field SQPARERR 0x08 223 field ILLOPCODE 0x04 224 field DSCTMOUT 0x02 225} 226 227/* 228 * Clear Error 229 */ 230register CLRERR { 231 address 0x004 232 access_mode WO 233 field CLRCIOPARERR 0x80 234 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 235 field CLRMPARERR 0x20 236 field CLRDPARERR 0x10 237 field CLRSQPARERR 0x08 238 field CLRILLOPCODE 0x04 239 field CLRDSCTMOUT 0x02 240} 241 242/* 243 * Host Control Register 244 * Overall host control of the device. 245 */ 246register HCNTRL { 247 address 0x005 248 access_mode RW 249 field SEQ_RESET 0x80 /* Rev B or greater */ 250 field POWRDN 0x40 251 field SWINT 0x10 252 field SWTIMER_START_B 0x08 /* Rev B or greater */ 253 field PAUSE 0x04 254 field INTEN 0x02 255 field CHIPRST 0x01 256 field CHIPRSTACK 0x01 257} 258 259/* 260 * Host New SCB Queue Offset 261 */ 262register HNSCB_QOFF { 263 address 0x006 264 access_mode RW 265 size 2 266} 267 268/* 269 * Host Empty SCB Queue Offset 270 */ 271register HESCB_QOFF { 272 address 0x008 273 access_mode RW 274} 275 276/* 277 * Host Mailbox 278 */ 279register HS_MAILBOX { 280 address 0x00B 281 access_mode RW 282 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 283 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ 284} 285 286/* 287 * Sequencer Interrupt Status 288 */ 289register SEQINTSTAT { 290 address 0x00C 291 access_mode RO 292 field SEQ_SWTMRTO 0x10 293 field SEQ_SEQINT 0x08 294 field SEQ_SCSIINT 0x04 295 field SEQ_PCIINT 0x02 296 field SEQ_SPLTINT 0x01 297} 298 299/* 300 * Clear SEQ Interrupt 301 */ 302register CLRSEQINTSTAT { 303 address 0x00C 304 access_mode WO 305 field CLRSEQ_SWTMRTO 0x10 306 field CLRSEQ_SEQINT 0x08 307 field CLRSEQ_SCSIINT 0x04 308 field CLRSEQ_PCIINT 0x02 309 field CLRSEQ_SPLTINT 0x01 310} 311 312/* 313 * Software Timer 314 */ 315register SWTIMER { 316 address 0x00E 317 access_mode RW 318 size 2 319} 320 321/* 322 * SEQ New SCB Queue Offset 323 */ 324register SNSCB_QOFF { 325 address 0x010 326 access_mode RW 327 size 2 328 modes M_CCHAN 329} 330 331/* 332 * SEQ Empty SCB Queue Offset 333 */ 334register SESCB_QOFF { 335 address 0x012 336 access_mode RW 337 modes M_CCHAN 338} 339 340/* 341 * SEQ Done SCB Queue Offset 342 */ 343register SDSCB_QOFF { 344 address 0x014 345 access_mode RW 346 modes M_CCHAN 347 size 2 348} 349 350/* 351 * Queue Offset Control & Status 352 */ 353register QOFF_CTLSTA { 354 address 0x016 355 access_mode RW 356 modes M_CCHAN 357 field EMPTY_SCB_AVAIL 0x80 358 field NEW_SCB_AVAIL 0x40 359 field SDSCB_ROLLOVR 0x20 360 field HS_MAILBOX_ACT 0x10 361 field SCB_QSIZE 0x0F { 362 SCB_QSIZE_4, 363 SCB_QSIZE_8, 364 SCB_QSIZE_16, 365 SCB_QSIZE_32, 366 SCB_QSIZE_64, 367 SCB_QSIZE_128, 368 SCB_QSIZE_256, 369 SCB_QSIZE_512, 370 SCB_QSIZE_1024, 371 SCB_QSIZE_2048, 372 SCB_QSIZE_4096, 373 SCB_QSIZE_8192, 374 SCB_QSIZE_16384 375 } 376} 377 378/* 379 * Interrupt Control 380 */ 381register INTCTL { 382 address 0x018 383 access_mode RW 384 field SWTMINTMASK 0x80 385 field SWTMINTEN 0x40 386 field SWTIMER_START 0x20 387 field AUTOCLRCMDINT 0x10 388 field PCIINTEN 0x08 389 field SCSIINTEN 0x04 390 field SEQINTEN 0x02 391 field SPLTINTEN 0x01 392} 393 394/* 395 * Data FIFO Control 396 */ 397register DFCNTRL { 398 address 0x019 399 access_mode RW 400 modes M_DFF0, M_DFF1 401 field PRELOADEN 0x80 402 field SCSIENWRDIS 0x40 /* Rev B only. */ 403 field SCSIEN 0x20 404 field SCSIENACK 0x20 405 field HDMAEN 0x08 406 field HDMAENACK 0x08 407 field DIRECTION 0x04 408 field DIRECTIONACK 0x04 409 field FIFOFLUSH 0x02 410 field FIFOFLUSHACK 0x02 411 field DIRECTIONEN 0x01 412} 413 414/* 415 * Device Space Command 0 416 */ 417register DSCOMMAND0 { 418 address 0x019 419 access_mode RW 420 modes M_CFG 421 field CACHETHEN 0x80 /* Cache Threshold enable */ 422 field DPARCKEN 0x40 /* Data Parity Check Enable */ 423 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 424 field EXTREQLCK 0x10 /* External Request Lock */ 425 field DISABLE_TWATE 0x02 /* Rev B or greater */ 426 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 427} 428 429/* 430 * Data FIFO Status 431 */ 432register DFSTATUS { 433 address 0x01A 434 access_mode RO 435 modes M_DFF0, M_DFF1 436 field PRELOAD_AVAIL 0x80 437 field PKT_PRELOAD_AVAIL 0x40 438 field MREQPEND 0x10 439 field HDONE 0x08 440 field DFTHRESH 0x04 441 field FIFOFULL 0x02 442 field FIFOEMP 0x01 443} 444 445/* 446 * S/G Cache Pointer 447 */ 448register SG_CACHE_PRE { 449 address 0x01B 450 access_mode WO 451 modes M_DFF0, M_DFF1 452 field SG_ADDR_MASK 0xf8 453 field ODD_SEG 0x04 454 field LAST_SEG 0x02 455} 456 457register SG_CACHE_SHADOW { 458 address 0x01B 459 access_mode RO 460 modes M_DFF0, M_DFF1 461 field SG_ADDR_MASK 0xf8 462 field ODD_SEG 0x04 463 field LAST_SEG 0x02 464 field LAST_SEG_DONE 0x01 465} 466 467/* 468 * Arbiter Control 469 */ 470register ARBCTL { 471 address 0x01B 472 access_mode RW 473 modes M_CFG 474 field RESET_HARB 0x80 475 field RETRY_SWEN 0x08 476 field USE_TIME 0x07 477} 478 479/* 480 * Data Channel Host Address 481 */ 482register HADDR { 483 address 0x070 484 access_mode RW 485 size 8 486 modes M_DFF0, M_DFF1 487} 488 489/* 490 * Host Overlay DMA Address 491 */ 492register HODMAADR { 493 address 0x070 494 access_mode RW 495 size 8 496 modes M_SCSI 497} 498 499/* 500 * PCI PLL Delay. 501 */ 502register PLLDELAY { 503 address 0x070 504 access_mode RW 505 size 1 506 modes M_CFG 507 field SPLIT_DROP_REQ 0x80 508} 509 510/* 511 * Data Channel Host Count 512 */ 513register HCNT { 514 address 0x078 515 access_mode RW 516 size 3 517 modes M_DFF0, M_DFF1 518} 519 520/* 521 * Host Overlay DMA Count 522 */ 523register HODMACNT { 524 address 0x078 525 access_mode RW 526 size 2 527 modes M_SCSI 528} 529 530/* 531 * Host Overlay DMA Enable 532 */ 533register HODMAEN { 534 address 0x07A 535 access_mode RW 536 modes M_SCSI 537} 538 539/* 540 * Scatter/Gather Host Address 541 */ 542register SGHADDR { 543 address 0x07C 544 access_mode RW 545 size 8 546 modes M_DFF0, M_DFF1 547} 548 549/* 550 * SCB Host Address 551 */ 552register SCBHADDR { 553 address 0x07C 554 access_mode RW 555 size 8 556 modes M_CCHAN 557} 558 559/* 560 * Scatter/Gather Host Count 561 */ 562register SGHCNT { 563 address 0x084 564 access_mode RW 565 modes M_DFF0, M_DFF1 566} 567 568/* 569 * SCB Host Count 570 */ 571register SCBHCNT { 572 address 0x084 573 access_mode RW 574 modes M_CCHAN 575} 576 577/* 578 * Data FIFO Threshold 579 */ 580register DFF_THRSH { 581 address 0x088 582 access_mode RW 583 modes M_CFG 584 field WR_DFTHRSH 0x70 { 585 WR_DFTHRSH_MIN, 586 WR_DFTHRSH_25, 587 WR_DFTHRSH_50, 588 WR_DFTHRSH_63, 589 WR_DFTHRSH_75, 590 WR_DFTHRSH_85, 591 WR_DFTHRSH_90, 592 WR_DFTHRSH_MAX 593 } 594 field RD_DFTHRSH 0x07 { 595 RD_DFTHRSH_MIN, 596 RD_DFTHRSH_25, 597 RD_DFTHRSH_50, 598 RD_DFTHRSH_63, 599 RD_DFTHRSH_75, 600 RD_DFTHRSH_85, 601 RD_DFTHRSH_90, 602 RD_DFTHRSH_MAX 603 } 604} 605 606/* 607 * ROM Address 608 */ 609register ROMADDR { 610 address 0x08A 611 access_mode RW 612 size 3 613} 614 615/* 616 * ROM Control 617 */ 618register ROMCNTRL { 619 address 0x08D 620 access_mode RW 621 field ROMOP 0xE0 622 field ROMSPD 0x18 623 field REPEAT 0x02 624 field RDY 0x01 625} 626 627/* 628 * ROM Data 629 */ 630register ROMDATA { 631 address 0x08E 632 access_mode RW 633} 634 635/* 636 * Data Channel Receive Message 0 637 */ 638register DCHRXMSG0 { 639 address 0x090 640 access_mode RO 641 modes M_DFF0, M_DFF1 642 field CDNUM 0xF8 643 field CFNUM 0x07 644} 645 646/* 647 * CMC Recieve Message 0 648 */ 649register CMCRXMSG0 { 650 address 0x090 651 access_mode RO 652 modes M_CCHAN 653 field CDNUM 0xF8 654 field CFNUM 0x07 655} 656 657/* 658 * Overlay Recieve Message 0 659 */ 660register OVLYRXMSG0 { 661 address 0x090 662 access_mode RO 663 modes M_SCSI 664 field CDNUM 0xF8 665 field CFNUM 0x07 666} 667 668/* 669 * Relaxed Order Enable 670 */ 671register ROENABLE { 672 address 0x090 673 access_mode RW 674 modes M_CFG 675 field MSIROEN 0x20 676 field OVLYROEN 0x10 677 field CMCROEN 0x08 678 field SGROEN 0x04 679 field DCH1ROEN 0x02 680 field DCH0ROEN 0x01 681} 682 683/* 684 * Data Channel Receive Message 1 685 */ 686register DCHRXMSG1 { 687 address 0x091 688 access_mode RO 689 modes M_DFF0, M_DFF1 690 field CBNUM 0xFF 691} 692 693/* 694 * CMC Recieve Message 1 695 */ 696register CMCRXMSG1 { 697 address 0x091 698 access_mode RO 699 modes M_CCHAN 700 field CBNUM 0xFF 701} 702 703/* 704 * Overlay Recieve Message 1 705 */ 706register OVLYRXMSG1 { 707 address 0x091 708 access_mode RO 709 modes M_SCSI 710 field CBNUM 0xFF 711} 712 713/* 714 * No Snoop Enable 715 */ 716register NSENABLE { 717 address 0x091 718 access_mode RW 719 modes M_CFG 720 field MSINSEN 0x20 721 field OVLYNSEN 0x10 722 field CMCNSEN 0x08 723 field SGNSEN 0x04 724 field DCH1NSEN 0x02 725 field DCH0NSEN 0x01 726} 727 728/* 729 * Data Channel Receive Message 2 730 */ 731register DCHRXMSG2 { 732 address 0x092 733 access_mode RO 734 modes M_DFF0, M_DFF1 735 field MINDEX 0xFF 736} 737 738/* 739 * CMC Recieve Message 2 740 */ 741register CMCRXMSG2 { 742 address 0x092 743 access_mode RO 744 modes M_CCHAN 745 field MINDEX 0xFF 746} 747 748/* 749 * Overlay Recieve Message 2 750 */ 751register OVLYRXMSG2 { 752 address 0x092 753 access_mode RO 754 modes M_SCSI 755 field MINDEX 0xFF 756} 757 758/* 759 * Outstanding Split Transactions 760 */ 761register OST { 762 address 0x092 763 access_mode RW 764 modes M_CFG 765} 766 767/* 768 * Data Channel Receive Message 3 769 */ 770register DCHRXMSG3 { 771 address 0x093 772 access_mode RO 773 modes M_DFF0, M_DFF1 774 field MCLASS 0x0F 775} 776 777/* 778 * CMC Recieve Message 3 779 */ 780register CMCRXMSG3 { 781 address 0x093 782 access_mode RO 783 modes M_CCHAN 784 field MCLASS 0x0F 785} 786 787/* 788 * Overlay Recieve Message 3 789 */ 790register OVLYRXMSG3 { 791 address 0x093 792 access_mode RO 793 modes M_SCSI 794 field MCLASS 0x0F 795} 796 797/* 798 * PCI-X Control 799 */ 800register PCIXCTL { 801 address 0x093 802 access_mode RW 803 modes M_CFG 804 field SERRPULSE 0x80 805 field UNEXPSCIEN 0x20 806 field SPLTSMADIS 0x10 807 field SPLTSTADIS 0x08 808 field SRSPDPEEN 0x04 809 field TSCSERREN 0x02 810 field CMPABCDIS 0x01 811} 812 813/* 814 * CMC Sequencer Byte Count 815 */ 816register CMCSEQBCNT { 817 address 0x094 818 access_mode RO 819 modes M_CCHAN 820} 821 822/* 823 * Overlay Sequencer Byte Count 824 */ 825register OVLYSEQBCNT { 826 address 0x094 827 access_mode RO 828 modes M_SCSI 829} 830 831/* 832 * Data Channel Sequencer Byte Count 833 */ 834register DCHSEQBCNT { 835 address 0x094 836 access_mode RO 837 size 2 838 modes M_DFF0, M_DFF1 839} 840 841/* 842 * Data Channel Split Status 0 843 */ 844register DCHSPLTSTAT0 { 845 address 0x096 846 access_mode RW 847 modes M_DFF0, M_DFF1 848 field STAETERM 0x80 849 field SCBCERR 0x40 850 field SCADERR 0x20 851 field SCDATBUCKET 0x10 852 field CNTNOTCMPLT 0x08 853 field RXOVRUN 0x04 854 field RXSCEMSG 0x02 855 field RXSPLTRSP 0x01 856} 857 858/* 859 * CMC Split Status 0 860 */ 861register CMCSPLTSTAT0 { 862 address 0x096 863 access_mode RW 864 modes M_CCHAN 865 field STAETERM 0x80 866 field SCBCERR 0x40 867 field SCADERR 0x20 868 field SCDATBUCKET 0x10 869 field CNTNOTCMPLT 0x08 870 field RXOVRUN 0x04 871 field RXSCEMSG 0x02 872 field RXSPLTRSP 0x01 873} 874 875/* 876 * Overlay Split Status 0 877 */ 878register OVLYSPLTSTAT0 { 879 address 0x096 880 access_mode RW 881 modes M_SCSI 882 field STAETERM 0x80 883 field SCBCERR 0x40 884 field SCADERR 0x20 885 field SCDATBUCKET 0x10 886 field CNTNOTCMPLT 0x08 887 field RXOVRUN 0x04 888 field RXSCEMSG 0x02 889 field RXSPLTRSP 0x01 890} 891 892/* 893 * Data Channel Split Status 1 894 */ 895register DCHSPLTSTAT1 { 896 address 0x097 897 access_mode RW 898 modes M_DFF0, M_DFF1 899 field RXDATABUCKET 0x01 900} 901 902/* 903 * CMC Split Status 1 904 */ 905register CMCSPLTSTAT1 { 906 address 0x097 907 access_mode RW 908 modes M_CCHAN 909 field RXDATABUCKET 0x01 910} 911 912/* 913 * Overlay Split Status 1 914 */ 915register OVLYSPLTSTAT1 { 916 address 0x097 917 access_mode RW 918 modes M_SCSI 919 field RXDATABUCKET 0x01 920} 921 922/* 923 * S/G Receive Message 0 924 */ 925register SGRXMSG0 { 926 address 0x098 927 access_mode RO 928 modes M_DFF0, M_DFF1 929 field CDNUM 0xF8 930 field CFNUM 0x07 931} 932 933/* 934 * S/G Receive Message 1 935 */ 936register SGRXMSG1 { 937 address 0x099 938 access_mode RO 939 modes M_DFF0, M_DFF1 940 field CBNUM 0xFF 941} 942 943/* 944 * S/G Receive Message 2 945 */ 946register SGRXMSG2 { 947 address 0x09A 948 access_mode RO 949 modes M_DFF0, M_DFF1 950 field MINDEX 0xFF 951} 952 953/* 954 * S/G Receive Message 3 955 */ 956register SGRXMSG3 { 957 address 0x09B 958 access_mode RO 959 modes M_DFF0, M_DFF1 960 field MCLASS 0x0F 961} 962 963/* 964 * Slave Split Out Address 0 965 */ 966register SLVSPLTOUTADR0 { 967 address 0x098 968 access_mode RO 969 modes M_SCSI 970 field LOWER_ADDR 0x7F 971} 972 973/* 974 * Slave Split Out Address 1 975 */ 976register SLVSPLTOUTADR1 { 977 address 0x099 978 access_mode RO 979 modes M_SCSI 980 field REQ_DNUM 0xF8 981 field REQ_FNUM 0x07 982} 983 984/* 985 * Slave Split Out Address 2 986 */ 987register SLVSPLTOUTADR2 { 988 address 0x09A 989 access_mode RO 990 modes M_SCSI 991 field REQ_BNUM 0xFF 992} 993 994/* 995 * Slave Split Out Address 3 996 */ 997register SLVSPLTOUTADR3 { 998 address 0x09B 999 access_mode RO 1000 modes M_SCSI 1001 field RLXORD 020 1002 field TAG_NUM 0x1F 1003} 1004 1005/* 1006 * SG Sequencer Byte Count 1007 */ 1008register SGSEQBCNT { 1009 address 0x09C 1010 access_mode RO 1011 modes M_DFF0, M_DFF1 1012} 1013 1014/* 1015 * Slave Split Out Attribute 0 1016 */ 1017register SLVSPLTOUTATTR0 { 1018 address 0x09C 1019 access_mode RO 1020 modes M_SCSI 1021 field LOWER_BCNT 0xFF 1022} 1023 1024/* 1025 * Slave Split Out Attribute 1 1026 */ 1027register SLVSPLTOUTATTR1 { 1028 address 0x09D 1029 access_mode RO 1030 modes M_SCSI 1031 field CMPLT_DNUM 0xF8 1032 field CMPLT_FNUM 0x07 1033} 1034 1035/* 1036 * Slave Split Out Attribute 2 1037 */ 1038register SLVSPLTOUTATTR2 { 1039 address 0x09E 1040 access_mode RO 1041 size 2 1042 modes M_SCSI 1043 field CMPLT_BNUM 0xFF 1044} 1045/* 1046 * S/G Split Status 0 1047 */ 1048register SGSPLTSTAT0 { 1049 address 0x09E 1050 access_mode RW 1051 modes M_DFF0, M_DFF1 1052 field STAETERM 0x80 1053 field SCBCERR 0x40 1054 field SCADERR 0x20 1055 field SCDATBUCKET 0x10 1056 field CNTNOTCMPLT 0x08 1057 field RXOVRUN 0x04 1058 field RXSCEMSG 0x02 1059 field RXSPLTRSP 0x01 1060} 1061 1062/* 1063 * S/G Split Status 1 1064 */ 1065register SGSPLTSTAT1 { 1066 address 0x09F 1067 access_mode RW 1068 modes M_DFF0, M_DFF1 1069 field RXDATABUCKET 0x01 1070} 1071 1072/* 1073 * Special Function 1074 */ 1075register SFUNCT { 1076 address 0x09f 1077 access_mode RW 1078 modes M_CFG 1079 field TEST_GROUP 0xF0 1080 field TEST_NUM 0x0F 1081} 1082 1083/* 1084 * Data FIFO 0 PCI Status 1085 */ 1086register DF0PCISTAT { 1087 address 0x0A0 1088 access_mode RW 1089 modes M_CFG 1090 field DPE 0x80 1091 field SSE 0x40 1092 field RMA 0x20 1093 field RTA 0x10 1094 field SCAAPERR 0x08 1095 field RDPERR 0x04 1096 field TWATERR 0x02 1097 field DPR 0x01 1098} 1099 1100/* 1101 * Data FIFO 1 PCI Status 1102 */ 1103register DF1PCISTAT { 1104 address 0x0A1 1105 access_mode RW 1106 modes M_CFG 1107 field DPE 0x80 1108 field SSE 0x40 1109 field RMA 0x20 1110 field RTA 0x10 1111 field SCAAPERR 0x08 1112 field RDPERR 0x04 1113 field TWATERR 0x02 1114 field DPR 0x01 1115} 1116 1117/* 1118 * S/G PCI Status 1119 */ 1120register SGPCISTAT { 1121 address 0x0A2 1122 access_mode RW 1123 modes M_CFG 1124 field DPE 0x80 1125 field SSE 0x40 1126 field RMA 0x20 1127 field RTA 0x10 1128 field SCAAPERR 0x08 1129 field RDPERR 0x04 1130 field DPR 0x01 1131} 1132 1133/* 1134 * CMC PCI Status 1135 */ 1136register CMCPCISTAT { 1137 address 0x0A3 1138 access_mode RW 1139 modes M_CFG 1140 field DPE 0x80 1141 field SSE 0x40 1142 field RMA 0x20 1143 field RTA 0x10 1144 field SCAAPERR 0x08 1145 field RDPERR 0x04 1146 field TWATERR 0x02 1147 field DPR 0x01 1148} 1149 1150/* 1151 * Overlay PCI Status 1152 */ 1153register OVLYPCISTAT { 1154 address 0x0A4 1155 access_mode RW 1156 modes M_CFG 1157 field DPE 0x80 1158 field SSE 0x40 1159 field RMA 0x20 1160 field RTA 0x10 1161 field SCAAPERR 0x08 1162 field RDPERR 0x04 1163 field DPR 0x01 1164} 1165 1166/* 1167 * PCI Status for MSI Master DMA Transfer 1168 */ 1169register MSIPCISTAT { 1170 address 0x0A6 1171 access_mode RW 1172 modes M_CFG 1173 field SSE 0x40 1174 field RMA 0x20 1175 field RTA 0x10 1176 field CLRPENDMSI 0x08 1177 field TWATERR 0x02 1178 field DPR 0x01 1179} 1180 1181/* 1182 * PCI Status for Target 1183 */ 1184register TARGPCISTAT { 1185 address 0x0A7 1186 access_mode RW 1187 modes M_CFG 1188 field DPE 0x80 1189 field SSE 0x40 1190 field STA 0x08 1191 field TWATERR 0x02 1192} 1193 1194/* 1195 * LQ Packet In 1196 * The last LQ Packet received 1197 */ 1198register LQIN { 1199 address 0x020 1200 access_mode RW 1201 size 20 1202 modes M_DFF0, M_DFF1, M_SCSI 1203} 1204 1205/* 1206 * SCB Type Pointer 1207 * SCB offset for Target Mode SCB type information 1208 */ 1209register TYPEPTR { 1210 address 0x020 1211 access_mode RW 1212 modes M_CFG 1213} 1214 1215/* 1216 * Queue Tag Pointer 1217 * SCB offset to the Two Byte tag identifier used for target mode. 1218 */ 1219register TAGPTR { 1220 address 0x021 1221 access_mode RW 1222 modes M_CFG 1223} 1224 1225/* 1226 * Logical Unit Number Pointer 1227 * SCB offset to the LSB (little endian) of the lun field. 1228 */ 1229register LUNPTR { 1230 address 0x022 1231 access_mode RW 1232 modes M_CFG 1233} 1234 1235/* 1236 * Data Length Pointer 1237 * SCB offset for the 4 byte data length field in target mode. 1238 */ 1239register DATALENPTR { 1240 address 0x023 1241 access_mode RW 1242 modes M_CFG 1243} 1244 1245/* 1246 * Status Length Pointer 1247 * SCB offset to the two byte status field in target SCBs. 1248 */ 1249register STATLENPTR { 1250 address 0x024 1251 access_mode RW 1252 modes M_CFG 1253} 1254 1255/* 1256 * Command Length Pointer 1257 * Scb offset for the CDB length field in initiator SCBs. 1258 */ 1259register CMDLENPTR { 1260 address 0x025 1261 access_mode RW 1262 modes M_CFG 1263} 1264 1265/* 1266 * Task Attribute Pointer 1267 * Scb offset for the byte field specifying the attribute byte 1268 * to be used in command packets. 1269 */ 1270register ATTRPTR { 1271 address 0x026 1272 access_mode RW 1273 modes M_CFG 1274} 1275 1276/* 1277 * Task Management Flags Pointer 1278 * Scb offset for the byte field specifying the attribute flags 1279 * byte to be used in command packets. 1280 */ 1281register FLAGPTR { 1282 address 0x027 1283 access_mode RW 1284 modes M_CFG 1285} 1286 1287/* 1288 * Command Pointer 1289 * Scb offset for the first byte in the CDB for initiator SCBs. 1290 */ 1291register CMDPTR { 1292 address 0x028 1293 access_mode RW 1294 modes M_CFG 1295} 1296 1297/* 1298 * Queue Next Pointer 1299 * Scb offset for the 2 byte "next scb link". 1300 */ 1301register QNEXTPTR { 1302 address 0x029 1303 access_mode RW 1304 modes M_CFG 1305} 1306 1307/* 1308 * SCSI ID Pointer 1309 * Scb offset to the value to place in the SCSIID register 1310 * during target mode connections. 1311 */ 1312register IDPTR { 1313 address 0x02A 1314 access_mode RW 1315 modes M_CFG 1316} 1317 1318/* 1319 * Command Aborted Byte Pointer 1320 * Offset to the SCB flags field that includes the 1321 * "SCB aborted" status bit. 1322 */ 1323register ABRTBYTEPTR { 1324 address 0x02B 1325 access_mode RW 1326 modes M_CFG 1327} 1328 1329/* 1330 * Command Aborted Bit Pointer 1331 * Bit offset in the SCB flags field for "SCB aborted" status. 1332 */ 1333register ABRTBITPTR { 1334 address 0x02C 1335 access_mode RW 1336 modes M_CFG 1337} 1338 1339/* 1340 * Rev B or greater. 1341 */ 1342register MAXCMDBYTES { 1343 address 0x02D 1344 access_mode RW 1345 modes M_CFG 1346} 1347 1348/* 1349 * Rev B or greater. 1350 */ 1351register MAXCMD2RCV { 1352 address 0x02E 1353 access_mode RW 1354 modes M_CFG 1355} 1356 1357/* 1358 * Rev B or greater. 1359 */ 1360register SHORTTHRESH { 1361 address 0x02F 1362 access_mode RW 1363 modes M_CFG 1364} 1365 1366/* 1367 * Logical Unit Number Length 1368 * The length, in bytes, of the SCB lun field. 1369 */ 1370register LUNLEN { 1371 address 0x030 1372 access_mode RW 1373 modes M_CFG 1374 mask ILUNLEN 0x0F 1375 mask TLUNLEN 0xF0 1376} 1377const LUNLEN_SINGLE_LEVEL_LUN 0xF 1378 1379/* 1380 * CDB Limit 1381 * The size, in bytes, of the embedded CDB field in initator SCBs. 1382 */ 1383register CDBLIMIT { 1384 address 0x031 1385 access_mode RW 1386 modes M_CFG 1387} 1388 1389/* 1390 * Maximum Commands 1391 * The maximum number of commands to issue during a 1392 * single packetized connection. 1393 */ 1394register MAXCMD { 1395 address 0x032 1396 access_mode RW 1397 modes M_CFG 1398} 1399 1400/* 1401 * Maximum Command Counter 1402 * The number of commands already sent during this connection 1403 */ 1404register MAXCMDCNT { 1405 address 0x033 1406 access_mode RW 1407 modes M_CFG 1408} 1409 1410/* 1411 * LQ Packet Reserved Bytes 1412 * The bytes to be sent in the currently reserved fileds 1413 * of all LQ packets. 1414 */ 1415register LQRSVD01 { 1416 address 0x034 1417 access_mode RW 1418 modes M_SCSI 1419} 1420register LQRSVD16 { 1421 address 0x035 1422 access_mode RW 1423 modes M_SCSI 1424} 1425register LQRSVD17 { 1426 address 0x036 1427 access_mode RW 1428 modes M_SCSI 1429} 1430 1431/* 1432 * Command Reserved 0 1433 * The byte to be sent for the reserved byte 0 of 1434 * outgoing command packets. 1435 */ 1436register CMDRSVD0 { 1437 address 0x037 1438 access_mode RW 1439 modes M_CFG 1440} 1441 1442/* 1443 * LQ Manager Control 0 1444 */ 1445register LQCTL0 { 1446 address 0x038 1447 access_mode RW 1448 modes M_CFG 1449 field LQITARGCLT 0xC0 1450 field LQIINITGCLT 0x30 1451 field LQ0TARGCLT 0x0C 1452 field LQ0INITGCLT 0x03 1453} 1454 1455/* 1456 * LQ Manager Control 1 1457 */ 1458register LQCTL1 { 1459 address 0x038 1460 access_mode RW 1461 modes M_DFF0, M_DFF1, M_SCSI 1462 field PCI2PCI 0x04 1463 field SINGLECMD 0x02 1464 field ABORTPENDING 0x01 1465} 1466 1467/* 1468 * LQ Manager Control 2 1469 */ 1470register LQCTL2 { 1471 address 0x039 1472 access_mode RW 1473 modes M_DFF0, M_DFF1, M_SCSI 1474 field LQIRETRY 0x80 1475 field LQICONTINUE 0x40 1476 field LQITOIDLE 0x20 1477 field LQIPAUSE 0x10 1478 field LQORETRY 0x08 1479 field LQOCONTINUE 0x04 1480 field LQOTOIDLE 0x02 1481 field LQOPAUSE 0x01 1482} 1483 1484/* 1485 * SCSI RAM BIST0 1486 */ 1487register SCSBIST0 { 1488 address 0x039 1489 access_mode RW 1490 modes M_CFG 1491 field GSBISTERR 0x40 1492 field GSBISTDONE 0x20 1493 field GSBISTRUN 0x10 1494 field OSBISTERR 0x04 1495 field OSBISTDONE 0x02 1496 field OSBISTRUN 0x01 1497} 1498 1499/* 1500 * SCSI Sequence Control0 1501 */ 1502register SCSISEQ0 { 1503 address 0x03A 1504 access_mode RW 1505 modes M_DFF0, M_DFF1, M_SCSI 1506 field TEMODEO 0x80 1507 field ENSELO 0x40 1508 field ENARBO 0x20 1509 field FORCEBUSFREE 0x10 1510 field SCSIRSTO 0x01 1511} 1512 1513/* 1514 * SCSI RAM BIST 1 1515 */ 1516register SCSBIST1 { 1517 address 0x03A 1518 access_mode RW 1519 modes M_CFG 1520 field NTBISTERR 0x04 1521 field NTBISTDONE 0x02 1522 field NTBISTRUN 0x01 1523} 1524 1525/* 1526 * SCSI Sequence Control 1 1527 */ 1528register SCSISEQ1 { 1529 address 0x03B 1530 access_mode RW 1531 modes M_DFF0, M_DFF1, M_SCSI 1532 field MANUALCTL 0x40 1533 field ENSELI 0x20 1534 field ENRSELI 0x10 1535 field MANUALP 0x0C 1536 field ENAUTOATNP 0x02 1537 field ALTSTIM 0x01 1538} 1539 1540/* 1541 * SCSI Transfer Control 0 1542 */ 1543register SXFRCTL0 { 1544 address 0x03C 1545 access_mode RW 1546 modes M_SCSI 1547 field DFON 0x80 1548 field DFPEXP 0x40 1549 field BIOSCANCELEN 0x10 1550 field SPIOEN 0x08 1551} 1552 1553/* 1554 * SCSI Transfer Control 1 1555 */ 1556register SXFRCTL1 { 1557 address 0x03D 1558 access_mode RW 1559 modes M_SCSI 1560 field BITBUCKET 0x80 1561 field ENSACHK 0x40 1562 field ENSPCHK 0x20 1563 field STIMESEL 0x18 1564 field ENSTIMER 0x04 1565 field ACTNEGEN 0x02 1566 field STPWEN 0x01 1567} 1568 1569/* 1570 * SCSI Transfer Control 2 1571 */ 1572register SXFRCTL2 { 1573 address 0x03E 1574 access_mode RW 1575 modes M_SCSI 1576 field AUTORSTDIS 0x10 1577 field CMDDMAEN 0x08 1578 field ASU 0x07 1579} 1580 1581/* 1582 * SCSI Bus Initiator IDs 1583 * Bitmask of observed initiators on the bus. 1584 */ 1585register BUSINITID { 1586 address 0x03C 1587 access_mode RW 1588 modes M_CFG 1589 size 2 1590} 1591 1592/* 1593 * Data Length Counters 1594 * Packet byte counter. 1595 */ 1596register DLCOUNT { 1597 address 0x03C 1598 access_mode RW 1599 modes M_DFF0, M_DFF1 1600 size 3 1601} 1602 1603/* 1604 * Data FIFO Status 1605 */ 1606register DFFSTAT { 1607 address 0x03F 1608 access_mode RW 1609 modes M_SCSI 1610 field FIFO1FREE 0x20 1611 field FIFO0FREE 0x10 1612 /* 1613 * On the B, this enum only works 1614 * in the read direction. For writes, 1615 * you must use the B version of the 1616 * CURRFIFO_0 definition which is defined 1617 * as a constant outside of this register 1618 * definition to avoid confusing the 1619 * register pretty printing code. 1620 */ 1621 enum CURRFIFO 0x03 { 1622 CURRFIFO_0, 1623 CURRFIFO_1, 1624 CURRFIFO_NONE 0x3 1625 } 1626} 1627 1628const B_CURRFIFO_0 0x2 1629 1630/* 1631 * SCSI Bus Target IDs 1632 * Bitmask of observed targets on the bus. 1633 */ 1634register BUSTARGID { 1635 address 0x03E 1636 access_mode RW 1637 modes M_CFG 1638 size 2 1639} 1640 1641/* 1642 * SCSI Control Signal Out 1643 */ 1644register SCSISIGO { 1645 address 0x040 1646 access_mode RW 1647 modes M_DFF0, M_DFF1, M_SCSI 1648 field CDO 0x80 1649 field IOO 0x40 1650 field MSGO 0x20 1651 field ATNO 0x10 1652 field SELO 0x08 1653 field BSYO 0x04 1654 field REQO 0x02 1655 field ACKO 0x01 1656/* 1657 * Possible phases to write into SCSISIG0 1658 */ 1659 enum PHASE_MASK CDO|IOO|MSGO { 1660 P_DATAOUT 0x0, 1661 P_DATAIN IOO, 1662 P_DATAOUT_DT P_DATAOUT|MSGO, 1663 P_DATAIN_DT P_DATAIN|MSGO, 1664 P_COMMAND CDO, 1665 P_MESGOUT CDO|MSGO, 1666 P_STATUS CDO|IOO, 1667 P_MESGIN CDO|IOO|MSGO 1668 } 1669} 1670 1671register SCSISIGI { 1672 address 0x041 1673 access_mode RO 1674 modes M_DFF0, M_DFF1, M_SCSI 1675 field CDI 0x80 1676 field IOI 0x40 1677 field MSGI 0x20 1678 field ATNI 0x10 1679 field SELI 0x08 1680 field BSYI 0x04 1681 field REQI 0x02 1682 field ACKI 0x01 1683/* 1684 * Possible phases in SCSISIGI 1685 */ 1686 enum PHASE_MASK CDO|IOO|MSGO { 1687 P_DATAOUT 0x0, 1688 P_DATAIN IOO, 1689 P_DATAOUT_DT P_DATAOUT|MSGO, 1690 P_DATAIN_DT P_DATAIN|MSGO, 1691 P_COMMAND CDO, 1692 P_MESGOUT CDO|MSGO, 1693 P_STATUS CDO|IOO, 1694 P_MESGIN CDO|IOO|MSGO 1695 } 1696} 1697 1698/* 1699 * Multiple Target IDs 1700 * Bitmask of ids to respond as a target. 1701 */ 1702register MULTARGID { 1703 address 0x040 1704 access_mode RW 1705 modes M_CFG 1706 size 2 1707} 1708 1709/* 1710 * SCSI Phase 1711 */ 1712register SCSIPHASE { 1713 address 0x042 1714 access_mode RO 1715 modes M_DFF0, M_DFF1, M_SCSI 1716 field STATUS_PHASE 0x20 1717 field COMMAND_PHASE 0x10 1718 field MSG_IN_PHASE 0x08 1719 field MSG_OUT_PHASE 0x04 1720 field DATA_PHASE_MASK 0x03 { 1721 DATA_OUT_PHASE 0x01, 1722 DATA_IN_PHASE 0x02 1723 } 1724} 1725 1726/* 1727 * SCSI Data 0 Image 1728 */ 1729register SCSIDAT0_IMG { 1730 address 0x043 1731 access_mode RW 1732 modes M_DFF0, M_DFF1, M_SCSI 1733} 1734 1735/* 1736 * SCSI Latched Data 1737 */ 1738register SCSIDAT { 1739 address 0x044 1740 access_mode RW 1741 modes M_DFF0, M_DFF1, M_SCSI 1742 size 2 1743} 1744 1745/* 1746 * SCSI Data Bus 1747 */ 1748register SCSIBUS { 1749 address 0x046 1750 access_mode RW 1751 modes M_DFF0, M_DFF1, M_SCSI 1752 size 2 1753} 1754 1755/* 1756 * Target ID In 1757 */ 1758register TARGIDIN { 1759 address 0x048 1760 access_mode RO 1761 modes M_DFF0, M_DFF1, M_SCSI 1762 field CLKOUT 0x80 1763 field TARGID 0x0F 1764} 1765 1766/* 1767 * Selection/Reselection ID 1768 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1769 * device did not set its own ID. 1770 */ 1771register SELID { 1772 address 0x049 1773 access_mode RW 1774 modes M_DFF0, M_DFF1, M_SCSI 1775 field SELID_MASK 0xf0 1776 field ONEBIT 0x08 1777} 1778 1779/* 1780 * SCSI Block Control 1781 * Controls Bus type and channel selection. SELWIDE allows for the 1782 * coexistence of 8bit and 16bit devices on a wide bus. 1783 */ 1784register SBLKCTL { 1785 address 0x04A 1786 access_mode RW 1787 modes M_DFF0, M_DFF1, M_SCSI 1788 field DIAGLEDEN 0x80 1789 field DIAGLEDON 0x40 1790 field ENAB40 0x08 /* LVD transceiver active */ 1791 field ENAB20 0x04 /* SE/HVD transceiver active */ 1792 field SELWIDE 0x02 1793} 1794 1795/* 1796 * Option Mode 1797 */ 1798register OPTIONMODE { 1799 address 0x04A 1800 access_mode RW 1801 modes M_CFG 1802 field BIOSCANCTL 0x80 1803 field AUTOACKEN 0x40 1804 field BIASCANCTL 0x20 1805 field BUSFREEREV 0x10 1806 field ENDGFORMCHK 0x04 1807 field AUTO_MSGOUT_DE 0x02 1808 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1809} 1810 1811/* 1812 * SCSI Status 0 1813 */ 1814register SSTAT0 { 1815 address 0x04B 1816 access_mode RO 1817 modes M_DFF0, M_DFF1, M_SCSI 1818 field TARGET 0x80 /* Board acting as target */ 1819 field SELDO 0x40 /* Selection Done */ 1820 field SELDI 0x20 /* Board has been selected */ 1821 field SELINGO 0x10 /* Selection In Progress */ 1822 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1823 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1824 field SPIORDY 0x02 /* SCSI PIO Ready */ 1825 field ARBDO 0x01 /* Arbitration Done Out */ 1826} 1827 1828/* 1829 * Clear SCSI Interrupt 0 1830 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1831 */ 1832register CLRSINT0 { 1833 address 0x04B 1834 access_mode WO 1835 modes M_DFF0, M_DFF1, M_SCSI 1836 field CLRSELDO 0x40 1837 field CLRSELDI 0x20 1838 field CLRSELINGO 0x10 1839 field CLRIOERR 0x08 1840 field CLROVERRUN 0x04 1841 field CLRSPIORDY 0x02 1842 field CLRARBDO 0x01 1843} 1844 1845/* 1846 * SCSI Interrupt Mode 0 1847 * Setting any bit will enable the corresponding function 1848 * in SIMODE0 to interrupt via the IRQ pin. 1849 */ 1850register SIMODE0 { 1851 address 0x04B 1852 access_mode RW 1853 modes M_CFG 1854 field ENSELDO 0x40 1855 field ENSELDI 0x20 1856 field ENSELINGO 0x10 1857 field ENIOERR 0x08 1858 field ENOVERRUN 0x04 1859 field ENSPIORDY 0x02 1860 field ENARBDO 0x01 1861} 1862 1863/* 1864 * SCSI Status 1 1865 */ 1866register SSTAT1 { 1867 address 0x04C 1868 access_mode RO 1869 modes M_DFF0, M_DFF1, M_SCSI 1870 field SELTO 0x80 1871 field ATNTARG 0x40 1872 field SCSIRSTI 0x20 1873 field PHASEMIS 0x10 1874 field BUSFREE 0x08 1875 field SCSIPERR 0x04 1876 field STRB2FAST 0x02 1877 field REQINIT 0x01 1878} 1879 1880/* 1881 * Clear SCSI Interrupt 1 1882 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1883 */ 1884register CLRSINT1 { 1885 address 0x04C 1886 access_mode WO 1887 modes M_DFF0, M_DFF1, M_SCSI 1888 field CLRSELTIMEO 0x80 1889 field CLRATNO 0x40 1890 field CLRSCSIRSTI 0x20 1891 field CLRBUSFREE 0x08 1892 field CLRSCSIPERR 0x04 1893 field CLRSTRB2FAST 0x02 1894 field CLRREQINIT 0x01 1895} 1896 1897/* 1898 * SCSI Status 2 1899 */ 1900register SSTAT2 { 1901 address 0x04d 1902 access_mode RO 1903 modes M_DFF0, M_DFF1, M_SCSI 1904 field BUSFREETIME 0xc0 { 1905 BUSFREE_LQO 0x40, 1906 BUSFREE_DFF0 0x80, 1907 BUSFREE_DFF1 0xC0 1908 } 1909 field NONPACKREQ 0x20 1910 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1911 field BSYX 0x08 /* Busy Expander */ 1912 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1913 field SDONE 0x02 /* Modes 0 and 1 only */ 1914 field DMADONE 0x01 /* Modes 0 and 1 only */ 1915} 1916 1917/* 1918 * Clear SCSI Interrupt 2 1919 */ 1920register CLRSINT2 { 1921 address 0x04D 1922 access_mode WO 1923 modes M_DFF0, M_DFF1, M_SCSI 1924 field CLRNONPACKREQ 0x20 1925 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1926 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1927 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1928} 1929 1930/* 1931 * SCSI Interrupt Mode 2 1932 */ 1933register SIMODE2 { 1934 address 0x04D 1935 access_mode RW 1936 modes M_CFG 1937 field ENWIDE_RES 0x04 1938 field ENSDONE 0x02 1939 field ENDMADONE 0x01 1940} 1941 1942/* 1943 * Physical Error Diagnosis 1944 */ 1945register PERRDIAG { 1946 address 0x04E 1947 access_mode RO 1948 modes M_DFF0, M_DFF1, M_SCSI 1949 field HIZERO 0x80 1950 field HIPERR 0x40 1951 field PREVPHASE 0x20 1952 field PARITYERR 0x10 1953 field AIPERR 0x08 1954 field CRCERR 0x04 1955 field DGFORMERR 0x02 1956 field DTERR 0x01 1957} 1958 1959/* 1960 * LQI Manager Current State 1961 */ 1962register LQISTATE { 1963 address 0x04E 1964 access_mode RO 1965 modes M_CFG 1966} 1967 1968/* 1969 * SCSI Offset Count 1970 */ 1971register SOFFCNT { 1972 address 0x04F 1973 access_mode RO 1974 modes M_DFF0, M_DFF1, M_SCSI 1975} 1976 1977/* 1978 * LQO Manager Current State 1979 */ 1980register LQOSTATE { 1981 address 0x04F 1982 access_mode RO 1983 modes M_CFG 1984} 1985 1986/* 1987 * LQI Manager Status 1988 */ 1989register LQISTAT0 { 1990 address 0x050 1991 access_mode RO 1992 modes M_DFF0, M_DFF1, M_SCSI 1993 field LQIATNQAS 0x20 1994 field LQICRCT1 0x10 1995 field LQICRCT2 0x08 1996 field LQIBADLQT 0x04 1997 field LQIATNLQ 0x02 1998 field LQIATNCMD 0x01 1999} 2000 2001/* 2002 * Clear LQI Interrupts 0 2003 */ 2004register CLRLQIINT0 { 2005 address 0x050 2006 access_mode WO 2007 modes M_DFF0, M_DFF1, M_SCSI 2008 field CLRLQIATNQAS 0x20 2009 field CLRLQICRCT1 0x10 2010 field CLRLQICRCT2 0x08 2011 field CLRLQIBADLQT 0x04 2012 field CLRLQIATNLQ 0x02 2013 field CLRLQIATNCMD 0x01 2014} 2015 2016/* 2017 * LQI Manager Interrupt Mode 0 2018 */ 2019register LQIMODE0 { 2020 address 0x050 2021 access_mode RW 2022 modes M_CFG 2023 field ENLQIATNQASK 0x20 2024 field ENLQICRCT1 0x10 2025 field ENLQICRCT2 0x08 2026 field ENLQIBADLQT 0x04 2027 field ENLQIATNLQ 0x02 2028 field ENLQIATNCMD 0x01 2029} 2030 2031/* 2032 * LQI Manager Status 1 2033 */ 2034register LQISTAT1 { 2035 address 0x051 2036 access_mode RO 2037 modes M_DFF0, M_DFF1, M_SCSI 2038 field LQIPHASE_LQ 0x80 2039 field LQIPHASE_NLQ 0x40 2040 field LQIABORT 0x20 2041 field LQICRCI_LQ 0x10 2042 field LQICRCI_NLQ 0x08 2043 field LQIBADLQI 0x04 2044 field LQIOVERI_LQ 0x02 2045 field LQIOVERI_NLQ 0x01 2046} 2047 2048/* 2049 * Clear LQI Manager Interrupts1 2050 */ 2051register CLRLQIINT1 { 2052 address 0x051 2053 access_mode WO 2054 modes M_DFF0, M_DFF1, M_SCSI 2055 field CLRLQIPHASE_LQ 0x80 2056 field CLRLQIPHASE_NLQ 0x40 2057 field CLRLIQABORT 0x20 2058 field CLRLQICRCI_LQ 0x10 2059 field CLRLQICRCI_NLQ 0x08 2060 field CLRLQIBADLQI 0x04 2061 field CLRLQIOVERI_LQ 0x02 2062 field CLRLQIOVERI_NLQ 0x01 2063} 2064 2065/* 2066 * LQI Manager Interrupt Mode 1 2067 */ 2068register LQIMODE1 { 2069 address 0x051 2070 access_mode RW 2071 modes M_CFG 2072 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2073 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2074 field ENLIQABORT 0x20 2075 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ 2076 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ 2077 field ENLQIBADLQI 0x04 2078 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ 2079 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ 2080} 2081 2082/* 2083 * LQI Manager Status 2 2084 */ 2085register LQISTAT2 { 2086 address 0x052 2087 access_mode RO 2088 modes M_DFF0, M_DFF1, M_SCSI 2089 field PACKETIZED 0x80 2090 field LQIPHASE_OUTPKT 0x40 2091 field LQIWORKONLQ 0x20 2092 field LQIWAITFIFO 0x10 2093 field LQISTOPPKT 0x08 2094 field LQISTOPLQ 0x04 2095 field LQISTOPCMD 0x02 2096 field LQIGSAVAIL 0x01 2097} 2098 2099/* 2100 * SCSI Status 3 2101 */ 2102register SSTAT3 { 2103 address 0x053 2104 access_mode RO 2105 modes M_DFF0, M_DFF1, M_SCSI 2106 field NTRAMPERR 0x02 2107 field OSRAMPERR 0x01 2108} 2109 2110/* 2111 * Clear SCSI Status 3 2112 */ 2113register CLRSINT3 { 2114 address 0x053 2115 access_mode WO 2116 modes M_DFF0, M_DFF1, M_SCSI 2117 field CLRNTRAMPERR 0x02 2118 field CLROSRAMPERR 0x01 2119} 2120 2121/* 2122 * SCSI Interrupt Mode 3 2123 */ 2124register SIMODE3 { 2125 address 0x053 2126 access_mode RW 2127 modes M_CFG 2128 field ENNTRAMPERR 0x02 2129 field ENOSRAMPERR 0x01 2130} 2131 2132/* 2133 * LQO Manager Status 0 2134 */ 2135register LQOSTAT0 { 2136 address 0x054 2137 access_mode RO 2138 modes M_DFF0, M_DFF1, M_SCSI 2139 field LQOTARGSCBPERR 0x10 2140 field LQOSTOPT2 0x08 2141 field LQOATNLQ 0x04 2142 field LQOATNPKT 0x02 2143 field LQOTCRC 0x01 2144} 2145 2146/* 2147 * Clear LQO Manager interrupt 0 2148 */ 2149register CLRLQOINT0 { 2150 address 0x054 2151 access_mode WO 2152 modes M_DFF0, M_DFF1, M_SCSI 2153 field CLRLQOTARGSCBPERR 0x10 2154 field CLRLQOSTOPT2 0x08 2155 field CLRLQOATNLQ 0x04 2156 field CLRLQOATNPKT 0x02 2157 field CLRLQOTCRC 0x01 2158} 2159 2160/* 2161 * LQO Manager Interrupt Mode 0 2162 */ 2163register LQOMODE0 { 2164 address 0x054 2165 access_mode RW 2166 modes M_CFG 2167 field ENLQOTARGSCBPERR 0x10 2168 field ENLQOSTOPT2 0x08 2169 field ENLQOATNLQ 0x04 2170 field ENLQOATNPKT 0x02 2171 field ENLQOTCRC 0x01 2172} 2173 2174/* 2175 * LQO Manager Status 1 2176 */ 2177register LQOSTAT1 { 2178 address 0x055 2179 access_mode RO 2180 modes M_DFF0, M_DFF1, M_SCSI 2181 field LQOINITSCBPERR 0x10 2182 field LQOSTOPI2 0x08 2183 field LQOBADQAS 0x04 2184 field LQOBUSFREE 0x02 2185 field LQOPHACHGINPKT 0x01 2186} 2187 2188/* 2189 * Clear LOQ Interrupt 1 2190 */ 2191register CLRLQOINT1 { 2192 address 0x055 2193 access_mode WO 2194 modes M_DFF0, M_DFF1, M_SCSI 2195 field CLRLQOINITSCBPERR 0x10 2196 field CLRLQOSTOPI2 0x08 2197 field CLRLQOBADQAS 0x04 2198 field CLRLQOBUSFREE 0x02 2199 field CLRLQOPHACHGINPKT 0x01 2200} 2201 2202/* 2203 * LQO Manager Interrupt Mode 1 2204 */ 2205register LQOMODE1 { 2206 address 0x055 2207 access_mode RW 2208 modes M_CFG 2209 field ENLQOINITSCBPERR 0x10 2210 field ENLQOSTOPI2 0x08 2211 field ENLQOBADQAS 0x04 2212 field ENLQOBUSFREE 0x02 2213 field ENLQOPHACHGINPKT 0x01 2214} 2215 2216/* 2217 * LQO Manager Status 2 2218 */ 2219register LQOSTAT2 { 2220 address 0x056 2221 access_mode RO 2222 modes M_DFF0, M_DFF1, M_SCSI 2223 field LQOPKT 0xE0 2224 field LQOWAITFIFO 0x10 2225 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2226 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2227} 2228 2229/* 2230 * Output Synchronizer Space Count 2231 */ 2232register OS_SPACE_CNT { 2233 address 0x056 2234 access_mode RO 2235 modes M_CFG 2236} 2237 2238/* 2239 * SCSI Interrupt Mode 1 2240 * Setting any bit will enable the corresponding function 2241 * in SIMODE1 to interrupt via the IRQ pin. 2242 */ 2243register SIMODE1 { 2244 address 0x057 2245 access_mode RW 2246 modes M_DFF0, M_DFF1, M_SCSI 2247 field ENSELTIMO 0x80 2248 field ENATNTARG 0x40 2249 field ENSCSIRST 0x20 2250 field ENPHASEMIS 0x10 2251 field ENBUSFREE 0x08 2252 field ENSCSIPERR 0x04 2253 field ENSTRB2FAST 0x02 2254 field ENREQINIT 0x01 2255} 2256 2257/* 2258 * Good Status FIFO 2259 */ 2260register GSFIFO { 2261 address 0x058 2262 access_mode RO 2263 size 2 2264 modes M_DFF0, M_DFF1, M_SCSI 2265} 2266 2267/* 2268 * Data FIFO SCSI Transfer Control 2269 */ 2270register DFFSXFRCTL { 2271 address 0x05A 2272 access_mode RW 2273 modes M_DFF0, M_DFF1 2274 field DFFBITBUCKET 0x08 2275 field CLRSHCNT 0x04 2276 field CLRCHN 0x02 2277 field RSTCHN 0x01 2278} 2279 2280/* 2281 * Next SCSI Control Block 2282 */ 2283register NEXTSCB { 2284 address 0x05A 2285 access_mode RW 2286 size 2 2287 modes M_SCSI 2288} 2289 2290/* Rev B only. */ 2291register LQOSCSCTL { 2292 address 0x05A 2293 access_mode RW 2294 size 1 2295 modes M_CFG 2296 field LQOH2A_VERSION 0x80 2297 field LQONOCHKOVER 0x01 2298} 2299 2300/* 2301 * SEQ Interrupts 2302 */ 2303register SEQINTSRC { 2304 address 0x05B 2305 access_mode RO 2306 modes M_DFF0, M_DFF1 2307 field CTXTDONE 0x40 2308 field SAVEPTRS 0x20 2309 field CFG4DATA 0x10 2310 field CFG4ISTAT 0x08 2311 field CFG4TSTAT 0x04 2312 field CFG4ICMD 0x02 2313 field CFG4TCMD 0x01 2314} 2315 2316/* 2317 * Clear Arp Interrupts 2318 */ 2319register CLRSEQINTSRC { 2320 address 0x05B 2321 access_mode WO 2322 modes M_DFF0, M_DFF1 2323 field CLRCTXTDONE 0x40 2324 field CLRSAVEPTRS 0x20 2325 field CLRCFG4DATA 0x10 2326 field CLRCFG4ISTAT 0x08 2327 field CLRCFG4TSTAT 0x04 2328 field CLRCFG4ICMD 0x02 2329 field CLRCFG4TCMD 0x01 2330} 2331 2332/* 2333 * SEQ Interrupt Enabled (Shared) 2334 */ 2335register SEQIMODE { 2336 address 0x05C 2337 access_mode RW 2338 modes M_DFF0, M_DFF1 2339 field ENCTXTDONE 0x40 2340 field ENSAVEPTRS 0x20 2341 field ENCFG4DATA 0x10 2342 field ENCFG4ISTAT 0x08 2343 field ENCFG4TSTAT 0x04 2344 field ENCFG4ICMD 0x02 2345 field ENCFG4TCMD 0x01 2346} 2347 2348/* 2349 * Current SCSI Control Block 2350 */ 2351register CURRSCB { 2352 address 0x05C 2353 access_mode RW 2354 size 2 2355 modes M_SCSI 2356} 2357 2358/* 2359 * Data FIFO Status 2360 */ 2361register MDFFSTAT { 2362 address 0x05D 2363 access_mode RO 2364 modes M_DFF0, M_DFF1 2365 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2366 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2367 field LASTSDONE 0x10 2368 field SHVALID 0x08 2369 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2370 field DATAINFIFO 0x02 2371 field FIFOFREE 0x01 2372} 2373 2374/* 2375 * CRC Control 2376 */ 2377register CRCCONTROL { 2378 address 0x05d 2379 access_mode RW 2380 modes M_CFG 2381 field CRCVALCHKEN 0x40 2382} 2383 2384/* 2385 * SCSI Test Control 2386 */ 2387register SCSITEST { 2388 address 0x05E 2389 access_mode RW 2390 modes M_CFG 2391 field CNTRTEST 0x08 2392 field SEL_TXPLL_DEBUG 0x04 2393} 2394 2395/* 2396 * Data FIFO Queue Tag 2397 */ 2398register DFFTAG { 2399 address 0x05E 2400 access_mode RW 2401 size 2 2402 modes M_DFF0, M_DFF1 2403} 2404 2405/* 2406 * Last SCSI Control Block 2407 */ 2408register LASTSCB { 2409 address 0x05E 2410 access_mode RW 2411 size 2 2412 modes M_SCSI 2413} 2414 2415/* 2416 * SCSI I/O Cell Power-down Control 2417 */ 2418register IOPDNCTL { 2419 address 0x05F 2420 access_mode RW 2421 modes M_CFG 2422 field DISABLE_OE 0x80 2423 field PDN_IDIST 0x04 2424 field PDN_DIFFSENSE 0x01 2425} 2426 2427/* 2428 * Shadow Host Address. 2429 */ 2430register SHADDR { 2431 address 0x060 2432 access_mode RO 2433 size 8 2434 modes M_DFF0, M_DFF1 2435} 2436 2437/* 2438 * Data Group CRC Interval. 2439 */ 2440register DGRPCRCI { 2441 address 0x060 2442 access_mode RW 2443 size 2 2444 modes M_CFG 2445} 2446 2447/* 2448 * Data Transfer Negotiation Address 2449 */ 2450register NEGOADDR { 2451 address 0x060 2452 access_mode RW 2453 modes M_SCSI 2454} 2455 2456/* 2457 * Data Transfer Negotiation Data - Period Byte 2458 */ 2459register NEGPERIOD { 2460 address 0x061 2461 access_mode RW 2462 modes M_SCSI 2463} 2464 2465/* 2466 * Packetized CRC Interval 2467 */ 2468register PACKCRCI { 2469 address 0x062 2470 access_mode RW 2471 size 2 2472 modes M_CFG 2473} 2474 2475/* 2476 * Data Transfer Negotiation Data - Offset Byte 2477 */ 2478register NEGOFFSET { 2479 address 0x062 2480 access_mode RW 2481 modes M_SCSI 2482} 2483 2484/* 2485 * Data Transfer Negotiation Data - PPR Options 2486 */ 2487register NEGPPROPTS { 2488 address 0x063 2489 access_mode RW 2490 modes M_SCSI 2491 field PPROPT_PACE 0x08 2492 field PPROPT_QAS 0x04 2493 field PPROPT_DT 0x02 2494 field PPROPT_IUT 0x01 2495} 2496 2497/* 2498 * Data Transfer Negotiation Data - Connection Options 2499 */ 2500register NEGCONOPTS { 2501 address 0x064 2502 access_mode RW 2503 modes M_SCSI 2504 field ENSNAPSHOT 0x40 2505 field RTI_WRTDIS 0x20 2506 field RTI_OVRDTRN 0x10 2507 field ENSLOWCRC 0x08 2508 field ENAUTOATNI 0x04 2509 field ENAUTOATNO 0x02 2510 field WIDEXFER 0x01 2511} 2512 2513/* 2514 * Negotiation Table Annex Column Index. 2515 */ 2516register ANNEXCOL { 2517 address 0x065 2518 access_mode RW 2519 modes M_SCSI 2520} 2521 2522register SCSCHKN { 2523 address 0x066 2524 access_mode RW 2525 modes M_CFG 2526 field STSELSKIDDIS 0x40 2527 field CURRFIFODEF 0x20 2528 field WIDERESEN 0x10 2529 field SDONEMSKDIS 0x08 2530 field DFFACTCLR 0x04 2531 field SHVALIDSTDIS 0x02 2532 field LSTSGCLRDIS 0x01 2533} 2534 2535const AHD_ANNEXCOL_PER_DEV0 4 2536const AHD_NUM_PER_DEV_ANNEXCOLS 4 2537const AHD_ANNEXCOL_PRECOMP_SLEW 4 2538const AHD_PRECOMP_MASK 0x07 2539const AHD_PRECOMP_SHIFT 0 2540const AHD_PRECOMP_CUTBACK_17 0x04 2541const AHD_PRECOMP_CUTBACK_29 0x06 2542const AHD_PRECOMP_CUTBACK_37 0x07 2543const AHD_SLEWRATE_MASK 0x78 2544const AHD_SLEWRATE_SHIFT 3 2545/* 2546 * Rev A has only a single bit (high bit of field) of slew adjustment. 2547 * Rev B has 4 bits. The current default happens to be the same for both. 2548 */ 2549const AHD_SLEWRATE_DEF_REVA 0x08 2550const AHD_SLEWRATE_DEF_REVB 0x08 2551 2552/* Rev A does not have any amplitude setting. */ 2553const AHD_ANNEXCOL_AMPLITUDE 6 2554const AHD_AMPLITUDE_MASK 0x7 2555const AHD_AMPLITUDE_SHIFT 0 2556const AHD_AMPLITUDE_DEF 0x7 2557 2558/* 2559 * Negotiation Table Annex Data Port. 2560 */ 2561register ANNEXDAT { 2562 address 0x066 2563 access_mode RW 2564 modes M_SCSI 2565} 2566 2567/* 2568 * Initiator's Own Id. 2569 * The SCSI ID to use for Selection Out and seen during a reselection.. 2570 */ 2571register IOWNID { 2572 address 0x067 2573 access_mode RW 2574 modes M_SCSI 2575} 2576 2577/* 2578 * 960MHz Phase-Locked Loop Control 0 2579 */ 2580register PLL960CTL0 { 2581 address 0x068 2582 access_mode RW 2583 modes M_CFG 2584 field PLL_VCOSEL 0x80 2585 field PLL_PWDN 0x40 2586 field PLL_NS 0x30 2587 field PLL_ENLUD 0x08 2588 field PLL_ENLPF 0x04 2589 field PLL_DLPF 0x02 2590 field PLL_ENFBM 0x01 2591} 2592 2593/* 2594 * Target Own Id 2595 */ 2596register TOWNID { 2597 address 0x069 2598 access_mode RW 2599 modes M_SCSI 2600} 2601 2602/* 2603 * 960MHz Phase-Locked Loop Control 1 2604 */ 2605register PLL960CTL1 { 2606 address 0x069 2607 access_mode RW 2608 modes M_CFG 2609 field PLL_CNTEN 0x80 2610 field PLL_CNTCLR 0x40 2611 field PLL_RST 0x01 2612} 2613 2614/* 2615 * Expander Signature 2616 */ 2617register XSIG { 2618 address 0x06A 2619 access_mode RW 2620 modes M_SCSI 2621} 2622 2623/* 2624 * Shadow Byte Count 2625 */ 2626register SHCNT { 2627 address 0x068 2628 access_mode RW 2629 size 3 2630 modes M_DFF0, M_DFF1 2631} 2632 2633/* 2634 * Selection Out ID 2635 */ 2636register SELOID { 2637 address 0x06B 2638 access_mode RW 2639 modes M_SCSI 2640} 2641 2642/* 2643 * 960-MHz Phase-Locked Loop Test Count 2644 */ 2645register PLL960CNT0 { 2646 address 0x06A 2647 access_mode RO 2648 size 2 2649 modes M_CFG 2650} 2651 2652/* 2653 * 400-MHz Phase-Locked Loop Control 0 2654 */ 2655register PLL400CTL0 { 2656 address 0x06C 2657 access_mode RW 2658 modes M_CFG 2659 field PLL_VCOSEL 0x80 2660 field PLL_PWDN 0x40 2661 field PLL_NS 0x30 2662 field PLL_ENLUD 0x08 2663 field PLL_ENLPF 0x04 2664 field PLL_DLPF 0x02 2665 field PLL_ENFBM 0x01 2666} 2667 2668/* 2669 * Arbitration Fairness 2670 */ 2671register FAIRNESS { 2672 address 0x06C 2673 access_mode RW 2674 size 2 2675 modes M_SCSI 2676} 2677 2678/* 2679 * 400-MHz Phase-Locked Loop Control 1 2680 */ 2681register PLL400CTL1 { 2682 address 0x06D 2683 access_mode RW 2684 modes M_CFG 2685 field PLL_CNTEN 0x80 2686 field PLL_CNTCLR 0x40 2687 field PLL_RST 0x01 2688} 2689 2690/* 2691 * Arbitration Unfairness 2692 */ 2693register UNFAIRNESS { 2694 address 0x06E 2695 access_mode RW 2696 size 2 2697 modes M_SCSI 2698} 2699 2700/* 2701 * 400-MHz Phase-Locked Loop Test Count 2702 */ 2703register PLL400CNT0 { 2704 address 0x06E 2705 access_mode RO 2706 size 2 2707 modes M_CFG 2708} 2709 2710/* 2711 * SCB Page Pointer 2712 */ 2713register SCBPTR { 2714 address 0x0A8 2715 access_mode RW 2716 size 2 2717 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2718} 2719 2720/* 2721 * CMC SCB Array Count 2722 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2723 * Transfers must be 8byte aligned and sized. 2724 */ 2725register CCSCBACNT { 2726 address 0x0AB 2727 access_mode RW 2728 modes M_CCHAN 2729} 2730 2731/* 2732 * SCB Autopointer 2733 * SCB-Next Address Snooping logic. When an SCB is transferred to 2734 * the card, the next SCB address to be used by the CMC array can 2735 * be autoloaded from that transfer. 2736 */ 2737register SCBAUTOPTR { 2738 address 0x0AB 2739 access_mode RW 2740 modes M_CFG 2741 field AUSCBPTR_EN 0x80 2742 field SCBPTR_ADDR 0x38 2743 field SCBPTR_OFF 0x07 2744} 2745 2746/* 2747 * CMC SG Ram Address Pointer 2748 */ 2749register CCSGADDR { 2750 address 0x0AC 2751 access_mode RW 2752 modes M_DFF0, M_DFF1 2753} 2754 2755/* 2756 * CMC SCB RAM Address Pointer 2757 */ 2758register CCSCBADDR { 2759 address 0x0AC 2760 access_mode RW 2761 modes M_CCHAN 2762} 2763 2764/* 2765 * CMC SCB Ram Back-up Address Pointer 2766 * Indicates the true stop location of transfers halted prior 2767 * to SCBHCNT going to 0. 2768 */ 2769register CCSCBADR_BK { 2770 address 0x0AC 2771 access_mode RO 2772 modes M_CFG 2773} 2774 2775/* 2776 * CMC SG Control 2777 */ 2778register CCSGCTL { 2779 address 0x0AD 2780 access_mode RW 2781 modes M_DFF0, M_DFF1 2782 field CCSGDONE 0x80 2783 field SG_CACHE_AVAIL 0x10 2784 field CCSGENACK 0x08 2785 mask CCSGEN 0x0C 2786 field SG_FETCH_REQ 0x02 2787 field CCSGRESET 0x01 2788} 2789 2790/* 2791 * CMD SCB Control 2792 */ 2793register CCSCBCTL { 2794 address 0x0AD 2795 access_mode RW 2796 modes M_CCHAN 2797 field CCSCBDONE 0x80 2798 field ARRDONE 0x40 2799 field CCARREN 0x10 2800 field CCSCBEN 0x08 2801 field CCSCBDIR 0x04 2802 field CCSCBRESET 0x01 2803} 2804 2805/* 2806 * CMC Ram BIST 2807 */ 2808register CMC_RAMBIST { 2809 address 0x0AD 2810 access_mode RW 2811 modes M_CFG 2812 field SG_ELEMENT_SIZE 0x80 2813 field SCBRAMBIST_FAIL 0x40 2814 field SG_BIST_FAIL 0x20 2815 field SG_BIST_EN 0x10 2816 field CMC_BUFFER_BIST_FAIL 0x02 2817 field CMC_BUFFER_BIST_EN 0x01 2818} 2819 2820/* 2821 * CMC SG RAM Data Port 2822 */ 2823register CCSGRAM { 2824 address 0x0B0 2825 access_mode RW 2826 modes M_DFF0, M_DFF1 2827} 2828 2829/* 2830 * CMC SCB RAM Data Port 2831 */ 2832register CCSCBRAM { 2833 address 0x0B0 2834 access_mode RW 2835 modes M_CCHAN 2836} 2837 2838/* 2839 * Flex DMA Address. 2840 */ 2841register FLEXADR { 2842 address 0x0B0 2843 access_mode RW 2844 size 3 2845 modes M_SCSI 2846} 2847 2848/* 2849 * Flex DMA Byte Count 2850 */ 2851register FLEXCNT { 2852 address 0x0B3 2853 access_mode RW 2854 size 2 2855 modes M_SCSI 2856} 2857 2858/* 2859 * Flex DMA Status 2860 */ 2861register FLEXDMASTAT { 2862 address 0x0B5 2863 access_mode RW 2864 modes M_SCSI 2865 field FLEXDMAERR 0x02 2866 field FLEXDMADONE 0x01 2867} 2868 2869/* 2870 * Flex DMA Data Port 2871 */ 2872register FLEXDATA { 2873 address 0x0B6 2874 access_mode RW 2875 modes M_SCSI 2876} 2877 2878/* 2879 * Board Data 2880 */ 2881register BRDDAT { 2882 address 0x0B8 2883 access_mode RW 2884 modes M_SCSI 2885} 2886 2887/* 2888 * Board Control 2889 */ 2890register BRDCTL { 2891 address 0x0B9 2892 access_mode RW 2893 modes M_SCSI 2894 field FLXARBACK 0x80 2895 field FLXARBREQ 0x40 2896 field BRDADDR 0x38 2897 field BRDEN 0x04 2898 field BRDRW 0x02 2899 field BRDSTB 0x01 2900} 2901 2902/* 2903 * Serial EEPROM Address 2904 */ 2905register SEEADR { 2906 address 0x0BA 2907 access_mode RW 2908 modes M_SCSI 2909} 2910 2911/* 2912 * Serial EEPROM Data 2913 */ 2914register SEEDAT { 2915 address 0x0BC 2916 access_mode RW 2917 size 2 2918 modes M_SCSI 2919} 2920 2921/* 2922 * Serial EEPROM Status 2923 */ 2924register SEESTAT { 2925 address 0x0BE 2926 access_mode RO 2927 modes M_SCSI 2928 field INIT_DONE 0x80 2929 field SEEOPCODE 0x70 2930 field LDALTID_L 0x08 2931 field SEEARBACK 0x04 2932 field SEEBUSY 0x02 2933 field SEESTART 0x01 2934} 2935 2936/* 2937 * Serial EEPROM Control 2938 */ 2939register SEECTL { 2940 address 0x0BE 2941 access_mode RW 2942 modes M_SCSI 2943 field SEEOPCODE 0x70 { 2944 SEEOP_ERASE 0x70, 2945 SEEOP_READ 0x60, 2946 SEEOP_WRITE 0x50, 2947 /* 2948 * The following four commands use special 2949 * addresses for differentiation. 2950 */ 2951 SEEOP_ERAL 0x40 2952 } 2953 mask SEEOP_EWEN 0x40 2954 mask SEEOP_WALL 0x40 2955 mask SEEOP_EWDS 0x40 2956 field SEERST 0x02 2957 field SEESTART 0x01 2958} 2959 2960const SEEOP_ERAL_ADDR 0x80 2961const SEEOP_EWEN_ADDR 0xC0 2962const SEEOP_WRAL_ADDR 0x40 2963const SEEOP_EWDS_ADDR 0x00 2964 2965/* 2966 * SCB Counter 2967 */ 2968register SCBCNT { 2969 address 0x0BF 2970 access_mode RW 2971 modes M_SCSI 2972} 2973 2974/* 2975 * Data FIFO Write Address 2976 * Pointer to the next QWD location to be written to the data FIFO. 2977 */ 2978register DFWADDR { 2979 address 0x0C0 2980 access_mode RW 2981 size 2 2982 modes M_DFF0, M_DFF1 2983} 2984 2985/* 2986 * DSP Filter Control 2987 */ 2988register DSPFLTRCTL { 2989 address 0x0C0 2990 access_mode RW 2991 modes M_CFG 2992 field FLTRDISABLE 0x20 2993 field EDGESENSE 0x10 2994 field DSPFCNTSEL 0x0F 2995} 2996 2997/* 2998 * DSP Data Channel Control 2999 */ 3000register DSPDATACTL { 3001 address 0x0C1 3002 access_mode RW 3003 modes M_CFG 3004 field BYPASSENAB 0x80 3005 field DESQDIS 0x10 3006 field RCVROFFSTDIS 0x04 3007 field XMITOFFSTDIS 0x02 3008} 3009 3010/* 3011 * Data FIFO Read Address 3012 * Pointer to the next QWD location to be read from the data FIFO. 3013 */ 3014register DFRADDR { 3015 address 0x0C2 3016 access_mode RW 3017 size 2 3018 modes M_DFF0, M_DFF1 3019} 3020 3021/* 3022 * DSP REQ Control 3023 */ 3024register DSPREQCTL { 3025 address 0x0C2 3026 access_mode RW 3027 modes M_CFG 3028 field MANREQCTL 0xC0 3029 field MANREQDLY 0x3F 3030} 3031 3032/* 3033 * DSP ACK Control 3034 */ 3035register DSPACKCTL { 3036 address 0x0C3 3037 access_mode RW 3038 modes M_CFG 3039 field MANACKCTL 0xC0 3040 field MANACKDLY 0x3F 3041} 3042 3043/* 3044 * Data FIFO Data 3045 * Read/Write byte port into the data FIFO. The read and write 3046 * FIFO pointers increment with each read and write respectively 3047 * to this port. 3048 */ 3049register DFDAT { 3050 address 0x0C4 3051 access_mode RW 3052 modes M_DFF0, M_DFF1 3053} 3054 3055/* 3056 * DSP Channel Select 3057 */ 3058register DSPSELECT { 3059 address 0x0C4 3060 access_mode RW 3061 modes M_CFG 3062 field AUTOINCEN 0x80 3063 field DSPSEL 0x1F 3064} 3065 3066const NUMDSPS 0x14 3067 3068/* 3069 * Write Bias Control 3070 */ 3071register WRTBIASCTL { 3072 address 0x0C5 3073 access_mode WO 3074 modes M_CFG 3075 field AUTOXBCDIS 0x80 3076 field XMITMANVAL 0x3F 3077} 3078 3079/* 3080 * Currently the WRTBIASCTL is the same as the default. 3081 */ 3082const WRTBIASCTL_HP_DEFAULT 0x0 3083 3084/* 3085 * Receiver Bias Control 3086 */ 3087register RCVRBIOSCTL { 3088 address 0x0C6 3089 access_mode WO 3090 modes M_CFG 3091 field AUTORBCDIS 0x80 3092 field RCVRMANVAL 0x3F 3093} 3094 3095/* 3096 * Write Bias Calculator 3097 */ 3098register WRTBIASCALC { 3099 address 0x0C7 3100 access_mode RO 3101 modes M_CFG 3102} 3103 3104/* 3105 * Data FIFO Pointers 3106 * Contains the byte offset from DFWADDR and DWRADDR to the current 3107 * FIFO write/read locations. 3108 */ 3109register DFPTRS { 3110 address 0x0C8 3111 access_mode RW 3112 modes M_DFF0, M_DFF1 3113} 3114 3115/* 3116 * Receiver Bias Calculator 3117 */ 3118register RCVRBIASCALC { 3119 address 0x0C8 3120 access_mode RO 3121 modes M_CFG 3122} 3123 3124/* 3125 * Data FIFO Backup Read Pointer 3126 * Contains the data FIFO address to be restored if the last 3127 * data accessed from the data FIFO was not transferred successfully. 3128 */ 3129register DFBKPTR { 3130 address 0x0C9 3131 access_mode RW 3132 size 2 3133 modes M_DFF0, M_DFF1 3134} 3135 3136/* 3137 * Skew Calculator 3138 */ 3139register SKEWCALC { 3140 address 0x0C9 3141 access_mode RO 3142 modes M_CFG 3143} 3144 3145/* 3146 * Data FIFO Debug Control 3147 */ 3148register DFDBCTL { 3149 address 0x0CB 3150 access_mode RW 3151 modes M_DFF0, M_DFF1 3152 field DFF_CIO_WR_RDY 0x20 3153 field DFF_CIO_RD_RDY 0x10 3154 field DFF_DIR_ERR 0x08 3155 field DFF_RAMBIST_FAIL 0x04 3156 field DFF_RAMBIST_DONE 0x02 3157 field DFF_RAMBIST_EN 0x01 3158} 3159 3160/* 3161 * Data FIFO Space Count 3162 * Number of FIFO locations that are free. 3163 */ 3164register DFSCNT { 3165 address 0x0CC 3166 access_mode RO 3167 size 2 3168 modes M_DFF0, M_DFF1 3169} 3170 3171/* 3172 * Data FIFO Byte Count 3173 * Number of filled FIFO locations. 3174 */ 3175register DFBCNT { 3176 address 0x0CE 3177 access_mode RO 3178 size 2 3179 modes M_DFF0, M_DFF1 3180} 3181 3182/* 3183 * Sequencer Program Overlay Address. 3184 * Low address must be written prior to high address. 3185 */ 3186register OVLYADDR { 3187 address 0x0D4 3188 modes M_SCSI 3189 size 2 3190 access_mode RW 3191} 3192 3193/* 3194 * Sequencer Control 0 3195 * Error detection mode, speed configuration, 3196 * single step, breakpoints and program load. 3197 */ 3198register SEQCTL0 { 3199 address 0x0D6 3200 access_mode RW 3201 field PERRORDIS 0x80 3202 field PAUSEDIS 0x40 3203 field FAILDIS 0x20 3204 field FASTMODE 0x10 3205 field BRKADRINTEN 0x08 3206 field STEP 0x04 3207 field SEQRESET 0x02 3208 field LOADRAM 0x01 3209} 3210 3211/* 3212 * Sequencer Control 1 3213 * Instruction RAM Diagnostics 3214 */ 3215register SEQCTL1 { 3216 address 0x0D7 3217 access_mode RW 3218 field OVRLAY_DATA_CHK 0x08 3219 field RAMBIST_DONE 0x04 3220 field RAMBIST_FAIL 0x02 3221 field RAMBIST_EN 0x01 3222} 3223 3224/* 3225 * Sequencer Flags 3226 * Zero and Carry state of the ALU. 3227 */ 3228register FLAGS { 3229 address 0x0D8 3230 access_mode RO 3231 field ZERO 0x02 3232 field CARRY 0x01 3233} 3234 3235/* 3236 * Sequencer Interrupt Control 3237 */ 3238register SEQINTCTL { 3239 address 0x0D9 3240 access_mode RW 3241 field INTVEC1DSL 0x80 3242 field INT1_CONTEXT 0x20 3243 field SCS_SEQ_INT1M1 0x10 3244 field SCS_SEQ_INT1M0 0x08 3245 field INTMASK2 0x04 3246 field INTMASK1 0x02 3247 field IRET 0x01 3248} 3249 3250/* 3251 * Sequencer RAM Data Port 3252 * Single byte window into the Sequencer Instruction Ram area starting 3253 * at the address specified by OVLYADDR. To write a full instruction word, 3254 * simply write four bytes in succession. OVLYADDR will increment after the 3255 * most significant instruction byte (the byte with the parity bit) is written. 3256 */ 3257register SEQRAM { 3258 address 0x0DA 3259 access_mode RW 3260} 3261 3262/* 3263 * Sequencer Program Counter 3264 * Low byte must be written prior to high byte. 3265 */ 3266register PRGMCNT { 3267 address 0x0DE 3268 access_mode RW 3269 size 2 3270} 3271 3272/* 3273 * Accumulator 3274 */ 3275register ACCUM { 3276 address 0x0E0 3277 access_mode RW 3278 accumulator 3279} 3280 3281/* 3282 * Source Index Register 3283 * Incrementing index for reads of SINDIR and the destination (low byte only) 3284 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3285 * Example: 3286 * mvi 0xFF call some_routine; 3287 * 3288 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3289 */ 3290register SINDEX { 3291 address 0x0E2 3292 access_mode RW 3293 size 2 3294 sindex 3295} 3296 3297/* 3298 * Destination Index Register 3299 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3300 */ 3301register DINDEX { 3302 address 0x0E4 3303 access_mode RW 3304 size 2 3305} 3306 3307/* 3308 * Break Address 3309 * Sequencer instruction breakpoint address address. 3310 */ 3311register BRKADDR0 { 3312 address 0x0E6 3313 access_mode RW 3314} 3315 3316register BRKADDR1 { 3317 address 0x0E6 3318 access_mode RW 3319 field BRKDIS 0x80 /* Disable Breakpoint */ 3320} 3321 3322/* 3323 * All Ones 3324 * All reads to this register return the value 0xFF. 3325 */ 3326register ALLONES { 3327 address 0x0E8 3328 access_mode RO 3329 allones 3330} 3331 3332/* 3333 * All Zeros 3334 * All reads to this register return the value 0. 3335 */ 3336register ALLZEROS { 3337 address 0x0EA 3338 access_mode RO 3339 allzeros 3340} 3341 3342/* 3343 * No Destination 3344 * Writes to this register have no effect. 3345 */ 3346register NONE { 3347 address 0x0EA 3348 access_mode WO 3349 none 3350} 3351 3352/* 3353 * Source Index Indirect 3354 * Reading this register is equivalent to reading (register_base + SINDEX) and 3355 * incrementing SINDEX by 1. 3356 */ 3357register SINDIR { 3358 address 0x0EC 3359 access_mode RO 3360} 3361 3362/* 3363 * Destination Index Indirect 3364 * Writing this register is equivalent to writing to (register_base + DINDEX) 3365 * and incrementing DINDEX by 1. 3366 */ 3367register DINDIR { 3368 address 0x0ED 3369 access_mode WO 3370} 3371 3372/* 3373 * Function One 3374 * 2's complement to bit value conversion. Write the 2's complement value 3375 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3376 * on the next read of this register. 3377 * Example: 3378 * Write 0x60 3379 * Read 0x40 3380 */ 3381register FUNCTION1 { 3382 address 0x0F0 3383 access_mode RW 3384} 3385 3386/* 3387 * Stack 3388 * Window into the stack. Each stack location is 10 bits wide reported 3389 * low byte followed by high byte. There are 8 stack locations. 3390 */ 3391register STACK { 3392 address 0x0F2 3393 access_mode RW 3394} 3395 3396/* 3397 * Interrupt Vector 1 Address 3398 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3399 */ 3400register INTVEC1_ADDR { 3401 address 0x0F4 3402 access_mode RW 3403 size 2 3404 modes M_CFG 3405} 3406 3407/* 3408 * Current Address 3409 * Address of the SEQRAM instruction currently executing instruction. 3410 */ 3411register CURADDR { 3412 address 0x0F4 3413 access_mode RW 3414 size 2 3415 modes M_SCSI 3416} 3417 3418/* 3419 * Interrupt Vector 2 Address 3420 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3421 */ 3422register INTVEC2_ADDR { 3423 address 0x0F6 3424 access_mode RW 3425 size 2 3426 modes M_CFG 3427} 3428 3429/* 3430 * Last Address 3431 * Address of the SEQRAM instruction executed prior to the current instruction. 3432 */ 3433register LASTADDR { 3434 address 0x0F6 3435 access_mode RW 3436 size 2 3437 modes M_SCSI 3438} 3439 3440register AHD_PCI_CONFIG_BASE { 3441 address 0x100 3442 access_mode RW 3443 size 256 3444 modes M_CFG 3445} 3446 3447/* ---------------------- Scratch RAM Offsets ------------------------- */ 3448scratch_ram { 3449 /* Mode Specific */ 3450 address 0x0A0 3451 size 8 3452 modes 0, 1, 2, 3 3453 REG0 { 3454 size 2 3455 } 3456 REG1 { 3457 size 2 3458 } 3459 REG_ISR { 3460 size 2 3461 } 3462 SG_STATE { 3463 size 1 3464 field SEGS_AVAIL 0x01 3465 field LOADING_NEEDED 0x02 3466 field FETCH_INPROG 0x04 3467 } 3468 /* 3469 * Track whether the transfer byte count for 3470 * the current data phase is odd. 3471 */ 3472 DATA_COUNT_ODD { 3473 size 1 3474 } 3475} 3476 3477scratch_ram { 3478 /* Mode Specific */ 3479 address 0x0F8 3480 size 8 3481 modes 0, 1, 2, 3 3482 LONGJMP_ADDR { 3483 size 2 3484 } 3485 ACCUM_SAVE { 3486 size 1 3487 } 3488} 3489 3490 3491scratch_ram { 3492 address 0x100 3493 size 128 3494 modes 0, 1, 2, 3 3495 /* 3496 * Per "other-id" execution queues. We use an array of 3497 * tail pointers into lists of SCBs sorted by "other-id". 3498 * The execution head pointer threads the head SCBs for 3499 * each list. 3500 */ 3501 WAITING_SCB_TAILS { 3502 size 32 3503 } 3504 WAITING_TID_HEAD { 3505 size 2 3506 } 3507 WAITING_TID_TAIL { 3508 size 2 3509 } 3510 /* 3511 * SCBID of the next SCB in the new SCB queue. 3512 */ 3513 NEXT_QUEUED_SCB_ADDR { 3514 size 4 3515 } 3516 /* 3517 * head of list of SCBs that have 3518 * completed but have not been 3519 * put into the qoutfifo. 3520 */ 3521 COMPLETE_SCB_HEAD { 3522 size 2 3523 } 3524 /* 3525 * The list of completed SCBs in 3526 * the active DMA. 3527 */ 3528 COMPLETE_SCB_DMAINPROG_HEAD { 3529 size 2 3530 } 3531 /* 3532 * head of list of SCBs that have 3533 * completed but need to be uploaded 3534 * to the host prior to being completed. 3535 */ 3536 COMPLETE_DMA_SCB_HEAD { 3537 size 2 3538 } 3539 /* 3540 * tail of list of SCBs that have 3541 * completed but need to be uploaded 3542 * to the host prior to being completed. 3543 */ 3544 COMPLETE_DMA_SCB_TAIL { 3545 size 2 3546 } 3547 /* 3548 * head of list of SCBs that have 3549 * been uploaded to the host, but cannot 3550 * be completed until the QFREEZE is in 3551 * full effect (i.e. no selections pending). 3552 */ 3553 COMPLETE_ON_QFREEZE_HEAD { 3554 size 2 3555 } 3556 /* 3557 * Counting semaphore to prevent new select-outs 3558 * The queue is frozen so long as the sequencer 3559 * and kernel freeze counts differ. 3560 */ 3561 QFREEZE_COUNT { 3562 size 2 3563 } 3564 KERNEL_QFREEZE_COUNT { 3565 size 2 3566 } 3567 /* 3568 * Mode to restore on legacy idle loop exit. 3569 */ 3570 SAVED_MODE { 3571 size 1 3572 } 3573 /* 3574 * Single byte buffer used to designate the type or message 3575 * to send to a target. 3576 */ 3577 MSG_OUT { 3578 size 1 3579 } 3580 /* Parameters for DMA Logic */ 3581 DMAPARAMS { 3582 size 1 3583 field PRELOADEN 0x80 3584 field WIDEODD 0x40 3585 field SCSIEN 0x20 3586 field SDMAEN 0x10 3587 field SDMAENACK 0x10 3588 field HDMAEN 0x08 3589 field HDMAENACK 0x08 3590 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3591 field FIFOFLUSH 0x02 3592 field FIFORESET 0x01 3593 } 3594 SEQ_FLAGS { 3595 size 1 3596 field NOT_IDENTIFIED 0x80 3597 field NO_CDB_SENT 0x40 3598 field TARGET_CMD_IS_TAGGED 0x40 3599 field DPHASE 0x20 3600 /* Target flags */ 3601 field TARG_CMD_PENDING 0x10 3602 field CMDPHASE_PENDING 0x08 3603 field DPHASE_PENDING 0x04 3604 field SPHASE_PENDING 0x02 3605 field NO_DISCONNECT 0x01 3606 } 3607 /* 3608 * Temporary storage for the 3609 * target/channel/lun of a 3610 * reconnecting target 3611 */ 3612 SAVED_SCSIID { 3613 size 1 3614 } 3615 SAVED_LUN { 3616 size 1 3617 } 3618 /* 3619 * The last bus phase as seen by the sequencer. 3620 */ 3621 LASTPHASE { 3622 size 1 3623 field CDI 0x80 3624 field IOI 0x40 3625 field MSGI 0x20 3626 field P_BUSFREE 0x01 3627 enum PHASE_MASK CDO|IOO|MSGO { 3628 P_DATAOUT 0x0, 3629 P_DATAIN IOO, 3630 P_DATAOUT_DT P_DATAOUT|MSGO, 3631 P_DATAIN_DT P_DATAIN|MSGO, 3632 P_COMMAND CDO, 3633 P_MESGOUT CDO|MSGO, 3634 P_STATUS CDO|IOO, 3635 P_MESGIN CDO|IOO|MSGO 3636 } 3637 } 3638 /* 3639 * Value to "or" into the SCBPTR[1] value to 3640 * indicate that an entry in the QINFIFO is valid. 3641 */ 3642 QOUTFIFO_ENTRY_VALID_TAG { 3643 size 1 3644 } 3645 /* 3646 * Kernel and sequencer offsets into the queue of 3647 * incoming target mode command descriptors. The 3648 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3649 */ 3650 KERNEL_TQINPOS { 3651 size 1 3652 } 3653 TQINPOS { 3654 size 1 3655 } 3656 /* 3657 * Base address of our shared data with the kernel driver in host 3658 * memory. This includes the qoutfifo and target mode 3659 * incoming command queue. 3660 */ 3661 SHARED_DATA_ADDR { 3662 size 4 3663 } 3664 /* 3665 * Pointer to location in host memory for next 3666 * position in the qoutfifo. 3667 */ 3668 QOUTFIFO_NEXT_ADDR { 3669 size 4 3670 } 3671 ARG_1 { 3672 size 1 3673 mask SEND_MSG 0x80 3674 mask SEND_SENSE 0x40 3675 mask SEND_REJ 0x20 3676 mask MSGOUT_PHASEMIS 0x10 3677 mask EXIT_MSG_LOOP 0x08 3678 mask CONT_MSG_LOOP_WRITE 0x04 3679 mask CONT_MSG_LOOP_READ 0x03 3680 mask CONT_MSG_LOOP_TARG 0x02 3681 alias RETURN_1 3682 } 3683 ARG_2 { 3684 size 1 3685 alias RETURN_2 3686 } 3687 3688 /* 3689 * Snapshot of MSG_OUT taken after each message is sent. 3690 */ 3691 LAST_MSG { 3692 size 1 3693 } 3694 3695 /* 3696 * Sequences the kernel driver has okayed for us. This allows 3697 * the driver to do things like prevent initiator or target 3698 * operations. 3699 */ 3700 SCSISEQ_TEMPLATE { 3701 size 1 3702 field MANUALCTL 0x40 3703 field ENSELI 0x20 3704 field ENRSELI 0x10 3705 field MANUALP 0x0C 3706 field ENAUTOATNP 0x02 3707 field ALTSTIM 0x01 3708 } 3709 3710 /* 3711 * The initiator specified tag for this target mode transaction. 3712 */ 3713 INITIATOR_TAG { 3714 size 1 3715 } 3716 3717 SEQ_FLAGS2 { 3718 size 1 3719 field PENDING_MK_MESSAGE 0x01 3720 field TARGET_MSG_PENDING 0x02 3721 field SELECTOUT_QFROZEN 0x04 3722 } 3723 3724 ALLOCFIFO_SCBPTR { 3725 size 2 3726 } 3727 3728 /* 3729 * The maximum amount of time to wait, when interrupt coalescing 3730 * is enabled, before issuing a CMDCMPLT interrupt for a completed 3731 * command. 3732 */ 3733 INT_COALESCING_TIMER { 3734 size 2 3735 } 3736 3737 /* 3738 * The maximum number of commands to coalesce into a single interrupt. 3739 * Actually the 2's complement of that value to simplify sequencer 3740 * code. 3741 */ 3742 INT_COALESCING_MAXCMDS { 3743 size 1 3744 } 3745 3746 /* 3747 * The minimum number of commands still outstanding required 3748 * to continue coalescing (2's complement of value). 3749 */ 3750 INT_COALESCING_MINCMDS { 3751 size 1 3752 } 3753 3754 /* 3755 * Number of commands "in-flight". 3756 */ 3757 CMDS_PENDING { 3758 size 2 3759 } 3760 3761 /* 3762 * The count of commands that have been coalesced. 3763 */ 3764 INT_COALESCING_CMDCOUNT { 3765 size 1 3766 } 3767 3768 /* 3769 * Since the HS_MAIBOX is self clearing, copy its contents to 3770 * this position in scratch ram every time it changes. 3771 */ 3772 LOCAL_HS_MAILBOX { 3773 size 1 3774 } 3775 /* 3776 * Target-mode CDB type to CDB length table used 3777 * in non-packetized operation. 3778 */ 3779 CMDSIZE_TABLE { 3780 size 8 3781 } 3782 /* 3783 * When an SCB with the MK_MESSAGE flag is 3784 * queued to the controller, it cannot enter 3785 * the waiting for selection list until the 3786 * selections for any previously queued 3787 * commands to that target complete. During 3788 * the wait, the MK_MESSAGE SCB is queued 3789 * here. 3790 */ 3791 MK_MESSAGE_SCB { 3792 size 2 3793 } 3794 /* 3795 * Saved SCSIID of MK_MESSAGE_SCB to avoid 3796 * an extra SCBPTR operation when deciding 3797 * if the MK_MESSAGE_SCB can be run. 3798 */ 3799 MK_MESSAGE_SCSIID { 3800 size 1 3801 } 3802} 3803 3804/************************* Hardware SCB Definition ****************************/ 3805scb { 3806 address 0x180 3807 size 64 3808 modes 0, 1, 2, 3 3809 SCB_RESIDUAL_DATACNT { 3810 size 4 3811 alias SCB_CDB_STORE 3812 alias SCB_HOST_CDB_PTR 3813 } 3814 SCB_RESIDUAL_SGPTR { 3815 size 4 3816 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3817 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3818 field SG_LIST_NULL 0x01 /* In the first byte */ 3819 } 3820 SCB_SCSI_STATUS { 3821 size 1 3822 alias SCB_HOST_CDB_LEN 3823 } 3824 SCB_TARGET_PHASES { 3825 size 1 3826 } 3827 SCB_TARGET_DATA_DIR { 3828 size 1 3829 } 3830 SCB_TARGET_ITAG { 3831 size 1 3832 } 3833 SCB_SENSE_BUSADDR { 3834 /* 3835 * Only valid if CDB length is less than 13 bytes or 3836 * we are using a CDB pointer. Otherwise contains 3837 * the last 4 bytes of embedded cdb information. 3838 */ 3839 size 4 3840 alias SCB_NEXT_COMPLETE 3841 } 3842 SCB_TAG { 3843 alias SCB_FIFO_USE_COUNT 3844 size 2 3845 } 3846 SCB_CONTROL { 3847 size 1 3848 field TARGET_SCB 0x80 3849 field DISCENB 0x40 3850 field TAG_ENB 0x20 3851 field MK_MESSAGE 0x10 3852 field STATUS_RCVD 0x08 3853 field DISCONNECTED 0x04 3854 field SCB_TAG_TYPE 0x03 3855 } 3856 SCB_SCSIID { 3857 size 1 3858 field TID 0xF0 3859 field OID 0x0F 3860 } 3861 SCB_LUN { 3862 size 1 3863 field LID 0xff 3864 } 3865 SCB_TASK_ATTRIBUTE { 3866 size 1 3867 /* 3868 * Overloaded field for non-packetized 3869 * ignore wide residue message handling. 3870 */ 3871 field SCB_XFERLEN_ODD 0x01 3872 } 3873 SCB_CDB_LEN { 3874 size 1 3875 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3876 } 3877 SCB_TASK_MANAGEMENT { 3878 size 1 3879 } 3880 SCB_DATAPTR { 3881 size 8 3882 } 3883 SCB_DATACNT { 3884 /* 3885 * The last byte is really the high address bits for 3886 * the data address. 3887 */ 3888 size 4 3889 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3890 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3891 } 3892 SCB_SGPTR { 3893 size 4 3894 field SG_STATUS_VALID 0x04 /* In the first byte */ 3895 field SG_FULL_RESID 0x02 /* In the first byte */ 3896 field SG_LIST_NULL 0x01 /* In the first byte */ 3897 } 3898 SCB_BUSADDR { 3899 size 4 3900 } 3901 SCB_NEXT { 3902 alias SCB_NEXT_SCB_BUSADDR 3903 size 2 3904 } 3905 SCB_NEXT2 { 3906 size 2 3907 } 3908 SCB_SPARE { 3909 size 8 3910 alias SCB_PKT_LUN 3911 } 3912 SCB_DISCONNECTED_LISTS { 3913 size 8 3914 } 3915} 3916 3917/*********************************** Constants ********************************/ 3918const MK_MESSAGE_BIT_OFFSET 4 3919const TID_SHIFT 4 3920const TARGET_CMD_CMPLT 0xfe 3921const INVALID_ADDR 0x80 3922#define SCB_LIST_NULL 0xff 3923#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 3924 3925const CCSGADDR_MAX 0x80 3926const CCSCBADDR_MAX 0x80 3927const CCSGRAM_MAXSEGS 16 3928 3929/* Selection Timeout Timer Constants */ 3930const STIMESEL_SHIFT 3 3931const STIMESEL_MIN 0x18 3932const STIMESEL_BUG_ADJ 0x8 3933 3934/* WDTR Message values */ 3935const BUS_8_BIT 0x00 3936const BUS_16_BIT 0x01 3937const BUS_32_BIT 0x02 3938 3939/* Offset maximums */ 3940const MAX_OFFSET 0xfe 3941const MAX_OFFSET_PACED 0xfe 3942const MAX_OFFSET_PACED_BUG 0x7f 3943/* 3944 * Some 160 devices incorrectly accept 0xfe as a 3945 * sync offset, but will overrun this value. Limit 3946 * to 0x7f for speed lower than U320 which will 3947 * avoid the persistent sync offset overruns. 3948 */ 3949const MAX_OFFSET_NON_PACED 0x7f 3950const HOST_MSG 0xff 3951 3952/* 3953 * The size of our sense buffers. 3954 * Sense buffer mapping can be handled in either of two ways. 3955 * The first is to allocate a dmamap for each transaction. 3956 * Depending on the architecture, dmamaps can be costly. The 3957 * alternative is to statically map the buffers in much the same 3958 * way we handle our scatter gather lists. The driver implements 3959 * the later. 3960 */ 3961const AHD_SENSE_BUFSIZE 256 3962 3963/* Target mode command processing constants */ 3964const CMD_GROUP_CODE_SHIFT 0x05 3965 3966const STATUS_BUSY 0x08 3967const STATUS_QUEUE_FULL 0x28 3968const STATUS_PKT_SENSE 0xFF 3969const TARGET_DATA_IN 1 3970 3971const SCB_TRANSFER_SIZE_FULL_LUN 56 3972const SCB_TRANSFER_SIZE_1BYTE_LUN 48 3973/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 3974const PKT_OVERRUN_BUFSIZE 512 3975 3976/* 3977 * Timer parameters. 3978 */ 3979const AHD_TIMER_US_PER_TICK 25 3980const AHD_TIMER_MAX_TICKS 0xFFFF 3981const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) 3982 3983/* 3984 * Downloaded (kernel inserted) constants 3985 */ 3986const SG_PREFETCH_CNT download 3987const SG_PREFETCH_CNT_LIMIT download 3988const SG_PREFETCH_ALIGN_MASK download 3989const SG_PREFETCH_ADDR_MASK download 3990const SG_SIZEOF download 3991const PKT_OVERRUN_BUFOFFSET download 3992const SCB_TRANSFER_SIZE download 3993const CACHELINE_MASK download 3994 3995/* 3996 * BIOS SCB offsets 3997 */ 3998const NVRAM_SCB_OFFSET 0x2C 3999