1/* $OpenBSD: aic7xxx.reg,v 1.5 2002/06/28 00:34:54 smurph Exp $ */ 2/* 3 * Aic7xxx register and scratch ram definitions. 4 * 5 * Copyright (c) 1994-2001 Justin Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * Alternatively, this software may be distributed under the terms of the 18 * GNU Public License ("GPL"). 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.39 2001/07/18 21:39:47 gibbs Exp $ 33 */ 34 35VERSION = "$Id: aic7xxx.reg,v 1.5 2002/06/28 00:34:54 smurph Exp $" 36 37/* 38 * This file is processed by the aic7xxx_asm utility for use in assembling 39 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 40 * a C header file for use in the kernel portion of the Aic7xxx driver. 41 * 42 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 43 * Adaptec's Technical Documents Department 1-800-934-2766 44 */ 45 46/* 47 * SCSI Sequence Control (p. 3-11). 48 * Each bit, when set starts a specific SCSI sequence on the bus 49 */ 50register SCSISEQ { 51 address 0x000 52 access_mode RW 53 bit TEMODE 0x80 54 bit ENSELO 0x40 55 bit ENSELI 0x20 56 bit ENRSELI 0x10 57 bit ENAUTOATNO 0x08 58 bit ENAUTOATNI 0x04 59 bit ENAUTOATNP 0x02 60 bit SCSIRSTO 0x01 61} 62 63/* 64 * SCSI Transfer Control 0 Register (pp. 3-13). 65 * Controls the SCSI module data path. 66 */ 67register SXFRCTL0 { 68 address 0x001 69 access_mode RW 70 bit DFON 0x80 71 bit DFPEXP 0x40 72 bit FAST20 0x20 73 bit CLRSTCNT 0x10 74 bit SPIOEN 0x08 75 bit SCAMEN 0x04 76 bit CLRCHN 0x02 77} 78 79/* 80 * SCSI Transfer Control 1 Register (pp. 3-14,15). 81 * Controls the SCSI module data path. 82 */ 83register SXFRCTL1 { 84 address 0x002 85 access_mode RW 86 bit BITBUCKET 0x80 87 bit SWRAPEN 0x40 88 bit ENSPCHK 0x20 89 mask STIMESEL 0x18 90 bit ENSTIMER 0x04 91 bit ACTNEGEN 0x02 92 bit STPWEN 0x01 /* Powered Termination */ 93} 94 95/* 96 * SCSI Control Signal Read Register (p. 3-15). 97 * Reads the actual state of the SCSI bus pins 98 */ 99register SCSISIGI { 100 address 0x003 101 access_mode RO 102 bit CDI 0x80 103 bit IOI 0x40 104 bit MSGI 0x20 105 bit ATNI 0x10 106 bit SELI 0x08 107 bit BSYI 0x04 108 bit REQI 0x02 109 bit ACKI 0x01 110/* 111 * Possible phases in SCSISIGI 112 */ 113 mask PHASE_MASK CDI|IOI|MSGI 114 mask P_DATAOUT 0x00 115 mask P_DATAIN IOI 116 mask P_DATAOUT_DT P_DATAOUT|MSGI 117 mask P_DATAIN_DT P_DATAIN|MSGI 118 mask P_COMMAND CDI 119 mask P_MESGOUT CDI|MSGI 120 mask P_STATUS CDI|IOI 121 mask P_MESGIN CDI|IOI|MSGI 122} 123 124/* 125 * SCSI Control Signal Write Register (p. 3-16). 126 * Writing to this register modifies the control signals on the bus. Only 127 * those signals that are allowed in the current mode (Initiator/Target) are 128 * asserted. 129 */ 130register SCSISIGO { 131 address 0x003 132 access_mode WO 133 bit CDO 0x80 134 bit IOO 0x40 135 bit MSGO 0x20 136 bit ATNO 0x10 137 bit SELO 0x08 138 bit BSYO 0x04 139 bit REQO 0x02 140 bit ACKO 0x01 141/* 142 * Possible phases to write into SCSISIG0 143 */ 144 mask PHASE_MASK CDI|IOI|MSGI 145 mask P_DATAOUT 0x00 146 mask P_DATAIN IOI 147 mask P_COMMAND CDI 148 mask P_MESGOUT CDI|MSGI 149 mask P_STATUS CDI|IOI 150 mask P_MESGIN CDI|IOI|MSGI 151} 152 153/* 154 * SCSI Rate Control (p. 3-17). 155 * Contents of this register determine the Synchronous SCSI data transfer 156 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 157 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 158 * greater than 0 enables synchronous transfers. 159 */ 160register SCSIRATE { 161 address 0x004 162 access_mode RW 163 bit WIDEXFER 0x80 /* Wide transfer control */ 164 bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 165 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 166 mask SXFR 0x70 /* Sync transfer rate */ 167 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 168 mask SOFS 0x0f /* Sync offset */ 169} 170 171/* 172 * SCSI ID (p. 3-18). 173 * Contains the ID of the board and the current target on the 174 * selected channel. 175 */ 176register SCSIID { 177 address 0x005 178 access_mode RW 179 mask TID 0xf0 /* Target ID mask */ 180 mask TWIN_TID 0x70 181 bit TWIN_CHNLB 0x80 182 mask OID 0x0f /* Our ID mask */ 183 /* 184 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 185 * The aic7890/91 allow an offset of up to 127 transfers in both wide 186 * and narrow mode. 187 */ 188 alias SCSIOFFSET 189 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 190} 191 192/* 193 * SCSI Latched Data (p. 3-19). 194 * Read/Write latches used to transfer data on the SCSI bus during 195 * Automatic or Manual PIO mode. SCSIDATH can be used for the 196 * upper byte of a 16bit wide asynchronouse data phase transfer. 197 */ 198register SCSIDATL { 199 address 0x006 200 access_mode RW 201} 202 203register SCSIDATH { 204 address 0x007 205 access_mode RW 206} 207 208/* 209 * SCSI Transfer Count (pp. 3-19,20) 210 * These registers count down the number of bytes transferred 211 * across the SCSI bus. The counter is decremented only once 212 * the data has been safely transferred. SDONE in SSTAT0 is 213 * set when STCNT goes to 0 214 */ 215register STCNT { 216 address 0x008 217 size 3 218 access_mode RW 219} 220 221/* ALT_MODE register on Ultra160 chips */ 222register OPTIONMODE { 223 address 0x008 224 access_mode RW 225 bit AUTORATEEN 0x80 226 bit AUTOACKEN 0x40 227 bit ATNMGMNTEN 0x20 228 bit BUSFREEREV 0x10 229 bit EXPPHASEDIS 0x08 230 bit SCSIDATL_IMGEN 0x04 231 bit AUTO_MSGOUT_DE 0x02 232 bit DIS_MSGIN_DUALEDGE 0x01 233 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 234} 235 236/* ALT_MODE register on Ultra160 chips */ 237register TARGCRCCNT { 238 address 0x00a 239 size 2 240 access_mode RW 241} 242 243/* 244 * Clear SCSI Interrupt 0 (p. 3-20) 245 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 246 */ 247register CLRSINT0 { 248 address 0x00b 249 access_mode WO 250 bit CLRSELDO 0x40 251 bit CLRSELDI 0x20 252 bit CLRSELINGO 0x10 253 bit CLRSWRAP 0x08 254 bit CLRIOERR 0x08 /* Ultra2 Only */ 255 bit CLRSPIORDY 0x02 256} 257 258/* 259 * SCSI Status 0 (p. 3-21) 260 * Contains one set of SCSI Interrupt codes 261 * These are most likely of interest to the sequencer 262 */ 263register SSTAT0 { 264 address 0x00b 265 access_mode RO 266 bit TARGET 0x80 /* Board acting as target */ 267 bit SELDO 0x40 /* Selection Done */ 268 bit SELDI 0x20 /* Board has been selected */ 269 bit SELINGO 0x10 /* Selection In Progress */ 270 bit SWRAP 0x08 /* 24bit counter wrap */ 271 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 272 bit SDONE 0x04 /* STCNT = 0x000000 */ 273 bit SPIORDY 0x02 /* SCSI PIO Ready */ 274 bit DMADONE 0x01 /* DMA transfer completed */ 275} 276 277/* 278 * Clear SCSI Interrupt 1 (p. 3-23) 279 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 280 */ 281register CLRSINT1 { 282 address 0x00c 283 access_mode WO 284 bit CLRSELTIMEO 0x80 285 bit CLRATNO 0x40 286 bit CLRSCSIRSTI 0x20 287 bit CLRBUSFREE 0x08 288 bit CLRSCSIPERR 0x04 289 bit CLRPHASECHG 0x02 290 bit CLRREQINIT 0x01 291} 292 293/* 294 * SCSI Status 1 (p. 3-24) 295 */ 296register SSTAT1 { 297 address 0x00c 298 access_mode RO 299 bit SELTO 0x80 300 bit ATNTARG 0x40 301 bit SCSIRSTI 0x20 302 bit PHASEMIS 0x10 303 bit BUSFREE 0x08 304 bit SCSIPERR 0x04 305 bit PHASECHG 0x02 306 bit REQINIT 0x01 307} 308 309/* 310 * SCSI Status 2 (pp. 3-25,26) 311 */ 312register SSTAT2 { 313 address 0x00d 314 access_mode RO 315 bit OVERRUN 0x80 316 bit SHVALID 0x40 /* Shaddow Layer non-zero */ 317 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 318 bit CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 319 bit CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 320 bit CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 321 bit DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 322 mask SFCNT 0x1f 323} 324 325/* 326 * SCSI Status 3 (p. 3-26) 327 */ 328register SSTAT3 { 329 address 0x00e 330 access_mode RO 331 mask SCSICNT 0xf0 332 mask OFFCNT 0x0f 333} 334 335/* 336 * SCSI ID for the aic7890/91 chips 337 */ 338register SCSIID_ULTRA2 { 339 address 0x00f 340 access_mode RW 341 mask TID 0xf0 /* Target ID mask */ 342 mask OID 0x0f /* Our ID mask */ 343} 344 345/* 346 * SCSI Interrupt Mode 1 (p. 3-28) 347 * Setting any bit will enable the corresponding function 348 * in SIMODE0 to interrupt via the IRQ pin. 349 */ 350register SIMODE0 { 351 address 0x010 352 access_mode RW 353 bit ENSELDO 0x40 354 bit ENSELDI 0x20 355 bit ENSELINGO 0x10 356 bit ENSWRAP 0x08 357 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 358 bit ENSDONE 0x04 359 bit ENSPIORDY 0x02 360 bit ENDMADONE 0x01 361} 362 363/* 364 * SCSI Interrupt Mode 1 (pp. 3-28,29) 365 * Setting any bit will enable the corresponding function 366 * in SIMODE1 to interrupt via the IRQ pin. 367 */ 368register SIMODE1 { 369 address 0x011 370 access_mode RW 371 bit ENSELTIMO 0x80 372 bit ENATNTARG 0x40 373 bit ENSCSIRST 0x20 374 bit ENPHASEMIS 0x10 375 bit ENBUSFREE 0x08 376 bit ENSCSIPERR 0x04 377 bit ENPHASECHG 0x02 378 bit ENREQINIT 0x01 379} 380 381/* 382 * SCSI Data Bus (High) (p. 3-29) 383 * This register reads data on the SCSI Data bus directly. 384 */ 385register SCSIBUSL { 386 address 0x012 387 access_mode RW 388} 389 390register SCSIBUSH { 391 address 0x013 392 access_mode RW 393} 394 395/* 396 * SCSI/Host Address (p. 3-30) 397 * These registers hold the host address for the byte about to be 398 * transferred on the SCSI bus. They are counted up in the same 399 * manner as STCNT is counted down. SHADDR should always be used 400 * to determine the address of the last byte transferred since HADDR 401 * can be skewed by write ahead. 402 */ 403register SHADDR { 404 address 0x014 405 size 4 406 access_mode RO 407} 408 409/* 410 * Selection Timeout Timer (p. 3-30) 411 */ 412register SELTIMER { 413 address 0x018 414 access_mode RW 415 bit STAGE6 0x20 416 bit STAGE5 0x10 417 bit STAGE4 0x08 418 bit STAGE3 0x04 419 bit STAGE2 0x02 420 bit STAGE1 0x01 421 alias TARGIDIN 422} 423 424/* 425 * Selection/Reselection ID (p. 3-31) 426 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 427 * device did not set its own ID. 428 */ 429register SELID { 430 address 0x019 431 access_mode RW 432 mask SELID_MASK 0xf0 433 bit ONEBIT 0x08 434} 435 436register SCAMCTL { 437 address 0x01a 438 access_mode RW 439 bit ENSCAMSELO 0x80 440 bit CLRSCAMSELID 0x40 441 bit ALTSTIM 0x20 442 bit DFLTTID 0x10 443 mask SCAMLVL 0x03 444} 445 446/* 447 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 448 */ 449register TARGID { 450 address 0x01b 451 size 2 452 access_mode RW 453} 454 455/* 456 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 457 * Indicates if external logic has been attached to the chip to 458 * perform the tasks of accessing a serial eeprom, testing termination 459 * strength, and performing cable detection. On the aic7860, most of 460 * these features are handled on chip, but on the aic7855 an attached 461 * aic3800 does the grunt work. 462 */ 463register SPIOCAP { 464 address 0x01b 465 access_mode RW 466 bit SOFT1 0x80 467 bit SOFT0 0x40 468 bit SOFTCMDEN 0x20 469 bit HAS_BRDCTL 0x10 /* External Board control */ 470 bit SEEPROM 0x08 /* External serial eeprom logic */ 471 bit EEPROM 0x04 /* Writable external BIOS ROM */ 472 bit ROM 0x02 /* Logic for accessing external ROM */ 473 bit SSPIOCPS 0x01 /* Termination and cable detection */ 474} 475 476register BRDCTL { 477 address 0x01d 478 bit BRDDAT7 0x80 479 bit BRDDAT6 0x40 480 bit BRDDAT5 0x20 481 bit BRDSTB 0x10 482 bit BRDCS 0x08 483 bit BRDRW 0x04 484 bit BRDCTL1 0x02 485 bit BRDCTL0 0x01 486 /* 7890 Definitions */ 487 bit BRDDAT4 0x10 488 bit BRDDAT3 0x08 489 bit BRDDAT2 0x04 490 bit BRDRW_ULTRA2 0x02 491 bit BRDSTB_ULTRA2 0x01 492} 493 494/* 495 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 496 * Controls the reading and writing of an external serial 1-bit 497 * EEPROM Device. In order to access the serial EEPROM, you must 498 * first set the SEEMS bit that generates a request to the memory 499 * port for access to the serial EEPROM device. When the memory 500 * port is not busy servicing another request, it reconfigures 501 * to allow access to the serial EEPROM. When this happens, SEERDY 502 * gets set high to verify that the memory port access has been 503 * granted. 504 * 505 * After successful arbitration for the memory port, the SEECS bit of 506 * the SEECTL register is connected to the chip select. The SEECK, 507 * SEEDO, and SEEDI are connected to the clock, data out, and data in 508 * lines respectively. The SEERDY bit of SEECTL is useful in that it 509 * gives us an 800 nsec timer. After a write to the SEECTL register, 510 * the SEERDY goes high 800 nsec later. The one exception to this is 511 * when we first request access to the memory port. The SEERDY goes 512 * high to signify that access has been granted and, for this case, has 513 * no implied timing. 514 * 515 * See 93cx6.c for detailed information on the protocol necessary to 516 * read the serial EEPROM. 517 */ 518register SEECTL { 519 address 0x01e 520 bit EXTARBACK 0x80 521 bit EXTARBREQ 0x40 522 bit SEEMS 0x20 523 bit SEERDY 0x10 524 bit SEECS 0x08 525 bit SEECK 0x04 526 bit SEEDO 0x02 527 bit SEEDI 0x01 528} 529/* 530 * SCSI Block Control (p. 3-32) 531 * Controls Bus type and channel selection. In a twin channel configuration 532 * addresses 0x00-0x1e are gated to the appropriate channel based on this 533 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 534 * on a wide bus. 535 */ 536register SBLKCTL { 537 address 0x01f 538 access_mode RW 539 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 540 bit DIAGLEDON 0x40 /* Aic78X0 only */ 541 bit AUTOFLUSHDIS 0x20 542 bit SELBUSB 0x08 543 bit ENAB40 0x08 /* LVD transceiver active */ 544 bit ENAB20 0x04 /* SE/HVD transceiver active */ 545 bit SELWIDE 0x02 546 bit XCVR 0x01 /* External transceiver active */ 547} 548 549/* 550 * Sequencer Control (p. 3-33) 551 * Error detection mode and speed configuration 552 */ 553register SEQCTL { 554 address 0x060 555 access_mode RW 556 bit PERRORDIS 0x80 557 bit PAUSEDIS 0x40 558 bit FAILDIS 0x20 559 bit FASTMODE 0x10 560 bit BRKADRINTEN 0x08 561 bit STEP 0x04 562 bit SEQRESET 0x02 563 bit LOADRAM 0x01 564} 565 566/* 567 * Sequencer RAM Data (p. 3-34) 568 * Single byte window into the Scratch Ram area starting at the address 569 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 570 * four bytes in succession. The SEQADDRs will increment after the most 571 * significant byte is written 572 */ 573register SEQRAM { 574 address 0x061 575 access_mode RW 576} 577 578/* 579 * Sequencer Address Registers (p. 3-35) 580 * Only the first bit of SEQADDR1 holds addressing information 581 */ 582register SEQADDR0 { 583 address 0x062 584 access_mode RW 585} 586 587register SEQADDR1 { 588 address 0x063 589 access_mode RW 590 mask SEQADDR1_MASK 0x01 591} 592 593/* 594 * Accumulator 595 * We cheat by passing arguments in the Accumulator up to the kernel driver 596 */ 597register ACCUM { 598 address 0x064 599 access_mode RW 600 accumulator 601} 602 603register SINDEX { 604 address 0x065 605 access_mode RW 606 sindex 607} 608 609register DINDEX { 610 address 0x066 611 access_mode RW 612} 613 614register ALLONES { 615 address 0x069 616 access_mode RO 617 allones 618} 619 620register ALLZEROS { 621 address 0x06a 622 access_mode RO 623 allzeros 624} 625 626register NONE { 627 address 0x06a 628 access_mode WO 629 none 630} 631 632register FLAGS { 633 address 0x06b 634 access_mode RO 635 bit ZERO 0x02 636 bit CARRY 0x01 637} 638 639register SINDIR { 640 address 0x06c 641 access_mode RO 642} 643 644register DINDIR { 645 address 0x06d 646 access_mode WO 647} 648 649register FUNCTION1 { 650 address 0x06e 651 access_mode RW 652} 653 654register STACK { 655 address 0x06f 656 access_mode RO 657} 658 659/* 660 * Board Control (p. 3-43) 661 */ 662register BCTL { 663 address 0x084 664 access_mode RW 665 bit ACE 0x08 666 bit ENABLE 0x01 667} 668 669/* 670 * On the aic78X0 chips, Board Control is replaced by the DSCommand 671 * register (p. 4-64) 672 */ 673register DSCOMMAND0 { 674 address 0x084 675 access_mode RW 676 bit CACHETHEN 0x80 /* Cache Threshold enable */ 677 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 678 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 679 bit EXTREQLCK 0x10 /* External Request Lock */ 680 /* aic7890/91/96/97 only */ 681 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 682 bit RAMPS 0x04 /* External SCB RAM Present */ 683 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 684 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 685} 686 687register DSCOMMAND1 { 688 address 0x085 689 access_mode RW 690 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ 691 bit HADDLDSEL1 0x02 /* Host Address Load Select Bits */ 692 bit HADDLDSEL0 0x01 693} 694 695/* 696 * Bus On/Off Time (p. 3-44) aic7770 only 697 */ 698register BUSTIME { 699 address 0x085 700 access_mode RW 701 mask BOFF 0xf0 702 mask BON 0x0f 703} 704 705/* 706 * Bus Speed (p. 3-45) aic7770 only 707 */ 708register BUSSPD { 709 address 0x086 710 access_mode RW 711 mask DFTHRSH 0xc0 712 mask STBOFF 0x38 713 mask STBON 0x07 714 mask DFTHRSH_100 0xc0 715 mask DFTHRSH_75 0x80 716} 717 718/* aic7850/55/60/70/80/95 only */ 719register DSPCISTATUS { 720 address 0x086 721 mask DFTHRSH_100 0xc0 722} 723 724/* aic7890/91/96/97 only */ 725register HS_MAILBOX { 726 address 0x086 727 mask HOST_MAILBOX 0xF0 728 mask SEQ_MAILBOX 0x0F 729 mask HOST_REQ_INT 0x10 730 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 731} 732 733const HOST_MAILBOX_SHIFT 4 734const SEQ_MAILBOX_SHIFT 0 735 736/* 737 * Host Control (p. 3-47) R/W 738 * Overall host control of the device. 739 */ 740register HCNTRL { 741 address 0x087 742 access_mode RW 743 bit POWRDN 0x40 744 bit SWINT 0x10 745 bit IRQMS 0x08 746 bit PAUSE 0x04 747 bit INTEN 0x02 748 bit CHIPRST 0x01 749 bit CHIPRSTACK 0x01 750} 751 752/* 753 * Host Address (p. 3-48) 754 * This register contains the address of the byte about 755 * to be transferred across the host bus. 756 */ 757register HADDR { 758 address 0x088 759 size 4 760 access_mode RW 761} 762 763register HCNT { 764 address 0x08c 765 size 3 766 access_mode RW 767} 768 769/* 770 * SCB Pointer (p. 3-49) 771 * Gate one of the SCBs into the SCBARRAY window. 772 */ 773register SCBPTR { 774 address 0x090 775 access_mode RW 776} 777 778/* 779 * Interrupt Status (p. 3-50) 780 * Status for system interrupts 781 */ 782register INTSTAT { 783 address 0x091 784 access_mode RW 785 bit BRKADRINT 0x08 786 bit SCSIINT 0x04 787 bit CMDCMPLT 0x02 788 bit SEQINT 0x01 789 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 790 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 791 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 792 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 793 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 794 mask PDATA_REINIT 0x50|SEQINT /* 795 * Returned to data phase 796 * that requires data 797 * transfer pointers to be 798 * recalculated from the 799 * transfer residual. 800 */ 801 mask HOST_MSG_LOOP 0x60|SEQINT /* 802 * The bus is ready for the 803 * host to perform another 804 * message transaction. This 805 * mechanism is used for things 806 * like sync/wide negotiation 807 * that require a kernel based 808 * message state engine. 809 */ 810 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 811 mask PERR_DETECTED 0x80|SEQINT /* 812 * Either the phase_lock 813 * or inb_next routine has 814 * noticed a parity error. 815 */ 816 mask DATA_OVERRUN 0x90|SEQINT /* 817 * Target attempted to write 818 * beyond the bounds of its 819 * command. 820 */ 821 mask MKMSG_FAILED 0xa0|SEQINT /* 822 * Target completed command 823 * without honoring our ATN 824 * request to issue a message. 825 */ 826 mask MISSED_BUSFREE 0xb0|SEQINT /* 827 * The sequencer never saw 828 * the bus go free after 829 * either a command complete 830 * or disconnect message. 831 */ 832 mask SCB_MISMATCH 0xc0|SEQINT /* 833 * Downloaded SCB's tag does 834 * not match the entry we 835 * intended to download. 836 */ 837 mask NO_FREE_SCB 0xd0|SEQINT /* 838 * get_free_or_disc_scb failed. 839 */ 840 mask OUT_OF_RANGE 0xe0|SEQINT 841 842 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 843 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 844} 845 846/* 847 * Hard Error (p. 3-53) 848 * Reporting of catastrophic errors. You usually cannot recover from 849 * these without a full board reset. 850 */ 851register ERROR { 852 address 0x092 853 access_mode RO 854 bit CIOPARERR 0x80 /* Ultra2 only */ 855 bit PCIERRSTAT 0x40 /* PCI only */ 856 bit MPARERR 0x20 /* PCI only */ 857 bit DPARERR 0x10 /* PCI only */ 858 bit SQPARERR 0x08 859 bit ILLOPCODE 0x04 860 bit ILLSADDR 0x02 861 bit ILLHADDR 0x01 862} 863 864/* 865 * Clear Interrupt Status (p. 3-52) 866 */ 867register CLRINT { 868 address 0x092 869 access_mode WO 870 bit CLRPARERR 0x10 /* PCI only */ 871 bit CLRBRKADRINT 0x08 872 bit CLRSCSIINT 0x04 873 bit CLRCMDINT 0x02 874 bit CLRSEQINT 0x01 875} 876 877register DFCNTRL { 878 address 0x093 879 access_mode RW 880 bit PRELOADEN 0x80 /* aic7890 only */ 881 bit WIDEODD 0x40 882 bit SCSIEN 0x20 883 bit SDMAEN 0x10 884 bit SDMAENACK 0x10 885 bit HDMAEN 0x08 886 bit HDMAENACK 0x08 887 bit DIRECTION 0x04 888 bit FIFOFLUSH 0x02 889 bit FIFORESET 0x01 890} 891 892register DFSTATUS { 893 address 0x094 894 access_mode RO 895 bit PRELOAD_AVAIL 0x80 896 bit DFCACHETH 0x40 897 bit FIFOQWDEMP 0x20 898 bit MREQPEND 0x10 899 bit HDONE 0x08 900 bit DFTHRESH 0x04 901 bit FIFOFULL 0x02 902 bit FIFOEMP 0x01 903} 904 905register DFWADDR { 906 address 0x95 907 access_mode RW 908} 909 910register DFRADDR { 911 address 0x97 912 access_mode RW 913} 914 915register DFDAT { 916 address 0x099 917 access_mode RW 918} 919 920/* 921 * SCB Auto Increment (p. 3-59) 922 * Byte offset into the SCB Array and an optional bit to allow auto 923 * incrementing of the address during download and upload operations 924 */ 925register SCBCNT { 926 address 0x09a 927 access_mode RW 928 bit SCBAUTO 0x80 929 mask SCBCNT_MASK 0x1f 930} 931 932/* 933 * Queue In FIFO (p. 3-60) 934 * Input queue for queued SCBs (commands that the seqencer has yet to start) 935 */ 936register QINFIFO { 937 address 0x09b 938 access_mode RW 939} 940 941/* 942 * Queue In Count (p. 3-60) 943 * Number of queued SCBs 944 */ 945register QINCNT { 946 address 0x09c 947 access_mode RO 948} 949 950/* 951 * Queue Out FIFO (p. 3-61) 952 * Queue of SCBs that have completed and await the host 953 */ 954register QOUTFIFO { 955 address 0x09d 956 access_mode WO 957} 958 959register CRCCONTROL1 { 960 address 0x09d 961 access_mode RW 962 bit CRCONSEEN 0x80 963 bit CRCVALCHKEN 0x40 964 bit CRCENDCHKEN 0x20 965 bit CRCREQCHKEN 0x10 966 bit TARGCRCENDEN 0x08 967 bit TARGCRCCNTEN 0x04 968} 969 970 971/* 972 * Queue Out Count (p. 3-61) 973 * Number of queued SCBs in the Out FIFO 974 */ 975register QOUTCNT { 976 address 0x09e 977 access_mode RO 978} 979 980register SCSIPHASE { 981 address 0x09e 982 access_mode RO 983 bit STATUS_PHASE 0x20 984 bit COMMAND_PHASE 0x10 985 bit MSG_IN_PHASE 0x08 986 bit MSG_OUT_PHASE 0x04 987 bit DATA_IN_PHASE 0x02 988 bit DATA_OUT_PHASE 0x01 989 mask DATA_PHASE_MASK 0x03 990} 991 992/* 993 * Special Function 994 */ 995register SFUNCT { 996 address 0x09f 997 access_mode RW 998 bit ALT_MODE 0x80 999} 1000 1001/* 1002 * SCB Definition (p. 5-4) 1003 */ 1004scb { 1005 address 0x0a0 1006 SCB_CDB_PTR { 1007 size 4 1008 alias SCB_RESIDUAL_DATACNT 1009 alias SCB_CDB_STORE 1010 alias SCB_TARGET_INFO 1011 } 1012 SCB_RESIDUAL_SGPTR { 1013 size 4 1014 } 1015 SCB_SCSI_STATUS { 1016 size 1 1017 } 1018 SCB_CDB_STORE_PAD { 1019 size 3 1020 } 1021 SCB_DATAPTR { 1022 size 4 1023 } 1024 SCB_DATACNT { 1025 /* 1026 * The last byte is really the high address bits for 1027 * the data address. 1028 */ 1029 size 4 1030 bit SG_LAST_SEG 0x80 /* In the fourth byte */ 1031 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1032 } 1033 SCB_SGPTR { 1034 size 4 1035 bit SG_RESID_VALID 0x04 /* In the first byte */ 1036 bit SG_FULL_RESID 0x02 /* In the first byte */ 1037 bit SG_LIST_NULL 0x01 /* In the first byte */ 1038 } 1039 SCB_CONTROL { 1040 size 1 1041 bit TARGET_SCB 0x80 1042 bit DISCENB 0x40 1043 bit TAG_ENB 0x20 1044 bit MK_MESSAGE 0x10 1045 bit ULTRAENB 0x08 1046 bit DISCONNECTED 0x04 1047 mask SCB_TAG_TYPE 0x03 1048 } 1049 SCB_SCSIID { 1050 size 1 1051 bit TWIN_CHNLB 0x80 1052 mask TWIN_TID 0x70 1053 mask TID 0xf0 1054 mask OID 0x0f 1055 } 1056 SCB_LUN { 1057 mask LID 0xff 1058 size 1 1059 } 1060 SCB_TAG { 1061 size 1 1062 } 1063 SCB_CDB_LEN { 1064 size 1 1065 } 1066 SCB_SCSIRATE { 1067 size 1 1068 } 1069 SCB_SCSIOFFSET { 1070 size 1 1071 } 1072 SCB_NEXT { 1073 size 1 1074 } 1075 SCB_64_SPARE { 1076 size 16 1077 } 1078 SCB_64_BTT { 1079 size 16 1080 } 1081} 1082 1083const SCB_UPLOAD_SIZE 32 1084const SCB_DOWNLOAD_SIZE 32 1085const SCB_DOWNLOAD_SIZE_64 48 1086 1087const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1088 1089/* --------------------- AHA-2840-only definitions -------------------- */ 1090 1091register SEECTL_2840 { 1092 address 0x0c0 1093 access_mode RW 1094 bit CS_2840 0x04 1095 bit CK_2840 0x02 1096 bit DO_2840 0x01 1097} 1098 1099register STATUS_2840 { 1100 address 0x0c1 1101 access_mode RW 1102 bit EEPROM_TF 0x80 1103 mask BIOS_SEL 0x60 1104 mask ADSEL 0x1e 1105 bit DI_2840 0x01 1106} 1107 1108/* --------------------- AIC-7870-only definitions -------------------- */ 1109 1110register CCHADDR { 1111 address 0x0E0 1112 size 8 1113} 1114 1115register CCHCNT { 1116 address 0x0E8 1117} 1118 1119register CCSGRAM { 1120 address 0x0E9 1121} 1122 1123register CCSGADDR { 1124 address 0x0EA 1125} 1126 1127register CCSGCTL { 1128 address 0x0EB 1129 bit CCSGDONE 0x80 1130 bit CCSGEN 0x08 1131 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1132 bit CCSGRESET 0x01 1133} 1134 1135register CCSCBCNT { 1136 address 0xEF 1137} 1138 1139register CCSCBCTL { 1140 address 0x0EE 1141 bit CCSCBDONE 0x80 1142 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1143 bit CCARREN 0x10 1144 bit CCSCBEN 0x08 1145 bit CCSCBDIR 0x04 1146 bit CCSCBRESET 0x01 1147} 1148 1149register CCSCBADDR { 1150 address 0x0ED 1151} 1152 1153register CCSCBRAM { 1154 address 0xEC 1155} 1156 1157/* 1158 * SCB bank address (7895/7896/97 only) 1159 */ 1160register SCBBADDR { 1161 address 0x0F0 1162 access_mode RW 1163} 1164 1165register CCSCBPTR { 1166 address 0x0F1 1167} 1168 1169register HNSCB_QOFF { 1170 address 0x0F4 1171} 1172 1173register SNSCB_QOFF { 1174 address 0x0F6 1175} 1176 1177register SDSCB_QOFF { 1178 address 0x0F8 1179} 1180 1181register QOFF_CTLSTA { 1182 address 0x0FA 1183 bit SCB_AVAIL 0x40 1184 bit SNSCB_ROLLOVER 0x20 1185 bit SDSCB_ROLLOVER 0x10 1186 mask SCB_QSIZE 0x07 1187 mask SCB_QSIZE_256 0x06 1188} 1189 1190register DFF_THRSH { 1191 address 0x0FB 1192 mask WR_DFTHRSH 0x70 1193 mask RD_DFTHRSH 0x07 1194 mask RD_DFTHRSH_MIN 0x00 1195 mask RD_DFTHRSH_25 0x01 1196 mask RD_DFTHRSH_50 0x02 1197 mask RD_DFTHRSH_63 0x03 1198 mask RD_DFTHRSH_75 0x04 1199 mask RD_DFTHRSH_85 0x05 1200 mask RD_DFTHRSH_90 0x06 1201 mask RD_DFTHRSH_MAX 0x07 1202 mask WR_DFTHRSH_MIN 0x00 1203 mask WR_DFTHRSH_25 0x10 1204 mask WR_DFTHRSH_50 0x20 1205 mask WR_DFTHRSH_63 0x30 1206 mask WR_DFTHRSH_75 0x40 1207 mask WR_DFTHRSH_85 0x50 1208 mask WR_DFTHRSH_90 0x60 1209 mask WR_DFTHRSH_MAX 0x70 1210} 1211 1212register SG_CACHE_PRE { 1213 access_mode WO 1214 address 0x0fc 1215 mask SG_ADDR_MASK 0xf8 1216 bit ODD_SEG 0x04 1217 bit LAST_SEG 0x02 1218 bit LAST_SEG_DONE 0x01 1219} 1220 1221register SG_CACHE_SHADOW { 1222 access_mode RO 1223 address 0x0fc 1224 mask SG_ADDR_MASK 0xf8 1225 bit ODD_SEG 0x04 1226 bit LAST_SEG 0x02 1227 bit LAST_SEG_DONE 0x01 1228} 1229/* ---------------------- Scratch RAM Offsets ------------------------- */ 1230/* These offsets are either to values that are initialized by the board's 1231 * BIOS or are specified by the sequencer code. 1232 * 1233 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1234 * device information, 32-33 and 5a-5f as well. As it turns out, the 1235 * BIOS trashes 20-2f, writing the synchronous negotiation results 1236 * on top of the BIOS values, so we re-use those for our per-target 1237 * scratchspace (actually a value that can be copied directly into 1238 * SCSIRATE). The kernel driver will enable synchronous negotiation 1239 * for all targets that have a value other than 0 in the lower four 1240 * bits of the target scratch space. This should work regardless of 1241 * whether the bios has been installed. 1242 */ 1243 1244scratch_ram { 1245 address 0x020 1246 1247 /* 1248 * 1 byte per target starting at this address for configuration values 1249 */ 1250 BUSY_TARGETS { 1251 alias TARG_SCSIRATE 1252 size 16 1253 } 1254 /* 1255 * Bit vector of targets that have ULTRA enabled as set by 1256 * the BIOS. The Sequencer relies on a per-SCB field to 1257 * control whether to enable Ultra transfers or not. During 1258 * initialization, we read this field and reuse it for 2 1259 * entries in the busy target table. 1260 */ 1261 ULTRA_ENB { 1262 alias CMDSIZE_TABLE 1263 size 2 1264 } 1265 /* 1266 * Bit vector of targets that have disconnection disabled as set by 1267 * the BIOS. The Sequencer relies in a per-SCB field to control the 1268 * disconnect priveldge. During initialization, we read this field 1269 * and reuse it for 2 entries in the busy target table. 1270 */ 1271 DISC_DSB { 1272 size 2 1273 } 1274 CMDSIZE_TABLE_TAIL { 1275 size 4 1276 } 1277 /* 1278 * Partial transfer past cacheline end to be 1279 * transferred using an extra S/G. 1280 */ 1281 MWI_RESIDUAL { 1282 size 1 1283 } 1284 /* 1285 * SCBID of the next SCB to be started by the controller. 1286 */ 1287 NEXT_QUEUED_SCB { 1288 size 1 1289 } 1290 /* 1291 * Single byte buffer used to designate the type or message 1292 * to send to a target. 1293 */ 1294 MSG_OUT { 1295 size 1 1296 } 1297 /* Parameters for DMA Logic */ 1298 DMAPARAMS { 1299 size 1 1300 bit PRELOADEN 0x80 1301 bit WIDEODD 0x40 1302 bit SCSIEN 0x20 1303 bit SDMAEN 0x10 1304 bit SDMAENACK 0x10 1305 bit HDMAEN 0x08 1306 bit HDMAENACK 0x08 1307 bit DIRECTION 0x04 1308 bit FIFOFLUSH 0x02 1309 bit FIFORESET 0x01 1310 } 1311 SEQ_FLAGS { 1312 size 1 1313 bit IDENTIFY_SEEN 0x80 1314 bit TARGET_CMD_IS_TAGGED 0x40 1315 bit DPHASE 0x20 1316 /* Target flags */ 1317 bit TARG_CMD_PENDING 0x10 1318 bit CMDPHASE_PENDING 0x08 1319 bit DPHASE_PENDING 0x04 1320 bit SPHASE_PENDING 0x02 1321 bit NO_DISCONNECT 0x01 1322 } 1323 /* 1324 * Temporary storage for the 1325 * target/channel/lun of a 1326 * reconnecting target 1327 */ 1328 SAVED_SCSIID { 1329 size 1 1330 } 1331 SAVED_LUN { 1332 size 1 1333 } 1334 /* 1335 * The last bus phase as seen by the sequencer. 1336 */ 1337 LASTPHASE { 1338 size 1 1339 bit CDI 0x80 1340 bit IOI 0x40 1341 bit MSGI 0x20 1342 mask PHASE_MASK CDI|IOI|MSGI 1343 mask P_DATAOUT 0x00 1344 mask P_DATAIN IOI 1345 mask P_COMMAND CDI 1346 mask P_MESGOUT CDI|MSGI 1347 mask P_STATUS CDI|IOI 1348 mask P_MESGIN CDI|IOI|MSGI 1349 mask P_BUSFREE 0x01 1350 } 1351 /* 1352 * head of list of SCBs awaiting 1353 * selection 1354 */ 1355 WAITING_SCBH { 1356 size 1 1357 } 1358 /* 1359 * head of list of SCBs that are 1360 * disconnected. Used for SCB 1361 * paging. 1362 */ 1363 DISCONNECTED_SCBH { 1364 size 1 1365 } 1366 /* 1367 * head of list of SCBs that are 1368 * not in use. Used for SCB paging. 1369 */ 1370 FREE_SCBH { 1371 size 1 1372 } 1373 /* 1374 * head of list of SCBs that have 1375 * completed but have not been 1376 * put into the qoutfifo. 1377 */ 1378 COMPLETE_SCBH { 1379 size 1 1380 } 1381 /* 1382 * Address of the hardware scb array in the host. 1383 */ 1384 HSCB_ADDR { 1385 size 4 1386 } 1387 /* 1388 * Base address of our shared data with the kernel driver in host 1389 * memory. This includes the qoutfifo and target mode 1390 * incoming command queue. 1391 */ 1392 SHARED_DATA_ADDR { 1393 size 4 1394 } 1395 KERNEL_QINPOS { 1396 size 1 1397 } 1398 QINPOS { 1399 size 1 1400 } 1401 QOUTPOS { 1402 size 1 1403 } 1404 /* 1405 * Kernel and sequencer offsets into the queue of 1406 * incoming target mode command descriptors. The 1407 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1408 */ 1409 KERNEL_TQINPOS { 1410 size 1 1411 } 1412 TQINPOS { 1413 size 1 1414 } 1415 ARG_1 { 1416 size 1 1417 mask SEND_MSG 0x80 1418 mask SEND_SENSE 0x40 1419 mask SEND_REJ 0x20 1420 mask MSGOUT_PHASEMIS 0x10 1421 mask EXIT_MSG_LOOP 0x08 1422 mask CONT_MSG_LOOP 0x04 1423 mask CONT_TARG_SESSION 0x02 1424 alias RETURN_1 1425 } 1426 ARG_2 { 1427 size 1 1428 alias RETURN_2 1429 } 1430 1431 /* 1432 * Snapshot of MSG_OUT taken after each message is sent. 1433 */ 1434 LAST_MSG { 1435 size 1 1436 } 1437 1438 /* 1439 * Sequences the kernel driver has okayed for us. This allows 1440 * the driver to do things like prevent initiator or target 1441 * operations. 1442 */ 1443 SCSISEQ_TEMPLATE { 1444 size 1 1445 bit ENSELO 0x40 1446 bit ENSELI 0x20 1447 bit ENRSELI 0x10 1448 bit ENAUTOATNO 0x08 1449 bit ENAUTOATNI 0x04 1450 bit ENAUTOATNP 0x02 1451 } 1452 1453 /* 1454 * Track whether the transfer byte count for 1455 * the current data phase is odd. 1456 */ 1457 DATA_COUNT_ODD { 1458 size 1 1459 } 1460 1461 /* 1462 * The initiator specified tag for this target mode transaction. 1463 */ 1464 INITIATOR_TAG { 1465 size 1 1466 } 1467 1468 SEQ_FLAGS2 { 1469 size 1 1470 bit SCB_DMA 0x01 1471 } 1472 /* 1473 * These are reserved registers in the card's scratch ram. Some of 1474 * the values are specified in the AHA2742 technical reference manual 1475 * and are initialized by the BIOS at boot time. 1476 */ 1477 SCSICONF { 1478 address 0x05a 1479 size 1 1480 bit TERM_ENB 0x80 1481 bit RESET_SCSI 0x40 1482 bit ENSPCHK 0x20 1483 mask HSCSIID 0x07 /* our SCSI ID */ 1484 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1485 } 1486 INTDEF { 1487 address 0x05c 1488 size 1 1489 bit EDGE_TRIG 0x80 1490 mask VECTOR 0x0f 1491 } 1492 HOSTCONF { 1493 address 0x05d 1494 size 1 1495 } 1496 HA_274_BIOSCTRL { 1497 address 0x05f 1498 size 1 1499 mask BIOSMODE 0x30 1500 mask BIOSDISABLED 0x30 1501 bit CHANNEL_B_PRIMARY 0x08 1502 } 1503 /* 1504 * Per target SCSI offset values for Ultra2 controllers. 1505 */ 1506 TARG_OFFSET { 1507 address 0x070 1508 size 16 1509 } 1510} 1511 1512const TID_SHIFT 4 1513const SCB_LIST_NULL 0xff 1514const TARGET_CMD_CMPLT 0xfe 1515 1516const CCSGADDR_MAX 0x80 1517const CCSGRAM_MAXSEGS 16 1518 1519/* WDTR Message values */ 1520const BUS_8_BIT 0x00 1521const BUS_16_BIT 0x01 1522const BUS_32_BIT 0x02 1523 1524/* Offset maximums */ 1525const MAX_OFFSET_8BIT 0x0f 1526const MAX_OFFSET_16BIT 0x08 1527const MAX_OFFSET_ULTRA2 0x7f 1528const HOST_MSG 0xff 1529 1530/* Target mode command processing constants */ 1531const CMD_GROUP_CODE_SHIFT 0x05 1532 1533const STATUS_BUSY 0x08 1534const STATUS_QUEUE_FULL 0x28 1535const SCB_TARGET_PHASES 0 1536const SCB_TARGET_DATA_DIR 1 1537const SCB_TARGET_STATUS 2 1538const SCB_INITIATOR_TAG 3 1539const TARGET_DATA_IN 1 1540 1541/* 1542 * Downloaded (kernel inserted) constants 1543 */ 1544/* Offsets into the SCBID array where different data is stored */ 1545const QOUTFIFO_OFFSET download 1546const QINFIFO_OFFSET download 1547const CACHESIZE_MASK download 1548const INVERTED_CACHESIZE_MASK download 1549const SG_PREFETCH_CNT download 1550const SG_PREFETCH_ALIGN_MASK download 1551const SG_PREFETCH_ADDR_MASK download 1552