1 /* $OpenBSD: ipgphyreg.h,v 1.2 2009/08/08 17:12:40 naddy Exp $ */ 2 3 /*- 4 * Copyright (c) 2006, Pyun YongHyeon 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #ifndef _DEV_MII_IPGPHYREG_H_ 32 #define _DEV_MII_IPGPHYREG_H_ 33 34 /* 35 * Registers for the IC Plus IPGA internal PHY. 36 */ 37 38 /* Control register */ 39 #define IPGPHY_MII_BMCR 0x00 40 #define IPGPHY_BMCR_FDX 0x0100 41 #define IPGPHY_BMCR_STARTNEG 0x0200 42 #define IPGPHY_BMCR_ISO 0x0400 43 #define IPGPHY_BMCR_PDOWN 0x0800 44 #define IPGPHY_BMCR_AUTOEN 0x1000 45 #define IPGPHY_BMCR_LOOP 0x4000 46 #define IPGPHY_BMCR_RESET 0x8000 47 48 #define IPGPHY_BMCR_10 0x0000 49 #define IPGPHY_BMCR_100 0x2000 50 #define IPGPHY_BMCR_1000 0x0040 51 52 /* Status register */ 53 #define IPGPHY_MII_BMSR 0x01 54 #define IPGPHY_BMSR_EXT 0x0001 55 #define IPGPHY_BMSR_LINK 0x0004 56 #define IPGPHY_BMSR_ANEG 0x0008 57 #define IPGPHY_BMSR_RFAULT 0x0010 58 #define IPGPHY_BMSR_ANEGCOMP 0x0020 59 #define IPGPHY_BMSR_EXTSTS 0x0100 60 61 #define IPGPHY_MII_ID1 0x02 62 63 /* Autonegotiation advertisement register */ 64 #define IPGPHY_MII_ANAR 0x04 65 #define IPGPHY_ANAR_CSMA 0x0001 66 #define IPGPHY_ANAR_10T 0x0020 67 #define IPGPHY_ANAR_10T_FDX 0x0040 68 #define IPGPHY_ANAR_100TX 0x0080 69 #define IPGPHY_ANAR_100TX_FDX 0x0100 70 #define IPGPHY_ANAR_100T4 0x0200 71 #define IPGPHY_ANAR_PAUSE 0x0400 72 #define IPGPHY_ANAR_APAUSE 0x0800 73 #define IPGPHY_ANAR_RFAULT 0x2000 74 #define IPGPHY_ANAR_NP 0x8000 75 76 /* Autonegotiation link parnet ability register */ 77 #define IPGPHY_MII_ANLPAR 0x05 78 #define IPGPHY_ANLPAR_10T 0x0020 79 #define IPGPHY_ANLPAR_10T_FDX 0x0040 80 #define IPGPHY_ANLPAR_100TX 0x0080 81 #define IPGPHY_ANLPAR_100TX_FDX 0x0100 82 #define IPGPHY_ANLPAR_100T4 0x0200 83 #define IPGPHY_ANLPAR_PAUSE 0x0400 84 #define IPGPHY_ANLPAR_APAUSE 0x0800 85 #define IPGPHY_ANLPAR_RFAULT 0x2000 86 #define IPGPHY_ANLPAR_ACK 0x4000 87 #define IPGPHY_ANLPAR_NP 0x8000 88 89 /* Autonegotiation expansion register */ 90 #define IPGPHY_MII_ANER 0x06 91 #define IPGPHY_ANER_LPNWAY 0x0001 92 #define IPGPHY_ANER_PRCVD 0x0002 93 #define IPGPHY_ANER_NEXTP 0x0004 94 #define IPGPHY_ANER_LPNEXTP 0x0008 95 #define IPGPHY_ANER_PDF 0x0100 96 97 /* Autonegotiation next page transmit register */ 98 #define IPGPHY_MII_NEXTP 0x07 99 #define IPGPHY_NEXTP_MSGC 0x0001 100 #define IPGPHY_NEXTP_TOGGLE 0x0800 101 #define IPGPHY_NEXTP_ACK2 0x1000 102 #define IPGPHY_NEXTP_MSGP 0x2000 103 #define IPGPHY_NEXTP_NEXTP 0x8000 104 105 /* Autonegotiation link partner next page register */ 106 #define IPGPHY_MII_NEXTPLP 0x08 107 #define IPGPHY_NEXTPLP_MSGC 0x0001 108 #define IPGPHY_NEXTPLP_TOGGLE 0x0800 109 #define IPGPHY_NEXTPLP_ACK2 0x1000 110 #define IPGPHY_NEXTPLP_MSGP 0x2000 111 #define IPGPHY_NEXTPLP_ACK 0x4000 112 #define IPGPHY_NEXTPLP_NEXTP 0x8000 113 114 /* 1000baseT control register */ 115 #define IPGPHY_MII_1000CR 0x09 116 #define IPGPHY_1000CR_1000T 0x0100 117 #define IPGPHY_1000CR_1000T_FDX 0x0200 118 #define IPGPHY_1000CR_MASTER 0x0400 119 #define IPGPHY_1000CR_MMASTER 0x0800 120 #define IPGPHY_1000CR_MANUAL 0x1000 121 #define IPGPHY_1000CR_TMNORMAL 0x0000 122 #define IPGPHY_1000CR_TM1 0x2000 123 #define IPGPHY_1000CR_TM2 0x4000 124 #define IPGPHY_1000CR_TM3 0x6000 125 #define IPGPHY_1000CR_TM4 0x8000 126 127 /* 1000baseT status register */ 128 #define IPGPHY_MII_1000SR 0x0A 129 #define IPGPHY_1000SR_LP 0x0400 130 #define IPGPHY_1000SR_LP_FDX 0x0800 131 #define IPGPHY_1000SR_RXSTAT 0x1000 132 #define IPGPHY_1000SR_LRXSTAT 0x2000 133 #define IPGPHY_1000SR_MASTER 0x4000 134 #define IPGPHY_1000SR_MASTERF 0x8000 135 136 /* Extended status register */ 137 #define IPGPHY_MII_EXTSTS 0x0F 138 #define IPGPHY_EXTSTS_1000T 0x1000 139 #define IPGPHY_EXTSTS_1000T_FDX 0x2000 140 #define IPGPHY_EXTSTS_1000X 0x4000 141 #define IPGPHY_EXTSTS_1000X_FDX 0x8000 142 143 /* PHY specific control & status register. IP1001 only. */ 144 #define IPGPHY_SCSR 0x10 145 #define IPGPHY_SCSR_RXPHASE_SEL 0x0001 146 #define IPGPHY_SCSR_TXPHASE_SEL 0x0002 147 #define IPGPHY_SCSR_REPEATOR_MODE 0x0004 148 #define IPGPHY_SCSR_RESERVED1_DEF 0x0008 149 #define IPGPHY_SCSR_RXCLK_DRV_MASK 0x0060 150 #define IPGPHY_SCSR_RXCLK_DRV_DEF 0x0040 151 #define IPGPHY_SCSR_RXD_DRV_MASK 0x0180 152 #define IPGPHY_SCSR_RXD_DRV_DEF 0x0100 153 #define IPGPHY_SCSR_JABBER_ENB 0x0200 154 #define IPGPHY_SCSR_HEART_BEAT_ENB 0x0400 155 #define IPGPHY_SCSR_DOWNSHIFT_ENB 0x0800 156 #define IPGPHY_SCSR_RESERVED2_DEF 0x1000 157 #define IPGPHY_SCSR_LED_DRV_4MA 0x0000 158 #define IPGPHY_SCSR_LED_DRV_8MA 0x2000 159 #define IPGPHY_SCSR_LED_MODE_MASK 0xC000 160 #define IPGPHY_SCSR_LED_MODE_DEF 0x0000 161 162 /* PHY link status register. IP1001 only. */ 163 #define IPGPHY_LSR 0x11 164 #define IPGPHY_LSR_JABBER_DET 0x0200 165 #define IPGPHY_LSR_APS_SLEEP 0x0400 166 #define IPGPHY_LSR_MDIX 0x0800 167 #define IPGPHY_LSR_FULL_DUPLEX 0x1000 168 #define IPGPHY_LSR_SPEED_10 0x0000 169 #define IPGPHY_LSR_SPEED_100 0x2000 170 #define IPGPHY_LSR_SPEED_1000 0x4000 171 #define IPGPHY_LSR_SPEED_MASK 0x6000 172 #define IPGPHY_LSR_LINKUP 0x8000 173 174 /* PHY specific control register 2. IP1001 only. */ 175 #define IPGPHY_SCR 176 #define IPGPHY_SCR_SEW_RATE_MASK 0x0003 177 #define IPGPHY_SCR_SEW_RATE_DEF 0x0003 178 #define IPGPHY_SCR_AUTO_XOVER 0x0004 179 #define IPGPHY_SCR_SPEED_10_100_ENB 0x0040 180 #define IPGPHY_SCR_FIFO_LATENCY_2 0x0000 181 #define IPGPHY_SCR_FIFO_LATENCY_3 0x0080 182 #define IPGPHY_SCR_FIFO_LATENCY_4 0x0100 183 #define IPGPHY_SCR_FIFO_LATENCY_5 0x0180 184 #define IPGPHY_SCR_MDIX_ENB 0x0200 185 #define IPGPHY_SCR_RESERVED_DEF 0x0400 186 #define IPGPHY_SCR_APS_ON 0x0800 187 188 #endif /* _DEV_MII_IPGPHYREG_H_ */ 189