1 /* $OpenBSD: ofw_pci.h,v 1.4 2008/06/26 05:42:17 ray Exp $ */ 2 /* $NetBSD: ofw_pci.h,v 1.4 2001/02/17 16:28:37 mrg Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_OFW_OFW_PCI_H_ 35 #define _DEV_OFW_OFW_PCI_H_ 36 37 /* 38 * PCI Bus Binding to: 39 * 40 * IEEE Std 1275-1994 41 * Standard for Boot (Initialization Configuration) Firmware 42 * 43 * Revision 2.1 44 */ 45 46 /* 47 * Section 2.2.1. Physical Address Formats 48 * 49 * A PCI physical address is represented by 3 address cells: 50 * 51 * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr 52 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 53 * phys.lo cell: llllllll llllllll llllllll llllllll 54 * 55 * n nonrelocatable 56 * p prefetchable 57 * t aliased below 1MB (memory) or 64k (i/o) 58 * ss space code 59 * b bus number 60 * d device number 61 * f function number 62 * r register number 63 * h high 32-bits of PCI address 64 * l low 32-bits of PCI address 65 */ 66 67 #define OFW_PCI_PHYS_HI_NONRELOCATABLE 0x80000000 68 #define OFW_PCI_PHYS_HI_PREFETCHABLE 0x40000000 69 #define OFW_PCI_PHYS_HI_ALIASED 0x20000000 70 #define OFW_PCI_PHYS_HI_SPACEMASK 0x03000000 71 #define OFW_PCI_PHYS_HI_BUSMASK 0x00ff0000 72 #define OFW_PCI_PHYS_HI_BUSSHIFT 16 73 #define OFW_PCI_PHYS_HI_DEVICEMASK 0x0000f800 74 #define OFW_PCI_PHYS_HI_DEVICESHIFT 11 75 #define OFW_PCI_PHYS_HI_FUNCTIONMASK 0x00000700 76 #define OFW_PCI_PHYS_HI_FUNCTIONSHIFT 8 77 #define OFW_PCI_PHYS_HI_REGISTERMASK 0x000000ff 78 79 #define OFW_PCI_PHYS_HI_SPACE_CONFIG 0x00000000 80 #define OFW_PCI_PHYS_HI_SPACE_IO 0x01000000 81 #define OFW_PCI_PHYS_HI_SPACE_MEM32 0x02000000 82 #define OFW_PCI_PHYS_HI_SPACE_MEM64 0x03000000 83 84 #define OFW_PCI_PHYS_HI_BUS(hi) \ 85 (((hi) & OFW_PCI_PHYS_HI_BUSMASK) >> OFW_PCI_PHYS_HI_BUSSHIFT) 86 #define OFW_PCI_PHYS_HI_DEVICE(hi) \ 87 (((hi) & OFW_PCI_PHYS_HI_DEVICEMASK) >> OFW_PCI_PHYS_HI_DEVICESHIFT) 88 #define OFW_PCI_PHYS_HI_FUNCTION(hi) \ 89 (((hi) & OFW_PCI_PHYS_HI_FUNCTIONMASK) >> OFW_PCI_PHYS_HI_FUNCTIONSHIFT) 90 91 /* 92 * This has the 3 32bit cell values, plus 2 more to make up a 64-bit size. 93 */ 94 struct ofw_pci_register { 95 u_int32_t phys_hi; 96 u_int32_t phys_mid; 97 u_int32_t phys_lo; 98 u_int32_t size_hi; 99 u_int32_t size_lo; 100 }; 101 102 #endif /* _DEV_OFW_OFW_PCI_H_ */ 103