1 /* $OpenBSD: agp_amd.c,v 1.21 2015/09/09 19:47:11 deraadt Exp $ */ 2 /* $NetBSD: agp_amd.c,v 1.6 2001/10/06 02:48:50 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Doug Rabson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_amd.c,v 1.6 2001/07/05 21:28:46 jhb Exp $ 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/device.h> 36 #include <sys/rwlock.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/vga_pcivar.h> 41 #include <dev/pci/agpvar.h> 42 #include <dev/pci/agpreg.h> 43 44 #include <dev/pci/pcidevs.h> 45 46 #define READ2(off) bus_space_read_2(asc->iot, asc->ioh, off) 47 #define READ4(off) bus_space_read_4(asc->iot, asc->ioh, off) 48 #define WRITE2(off,v) bus_space_write_2(asc->iot, asc->ioh, off, v) 49 #define WRITE4(off,v) bus_space_write_4(asc->iot, asc->ioh, off, v) 50 51 struct agp_amd_gatt { 52 bus_dmamap_t ag_dmamap; 53 bus_dma_segment_t ag_dmaseg; 54 int ag_nseg; 55 u_int32_t ag_entries; 56 u_int32_t *ag_vdir; /* virtual address of page dir */ 57 bus_addr_t ag_pdir; /* bus address of page dir */ 58 u_int32_t *ag_virtual; /* virtual address of gatt */ 59 bus_addr_t ag_physical; /* bus address of gatt */ 60 size_t ag_size; 61 }; 62 63 struct agp_amd_softc { 64 struct device dev; 65 struct agp_softc *agpdev; 66 struct agp_amd_gatt *gatt; 67 pci_chipset_tag_t asc_pc; 68 pcitag_t asc_tag; 69 bus_space_handle_t ioh; 70 bus_space_tag_t iot; 71 bus_addr_t asc_apaddr; 72 bus_size_t asc_apsize; 73 pcireg_t asc_apctrl; 74 pcireg_t asc_modectrl; 75 u_int16_t asc_status; 76 }; 77 78 void agp_amd_attach(struct device *, struct device *, void *); 79 int agp_amd_activate(struct device *, int); 80 void agp_amd_save(struct agp_amd_softc *); 81 void agp_amd_restore(struct agp_amd_softc *); 82 int agp_amd_probe(struct device *, void *, void *); 83 bus_size_t agp_amd_get_aperture(void *); 84 struct agp_amd_gatt *agp_amd_alloc_gatt(bus_dma_tag_t, bus_size_t); 85 int agp_amd_set_aperture(void *, bus_size_t); 86 void agp_amd_bind_page(void *, bus_size_t, paddr_t, int); 87 void agp_amd_unbind_page(void *, bus_size_t); 88 void agp_amd_flush_tlb(void *); 89 90 struct cfattach amdagp_ca = { 91 sizeof(struct agp_amd_softc), agp_amd_probe, agp_amd_attach, NULL, 92 agp_amd_activate 93 }; 94 95 struct cfdriver amdagp_cd = { 96 NULL, "amdagp", DV_DULL 97 }; 98 99 const struct agp_methods agp_amd_methods = { 100 agp_amd_bind_page, 101 agp_amd_unbind_page, 102 agp_amd_flush_tlb, 103 }; 104 105 106 struct agp_amd_gatt * 107 agp_amd_alloc_gatt(bus_dma_tag_t dmat, bus_size_t apsize) 108 { 109 bus_size_t entries = apsize >> AGP_PAGE_SHIFT; 110 struct agp_amd_gatt *gatt; 111 int i, npages; 112 caddr_t vdir; 113 114 gatt = malloc(sizeof(struct agp_amd_gatt), M_AGP, M_NOWAIT); 115 if (!gatt) 116 return (0); 117 gatt->ag_size = AGP_PAGE_SIZE + entries * sizeof(u_int32_t); 118 119 if (agp_alloc_dmamem(dmat, gatt->ag_size, &gatt->ag_dmamap, 120 &gatt->ag_pdir, &gatt->ag_dmaseg) != 0) { 121 printf("failed to allocate GATT\n"); 122 free(gatt, M_AGP, sizeof *gatt); 123 return (NULL); 124 } 125 126 if (bus_dmamem_map(dmat, &gatt->ag_dmaseg, 1, gatt->ag_size, 127 &vdir, BUS_DMA_NOWAIT) != 0) { 128 printf("failed to map GATT\n"); 129 agp_free_dmamem(dmat, gatt->ag_size, gatt->ag_dmamap, 130 &gatt->ag_dmaseg); 131 free(gatt, M_AGP, sizeof *gatt); 132 return (NULL); 133 } 134 135 gatt->ag_vdir = (u_int32_t *)vdir; 136 gatt->ag_entries = entries; 137 gatt->ag_virtual = (u_int32_t *)(vdir + AGP_PAGE_SIZE); 138 gatt->ag_physical = gatt->ag_pdir + AGP_PAGE_SIZE; 139 140 /* 141 * Map the pages of the GATT into the page directory. 142 */ 143 npages = ((gatt->ag_size - 1) >> AGP_PAGE_SHIFT); 144 145 for (i = 0; i < npages; i++) 146 gatt->ag_vdir[i] = (gatt->ag_physical + i * AGP_PAGE_SIZE) | 1; 147 148 /* 149 * Make sure the chipset can see everything. 150 */ 151 agp_flush_cache(); 152 153 return (gatt); 154 } 155 156 int 157 agp_amd_probe(struct device *parent, void *match, void *aux) 158 { 159 struct agp_attach_args *aa = aux; 160 struct pci_attach_args *pa = aa->aa_pa; 161 162 /* Must be a pchb */ 163 if (agpbus_probe(aa) == 1 && PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 164 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC751_SC || 165 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_761_PCHB || 166 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_762_PCHB)) 167 return (1); 168 return (0); 169 } 170 171 void 172 agp_amd_attach(struct device *parent, struct device *self, void *aux) 173 { 174 struct agp_amd_softc *asc = (struct agp_amd_softc *)self; 175 struct agp_attach_args *aa = aux; 176 struct pci_attach_args *pa = aa->aa_pa; 177 struct agp_amd_gatt *gatt; 178 pcireg_t reg; 179 int error; 180 181 asc->asc_pc = pa->pa_pc; 182 asc->asc_tag = pa->pa_tag; 183 184 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, AGP_APBASE, 185 PCI_MAPREG_TYPE_MEM, &asc->asc_apaddr, NULL, NULL) != 0) { 186 printf(": can't get aperture info\n"); 187 return; 188 } 189 190 error = pci_mapreg_map(pa, AGP_AMD751_REGISTERS, 191 PCI_MAPREG_TYPE_MEM, 0, &asc->iot, &asc->ioh, NULL, NULL, 0); 192 if (error != 0) { 193 printf("can't map AGP registers\n"); 194 return; 195 } 196 197 asc->asc_apsize = agp_amd_get_aperture(asc); 198 199 for (;;) { 200 gatt = agp_amd_alloc_gatt(pa->pa_dmat, asc->asc_apsize); 201 if (gatt != NULL) 202 break; 203 204 /* 205 * almost certainly error allocating contigious dma memory 206 * so reduce aperture so that the gatt size reduces. 207 */ 208 asc->asc_apsize /= 2; 209 if (agp_amd_set_aperture(asc, asc->asc_apsize)) { 210 printf(": failed to set aperture\n"); 211 return; 212 } 213 } 214 asc->gatt = gatt; 215 216 /* Install the gatt. */ 217 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_physical); 218 219 /* Enable synchronisation between host and agp. */ 220 reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_AMD751_MODECTRL); 221 reg &= ~0x00ff00ff; 222 reg |= (AGP_AMD751_MODECTRL_SYNEN) | (AGP_AMD751_MODECTRL2_GPDCE << 16); 223 pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_AMD751_MODECTRL, reg); 224 /* Enable the TLB and flush */ 225 WRITE2(AGP_AMD751_STATUS, 226 READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE); 227 agp_amd_flush_tlb(asc); 228 229 asc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_amd_methods, 230 asc->asc_apaddr, asc->asc_apsize, &asc->dev); 231 return; 232 } 233 234 int 235 agp_amd_activate(struct device *arg, int act) 236 { 237 struct agp_amd_softc *asc = (struct agp_amd_softc *)arg; 238 239 switch (act) { 240 case DVACT_SUSPEND: 241 agp_amd_save(asc); 242 break; 243 case DVACT_RESUME: 244 agp_amd_restore(asc); 245 break; 246 } 247 248 return (0); 249 } 250 251 void 252 agp_amd_save(struct agp_amd_softc *asc) 253 { 254 asc->asc_apctrl = pci_conf_read(asc->asc_pc, asc->asc_tag, 255 AGP_AMD751_APCTRL); 256 asc->asc_modectrl = pci_conf_read(asc->asc_pc, asc->asc_tag, 257 AGP_AMD751_MODECTRL); 258 asc->asc_status = READ2(AGP_AMD751_STATUS); 259 } 260 261 void 262 agp_amd_restore(struct agp_amd_softc *asc) 263 { 264 265 /* restore aperture size */ 266 pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_AMD751_APCTRL, 267 asc->asc_apctrl); 268 269 /* Install the gatt. */ 270 WRITE4(AGP_AMD751_ATTBASE, asc->gatt->ag_physical); 271 272 /* Reenable synchronisation between host and agp. */ 273 pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_AMD751_MODECTRL, 274 asc->asc_modectrl); 275 /* Enable the TLB and flush */ 276 WRITE2(AGP_AMD751_STATUS, asc->asc_status); 277 agp_amd_flush_tlb(asc); 278 } 279 280 bus_size_t 281 agp_amd_get_aperture(void *sc) 282 { 283 struct agp_amd_softc *asc = sc; 284 int vas; 285 286 vas = (pci_conf_read(asc->asc_pc, asc->asc_tag, 287 AGP_AMD751_APCTRL) & 0x06); 288 vas >>= 1; 289 /* 290 * The aperture size is equal to 32M<<vas. 291 */ 292 return ((32 * 1024 * 1024) << vas); 293 } 294 295 int 296 agp_amd_set_aperture(void *sc, bus_size_t aperture) 297 { 298 struct agp_amd_softc *asc = sc; 299 int vas; 300 pcireg_t reg; 301 302 /* 303 * Check for a power of two and make sure its within the 304 * programmable range. 305 */ 306 if (aperture & (aperture - 1) 307 || aperture < 32*1024*1024 308 || aperture > 2U*1024*1024*1024) 309 return (EINVAL); 310 311 vas = ffs(aperture / 32*1024*1024) - 1; 312 313 reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_AMD751_APCTRL); 314 reg = (reg & ~0x06) | (vas << 1); 315 pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_AMD751_APCTRL, reg); 316 317 return (0); 318 } 319 320 void 321 agp_amd_bind_page(void *sc, bus_size_t offset, paddr_t physical, int flags) 322 { 323 struct agp_amd_softc *asc = sc; 324 325 asc->gatt->ag_virtual[(offset - asc->asc_apaddr) >> AGP_PAGE_SHIFT] = 326 physical | 1; 327 } 328 329 void 330 agp_amd_unbind_page(void *sc, bus_size_t offset) 331 { 332 struct agp_amd_softc *asc = sc; 333 334 asc->gatt->ag_virtual[(offset - asc->asc_apaddr) >> AGP_PAGE_SHIFT] = 0; 335 } 336 337 void 338 agp_amd_flush_tlb(void *sc) 339 { 340 struct agp_amd_softc *asc = sc; 341 342 /* Set the cache invalidate bit and wait for the chipset to clear */ 343 WRITE4(AGP_AMD751_TLBCTRL, 1); 344 do { 345 DELAY(1); 346 } while (READ4(AGP_AMD751_TLBCTRL)); 347 } 348