1 /* $OpenBSD: agp_i810.c,v 1.69 2010/09/06 15:00:50 oga Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/agpio.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/agpvar.h> 44 #include <dev/pci/agpreg.h> 45 #include <dev/pci/vga_pcivar.h> 46 47 #include <machine/bus.h> 48 49 #define READ1(off) bus_space_read_1(isc->map->bst, isc->map->bsh, off) 50 #define READ4(off) bus_space_read_4(isc->map->bst, isc->map->bsh, off) 51 #define WRITE4(off,v) bus_space_write_4(isc->map->bst, isc->map->bsh, off, v) 52 53 /* 54 * Intel IGP gtt bits. 55 */ 56 /* PTE is enabled */ 57 #define INTEL_ENABLED 0x1 58 /* I810/I815 only, memory is in dcache */ 59 #define INTEL_LOCAL 0x2 60 /* Memory is snooped, must not be accessed through gtt from the cpu. */ 61 #define INTEL_COHERENT 0x6 62 63 enum { 64 CHIP_NONE = 0, /* not integrated graphics */ 65 CHIP_I810 = 1, /* i810/i815 */ 66 CHIP_I830 = 2, /* i830/i845 */ 67 CHIP_I855 = 3, /* i852GM/i855GM/i865G */ 68 CHIP_I915 = 4, /* i915G/i915GM */ 69 CHIP_I965 = 5, /* i965/i965GM */ 70 CHIP_G33 = 6, /* G33/Q33/Q35 */ 71 CHIP_G4X = 7, /* G4X */ 72 CHIP_PINEVIEW = 8, /* Pineview/Pineview M */ 73 CHIP_IRONLAKE = 9, /* Clarkdale/Arrandale */ 74 }; 75 76 struct agp_i810_softc { 77 struct device dev; 78 bus_dma_segment_t scrib_seg; 79 struct agp_softc *agpdev; 80 struct agp_gatt *gatt; 81 struct vga_pci_bar *map; 82 struct vga_pci_bar *gtt_map; 83 bus_dmamap_t scrib_dmamap; 84 bus_addr_t isc_apaddr; 85 bus_size_t isc_apsize; /* current aperture size */ 86 int chiptype; /* i810-like or i830 */ 87 u_int32_t dcache_size; /* i810 only */ 88 u_int32_t stolen; /* number of i830/845 gtt 89 entries for stolen memory */ 90 }; 91 92 void agp_i810_attach(struct device *, struct device *, void *); 93 int agp_i810_activate(struct device *, int); 94 void agp_i810_configure(struct agp_i810_softc *); 95 int agp_i810_probe(struct device *, void *, void *); 96 int agp_i810_get_chiptype(struct pci_attach_args *); 97 void agp_i810_bind_page(void *, bus_size_t, paddr_t, int); 98 void agp_i810_unbind_page(void *, bus_size_t); 99 void agp_i810_flush_tlb(void *); 100 int agp_i810_enable(void *, u_int32_t mode); 101 struct agp_memory * agp_i810_alloc_memory(void *, int, vsize_t); 102 int agp_i810_free_memory(void *, struct agp_memory *); 103 int agp_i810_bind_memory(void *, struct agp_memory *, bus_size_t); 104 int agp_i810_unbind_memory(void *, struct agp_memory *); 105 void intagp_write_gtt(struct agp_i810_softc *, bus_size_t, paddr_t); 106 int intagp_gmch_match(struct pci_attach_args *); 107 108 extern void intagp_dma_sync(bus_dma_tag_t, bus_dmamap_t, 109 bus_addr_t, bus_size_t, int); 110 111 struct cfattach intagp_ca = { 112 sizeof(struct agp_i810_softc), agp_i810_probe, agp_i810_attach, 113 NULL, agp_i810_activate, 114 }; 115 116 struct cfdriver intagp_cd = { 117 NULL, "intagp", DV_DULL 118 }; 119 120 struct agp_methods agp_i810_methods = { 121 agp_i810_bind_page, 122 agp_i810_unbind_page, 123 agp_i810_flush_tlb, 124 intagp_dma_sync, 125 agp_i810_enable, 126 agp_i810_alloc_memory, 127 agp_i810_free_memory, 128 agp_i810_bind_memory, 129 agp_i810_unbind_memory, 130 }; 131 132 int 133 agp_i810_get_chiptype(struct pci_attach_args *pa) 134 { 135 switch (PCI_PRODUCT(pa->pa_id)) { 136 case PCI_PRODUCT_INTEL_82810_IGD: 137 case PCI_PRODUCT_INTEL_82810_DC100_IGD: 138 case PCI_PRODUCT_INTEL_82810E_IGD: 139 case PCI_PRODUCT_INTEL_82815_IGD: 140 return (CHIP_I810); 141 break; 142 case PCI_PRODUCT_INTEL_82830M_IGD: 143 case PCI_PRODUCT_INTEL_82845G_IGD: 144 return (CHIP_I830); 145 break; 146 case PCI_PRODUCT_INTEL_82855GM_IGD: 147 case PCI_PRODUCT_INTEL_82865G_IGD: 148 return (CHIP_I855); 149 break; 150 case PCI_PRODUCT_INTEL_82915G_IGD_1: 151 case PCI_PRODUCT_INTEL_82915G_IGD_2: 152 case PCI_PRODUCT_INTEL_82915GM_IGD_1: 153 case PCI_PRODUCT_INTEL_82915GM_IGD_2: 154 case PCI_PRODUCT_INTEL_82945G_IGD_1: 155 case PCI_PRODUCT_INTEL_82945G_IGD_2: 156 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 157 case PCI_PRODUCT_INTEL_82945GM_IGD_2: 158 case PCI_PRODUCT_INTEL_82945GME_IGD_1: 159 return (CHIP_I915); 160 break; 161 case PCI_PRODUCT_INTEL_82946GZ_IGD_1: 162 case PCI_PRODUCT_INTEL_82946GZ_IGD_2: 163 case PCI_PRODUCT_INTEL_82Q965_IGD_1: 164 case PCI_PRODUCT_INTEL_82Q965_IGD_2: 165 case PCI_PRODUCT_INTEL_82G965_IGD_1: 166 case PCI_PRODUCT_INTEL_82G965_IGD_2: 167 case PCI_PRODUCT_INTEL_82GM965_IGD_1: 168 case PCI_PRODUCT_INTEL_82GM965_IGD_2: 169 case PCI_PRODUCT_INTEL_82GME965_IGD_1: 170 case PCI_PRODUCT_INTEL_82GME965_IGD_2: 171 case PCI_PRODUCT_INTEL_82G35_IGD_1: 172 case PCI_PRODUCT_INTEL_82G35_IGD_2: 173 return (CHIP_I965); 174 break; 175 case PCI_PRODUCT_INTEL_82G33_IGD_1: 176 case PCI_PRODUCT_INTEL_82G33_IGD_2: 177 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 178 case PCI_PRODUCT_INTEL_82Q35_IGD_2: 179 return (CHIP_G33); 180 break; 181 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 182 case PCI_PRODUCT_INTEL_82Q45_IGD_1: 183 case PCI_PRODUCT_INTEL_82G45_IGD_1: 184 case PCI_PRODUCT_INTEL_82G41_IGD_1: 185 return (CHIP_G4X); 186 case PCI_PRODUCT_INTEL_PINEVIEW_IGC_1: 187 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGC_1: 188 return (CHIP_PINEVIEW); 189 case PCI_PRODUCT_INTEL_CLARKDALE_IGD: 190 case PCI_PRODUCT_INTEL_ARRANDALE_IGD: 191 return (CHIP_IRONLAKE); 192 break; 193 } 194 return (CHIP_NONE); 195 } 196 197 /* 198 * We're intel IGD, bus 0 function 0 dev 0 should be the GMCH, so it should 199 * be Intel 200 */ 201 int 202 intagp_gmch_match(struct pci_attach_args *pa) 203 { 204 if (pa->pa_bus == 0 && pa->pa_device == 0 && pa->pa_function == 0 && 205 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 206 PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 207 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) 208 return (1); 209 return (0); 210 } 211 212 int 213 agp_i810_probe(struct device *parent, void *match, void *aux) 214 { 215 struct pci_attach_args *pa = aux; 216 217 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 218 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 219 return (0); 220 221 return (agp_i810_get_chiptype(pa) != CHIP_NONE); 222 } 223 224 void 225 agp_i810_attach(struct device *parent, struct device *self, void *aux) 226 { 227 struct agp_i810_softc *isc = (struct agp_i810_softc *)self; 228 struct agp_gatt *gatt; 229 struct pci_attach_args *pa = aux, bpa; 230 struct vga_pci_softc *vga = (struct vga_pci_softc *)parent; 231 bus_addr_t mmaddr, gmaddr, tmp; 232 pcireg_t memtype, reg; 233 u_int32_t stolen; 234 u_int16_t gcc1; 235 236 isc->chiptype = agp_i810_get_chiptype(pa); 237 238 switch (isc->chiptype) { 239 case CHIP_I915: 240 case CHIP_G33: 241 case CHIP_PINEVIEW: 242 gmaddr = AGP_I915_GMADR; 243 mmaddr = AGP_I915_MMADR; 244 memtype = PCI_MAPREG_TYPE_MEM; 245 break; 246 case CHIP_I965: 247 case CHIP_G4X: 248 case CHIP_IRONLAKE: 249 gmaddr = AGP_I965_GMADR; 250 mmaddr = AGP_I965_MMADR; 251 memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT; 252 break; 253 default: 254 gmaddr = AGP_APBASE; 255 mmaddr = AGP_I810_MMADR; 256 memtype = PCI_MAPREG_TYPE_MEM; 257 break; 258 } 259 260 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, gmaddr, memtype, 261 &isc->isc_apaddr, &isc->isc_apsize, NULL) != 0) { 262 printf("can't get aperture info\n"); 263 return; 264 } 265 266 isc->map = vga_pci_bar_map(vga, mmaddr, 0, BUS_SPACE_MAP_LINEAR); 267 if (isc->map == NULL) { 268 printf("can't map mmadr registers\n"); 269 return; 270 } 271 272 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33 || 273 isc->chiptype == CHIP_PINEVIEW) { 274 isc->gtt_map = vga_pci_bar_map(vga, AGP_I915_GTTADR, 0, 275 BUS_SPACE_MAP_LINEAR); 276 if (isc->gtt_map == NULL) { 277 printf("can't map gatt registers\n"); 278 goto out; 279 } 280 } 281 282 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT | M_ZERO); 283 if (gatt == NULL) { 284 printf("can't alloc gatt\n"); 285 goto out; 286 } 287 isc->gatt = gatt; 288 289 gatt->ag_entries = isc->isc_apsize >> AGP_PAGE_SHIFT; 290 291 /* 292 * Find the GMCH, some of the registers we need to read for 293 * configuration purposes are on there. it's always at 294 * 0/0/0 (bus/dev/func). 295 */ 296 if (pci_find_device(&bpa, intagp_gmch_match) == 0) { 297 printf("can't find GMCH\n"); 298 goto out; 299 } 300 301 switch (isc->chiptype) { 302 case CHIP_I810: 303 /* Some i810s have on-chip memory called dcache */ 304 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 305 isc->dcache_size = 4 * 1024 * 1024; 306 else 307 isc->dcache_size = 0; 308 309 /* According to the specs the gatt on the i810 must be 64k */ 310 if (agp_alloc_dmamem(pa->pa_dmat, 64 * 1024, &gatt->ag_dmamap, 311 &gatt->ag_physical, &gatt->ag_dmaseg) != 0) { 312 goto out; 313 } 314 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 315 316 if (bus_dmamem_map(pa->pa_dmat, &gatt->ag_dmaseg, 1, 64 * 1024, 317 (caddr_t *)&gatt->ag_virtual, BUS_DMA_NOWAIT) != 0) 318 goto out; 319 break; 320 321 case CHIP_I830: 322 /* The i830 automatically initializes the 128k gatt on boot. */ 323 324 reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I830_GCC0); 325 gcc1 = (u_int16_t)(reg >> 16); 326 switch (gcc1 & AGP_I830_GCC1_GMS) { 327 case AGP_I830_GCC1_GMS_STOLEN_512: 328 isc->stolen = (512 - 132) * 1024 / 4096; 329 break; 330 case AGP_I830_GCC1_GMS_STOLEN_1024: 331 isc->stolen = (1024 - 132) * 1024 / 4096; 332 break; 333 case AGP_I830_GCC1_GMS_STOLEN_8192: 334 isc->stolen = (8192 - 132) * 1024 / 4096; 335 break; 336 default: 337 isc->stolen = 0; 338 printf("unknown memory configuration, disabling\n"); 339 goto out; 340 } 341 #ifdef DEBUG 342 if (isc->stolen > 0) { 343 printf(": detected %dk stolen memory", 344 isc->stolen * 4); 345 } else 346 printf(": no preallocated video memory\n"); 347 #endif 348 349 /* GATT address is already in there, make sure it's enabled */ 350 gatt->ag_physical = READ4(AGP_I810_PGTBL_CTL) & ~1; 351 break; 352 353 case CHIP_I855: 354 /* FALLTHROUGH */ 355 case CHIP_I915: 356 /* FALLTHROUGH */ 357 case CHIP_I965: 358 /* FALLTHROUGH */ 359 case CHIP_G33: 360 /* FALLTHROUGH */ 361 case CHIP_G4X: 362 case CHIP_PINEVIEW: 363 case CHIP_IRONLAKE: 364 365 /* Stolen memory is set up at the beginning of the aperture by 366 * the BIOS, consisting of the GATT followed by 4kb for the 367 * BIOS display. 368 */ 369 370 reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I855_GCC1); 371 gcc1 = (u_int16_t)(reg >> 16); 372 switch (isc->chiptype) { 373 case CHIP_I855: 374 /* The 855GM automatically initializes the 128k gatt on boot. */ 375 stolen = 128 + 4; 376 break; 377 case CHIP_I915: 378 /* The 915G automatically initializes the 256k gatt on boot. */ 379 stolen = 256 + 4; 380 break; 381 case CHIP_I965: 382 switch (READ4(AGP_I810_PGTBL_CTL) & 383 AGP_I810_PGTBL_SIZE_MASK) { 384 case AGP_I810_PGTBL_SIZE_512KB: 385 stolen = 512 + 4; 386 break; 387 case AGP_I810_PGTBL_SIZE_256KB: 388 stolen = 256 + 4; 389 break; 390 case AGP_I810_PGTBL_SIZE_128KB: 391 default: 392 stolen = 128 + 4; 393 break; 394 } 395 break; 396 case CHIP_G33: 397 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 398 case AGP_G33_PGTBL_SIZE_2M: 399 stolen = 2048 + 4; 400 break; 401 case AGP_G33_PGTBL_SIZE_1M: 402 default: 403 stolen = 1024 + 4; 404 break; 405 } 406 break; 407 case CHIP_G4X: 408 case CHIP_PINEVIEW: 409 case CHIP_IRONLAKE: 410 /* 411 * GTT stolen is separate from graphics stolen on 412 * 4 series hardware. so ignore it in stolen gtt entries 413 * counting. However, 4Kb of stolen memory isn't mapped 414 * to the GTT. 415 */ 416 stolen = 4; 417 break; 418 default: 419 printf("bad chiptype\n"); 420 goto out; 421 } 422 423 switch (gcc1 & AGP_I855_GCC1_GMS) { 424 case AGP_I855_GCC1_GMS_STOLEN_1M: 425 isc->stolen = (1024 - stolen) * 1024 / 4096; 426 break; 427 case AGP_I855_GCC1_GMS_STOLEN_4M: 428 isc->stolen = (4096 - stolen) * 1024 / 4096; 429 break; 430 case AGP_I855_GCC1_GMS_STOLEN_8M: 431 isc->stolen = (8192 - stolen) * 1024 / 4096; 432 break; 433 case AGP_I855_GCC1_GMS_STOLEN_16M: 434 isc->stolen = (16384 - stolen) * 1024 / 4096; 435 break; 436 case AGP_I855_GCC1_GMS_STOLEN_32M: 437 isc->stolen = (32768 - stolen) * 1024 / 4096; 438 break; 439 case AGP_I915_GCC1_GMS_STOLEN_48M: 440 isc->stolen = (49152 - stolen) * 1024 / 4096; 441 break; 442 case AGP_I915_GCC1_GMS_STOLEN_64M: 443 isc->stolen = (65536 - stolen) * 1024 / 4096; 444 break; 445 case AGP_G33_GCC1_GMS_STOLEN_128M: 446 isc->stolen = (131072 - stolen) * 1024 / 4096; 447 break; 448 case AGP_G33_GCC1_GMS_STOLEN_256M: 449 isc->stolen = (262144 - stolen) * 1024 / 4096; 450 break; 451 case AGP_INTEL_GMCH_GMS_STOLEN_96M: 452 isc->stolen = (98304 - stolen) * 1024 / 4096; 453 break; 454 case AGP_INTEL_GMCH_GMS_STOLEN_160M: 455 isc->stolen = (163840 - stolen) * 1024 / 4096; 456 break; 457 case AGP_INTEL_GMCH_GMS_STOLEN_224M: 458 isc->stolen = (229376 - stolen) * 1024 / 4096; 459 break; 460 case AGP_INTEL_GMCH_GMS_STOLEN_352M: 461 isc->stolen = (360448 - stolen) * 1024 / 4096; 462 break; 463 default: 464 isc->stolen = 0; 465 printf("unknown memory configuration, disabling\n"); 466 goto out; 467 } 468 #ifdef DEBUG 469 if (isc->stolen > 0) { 470 printf(": detected %dk stolen memory", 471 isc->stolen * 4); 472 } else 473 printf(": no preallocated video memory\n"); 474 #endif 475 476 /* GATT address is already in there, make sure it's enabled */ 477 gatt->ag_physical = READ4(AGP_I810_PGTBL_CTL) & ~1; 478 break; 479 480 default: 481 printf(": unknown initialisation\n"); 482 return; 483 } 484 /* Intel recommends that you have a fake page bound to the gtt always */ 485 if (agp_alloc_dmamem(pa->pa_dmat, AGP_PAGE_SIZE, &isc->scrib_dmamap, 486 &tmp, &isc->scrib_seg) != 0) { 487 printf(": can't get scribble page\n"); 488 return; 489 } 490 agp_i810_configure(isc); 491 492 isc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_i810_methods, 493 isc->isc_apaddr, isc->isc_apsize, &isc->dev); 494 return; 495 out: 496 497 if (isc->gatt) { 498 if (isc->gatt->ag_size != 0) 499 agp_free_dmamem(pa->pa_dmat, isc->gatt->ag_size, 500 isc->gatt->ag_dmamap, &isc->gatt->ag_dmaseg); 501 free(isc->gatt, M_AGP); 502 } 503 if (isc->gtt_map != NULL) 504 vga_pci_bar_unmap(isc->gtt_map); 505 if (isc->map != NULL) 506 vga_pci_bar_unmap(isc->map); 507 } 508 509 int 510 agp_i810_activate(struct device *arg, int act) 511 { 512 struct agp_i810_softc *isc = (struct agp_i810_softc *)arg; 513 bus_space_tag_t bst = isc->map->bst; 514 bus_space_handle_t bsh = isc->map->bsh; 515 bus_size_t offset; 516 517 if (isc->chiptype == CHIP_I915 || 518 isc->chiptype == CHIP_G33 || 519 isc->chiptype == CHIP_PINEVIEW) { 520 bst = isc->gtt_map->bst; 521 bsh = isc->gtt_map->bsh; 522 } 523 524 switch(isc->chiptype) { 525 case CHIP_I915: 526 case CHIP_G33: 527 case CHIP_PINEVIEW: 528 offset = 0; 529 break; 530 case CHIP_I965: 531 offset = AGP_I965_GTT; 532 break; 533 case CHIP_G4X: 534 case CHIP_IRONLAKE: 535 offset = AGP_G4X_GTT; 536 break; 537 default: 538 offset = AGP_I810_GTT; 539 break; 540 } 541 542 /* 543 * Anything kept in agp over a suspend/resume cycle (and thus by X 544 * over a vt switch cycle) is undefined upon resume. 545 */ 546 switch (act) { 547 case DVACT_RESUME: 548 agp_i810_configure(isc); 549 break; 550 } 551 552 return (0); 553 } 554 void 555 agp_i810_configure(struct agp_i810_softc *isc) 556 { 557 bus_addr_t tmp; 558 559 tmp = isc->isc_apaddr; 560 if (isc->chiptype == CHIP_I810) { 561 tmp += isc->dcache_size; 562 } else { 563 tmp += isc->stolen << AGP_PAGE_SHIFT; 564 } 565 566 agp_flush_cache(); 567 /* Install the GATT. */ 568 WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | 1); 569 570 /* initialise all gtt entries to point to scribble page */ 571 for (; tmp < (isc->isc_apaddr + isc->isc_apsize); 572 tmp += AGP_PAGE_SIZE) 573 agp_i810_unbind_page(isc, tmp); 574 /* XXX we'll need to restore the GTT contents when we go kms */ 575 576 /* 577 * Make sure the chipset can see everything. 578 */ 579 agp_flush_cache(); 580 } 581 582 #if 0 583 int 584 agp_i810_detach(struct agp_softc *sc) 585 { 586 int error; 587 struct agp_i810_softc *isc = sc->sc_chipc; 588 589 error = agp_generic_detach(sc); 590 if (error) 591 return (error); 592 593 /* Clear the GATT base. */ 594 if (sc->chiptype == CHIP_I810) { 595 WRITE4(AGP_I810_PGTBL_CTL, 0); 596 } else { 597 unsigned int pgtblctl; 598 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 599 pgtblctl &= ~1; 600 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 601 } 602 603 if (sc->chiptype == CHIP_I810) { 604 bus_dmamem_unmap(pa->pa_dmat, isc->gatt->ag_virtual, 605 gatt->ag_size); 606 agp_free_dmamem(sc->sc_dmat, gatt->ag_size, gatt->ag_dmamap, 607 &gatt->ag_dmaseg); 608 } 609 free(sc->gatt, M_AGP); 610 611 return (0); 612 } 613 #endif 614 615 void 616 agp_i810_bind_page(void *sc, bus_addr_t offset, paddr_t physical, int flags) 617 { 618 struct agp_i810_softc *isc = sc; 619 /* 620 * COHERENT mappings mean set the snoop bit. this should never be 621 * accessed by the gpu through the gtt. 622 */ 623 if (flags & BUS_DMA_COHERENT) 624 physical |= INTEL_COHERENT; 625 626 intagp_write_gtt(isc, offset - isc->isc_apaddr, physical); 627 } 628 629 void 630 agp_i810_unbind_page(void *sc, bus_size_t offset) 631 { 632 struct agp_i810_softc *isc = sc; 633 634 intagp_write_gtt(isc, offset - isc->isc_apaddr, 635 isc->scrib_dmamap->dm_segs[0].ds_addr); 636 } 637 638 /* 639 * Writing via memory mapped registers already flushes all TLBs. 640 */ 641 void 642 agp_i810_flush_tlb(void *sc) 643 { 644 } 645 646 int 647 agp_i810_enable(void *sc, u_int32_t mode) 648 { 649 return (0); 650 } 651 652 struct agp_memory * 653 agp_i810_alloc_memory(void *softc, int type, vsize_t size) 654 { 655 struct agp_i810_softc *isc = softc; 656 struct agp_softc *sc = isc->agpdev; 657 struct agp_memory *mem; 658 int error; 659 660 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 661 return (NULL); 662 663 if (sc->sc_allocated + size > sc->sc_maxmem) 664 return (NULL); 665 666 if (type == 1) { 667 /* 668 * Mapping local DRAM into GATT. 669 */ 670 if (isc->chiptype != CHIP_I810 || size != isc->dcache_size) 671 return (NULL); 672 } else if (type == 2) { 673 /* 674 * Bogus mapping of 1 or 4 pages for the hardware cursor. 675 */ 676 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) { 677 #ifdef DEBUG 678 printf("agp: trying to map %lu for hw cursor\n", size); 679 #endif 680 return (NULL); 681 } 682 } 683 684 mem = malloc(sizeof *mem, M_AGP, M_WAITOK | M_ZERO); 685 mem->am_id = sc->sc_nextid++; 686 mem->am_size = size; 687 mem->am_type = type; 688 689 if (type == 2) { 690 /* 691 * Allocate and wire down the pages now so that we can 692 * get their physical address. 693 */ 694 if ((mem->am_dmaseg = malloc(sizeof (*mem->am_dmaseg), M_AGP, 695 M_WAITOK | M_CANFAIL)) == NULL) { 696 free(mem, M_AGP); 697 return (NULL); 698 } 699 700 if ((error = agp_alloc_dmamem(sc->sc_dmat, size, 701 &mem->am_dmamap, &mem->am_physical, mem->am_dmaseg)) != 0) { 702 free(mem->am_dmaseg, M_AGP); 703 free(mem, M_AGP); 704 printf("agp: agp_alloc_dmamem(%d)\n", error); 705 return (NULL); 706 } 707 } else if (type != 1) { 708 if ((error = bus_dmamap_create(sc->sc_dmat, size, 709 size / PAGE_SIZE + 1, size, 0, BUS_DMA_NOWAIT, 710 &mem->am_dmamap)) != 0) { 711 free(mem, M_AGP); 712 printf("agp: bus_dmamap_create(%d)\n", error); 713 return (NULL); 714 } 715 } 716 717 TAILQ_INSERT_TAIL(&sc->sc_memory, mem, am_link); 718 sc->sc_allocated += size; 719 720 return (mem); 721 } 722 723 int 724 agp_i810_free_memory(void *softc, struct agp_memory *mem) 725 { 726 struct agp_i810_softc *isc = softc; 727 struct agp_softc *sc = isc->agpdev; 728 729 if (mem->am_is_bound) 730 return (EBUSY); 731 732 if (mem->am_type == 2) { 733 agp_free_dmamem(sc->sc_dmat, mem->am_size, mem->am_dmamap, 734 mem->am_dmaseg); 735 free(mem->am_dmaseg, M_AGP); 736 } else if (mem->am_type != 1) { 737 bus_dmamap_destroy(sc->sc_dmat, mem->am_dmamap); 738 } 739 740 sc->sc_allocated -= mem->am_size; 741 TAILQ_REMOVE(&sc->sc_memory, mem, am_link); 742 free(mem, M_AGP); 743 return (0); 744 } 745 746 int 747 agp_i810_bind_memory(void *sc, struct agp_memory *mem, bus_size_t offset) 748 { 749 struct agp_i810_softc *isc = sc; 750 u_int32_t regval, i; 751 752 if (mem->am_is_bound != 0) 753 return (EINVAL); 754 755 if (isc->chiptype != CHIP_I810 && (offset >> AGP_PAGE_SHIFT) < 756 isc->stolen) { 757 #ifdef DEBUG 758 printf("agp: trying to bind into stolen memory\n"); 759 #endif 760 return (EINVAL); 761 } 762 763 /* 764 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 765 * X server for mysterious reasons which leads to crashes if we write 766 * to the GTT through the MMIO window. 767 * Until the issue is solved, simply restore it. 768 */ 769 regval = READ4(AGP_I810_PGTBL_CTL); 770 if (regval != (isc->gatt->ag_physical | 1)) { 771 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 772 regval); 773 WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | 774 INTEL_ENABLED); 775 } 776 777 if (mem->am_type == 2) { 778 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 779 agp_i810_bind_page(isc, isc->isc_apaddr + offset + i, 780 mem->am_physical + i, 0); 781 mem->am_offset = offset; 782 mem->am_is_bound = 1; 783 return (0); 784 } 785 786 if (mem->am_type != 1) 787 return (agp_generic_bind_memory(isc->agpdev, mem, offset)); 788 789 if (isc->chiptype != CHIP_I810) 790 return (EINVAL); 791 792 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 793 intagp_write_gtt(isc, i, i | INTEL_ENABLED | INTEL_LOCAL); 794 mem->am_is_bound = 1; 795 return (0); 796 } 797 798 int 799 agp_i810_unbind_memory(void *sc, struct agp_memory *mem) 800 { 801 struct agp_i810_softc *isc = sc; 802 u_int32_t i; 803 804 if (mem->am_is_bound == 0) 805 return (EINVAL); 806 807 if (mem->am_type == 2) { 808 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 809 agp_i810_unbind_page(isc, isc->isc_apaddr + 810 mem->am_offset + i); 811 mem->am_offset = 0; 812 mem->am_is_bound = 0; 813 return (0); 814 } 815 816 if (mem->am_type != 1) 817 return (agp_generic_unbind_memory(isc->agpdev, mem)); 818 819 if (isc->chiptype != CHIP_I810) 820 return (EINVAL); 821 822 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 823 intagp_write_gtt(isc, i, 0); 824 mem->am_is_bound = 0; 825 return (0); 826 } 827 828 void 829 intagp_write_gtt(struct agp_i810_softc *isc, bus_size_t off, paddr_t v) 830 { 831 u_int32_t pte = 0; 832 bus_size_t baseoff, wroff; 833 834 if (isc->chiptype != CHIP_I810 && 835 (off >> AGP_PAGE_SHIFT) < isc->stolen) { 836 printf("intagp: binding into stolen memory!\n"); 837 } 838 839 if (v != 0) { 840 pte = v | INTEL_ENABLED; 841 /* 965+ can do 36-bit addressing, add in the extra bits */ 842 if (isc->chiptype == CHIP_I965 || 843 isc->chiptype == CHIP_G4X || 844 isc->chiptype == CHIP_PINEVIEW || 845 isc->chiptype == CHIP_G33 || 846 isc->chiptype == CHIP_IRONLAKE) { 847 pte |= (v & 0x0000000f00000000ULL) >> 28; 848 } 849 } 850 851 wroff = (off >> AGP_PAGE_SHIFT) * 4; 852 853 switch(isc->chiptype) { 854 case CHIP_I915: 855 /* FALLTHROUGH */ 856 case CHIP_G33: 857 case CHIP_PINEVIEW: 858 bus_space_write_4(isc->gtt_map->bst, isc->gtt_map->bsh, 859 wroff, pte); 860 return; 861 case CHIP_I965: 862 baseoff = AGP_I965_GTT; 863 break; 864 case CHIP_G4X: 865 case CHIP_IRONLAKE: 866 baseoff = AGP_G4X_GTT; 867 break; 868 default: 869 baseoff = AGP_I810_GTT; 870 break; 871 } 872 bus_space_write_4(isc->map->bst, isc->map->bsh, baseoff + wroff, pte); 873 } 874