1 /* $OpenBSD: ahc_pci.c,v 1.53 2008/05/13 02:24:08 brad Exp $ */ 2 /* $NetBSD: ahc_pci.c,v 1.43 2003/08/18 09:16:22 taca Exp $ */ 3 4 /* 5 * Product specific probe and attach routines for: 6 * 3940, 2940, aic7895, aic7890, aic7880, 7 * aic7870, aic7860 and aic7850 SCSI controllers 8 * 9 * Copyright (c) 1994-2001 Justin T. Gibbs. 10 * Copyright (c) 2000-2001 Adaptec Inc. 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions, and the following disclaimer, 18 * without modification. 19 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 20 * substantially similar to the "NO WARRANTY" disclaimer below 21 * ("Disclaimer") and any redistribution must be conditioned upon 22 * including a substantially similar Disclaimer requirement for further 23 * binary redistribution. 24 * 3. Neither the names of the above-listed copyright holders nor the names 25 * of any contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * Alternatively, this software may be distributed under the terms of the 29 * GNU General Public License ("GPL") version 2 as published by the Free 30 * Software Foundation. 31 * 32 * NO WARRANTY 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 37 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 42 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 43 * POSSIBILITY OF SUCH DAMAGES. 44 * 45 * $Id: ahc_pci.c,v 1.53 2008/05/13 02:24:08 brad Exp $ 46 * 47 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 48 * 49 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 50 */ 51 /* 52 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 53 */ 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 70 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 71 72 #include <dev/ic/aic7xxx_openbsd.h> 73 #include <dev/ic/aic7xxx_inline.h> 74 75 #include <dev/ic/smc93cx6var.h> 76 77 #ifndef __i386__ 78 #define AHC_ALLOW_MEMIO 79 #endif 80 81 static __inline uint64_t 82 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 83 { 84 uint64_t id; 85 86 id = subvendor 87 | (subdevice << 16) 88 | ((uint64_t)vendor << 32) 89 | ((uint64_t)device << 48); 90 91 return (id); 92 } 93 94 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 95 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 96 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 97 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 98 #define ID_9005_SISL_ID 0x0005900500000000ull 99 #define ID_AIC7850 0x5078900400000000ull 100 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 101 #define ID_AIC7855 0x5578900400000000ull 102 #define ID_AIC7859 0x3860900400000000ull 103 #define ID_AHA_2930CU 0x3860900438699004ull 104 #define ID_AIC7860 0x6078900400000000ull 105 #define ID_AIC7860C 0x6078900478609004ull 106 #define ID_AHA_1480A 0x6075900400000000ull 107 #define ID_AHA_2940AU_0 0x6178900400000000ull 108 #define ID_AHA_2940AU_1 0x6178900478619004ull 109 #define ID_AHA_2940AU_CN 0x2178900478219004ull 110 #define ID_AHA_2930C_VAR 0x6038900438689004ull 111 112 #define ID_AIC7870 0x7078900400000000ull 113 #define ID_AHA_2940 0x7178900400000000ull 114 #define ID_AHA_3940 0x7278900400000000ull 115 #define ID_AHA_398X 0x7378900400000000ull 116 #define ID_AHA_2944 0x7478900400000000ull 117 #define ID_AHA_3944 0x7578900400000000ull 118 #define ID_AHA_4944 0x7678900400000000ull 119 120 #define ID_AIC7880 0x8078900400000000ull 121 #define ID_AIC7880_B 0x8078900478809004ull 122 #define ID_AHA_2940U 0x8178900400000000ull 123 #define ID_AHA_3940U 0x8278900400000000ull 124 #define ID_AHA_2944U 0x8478900400000000ull 125 #define ID_AHA_3944U 0x8578900400000000ull 126 #define ID_AHA_398XU 0x8378900400000000ull 127 #define ID_AHA_4944U 0x8678900400000000ull 128 #define ID_AHA_2940UB 0x8178900478819004ull 129 #define ID_AHA_2930U 0x8878900478889004ull 130 #define ID_AHA_2940U_PRO 0x8778900478879004ull 131 #define ID_AHA_2940U_CN 0x0078900478009004ull 132 133 #define ID_AIC7895 0x7895900478959004ull 134 #define ID_AIC7895_ARO 0x7890900478939004ull 135 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 136 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 137 #define ID_AHA_3940AU 0x7895900478929004ull 138 #define ID_AHA_3944AU 0x7895900478949004ull 139 140 #define ID_AIC7890 0x001F9005000F9005ull 141 #define ID_AIC7890_ARO 0x00139005000F9005ull 142 #define ID_AAA_131U2 0x0013900500039005ull 143 #define ID_AHA_2930U2 0x0011900501819005ull 144 #define ID_AHA_2940U2B 0x00109005A1009005ull 145 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 146 #define ID_AHA_2940U2 0x00109005A1809005ull 147 #define ID_AHA_2950U2B 0x00109005E1009005ull 148 149 #define ID_AIC7892 0x008F9005FFFF9005ull 150 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 151 #define ID_AHA_2915LP 0x0082900502109005ull 152 #define ID_AHA_29160 0x00809005E2A09005ull 153 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 154 #define ID_AHA_29160N 0x0080900562A09005ull 155 #define ID_AHA_29160C 0x0080900562209005ull 156 #define ID_AHA_29160B 0x00809005E2209005ull 157 #define ID_AHA_19160B 0x0081900562A19005ull 158 159 #define ID_AIC7896 0x005F9005FFFF9005ull 160 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 161 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 162 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 163 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 164 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 165 166 #define ID_AIC7899 0x00CF9005FFFF9005ull 167 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 168 #define ID_AHA_3960D 0x00C09005F6209005ull 169 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 170 171 #define ID_AIC7810 0x1078900400000000ull 172 #define ID_AIC7815 0x7815900400000000ull 173 174 #define DEVID_9005_TYPE(id) ((id) & 0xF) 175 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 176 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 177 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 178 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 179 180 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 181 #define DEVID_9005_MAXRATE_U160 0x0 182 #define DEVID_9005_MAXRATE_ULTRA2 0x1 183 #define DEVID_9005_MAXRATE_ULTRA 0x2 184 #define DEVID_9005_MAXRATE_FAST 0x3 185 186 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 187 188 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 189 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 190 191 #define SUBID_9005_TYPE(id) ((id) & 0xF) 192 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 193 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 194 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 195 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 196 197 #define SUBID_9005_TYPE_KNOWN(id) \ 198 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 199 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 200 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 201 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 202 203 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 204 #define SUBID_9005_MAXRATE_ULTRA2 0x0 205 #define SUBID_9005_MAXRATE_ULTRA 0x1 206 #define SUBID_9005_MAXRATE_U160 0x2 207 #define SUBID_9005_MAXRATE_RESERVED 0x3 208 209 #define SUBID_9005_SEEPTYPE(id) \ 210 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 211 ? ((id) & 0xC0) >> 6 \ 212 : ((id) & 0x300) >> 8) 213 #define SUBID_9005_SEEPTYPE_NONE 0x0 214 #define SUBID_9005_SEEPTYPE_1K 0x1 215 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 216 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 217 #define SUBID_9005_AUTOTERM(id) \ 218 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 219 ? (((id) & 0x400) >> 10) == 0 \ 220 : (((id) & 0x40) >> 6) == 0) 221 222 #define SUBID_9005_NUMCHAN(id) \ 223 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 224 ? ((id) & 0x300) >> 8 \ 225 : ((id) & 0xC00) >> 10) 226 227 #define SUBID_9005_LEGACYCONN(id) \ 228 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 229 ? 0 \ 230 : ((id) & 0x80) >> 7) 231 232 #define SUBID_9005_MFUNCENB(id) \ 233 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 234 ? ((id) & 0x800) >> 11 \ 235 : ((id) & 0x1000) >> 12) 236 /* 237 * Informational only. Should use chip register to be 238 * certain, but may be use in identification strings. 239 */ 240 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 241 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 242 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 243 244 static ahc_device_setup_t ahc_aic785X_setup; 245 static ahc_device_setup_t ahc_aic7860_setup; 246 static ahc_device_setup_t ahc_apa1480_setup; 247 static ahc_device_setup_t ahc_aic7870_setup; 248 static ahc_device_setup_t ahc_aha394X_setup; 249 static ahc_device_setup_t ahc_aha494X_setup; 250 static ahc_device_setup_t ahc_aha398X_setup; 251 static ahc_device_setup_t ahc_aic7880_setup; 252 static ahc_device_setup_t ahc_aha2940Pro_setup; 253 static ahc_device_setup_t ahc_aha394XU_setup; 254 static ahc_device_setup_t ahc_aha398XU_setup; 255 static ahc_device_setup_t ahc_aic7890_setup; 256 static ahc_device_setup_t ahc_aic7892_setup; 257 static ahc_device_setup_t ahc_aic7895_setup; 258 static ahc_device_setup_t ahc_aic7896_setup; 259 static ahc_device_setup_t ahc_aic7899_setup; 260 static ahc_device_setup_t ahc_aha29160C_setup; 261 static ahc_device_setup_t ahc_raid_setup; 262 static ahc_device_setup_t ahc_aha394XX_setup; 263 static ahc_device_setup_t ahc_aha494XX_setup; 264 static ahc_device_setup_t ahc_aha398XX_setup; 265 266 struct ahc_pci_identity ahc_pci_ident_table [] = 267 { 268 /* aic7850 based controllers */ 269 { 270 ID_AHA_2902_04_10_15_20_30C, 271 ID_ALL_MASK, 272 ahc_aic785X_setup 273 }, 274 /* aic7860 based controllers */ 275 { 276 ID_AHA_2930CU, 277 ID_ALL_MASK, 278 ahc_aic7860_setup 279 }, 280 { 281 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 282 ID_DEV_VENDOR_MASK, 283 ahc_apa1480_setup 284 }, 285 { 286 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 ahc_aic7860_setup 289 }, 290 { 291 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 292 ID_DEV_VENDOR_MASK, 293 ahc_aic7860_setup 294 }, 295 { 296 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 297 ID_DEV_VENDOR_MASK, 298 ahc_aic7860_setup 299 }, 300 /* aic7870 based controllers */ 301 { 302 ID_AHA_2940, 303 ID_ALL_MASK, 304 ahc_aic7870_setup 305 }, 306 { 307 ID_AHA_3940, 308 ID_ALL_MASK, 309 ahc_aha394X_setup 310 }, 311 { 312 ID_AHA_398X, 313 ID_ALL_MASK, 314 ahc_aha398X_setup 315 }, 316 { 317 ID_AHA_2944, 318 ID_ALL_MASK, 319 ahc_aic7870_setup 320 }, 321 { 322 ID_AHA_3944, 323 ID_ALL_MASK, 324 ahc_aha394X_setup 325 }, 326 { 327 ID_AHA_4944, 328 ID_ALL_MASK, 329 ahc_aha494X_setup 330 }, 331 /* aic7880 based controllers */ 332 { 333 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 334 ID_DEV_VENDOR_MASK, 335 ahc_aic7880_setup 336 }, 337 { 338 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 339 ID_DEV_VENDOR_MASK, 340 ahc_aha394XU_setup 341 }, 342 { 343 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 344 ID_DEV_VENDOR_MASK, 345 ahc_aic7880_setup 346 }, 347 { 348 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 ahc_aha394XU_setup 351 }, 352 { 353 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 354 ID_DEV_VENDOR_MASK, 355 ahc_aha398XU_setup 356 }, 357 { 358 /* 359 * XXX Don't know the slot numbers 360 * so we can't identify channels 361 */ 362 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 363 ID_DEV_VENDOR_MASK, 364 ahc_aic7880_setup 365 }, 366 { 367 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 368 ID_DEV_VENDOR_MASK, 369 ahc_aic7880_setup 370 }, 371 { 372 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 ahc_aha2940Pro_setup 375 }, 376 { 377 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 378 ID_DEV_VENDOR_MASK, 379 ahc_aic7880_setup 380 }, 381 /* Ignore all SISL (AAC on MB) based controllers. */ 382 { 383 ID_9005_SISL_ID, 384 ID_9005_SISL_MASK, 385 NULL 386 }, 387 /* aic7890 based controllers */ 388 { 389 ID_AHA_2930U2, 390 ID_ALL_MASK, 391 ahc_aic7890_setup 392 }, 393 { 394 ID_AHA_2940U2B, 395 ID_ALL_MASK, 396 ahc_aic7890_setup 397 }, 398 { 399 ID_AHA_2940U2_OEM, 400 ID_ALL_MASK, 401 ahc_aic7890_setup 402 }, 403 { 404 ID_AHA_2940U2, 405 ID_ALL_MASK, 406 ahc_aic7890_setup 407 }, 408 { 409 ID_AHA_2950U2B, 410 ID_ALL_MASK, 411 ahc_aic7890_setup 412 }, 413 { 414 ID_AIC7890_ARO, 415 ID_ALL_MASK, 416 ahc_aic7890_setup 417 }, 418 { 419 ID_AAA_131U2, 420 ID_ALL_MASK, 421 ahc_aic7890_setup 422 }, 423 /* aic7892 based controllers */ 424 { 425 ID_AHA_29160, 426 ID_ALL_MASK, 427 ahc_aic7892_setup 428 }, 429 { 430 ID_AHA_29160_CPQ, 431 ID_ALL_MASK, 432 ahc_aic7892_setup 433 }, 434 { 435 ID_AHA_29160N, 436 ID_ALL_MASK, 437 ahc_aic7892_setup 438 }, 439 { 440 ID_AHA_29160C, 441 ID_ALL_MASK, 442 ahc_aha29160C_setup 443 }, 444 { 445 ID_AHA_29160B, 446 ID_ALL_MASK, 447 ahc_aic7892_setup 448 }, 449 { 450 ID_AHA_19160B, 451 ID_ALL_MASK, 452 ahc_aic7892_setup 453 }, 454 { 455 ID_AIC7892_ARO, 456 ID_ALL_MASK, 457 ahc_aic7892_setup 458 }, 459 { 460 ID_AHA_2915LP, 461 ID_ALL_MASK, 462 ahc_aic7892_setup 463 }, 464 /* aic7895 based controllers */ 465 { 466 ID_AHA_2940U_DUAL, 467 ID_ALL_MASK, 468 ahc_aic7895_setup 469 }, 470 { 471 ID_AHA_3940AU, 472 ID_ALL_MASK, 473 ahc_aic7895_setup 474 }, 475 { 476 ID_AHA_3944AU, 477 ID_ALL_MASK, 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AIC7895_ARO, 482 ID_AIC7895_ARO_MASK, 483 ahc_aic7895_setup 484 }, 485 /* aic7896/97 based controllers */ 486 { 487 ID_AHA_3950U2B_0, 488 ID_ALL_MASK, 489 ahc_aic7896_setup 490 }, 491 { 492 ID_AHA_3950U2B_1, 493 ID_ALL_MASK, 494 ahc_aic7896_setup 495 }, 496 { 497 ID_AHA_3950U2D_0, 498 ID_ALL_MASK, 499 ahc_aic7896_setup 500 }, 501 { 502 ID_AHA_3950U2D_1, 503 ID_ALL_MASK, 504 ahc_aic7896_setup 505 }, 506 { 507 ID_AIC7896_ARO, 508 ID_ALL_MASK, 509 ahc_aic7896_setup 510 }, 511 /* aic7899 based controllers */ 512 { 513 ID_AHA_3960D, 514 ID_ALL_MASK, 515 ahc_aic7899_setup 516 }, 517 { 518 ID_AHA_3960D_CPQ, 519 ID_ALL_MASK, 520 ahc_aic7899_setup 521 }, 522 { 523 ID_AIC7899_ARO, 524 ID_ALL_MASK, 525 ahc_aic7899_setup 526 }, 527 /* Generic chip probes for devices we don't know 'exactly' */ 528 { 529 ID_AIC7850 & ID_DEV_VENDOR_MASK, 530 ID_DEV_VENDOR_MASK, 531 ahc_aic785X_setup 532 }, 533 { 534 ID_AIC7855 & ID_DEV_VENDOR_MASK, 535 ID_DEV_VENDOR_MASK, 536 ahc_aic785X_setup 537 }, 538 { 539 ID_AIC7859 & ID_DEV_VENDOR_MASK, 540 ID_DEV_VENDOR_MASK, 541 ahc_aic7860_setup 542 }, 543 { 544 ID_AIC7860 & ID_DEV_VENDOR_MASK, 545 ID_DEV_VENDOR_MASK, 546 ahc_aic7860_setup 547 }, 548 { 549 ID_AIC7870 & ID_DEV_VENDOR_MASK, 550 ID_DEV_VENDOR_MASK, 551 ahc_aic7870_setup 552 }, 553 { 554 ID_AIC7880 & ID_DEV_VENDOR_MASK, 555 ID_DEV_VENDOR_MASK, 556 ahc_aic7880_setup 557 }, 558 { 559 ID_AIC7890 & ID_9005_GENERIC_MASK, 560 ID_9005_GENERIC_MASK, 561 ahc_aic7890_setup 562 }, 563 { 564 ID_AIC7892 & ID_9005_GENERIC_MASK, 565 ID_9005_GENERIC_MASK, 566 ahc_aic7892_setup 567 }, 568 { 569 ID_AIC7895 & ID_DEV_VENDOR_MASK, 570 ID_DEV_VENDOR_MASK, 571 ahc_aic7895_setup 572 }, 573 { 574 ID_AIC7896 & ID_9005_GENERIC_MASK, 575 ID_9005_GENERIC_MASK, 576 ahc_aic7896_setup 577 }, 578 { 579 ID_AIC7899 & ID_9005_GENERIC_MASK, 580 ID_9005_GENERIC_MASK, 581 ahc_aic7899_setup 582 }, 583 { 584 ID_AIC7810 & ID_DEV_VENDOR_MASK, 585 ID_DEV_VENDOR_MASK, 586 ahc_raid_setup 587 }, 588 { 589 ID_AIC7815 & ID_DEV_VENDOR_MASK, 590 ID_DEV_VENDOR_MASK, 591 ahc_raid_setup 592 } 593 }; 594 595 #define AHC_394X_SLOT_CHANNEL_A 4 596 #define AHC_394X_SLOT_CHANNEL_B 5 597 598 #define AHC_398X_SLOT_CHANNEL_A 4 599 #define AHC_398X_SLOT_CHANNEL_B 8 600 #define AHC_398X_SLOT_CHANNEL_C 12 601 602 #define AHC_494X_SLOT_CHANNEL_A 4 603 #define AHC_494X_SLOT_CHANNEL_B 5 604 #define AHC_494X_SLOT_CHANNEL_C 6 605 #define AHC_494X_SLOT_CHANNEL_D 7 606 607 #define DEVCONFIG 0x40 608 #define PCIERRGENDIS 0x80000000ul 609 #define SCBSIZE32 0x00010000ul /* aic789X only */ 610 #define REXTVALID 0x00001000ul /* ultra cards only */ 611 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 612 #define RAMPSM 0x00000200ul /* aic7870+ only */ 613 #define VOLSENSE 0x00000100ul 614 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 615 #define SCBRAMSEL 0x00000080ul 616 #define MRDCEN 0x00000040ul 617 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 618 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 619 #define BERREN 0x00000008ul 620 #define DACEN 0x00000004ul 621 #define STPWLEVEL 0x00000002ul 622 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 623 624 #define CSIZE_LATTIME 0x0c 625 #define CACHESIZE 0x0000003ful /* only 5 bits */ 626 #define LATTIME 0x0000ff00ul 627 628 /* PCI STATUS definitions */ 629 #define DPE 0x80 630 #define SSE 0x40 631 #define RMA 0x20 632 #define RTA 0x10 633 #define STA 0x08 634 #define DPR 0x01 635 636 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 637 uint16_t subvendor, uint16_t subdevice); 638 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 639 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 640 int pcheck, int fast, int large); 641 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 642 static int ahc_pci_chip_init(struct ahc_softc *ahc); 643 644 int ahc_pci_probe(struct device *, void *, void *); 645 void ahc_pci_attach(struct device *, struct device *, void *); 646 647 648 struct cfattach ahc_pci_ca = { 649 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 650 }; 651 652 const struct ahc_pci_identity * 653 ahc_find_pci_device(id, subid, func) 654 pcireg_t id, subid; 655 u_int func; 656 { 657 u_int64_t full_id; 658 const struct ahc_pci_identity *entry; 659 u_int i; 660 661 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 662 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 663 664 /* 665 * If the second function is not hooked up, ignore it. 666 * Unfortunately, not all MB vendors implement the 667 * subdevice ID as per the Adaptec spec, so do our best 668 * to sanity check it prior to accepting the subdevice 669 * ID as valid. 670 */ 671 if (func > 0 672 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 673 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 674 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 675 return (NULL); 676 677 for (i = 0; i < NUM_ELEMENTS(ahc_pci_ident_table); i++) { 678 entry = &ahc_pci_ident_table[i]; 679 if (entry->full_id == (full_id & entry->id_mask)) 680 return (entry); 681 } 682 return (NULL); 683 } 684 685 int 686 ahc_pci_probe(parent, match, aux) 687 struct device *parent; 688 void *match, *aux; 689 { 690 struct pci_attach_args *pa = aux; 691 const struct ahc_pci_identity *entry; 692 pcireg_t subid; 693 694 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 695 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 696 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 697 } 698 699 void 700 ahc_pci_attach(parent, self, aux) 701 struct device *parent, *self; 702 void *aux; 703 { 704 struct pci_attach_args *pa = aux; 705 const struct ahc_pci_identity *entry; 706 struct ahc_softc *ahc = (void *)self; 707 pcireg_t command; 708 u_int our_id = 0; 709 u_int sxfrctl1; 710 u_int scsiseq; 711 u_int sblkctl; 712 uint8_t dscommand0; 713 uint32_t devconfig; 714 int error; 715 pcireg_t subid; 716 int ioh_valid; 717 bus_space_tag_t st, iot; 718 bus_space_handle_t sh, ioh; 719 #ifdef AHC_ALLOW_MEMIO 720 int memh_valid; 721 bus_space_tag_t memt; 722 bus_space_handle_t memh; 723 pcireg_t memtype; 724 #endif 725 pci_intr_handle_t ih; 726 const char *intrstr; 727 struct ahc_pci_busdata *bd; 728 int i; 729 730 /* 731 * Instead of ahc_alloc() as in FreeBSD, do the few relevant 732 * initializations manually. 733 */ 734 LIST_INIT(&ahc->pending_scbs); 735 ahc->channel = 'A'; 736 ahc->seqctl = FASTMODE; 737 for (i = 0; i < AHC_NUM_TARGETS; i++) 738 TAILQ_INIT(&ahc->untagged_queues[i]); 739 740 /* 741 * SCSI_IS_SCSIBUS_B() must returns false until sc_channel_b 742 * has been properly initialized. XXX Breaks if >254 scsi buses. 743 */ 744 ahc->sc_channel_b.scsibus = 0xff; 745 746 ahc->dev_softc = pa; 747 748 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 749 ahc->parent_dmat = pa->pa_dmat; 750 751 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 752 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 753 if (entry == NULL) 754 return; 755 756 /* Keep information about the PCI bus */ 757 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, 758 M_NOWAIT | M_ZERO); 759 if (bd == NULL) { 760 printf("%s: unable to allocate bus-specific data\n", 761 ahc_name(ahc)); 762 return; 763 } 764 765 bd->pc = pa->pa_pc; 766 bd->tag = pa->pa_tag; 767 bd->func = pa->pa_function; 768 bd->dev = pa->pa_device; 769 bd->class = pa->pa_class; 770 771 ahc->bd = bd; 772 773 error = entry->setup(ahc); 774 if (error != 0) 775 return; 776 777 ioh_valid = 0; 778 779 #ifdef AHC_ALLOW_MEMIO 780 memh_valid = 0; 781 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 782 switch (memtype) { 783 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 784 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 785 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 786 memtype, 0, &memt, &memh, NULL, NULL, 0) == 0); 787 break; 788 default: 789 memh_valid = 0; 790 } 791 if (memh_valid == 0) 792 #endif 793 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 794 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0); 795 #if 0 796 printf("%s: mem mapping: memt 0x%x, memh 0x%x, iot 0x%x, ioh 0x%lx\n", 797 ahc_name(ahc), memt, (u_int32_t)memh, (u_int32_t)iot, ioh); 798 #endif 799 800 if (ioh_valid) { 801 st = iot; 802 sh = ioh; 803 #ifdef AHC_ALLOW_MEMIO 804 } else if (memh_valid) { 805 st = memt; 806 sh = memh; 807 #endif 808 } else { 809 printf(": unable to map registers\n"); 810 return; 811 } 812 ahc->tag = st; 813 ahc->bsh = sh; 814 815 ahc->chip |= AHC_PCI; 816 /* 817 * Before we continue probing the card, ensure that 818 * its interrupts are *disabled*. We don't want 819 * a misstep to hang the machine in an interrupt 820 * storm. 821 */ 822 ahc_intr_enable(ahc, FALSE); 823 824 /* 825 * XXX somehow reading this once fails on some sparc64 systems. 826 * This may be a problem in the sparc64 PCI code. Doing it 827 * twice works around it. 828 */ 829 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 830 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 831 832 /* 833 * If we need to support high memory, enable dual 834 * address cycles. This bit must be set to enable 835 * high address bit generation even if we are on a 836 * 64bit bus (PCI64BIT set in devconfig). 837 */ 838 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 839 840 if (1/*bootverbose*/) 841 printf("%s: Enabling 39Bit Addressing\n", 842 ahc_name(ahc)); 843 devconfig |= DACEN; 844 } 845 846 /* Ensure that pci error generation, a test feature, is disabled. */ 847 devconfig |= PCIERRGENDIS; 848 849 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 850 851 /* 852 * Disable PCI parity error reporting. Users typically 853 * do this to work around broken PCI chipsets that get 854 * the parity timing wrong and thus generate lots of spurious 855 * errors. 856 */ 857 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) { 858 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 859 PCI_COMMAND_STATUS_REG); 860 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 861 command & ~PCI_COMMAND_PARITY_ENABLE); 862 } 863 864 /* On all PCI adapters, we allow SCB paging */ 865 ahc->flags |= AHC_PAGESCBS; 866 error = ahc_softc_init(ahc); 867 if (error != 0) 868 goto error_out; 869 870 ahc->bus_intr = ahc_pci_intr; 871 ahc->bus_chip_init = ahc_pci_chip_init; 872 873 /* Remember how the card was setup in case there is no SEEPROM */ 874 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 875 ahc_pause(ahc); 876 if ((ahc->features & AHC_ULTRA2) != 0) 877 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 878 else 879 our_id = ahc_inb(ahc, SCSIID) & OID; 880 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 881 scsiseq = ahc_inb(ahc, SCSISEQ); 882 } else { 883 sxfrctl1 = STPWEN; 884 our_id = 7; 885 scsiseq = 0; 886 } 887 888 error = ahc_reset(ahc, /*reinit*/FALSE); 889 if (error != 0) 890 goto error_out; 891 892 if ((ahc->features & AHC_DT) != 0) { 893 u_int sfunct; 894 895 /* Perform ALT-Mode Setup */ 896 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 897 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 898 ahc_outb(ahc, OPTIONMODE, 899 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 900 ahc_outb(ahc, SFUNCT, sfunct); 901 902 /* Normal mode setup */ 903 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 904 |TARGCRCENDEN); 905 } 906 907 if (pci_intr_map(pa, &ih)) { 908 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 909 ahc_free(ahc); 910 return; 911 } 912 intrstr = pci_intr_string(pa->pa_pc, ih); 913 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 914 ahc_platform_intr, ahc, ahc->sc_dev.dv_xname); 915 if (ahc->ih == NULL) { 916 printf(": couldn't establish interrupt"); 917 if (intrstr != NULL) 918 printf(" at %s", intrstr); 919 printf("\n"); 920 ahc_free(ahc); 921 return; 922 } else 923 printf(": %s\n", intrstr ? intrstr : "?"); 924 925 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 926 dscommand0 |= MPARCKEN|CACHETHEN; 927 if ((ahc->features & AHC_ULTRA2) != 0) { 928 929 /* 930 * DPARCKEN doesn't work correctly on 931 * some MBs so don't use it. 932 */ 933 dscommand0 &= ~DPARCKEN; 934 } 935 936 /* 937 * Handle chips that must have cache line 938 * streaming (dis/en)abled. 939 */ 940 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 941 dscommand0 |= CACHETHEN; 942 943 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 944 dscommand0 &= ~CACHETHEN; 945 946 ahc_outb(ahc, DSCOMMAND0, dscommand0); 947 948 ahc->pci_cachesize = 949 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 950 ahc->pci_cachesize *= 4; 951 952 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 953 && ahc->pci_cachesize == 4) { 954 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 955 ahc->pci_cachesize = 0; 956 } 957 958 /* 959 * We cannot perform ULTRA speeds without the presence 960 * of the external precision resistor. 961 */ 962 if ((ahc->features & AHC_ULTRA) != 0) { 963 uint32_t devconfig; 964 965 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 966 if ((devconfig & REXTVALID) == 0) 967 ahc->features &= ~AHC_ULTRA; 968 } 969 970 ahc->seep_config = malloc(sizeof(*ahc->seep_config), M_DEVBUF, 971 M_NOWAIT | M_ZERO); 972 if (ahc->seep_config == NULL) 973 goto error_out; 974 975 /* See if we have a SEEPROM and perform auto-term */ 976 ahc_check_extport(ahc, &sxfrctl1); 977 978 /* 979 * Take the LED out of diagnostic mode 980 */ 981 sblkctl = ahc_inb(ahc, SBLKCTL); 982 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 983 984 if ((ahc->features & AHC_ULTRA2) != 0) { 985 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 986 } else { 987 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 988 } 989 990 if (ahc->flags & AHC_USEDEFAULTS) { 991 /* 992 * PCI Adapter default setup 993 * Should only be used if the adapter does not have 994 * a SEEPROM. 995 */ 996 /* See if someone else set us up already */ 997 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 998 && scsiseq != 0) { 999 printf("%s: Using left over BIOS settings\n", 1000 ahc_name(ahc)); 1001 ahc->flags &= ~AHC_USEDEFAULTS; 1002 ahc->flags |= AHC_BIOS_ENABLED; 1003 } else { 1004 /* 1005 * Assume only one connector and always turn 1006 * on termination. 1007 */ 1008 our_id = 0x07; 1009 sxfrctl1 = STPWEN; 1010 } 1011 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1012 1013 ahc->our_id = our_id; 1014 } 1015 1016 /* 1017 * Take a look to see if we have external SRAM. 1018 * We currently do not attempt to use SRAM that is 1019 * shared among multiple controllers. 1020 */ 1021 ahc_probe_ext_scbram(ahc); 1022 1023 /* 1024 * Record our termination setting for the 1025 * generic initialization routine. 1026 */ 1027 if ((sxfrctl1 & STPWEN) != 0) 1028 ahc->flags |= AHC_TERM_ENB_A; 1029 1030 /* 1031 * Save chip register configuration data for chip resets 1032 * that occur during runtime and resume events. 1033 */ 1034 ahc->bus_softc.pci_softc.devconfig = 1035 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1036 ahc->bus_softc.pci_softc.command = 1037 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1038 ahc->bus_softc.pci_softc.csize_lattime = 1039 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME); 1040 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1041 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 1042 if ((ahc->features & AHC_DT) != 0) { 1043 u_int sfunct; 1044 1045 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1046 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1047 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 1048 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 1049 ahc_outb(ahc, SFUNCT, sfunct); 1050 ahc->bus_softc.pci_softc.crccontrol1 = 1051 ahc_inb(ahc, CRCCONTROL1); 1052 } 1053 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1054 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 1055 1056 if ((ahc->features & AHC_ULTRA2) != 0) 1057 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 1058 1059 /* Core initialization */ 1060 if (ahc_init(ahc)) 1061 goto error_out; 1062 1063 ahc_attach(ahc); 1064 1065 return; 1066 1067 error_out: 1068 ahc_free(ahc); 1069 return; 1070 } 1071 1072 static int 1073 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1074 uint16_t subdevice, uint16_t subvendor) 1075 { 1076 int result; 1077 1078 /* Default to invalid. */ 1079 result = 0; 1080 if (vendor == 0x9005 1081 && subvendor == 0x9005 1082 && subdevice != device 1083 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1084 1085 switch (SUBID_9005_TYPE(subdevice)) { 1086 case SUBID_9005_TYPE_MB: 1087 break; 1088 case SUBID_9005_TYPE_CARD: 1089 case SUBID_9005_TYPE_LCCARD: 1090 /* 1091 * Currently only trust Adaptec cards to 1092 * get the sub device info correct. 1093 */ 1094 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1095 result = 1; 1096 break; 1097 case SUBID_9005_TYPE_RAID: 1098 break; 1099 default: 1100 break; 1101 } 1102 } 1103 return (result); 1104 } 1105 1106 1107 /* 1108 * Test for the presense of external sram in an 1109 * "unshared" configuration. 1110 */ 1111 static int 1112 ahc_ext_scbram_present(struct ahc_softc *ahc) 1113 { 1114 u_int chip; 1115 int ramps; 1116 int single_user; 1117 uint32_t devconfig; 1118 1119 chip = ahc->chip & AHC_CHIPID_MASK; 1120 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1121 single_user = (devconfig & MPORTMODE) != 0; 1122 1123 if ((ahc->features & AHC_ULTRA2) != 0) 1124 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1125 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1126 /* 1127 * External SCBRAM arbitration is flakey 1128 * on these chips. Unfortunately this means 1129 * we don't use the extra SCB ram space on the 1130 * 3940AUW. 1131 */ 1132 ramps = 0; 1133 else if (chip >= AHC_AIC7870) 1134 ramps = (devconfig & RAMPSM) != 0; 1135 else 1136 ramps = 0; 1137 1138 if (ramps && single_user) 1139 return (1); 1140 return (0); 1141 } 1142 1143 /* 1144 * Enable external scbram. 1145 */ 1146 static void 1147 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1148 int fast, int large) 1149 { 1150 uint32_t devconfig; 1151 1152 if (ahc->features & AHC_MULTI_FUNC) { 1153 /* 1154 * Set the SCB Base addr (highest address bit) 1155 * depending on which channel we are. 1156 */ 1157 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1158 } 1159 1160 ahc->flags &= ~AHC_LSCBS_ENABLED; 1161 if (large) 1162 ahc->flags |= AHC_LSCBS_ENABLED; 1163 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1164 if ((ahc->features & AHC_ULTRA2) != 0) { 1165 u_int dscommand0; 1166 1167 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1168 if (enable) 1169 dscommand0 &= ~INTSCBRAMSEL; 1170 else 1171 dscommand0 |= INTSCBRAMSEL; 1172 if (large) 1173 dscommand0 &= ~USCBSIZE32; 1174 else 1175 dscommand0 |= USCBSIZE32; 1176 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1177 } else { 1178 if (fast) 1179 devconfig &= ~EXTSCBTIME; 1180 else 1181 devconfig |= EXTSCBTIME; 1182 if (enable) 1183 devconfig &= ~SCBRAMSEL; 1184 else 1185 devconfig |= SCBRAMSEL; 1186 if (large) 1187 devconfig &= ~SCBSIZE32; 1188 else 1189 devconfig |= SCBSIZE32; 1190 } 1191 if (pcheck) 1192 devconfig |= EXTSCBPEN; 1193 else 1194 devconfig &= ~EXTSCBPEN; 1195 1196 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1197 } 1198 1199 /* 1200 * Take a look to see if we have external SRAM. 1201 * We currently do not attempt to use SRAM that is 1202 * shared among multiple controllers. 1203 */ 1204 static void 1205 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1206 { 1207 int num_scbs; 1208 int test_num_scbs; 1209 int enable; 1210 int pcheck; 1211 int fast; 1212 int large; 1213 1214 enable = FALSE; 1215 pcheck = FALSE; 1216 fast = FALSE; 1217 large = FALSE; 1218 num_scbs = 0; 1219 1220 if (ahc_ext_scbram_present(ahc) == 0) 1221 goto done; 1222 1223 /* 1224 * Probe for the best parameters to use. 1225 */ 1226 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1227 num_scbs = ahc_probe_scbs(ahc); 1228 if (num_scbs == 0) { 1229 /* The SRAM wasn't really present. */ 1230 goto done; 1231 } 1232 enable = TRUE; 1233 1234 /* 1235 * Clear any outstanding parity error 1236 * and ensure that parity error reporting 1237 * is enabled. 1238 */ 1239 ahc_outb(ahc, SEQCTL, 0); 1240 ahc_outb(ahc, CLRINT, CLRPARERR); 1241 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1242 1243 /* Now see if we can do parity */ 1244 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1245 num_scbs = ahc_probe_scbs(ahc); 1246 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1247 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1248 pcheck = TRUE; 1249 1250 /* Clear any resulting parity error */ 1251 ahc_outb(ahc, CLRINT, CLRPARERR); 1252 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1253 1254 /* Now see if we can do fast timing */ 1255 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1256 test_num_scbs = ahc_probe_scbs(ahc); 1257 if (test_num_scbs == num_scbs 1258 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1259 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1260 fast = TRUE; 1261 1262 /* 1263 * See if we can use large SCBs and still maintain 1264 * the same overall count of SCBs. 1265 */ 1266 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1267 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1268 test_num_scbs = ahc_probe_scbs(ahc); 1269 if (test_num_scbs >= num_scbs) { 1270 large = TRUE; 1271 num_scbs = test_num_scbs; 1272 if (num_scbs >= 64) { 1273 /* 1274 * We have enough space to move the 1275 * "busy targets table" into SCB space 1276 * and make it qualify all the way to the 1277 * lun level. 1278 */ 1279 ahc->flags |= AHC_SCB_BTT; 1280 } 1281 } 1282 } 1283 done: 1284 /* 1285 * Disable parity error reporting until we 1286 * can load instruction ram. 1287 */ 1288 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1289 /* Clear any latched parity error */ 1290 ahc_outb(ahc, CLRINT, CLRPARERR); 1291 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1292 if (1/*bootverbose*/ && enable) { 1293 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1294 ahc_name(ahc), fast ? "fast" : "slow", 1295 pcheck ? ", parity checking enabled" : "", 1296 large ? 64 : 32); 1297 } 1298 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1299 } 1300 1301 #if 0 1302 /* 1303 * Perform some simple tests that should catch situations where 1304 * our registers are invalidly mapped. 1305 */ 1306 int 1307 ahc_pci_test_register_access(struct ahc_softc *ahc) 1308 { 1309 int error; 1310 u_int status1; 1311 uint32_t cmd; 1312 uint8_t hcntrl; 1313 1314 error = EIO; 1315 1316 /* 1317 * Enable PCI error interrupt status, but suppress NMIs 1318 * generated by SERR raised due to target aborts. 1319 */ 1320 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1321 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1322 cmd & ~PCIM_CMD_SERRESPEN); 1323 1324 /* 1325 * First a simple test to see if any 1326 * registers can be read. Reading 1327 * HCNTRL has no side effects and has 1328 * at least one bit that is guaranteed to 1329 * be zero so it is a good register to 1330 * use for this test. 1331 */ 1332 hcntrl = ahc_inb(ahc, HCNTRL); 1333 if (hcntrl == 0xFF) 1334 goto fail; 1335 1336 /* 1337 * Next create a situation where write combining 1338 * or read prefetching could be initiated by the 1339 * CPU or host bridge. Our device does not support 1340 * either, so look for data corruption and/or flagged 1341 * PCI errors. 1342 */ 1343 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1344 while (ahc_is_paused(ahc) == 0) 1345 ; 1346 ahc_outb(ahc, SEQCTL, PERRORDIS); 1347 ahc_outb(ahc, SCBPTR, 0); 1348 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1349 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1350 goto fail; 1351 1352 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1353 PCI_COMMAND_STATUS_REG + 1); 1354 if ((status1 & STA) != 0) 1355 goto fail; 1356 1357 error = 0; 1358 1359 fail: 1360 /* Silently clear any latched errors. */ 1361 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1); 1362 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1363 status1, /*bytes*/1); 1364 ahc_outb(ahc, CLRINT, CLRPARERR); 1365 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1366 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1367 return (error); 1368 } 1369 #endif 1370 1371 void 1372 ahc_pci_intr(struct ahc_softc *ahc) 1373 { 1374 u_int error; 1375 u_int status1; 1376 1377 error = ahc_inb(ahc, ERROR); 1378 if ((error & PCIERRSTAT) == 0) 1379 return; 1380 1381 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1382 1383 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1384 ahc_name(ahc), 1385 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1386 1387 if (status1 & DPE) { 1388 printf("%s: Data Parity Error Detected during address " 1389 "or write data phase\n", ahc_name(ahc)); 1390 } 1391 if (status1 & SSE) { 1392 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1393 } 1394 if (status1 & RMA) { 1395 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1396 } 1397 if (status1 & RTA) { 1398 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1399 } 1400 if (status1 & STA) { 1401 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1402 } 1403 if (status1 & DPR) { 1404 printf("%s: Data Parity Error has been reported via PERR#\n", 1405 ahc_name(ahc)); 1406 } 1407 1408 /* Clear latched errors. */ 1409 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1); 1410 1411 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1412 printf("%s: Latched PCIERR interrupt with " 1413 "no status bits set\n", ahc_name(ahc)); 1414 } else { 1415 ahc_outb(ahc, CLRINT, CLRPARERR); 1416 } 1417 1418 ahc_unpause(ahc); 1419 } 1420 1421 static int 1422 ahc_pci_chip_init(struct ahc_softc *ahc) 1423 { 1424 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 1425 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 1426 if ((ahc->features & AHC_DT) != 0) { 1427 u_int sfunct; 1428 1429 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1430 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1431 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 1432 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 1433 ahc_outb(ahc, SFUNCT, sfunct); 1434 ahc_outb(ahc, CRCCONTROL1, 1435 ahc->bus_softc.pci_softc.crccontrol1); 1436 } 1437 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1438 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 1439 1440 if ((ahc->features & AHC_ULTRA2) != 0) 1441 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 1442 1443 return (ahc_chip_init(ahc)); 1444 } 1445 1446 static int 1447 ahc_aic785X_setup(struct ahc_softc *ahc) 1448 { 1449 uint8_t rev; 1450 1451 ahc->channel = 'A'; 1452 ahc->chip = AHC_AIC7850; 1453 ahc->features = AHC_AIC7850_FE; 1454 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1455 rev = PCI_REVISION(ahc->bd->class); 1456 if (rev >= 1) 1457 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1458 ahc->instruction_ram_size = 512; 1459 return (0); 1460 } 1461 1462 static int 1463 ahc_aic7860_setup(struct ahc_softc *ahc) 1464 { 1465 uint8_t rev; 1466 1467 ahc->channel = 'A'; 1468 ahc->chip = AHC_AIC7860; 1469 ahc->features = AHC_AIC7860_FE; 1470 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1471 rev = PCI_REVISION(ahc->bd->class); 1472 if (rev >= 1) 1473 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1474 ahc->instruction_ram_size = 512; 1475 return (0); 1476 } 1477 1478 static int 1479 ahc_apa1480_setup(struct ahc_softc *ahc) 1480 { 1481 int error; 1482 1483 error = ahc_aic7860_setup(ahc); 1484 if (error != 0) 1485 return (error); 1486 ahc->features |= AHC_REMOVABLE; 1487 return (0); 1488 } 1489 1490 static int 1491 ahc_aic7870_setup(struct ahc_softc *ahc) 1492 { 1493 1494 ahc->channel = 'A'; 1495 ahc->chip = AHC_AIC7870; 1496 ahc->features = AHC_AIC7870_FE; 1497 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1498 ahc->instruction_ram_size = 512; 1499 return (0); 1500 } 1501 1502 static int 1503 ahc_aha394X_setup(struct ahc_softc *ahc) 1504 { 1505 int error; 1506 1507 error = ahc_aic7870_setup(ahc); 1508 if (error == 0) 1509 error = ahc_aha394XX_setup(ahc); 1510 return (error); 1511 } 1512 1513 static int 1514 ahc_aha398X_setup(struct ahc_softc *ahc) 1515 { 1516 int error; 1517 1518 error = ahc_aic7870_setup(ahc); 1519 if (error == 0) 1520 error = ahc_aha398XX_setup(ahc); 1521 return (error); 1522 } 1523 1524 static int 1525 ahc_aha494X_setup(struct ahc_softc *ahc) 1526 { 1527 int error; 1528 1529 error = ahc_aic7870_setup(ahc); 1530 if (error == 0) 1531 error = ahc_aha494XX_setup(ahc); 1532 return (error); 1533 } 1534 1535 static int 1536 ahc_aic7880_setup(struct ahc_softc *ahc) 1537 { 1538 uint8_t rev; 1539 1540 ahc->channel = 'A'; 1541 ahc->chip = AHC_AIC7880; 1542 ahc->features = AHC_AIC7880_FE; 1543 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1544 rev = PCI_REVISION(ahc->bd->class); 1545 if (rev >= 1) { 1546 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1547 } else { 1548 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1549 } 1550 ahc->instruction_ram_size = 512; 1551 return (0); 1552 } 1553 1554 static int 1555 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1556 { 1557 1558 ahc->flags |= AHC_INT50_SPEEDFLEX; 1559 return (ahc_aic7880_setup(ahc)); 1560 } 1561 1562 static int 1563 ahc_aha394XU_setup(struct ahc_softc *ahc) 1564 { 1565 int error; 1566 1567 error = ahc_aic7880_setup(ahc); 1568 if (error == 0) 1569 error = ahc_aha394XX_setup(ahc); 1570 return (error); 1571 } 1572 1573 static int 1574 ahc_aha398XU_setup(struct ahc_softc *ahc) 1575 { 1576 int error; 1577 1578 error = ahc_aic7880_setup(ahc); 1579 if (error == 0) 1580 error = ahc_aha398XX_setup(ahc); 1581 return (error); 1582 } 1583 1584 static int 1585 ahc_aic7890_setup(struct ahc_softc *ahc) 1586 { 1587 uint8_t rev; 1588 1589 ahc->channel = 'A'; 1590 ahc->chip = AHC_AIC7890; 1591 ahc->features = AHC_AIC7890_FE; 1592 ahc->flags |= AHC_NEWEEPROM_FMT; 1593 rev = PCI_REVISION(ahc->bd->class); 1594 if (rev == 0) 1595 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1596 ahc->instruction_ram_size = 768; 1597 return (0); 1598 } 1599 1600 static int 1601 ahc_aic7892_setup(struct ahc_softc *ahc) 1602 { 1603 1604 ahc->channel = 'A'; 1605 ahc->chip = AHC_AIC7892; 1606 ahc->features = AHC_AIC7892_FE; 1607 ahc->flags |= AHC_NEWEEPROM_FMT; 1608 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1609 ahc->instruction_ram_size = 1024; 1610 return (0); 1611 } 1612 1613 static int 1614 ahc_aic7895_setup(struct ahc_softc *ahc) 1615 { 1616 uint8_t rev; 1617 1618 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1619 /* 1620 * The 'C' revision of the aic7895 has a few additional features. 1621 */ 1622 rev = PCI_REVISION(ahc->bd->class); 1623 if (rev >= 4) { 1624 ahc->chip = AHC_AIC7895C; 1625 ahc->features = AHC_AIC7895C_FE; 1626 } else { 1627 u_int command; 1628 1629 ahc->chip = AHC_AIC7895; 1630 ahc->features = AHC_AIC7895_FE; 1631 1632 /* 1633 * The BIOS disables the use of MWI transactions 1634 * since it does not have the MWI bug work around 1635 * we have. Disabling MWI reduces performance, so 1636 * turn it on again. 1637 */ 1638 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1639 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1640 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command); 1641 ahc->bugs |= AHC_PCI_MWI_BUG; 1642 } 1643 /* 1644 * XXX Does CACHETHEN really not work??? What about PCI retry? 1645 * on C level chips. Need to test, but for now, play it safe. 1646 */ 1647 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1648 | AHC_CACHETHEN_BUG; 1649 1650 #if 0 1651 uint32_t devconfig; 1652 1653 /* 1654 * Cachesize must also be zero due to stray DAC 1655 * problem when sitting behind some bridges. 1656 */ 1657 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1658 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1659 devconfig |= MRDCEN; 1660 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1661 #endif 1662 ahc->flags |= AHC_NEWEEPROM_FMT; 1663 ahc->instruction_ram_size = 512; 1664 return (0); 1665 } 1666 1667 static int 1668 ahc_aic7896_setup(struct ahc_softc *ahc) 1669 { 1670 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1671 ahc->chip = AHC_AIC7896; 1672 ahc->features = AHC_AIC7896_FE; 1673 ahc->flags |= AHC_NEWEEPROM_FMT; 1674 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1675 ahc->instruction_ram_size = 768; 1676 return (0); 1677 } 1678 1679 static int 1680 ahc_aic7899_setup(struct ahc_softc *ahc) 1681 { 1682 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1683 ahc->chip = AHC_AIC7899; 1684 ahc->features = AHC_AIC7899_FE; 1685 ahc->flags |= AHC_NEWEEPROM_FMT; 1686 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1687 ahc->instruction_ram_size = 1024; 1688 return (0); 1689 } 1690 1691 static int 1692 ahc_aha29160C_setup(struct ahc_softc *ahc) 1693 { 1694 int error; 1695 1696 error = ahc_aic7899_setup(ahc); 1697 if (error != 0) 1698 return (error); 1699 ahc->features |= AHC_REMOVABLE; 1700 return (0); 1701 } 1702 1703 static int 1704 ahc_raid_setup(struct ahc_softc *ahc) 1705 { 1706 printf("RAID functionality unsupported\n"); 1707 return (ENXIO); 1708 } 1709 1710 static int 1711 ahc_aha394XX_setup(struct ahc_softc *ahc) 1712 { 1713 1714 switch (ahc->bd->dev) { 1715 case AHC_394X_SLOT_CHANNEL_A: 1716 ahc->channel = 'A'; 1717 break; 1718 case AHC_394X_SLOT_CHANNEL_B: 1719 ahc->channel = 'B'; 1720 break; 1721 default: 1722 printf("adapter at unexpected slot %d\n" 1723 "unable to map to a channel\n", 1724 ahc->bd->dev); 1725 ahc->channel = 'A'; 1726 } 1727 return (0); 1728 } 1729 1730 static int 1731 ahc_aha398XX_setup(struct ahc_softc *ahc) 1732 { 1733 1734 switch (ahc->bd->dev) { 1735 case AHC_398X_SLOT_CHANNEL_A: 1736 ahc->channel = 'A'; 1737 break; 1738 case AHC_398X_SLOT_CHANNEL_B: 1739 ahc->channel = 'B'; 1740 break; 1741 case AHC_398X_SLOT_CHANNEL_C: 1742 ahc->channel = 'C'; 1743 break; 1744 default: 1745 printf("adapter at unexpected slot %d\n" 1746 "unable to map to a channel\n", 1747 ahc->bd->dev); 1748 ahc->channel = 'A'; 1749 break; 1750 } 1751 ahc->flags |= AHC_LARGE_SEEPROM; 1752 return (0); 1753 } 1754 1755 static int 1756 ahc_aha494XX_setup(struct ahc_softc *ahc) 1757 { 1758 1759 switch (ahc->bd->dev) { 1760 case AHC_494X_SLOT_CHANNEL_A: 1761 ahc->channel = 'A'; 1762 break; 1763 case AHC_494X_SLOT_CHANNEL_B: 1764 ahc->channel = 'B'; 1765 break; 1766 case AHC_494X_SLOT_CHANNEL_C: 1767 ahc->channel = 'C'; 1768 break; 1769 case AHC_494X_SLOT_CHANNEL_D: 1770 ahc->channel = 'D'; 1771 break; 1772 default: 1773 printf("adapter at unexpected slot %d\n" 1774 "unable to map to a channel\n", 1775 ahc->bd->dev); 1776 ahc->channel = 'A'; 1777 } 1778 ahc->flags |= AHC_LARGE_SEEPROM; 1779 return (0); 1780 } 1781