1 /* $OpenBSD: ahd_pci.c,v 1.24 2014/07/12 18:48:51 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Milos Urbanek, Kenneth R. Westerback & Marco Peereboom 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Product specific probe and attach routines for: 32 * aic7901 and aic7902 SCSI controllers 33 * 34 * Copyright (c) 1994-2001 Justin T. Gibbs. 35 * Copyright (c) 2000-2002 Adaptec Inc. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions, and the following disclaimer, 43 * without modification. 44 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 45 * substantially similar to the "NO WARRANTY" disclaimer below 46 * ("Disclaimer") and any redistribution must be conditioned upon 47 * including a substantially similar Disclaimer requirement for further 48 * binary redistribution. 49 * 3. Neither the names of the above-listed copyright holders nor the names 50 * of any contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * Alternatively, this software may be distributed under the terms of the 54 * GNU General Public License ("GPL") version 2 as published by the Free 55 * Software Foundation. 56 * 57 * NO WARRANTY 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 59 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 60 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 61 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 62 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 67 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGES. 69 * 70 */ 71 72 #include <dev/ic/aic79xx_openbsd.h> 73 #include <dev/ic/aic79xx_inline.h> 74 #include <dev/ic/aic79xx.h> 75 76 #include <dev/pci/pcivar.h> 77 78 __inline uint64_t ahd_compose_id(u_int, u_int, u_int, u_int); 79 __inline uint64_t 80 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 81 { 82 uint64_t id; 83 84 id = subvendor 85 | (subdevice << 16) 86 | ((uint64_t)vendor << 32) 87 | ((uint64_t)device << 48); 88 89 return (id); 90 } 91 92 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 93 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 94 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 95 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 96 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 97 98 #define ID_AIC7901 0x800F9005FFFF9005ull 99 #define ID_AHA_29320A 0x8000900500609005ull 100 #define ID_AHA_29320ALP 0x8017900500449005ull 101 #define ID_AHA_29320LPE 0x8017900500459005ull 102 103 #define ID_AIC7901A 0x801E9005FFFF9005ull 104 #define ID_AHA_29320LP 0x8014900500449005ull 105 106 #define ID_AIC7902 0x801F9005FFFF9005ull 107 #define ID_AIC7902_B 0x801D9005FFFF9005ull 108 #define ID_AHA_39320 0x8010900500409005ull 109 #define ID_AHA_29320 0x8012900500429005ull 110 #define ID_AHA_29320B 0x8013900500439005ull 111 #define ID_AHA_39320_B 0x8015900500409005ull 112 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 113 #define ID_AHA_39320A 0x8016900500409005ull 114 #define ID_AHA_39320D 0x8011900500419005ull 115 #define ID_AHA_39320D_B 0x801C900500419005ull 116 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 117 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 118 #define ID_AIC7902_PCI_REV_A4 0x3 119 #define ID_AIC7902_PCI_REV_B0 0x10 120 #define SUBID_HP 0x0E11 121 122 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 123 124 #define DEVID_9005_TYPE(id) ((id) & 0xF) 125 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 126 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 127 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 128 129 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 130 131 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 132 133 #define SUBID_9005_TYPE(id) ((id) & 0xF) 134 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 135 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 136 137 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 138 139 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 140 141 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 142 #define SUBID_9005_SEEPTYPE_NONE 0x0 143 #define SUBID_9005_SEEPTYPE_4K 0x1 144 145 ahd_device_setup_t ahd_aic7901_setup; 146 ahd_device_setup_t ahd_aic7901A_setup; 147 ahd_device_setup_t ahd_aic7902_setup; 148 ahd_device_setup_t ahd_aic790X_setup; 149 150 struct ahd_pci_identity ahd_pci_ident_table [] = 151 { 152 /* aic7901 based controllers */ 153 { 154 ID_AHA_29320A, 155 ID_ALL_MASK, 156 ahd_aic7901_setup 157 }, 158 { 159 ID_AHA_29320ALP, 160 ID_ALL_MASK, 161 ahd_aic7901_setup 162 }, 163 { 164 ID_AHA_29320LPE, 165 ID_ALL_MASK, 166 ahd_aic7901_setup 167 }, 168 /* aic7901A based controllers */ 169 { 170 ID_AHA_29320LP, 171 ID_ALL_MASK, 172 ahd_aic7901A_setup 173 }, 174 /* aic7902 based controllers */ 175 { 176 ID_AHA_29320, 177 ID_ALL_MASK, 178 ahd_aic7902_setup 179 }, 180 { 181 ID_AHA_29320B, 182 ID_ALL_MASK, 183 ahd_aic7902_setup 184 }, 185 { 186 ID_AHA_39320, 187 ID_ALL_MASK, 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320_B, 192 ID_ALL_MASK, 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320_B_DELL, 197 ID_ALL_MASK, 198 ahd_aic7902_setup 199 }, 200 { 201 ID_AHA_39320A, 202 ID_ALL_MASK, 203 ahd_aic7902_setup 204 }, 205 { 206 ID_AHA_39320D, 207 ID_ALL_MASK, 208 ahd_aic7902_setup 209 }, 210 { 211 ID_AHA_39320D_HP, 212 ID_ALL_MASK, 213 ahd_aic7902_setup 214 }, 215 { 216 ID_AHA_39320D_B, 217 ID_ALL_MASK, 218 ahd_aic7902_setup 219 }, 220 { 221 ID_AHA_39320D_B_HP, 222 ID_ALL_MASK, 223 ahd_aic7902_setup 224 }, 225 /* Generic chip probes for devices we don't know 'exactly' */ 226 { 227 ID_AIC7901 & ID_9005_GENERIC_MASK, 228 ID_9005_GENERIC_MASK, 229 ahd_aic7901_setup 230 }, 231 { 232 ID_AIC7901A & ID_DEV_VENDOR_MASK, 233 ID_DEV_VENDOR_MASK, 234 ahd_aic7901A_setup 235 }, 236 { 237 ID_AIC7902 & ID_9005_GENERIC_MASK, 238 ID_9005_GENERIC_MASK, 239 ahd_aic7902_setup 240 } 241 }; 242 243 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 244 245 #define DEVCONFIG 0x40 246 #define PCIXINITPAT 0x0000E000ul 247 #define PCIXINIT_PCI33_66 0x0000E000ul 248 #define PCIXINIT_PCIX50_66 0x0000C000ul 249 #define PCIXINIT_PCIX66_100 0x0000A000ul 250 #define PCIXINIT_PCIX100_133 0x00008000ul 251 #define PCI_BUS_MODES_INDEX(devconfig) \ 252 (((devconfig) & PCIXINITPAT) >> 13) 253 254 static const char *pci_bus_modes[] = 255 { 256 "PCI bus mode unknown", 257 "PCI bus mode unknown", 258 "PCI bus mode unknown", 259 "PCI bus mode unknown", 260 "PCI-X 101-133MHz", 261 "PCI-X 67-100MHz", 262 "PCI-X 50-66MHz", 263 "PCI 33 or 66MHz" 264 }; 265 266 #define TESTMODE 0x00000800ul 267 #define IRDY_RST 0x00000200ul 268 #define FRAME_RST 0x00000100ul 269 #define PCI64BIT 0x00000080ul 270 #define MRDCEN 0x00000040ul 271 #define ENDIANSEL 0x00000020ul 272 #define MIXQWENDIANEN 0x00000008ul 273 #define DACEN 0x00000004ul 274 #define STPWLEVEL 0x00000002ul 275 #define QWENDIANSEL 0x00000001ul 276 277 #define DEVCONFIG1 0x44 278 #define PREQDIS 0x01 279 280 #define CSIZE_LATTIME 0x0c 281 #define CACHESIZE 0x000000fful 282 #define LATTIME 0x0000ff00ul 283 284 int ahd_pci_probe(struct device *, void *, void *); 285 void ahd_pci_attach(struct device *, struct device *, void *); 286 int ahd_activate(struct device *, int); 287 288 struct cfattach ahd_pci_ca = { 289 sizeof(struct ahd_softc), ahd_pci_probe, ahd_pci_attach, 290 NULL, ahd_activate 291 }; 292 293 int ahd_check_extport(struct ahd_softc *ahd); 294 void ahd_configure_termination(struct ahd_softc *ahd, 295 u_int adapter_control); 296 void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 297 298 const struct ahd_pci_identity * 299 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 300 { 301 const struct ahd_pci_identity *entry; 302 u_int64_t full_id; 303 u_int i; 304 305 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 306 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 307 308 /* 309 * If we are configured to attach to HostRAID 310 * controllers, mask out the IROC/HostRAID bit 311 * in the 312 */ 313 if (ahd_attach_to_HostRAID_controllers) 314 full_id &= ID_ALL_IROC_MASK; 315 316 for (i = 0; i < ahd_num_pci_devs; i++) { 317 entry = &ahd_pci_ident_table[i]; 318 if (entry->full_id == (full_id & entry->id_mask)) { 319 return (entry); 320 } 321 } 322 return (NULL); 323 } 324 325 int 326 ahd_pci_probe(struct device *parent, void *match, void *aux) 327 { 328 const struct ahd_pci_identity *entry; 329 struct pci_attach_args *pa = aux; 330 pcireg_t subid; 331 332 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 333 entry = ahd_find_pci_device(pa->pa_id, subid); 334 return entry != NULL ? 1 : 0; 335 } 336 337 void 338 ahd_pci_attach(struct device *parent, struct device *self, void *aux) 339 { 340 const struct ahd_pci_identity *entry; 341 struct pci_attach_args *pa = aux; 342 struct ahd_softc *ahd = (void *)self; 343 pci_intr_handle_t ih; 344 const char *intrstr; 345 pcireg_t devconfig, memtype, subid; 346 uint16_t device, subvendor; 347 int error, ioh_valid, ioh2_valid, l, memh_valid; 348 349 ahd->dev_softc = pa; 350 ahd->parent_dmat = pa->pa_dmat; 351 352 if (ahd_alloc(ahd, ahd->sc_dev.dv_xname) == NULL) 353 return; 354 355 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 356 entry = ahd_find_pci_device(pa->pa_id, subid); 357 if (entry == NULL) 358 return; 359 360 /* 361 * Record if this is a HostRAID board. 362 */ 363 device = PCI_PRODUCT(pa->pa_id); 364 if (DEVID_9005_HOSTRAID(device)) 365 ahd->flags |= AHD_HOSTRAID_BOARD; 366 367 /* 368 * Record if this is an HP board. 369 */ 370 subvendor = PCI_VENDOR(subid); 371 if (subvendor == SUBID_HP) 372 ahd->flags |= AHD_HP_BOARD; 373 374 error = entry->setup(ahd, pa); 375 if (error != 0) 376 return; 377 378 /* XXX ahc on sparc64 needs this twice */ 379 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 380 381 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 382 ahd->chip |= AHD_PCI; 383 /* Disable PCIX workarounds when running in PCI mode. */ 384 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 385 } else { 386 ahd->chip |= AHD_PCIX; 387 } 388 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 389 390 memh_valid = ioh_valid = ioh2_valid = 0; 391 392 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 393 &ahd->pcix_off, NULL)) { 394 if (ahd->chip & AHD_PCIX) 395 printf("%s: warning: can't find PCI-X capability\n", 396 ahd_name(ahd)); 397 ahd->chip &= ~AHD_PCIX; 398 ahd->chip |= AHD_PCI; 399 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 400 } 401 402 /* 403 * Map PCI registers 404 */ 405 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 406 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 407 AHD_PCI_MEMADDR); 408 switch (memtype) { 409 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 410 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 411 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 412 memtype, 0, &ahd->tags[0], &ahd->bshs[0], NULL, 413 NULL, 0) == 0); 414 if (memh_valid) { 415 ahd->tags[1] = ahd->tags[0]; 416 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 417 /*offset*/0x100, /*size*/0x100, 418 &ahd->bshs[1]); 419 if (ahd_pci_test_register_access(ahd) != 0) 420 memh_valid = 0; 421 } 422 break; 423 default: 424 memh_valid = 0; 425 printf("%s: unknown memory type: 0x%x\n", 426 ahd_name(ahd), memtype); 427 break; 428 } 429 430 #ifdef AHD_DEBUG 431 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, shs0 " 432 "0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 433 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 434 #endif 435 } 436 437 if (!memh_valid) { 438 /* First BAR */ 439 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 440 PCI_MAPREG_TYPE_IO, 0, &ahd->tags[0], &ahd->bshs[0], NULL, 441 NULL, 0) == 0); 442 443 /* 2nd BAR */ 444 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 445 PCI_MAPREG_TYPE_IO, 0, &ahd->tags[1], &ahd->bshs[1], NULL, 446 NULL, 0) == 0); 447 448 #ifdef AHD_DEBUG 449 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, " 450 "shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], ahd->tags[1], 451 ahd->bshs[0], ahd->bshs[1]); 452 #endif 453 } 454 455 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 456 printf("%s: unable to map registers\n", ahd_name(ahd)); 457 return; 458 } 459 460 /* 461 * Set Power State D0. 462 */ 463 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 464 465 /* 466 * Should we bother disabling 39Bit addressing 467 * based on installed memory? 468 */ 469 if (sizeof(bus_addr_t) > 4) 470 ahd->flags |= AHD_39BIT_ADDRESSING; 471 472 /* 473 * If we need to support high memory, enable dual 474 * address cycles. This bit must be set to enable 475 * high address bit generation even if we are on a 476 * 64bit bus (PCI64BIT set in devconfig). 477 */ 478 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 479 if (bootverbose) 480 printf("%s: Enabling 39Bit Addressing\n", 481 ahd_name(ahd)); 482 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 483 devconfig |= DACEN; 484 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 485 } 486 487 ahd_softc_init(ahd); 488 489 /* 490 * Map the interrupts routines 491 */ 492 ahd->bus_intr = ahd_pci_intr; 493 494 error = ahd_reset(ahd, /*reinit*/FALSE); 495 if (error != 0) { 496 ahd_free(ahd); 497 return; 498 } 499 500 if (pci_intr_map(pa, &ih)) { 501 printf("%s: couldn't map interrupt\n", ahd_name(ahd)); 502 ahd_free(ahd); 503 return; 504 } 505 intrstr = pci_intr_string(pa->pa_pc, ih); 506 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 507 ahd_platform_intr, ahd, ahd->sc_dev.dv_xname); 508 if (ahd->ih == NULL) { 509 printf("%s: couldn't establish interrupt", ahd_name(ahd)); 510 if (intrstr != NULL) 511 printf(" at %s", intrstr); 512 printf("\n"); 513 ahd_free(ahd); 514 return; 515 } 516 if (intrstr != NULL) 517 printf(": %s\n", intrstr); 518 519 /* Get the size of the cache */ 520 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 521 ahd->pci_cachesize *= 4; 522 523 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 524 /* See if we have a SEEPROM and perform auto-term */ 525 error = ahd_check_extport(ahd); 526 if (error != 0) 527 return; 528 529 /* Core initialization */ 530 error = ahd_init(ahd); 531 if (error != 0) 532 return; 533 534 ahd_list_lock(&l); 535 /* 536 * Link this softc in with all other ahd instances. 537 */ 538 ahd_softc_insert(ahd); 539 ahd_list_unlock(&l); 540 541 /* complete the attach */ 542 ahd_attach(ahd); 543 } 544 545 int 546 ahd_activate(struct device *self, int act) 547 { 548 int ret = 0; 549 550 ret = config_activate_children(self, act); 551 552 switch (act) { 553 case DVACT_POWERDOWN: 554 ahd_shutdown(self); 555 break; 556 } 557 558 return (ret); 559 } 560 561 /* 562 * Perform some simple tests that should catch situations where 563 * our registers are invalidly mapped. 564 */ 565 int 566 ahd_pci_test_register_access(struct ahd_softc *ahd) 567 { 568 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 569 const pcitag_t tag = ahd->dev_softc->pa_tag; 570 pcireg_t cmd; 571 u_int targpcistat; 572 pcireg_t pci_status1; 573 int error; 574 uint8_t hcntrl; 575 576 error = EIO; 577 578 /* 579 * Enable PCI error interrupt status, but suppress NMIs 580 * generated by SERR raised due to target aborts. 581 */ 582 cmd = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 583 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 584 cmd & ~PCI_COMMAND_SERR_ENABLE); 585 586 /* 587 * First a simple test to see if any 588 * registers can be read. Reading 589 * HCNTRL has no side effects and has 590 * at least one bit that is guaranteed to 591 * be zero so it is a good register to 592 * use for this test. 593 */ 594 hcntrl = ahd_inb(ahd, HCNTRL); 595 if (hcntrl == 0xFF) 596 goto fail; 597 598 /* 599 * Next create a situation where write combining 600 * or read prefetching could be initiated by the 601 * CPU or host bridge. Our device does not support 602 * either, so look for data corruption and/or flaged 603 * PCI errors. First pause without causing another 604 * chip reset. 605 */ 606 hcntrl &= ~CHIPRST; 607 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 608 while (ahd_is_paused(ahd) == 0) 609 ; 610 611 /* Clear any PCI errors that occurred before our driver attached. */ 612 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 613 targpcistat = ahd_inb(ahd, TARGPCISTAT); 614 ahd_outb(ahd, TARGPCISTAT, targpcistat); 615 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 616 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1); 617 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 618 ahd_outb(ahd, CLRINT, CLRPCIINT); 619 620 ahd_outb(ahd, SEQCTL0, PERRORDIS); 621 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 622 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 623 goto fail; 624 625 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 626 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 627 targpcistat = ahd_inb(ahd, TARGPCISTAT); 628 if ((targpcistat & STA) != 0) 629 goto fail; 630 } 631 632 error = 0; 633 634 fail: 635 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 636 637 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 638 targpcistat = ahd_inb(ahd, TARGPCISTAT); 639 640 /* Silently clear any latched errors. */ 641 ahd_outb(ahd, TARGPCISTAT, targpcistat); 642 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 643 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1); 644 ahd_outb(ahd, CLRINT, CLRPCIINT); 645 } 646 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 647 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, cmd); 648 return (error); 649 } 650 651 /* 652 * Check the external port logic for a serial eeprom 653 * and termination/cable detection contrls. 654 */ 655 int 656 ahd_check_extport(struct ahd_softc *ahd) 657 { 658 struct vpd_config vpd; 659 struct seeprom_config *sc; 660 u_int adapter_control; 661 int have_seeprom; 662 int error; 663 664 sc = ahd->seep_config; 665 have_seeprom = ahd_acquire_seeprom(ahd); 666 if (have_seeprom) { 667 u_int start_addr; 668 669 /* 670 * Fetch VPD for this function and parse it. 671 */ 672 if (bootverbose) 673 printf("%s: Reading VPD from SEEPROM...", 674 ahd_name(ahd)); 675 676 /* Address is always in units of 16bit words */ 677 start_addr = ((2 * sizeof(*sc)) 678 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 679 680 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 681 start_addr, sizeof(vpd)/2, 682 /*bytestream*/TRUE); 683 if (error == 0) 684 error = ahd_parse_vpddata(ahd, &vpd); 685 if (bootverbose) 686 printf("%s: VPD parsing %s\n", 687 ahd_name(ahd), 688 error == 0 ? "successful" : "failed"); 689 690 if (bootverbose) 691 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 692 693 /* Address is always in units of 16bit words */ 694 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 695 696 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 697 start_addr, sizeof(*sc)/2, 698 /*bytestream*/FALSE); 699 700 if (error != 0) { 701 printf("Unable to read SEEPROM\n"); 702 have_seeprom = 0; 703 } else { 704 have_seeprom = ahd_verify_cksum(sc); 705 706 if (bootverbose) { 707 if (have_seeprom == 0) 708 printf ("checksum error\n"); 709 else 710 printf ("done.\n"); 711 } 712 } 713 ahd_release_seeprom(ahd); 714 } 715 716 if (!have_seeprom) { 717 u_int nvram_scb; 718 719 /* 720 * Pull scratch ram settings and treat them as 721 * if they are the contents of an seeprom if 722 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 723 * in SCB 0xFF. We manually compose the data as 16bit 724 * values to avoid endian issues. 725 */ 726 ahd_set_scbptr(ahd, 0xFF); 727 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 728 if (nvram_scb != 0xFF 729 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 730 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 731 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 732 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 733 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 734 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 735 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 736 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 737 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 738 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 739 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 740 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 741 uint16_t *sc_data; 742 int i; 743 744 ahd_set_scbptr(ahd, nvram_scb); 745 sc_data = (uint16_t *)sc; 746 for (i = 0; i < 64; i += 2) 747 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 748 have_seeprom = ahd_verify_cksum(sc); 749 if (have_seeprom) 750 ahd->flags |= AHD_SCB_CONFIG_USED; 751 } 752 } 753 754 #ifdef AHD_DEBUG 755 if (have_seeprom != 0 756 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 757 uint16_t *sc_data; 758 int i; 759 760 printf("%s: Seeprom Contents:", ahd_name(ahd)); 761 sc_data = (uint16_t *)sc; 762 for (i = 0; i < (sizeof(*sc)); i += 2) 763 printf("\n\t0x%.4x", sc_data[i]); 764 printf("\n"); 765 } 766 #endif 767 768 if (!have_seeprom) { 769 if (bootverbose) 770 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 771 ahd->flags |= AHD_USEDEFAULTS; 772 error = ahd_default_config(ahd); 773 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 774 free(ahd->seep_config, M_DEVBUF, 0); 775 ahd->seep_config = NULL; 776 } else { 777 error = ahd_parse_cfgdata(ahd, sc); 778 adapter_control = sc->adapter_control; 779 } 780 if (error != 0) 781 return (error); 782 783 ahd_configure_termination(ahd, adapter_control); 784 785 return (0); 786 } 787 788 void 789 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 790 { 791 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 792 const pcitag_t tag = ahd->dev_softc->pa_tag; 793 int error; 794 u_int sxfrctl1; 795 uint8_t termctl; 796 pcireg_t devconfig; 797 798 devconfig = pci_conf_read(pc, tag, DEVCONFIG); 799 devconfig &= ~STPWLEVEL; 800 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 801 devconfig |= STPWLEVEL; 802 if (bootverbose) 803 printf("%s: STPWLEVEL is %s\n", 804 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 805 pci_conf_write(pc, tag, DEVCONFIG, devconfig); 806 807 /* Make sure current sensing is off. */ 808 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 809 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 810 } 811 812 /* 813 * Read to sense. Write to set. 814 */ 815 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 816 if ((adapter_control & CFAUTOTERM) == 0) { 817 if (bootverbose) 818 printf("%s: Manual Primary Termination\n", 819 ahd_name(ahd)); 820 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 821 if ((adapter_control & CFSTERM) != 0) 822 termctl |= FLX_TERMCTL_ENPRILOW; 823 if ((adapter_control & CFWSTERM) != 0) 824 termctl |= FLX_TERMCTL_ENPRIHIGH; 825 } else if (error != 0) { 826 printf("%s: Primary Auto-Term Sensing failed! " 827 "Using Defaults.\n", ahd_name(ahd)); 828 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 829 } 830 831 if ((adapter_control & CFSEAUTOTERM) == 0) { 832 if (bootverbose) 833 printf("%s: Manual Secondary Termination\n", 834 ahd_name(ahd)); 835 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 836 if ((adapter_control & CFSELOWTERM) != 0) 837 termctl |= FLX_TERMCTL_ENSECLOW; 838 if ((adapter_control & CFSEHIGHTERM) != 0) 839 termctl |= FLX_TERMCTL_ENSECHIGH; 840 } else if (error != 0) { 841 printf("%s: Secondary Auto-Term Sensing failed! " 842 "Using Defaults.\n", ahd_name(ahd)); 843 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 844 } 845 846 /* 847 * Now set the termination based on what we found. 848 */ 849 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 850 ahd->flags &= ~AHD_TERM_ENB_A; 851 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 852 ahd->flags |= AHD_TERM_ENB_A; 853 sxfrctl1 |= STPWEN; 854 } 855 /* Must set the latch once in order to be effective. */ 856 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 857 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 858 859 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 860 if (error != 0) { 861 printf("%s: Unable to set termination settings!\n", 862 ahd_name(ahd)); 863 } else if (bootverbose) { 864 printf("%s: Primary High byte termination %sabled\n", 865 ahd_name(ahd), 866 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 867 868 printf("%s: Primary Low byte termination %sabled\n", 869 ahd_name(ahd), 870 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 871 872 printf("%s: Secondary High byte termination %sabled\n", 873 ahd_name(ahd), 874 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 875 876 printf("%s: Secondary Low byte termination %sabled\n", 877 ahd_name(ahd), 878 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 879 } 880 return; 881 } 882 883 #define DPE 0x80 884 #define SSE 0x40 885 #define RMA 0x20 886 #define RTA 0x10 887 #define STA 0x08 888 #define DPR 0x01 889 890 static const char *split_status_source[] = 891 { 892 "DFF0", 893 "DFF1", 894 "OVLY", 895 "CMC", 896 }; 897 898 static const char *pci_status_source[] = 899 { 900 "DFF0", 901 "DFF1", 902 "SG", 903 "CMC", 904 "OVLY", 905 "NONE", 906 "MSI", 907 "TARG" 908 }; 909 910 static const char *split_status_strings[] = 911 { 912 "Received split response", 913 "Received split completion error message", 914 "Receive overrun", 915 "Count not complete", 916 "Split completion data bucket", 917 "Split completion address error", 918 "Split completion byte count error", 919 "Signaled Target-abort to early terminate a split" 920 }; 921 922 static const char *pci_status_strings[] = 923 { 924 "Data Parity Error has been reported via PERR#", 925 "Target initial wait state error", 926 "Split completion read data parity error", 927 "Split completion address attribute parity error", 928 "Received a Target Abort", 929 "Received a Master Abort", 930 "Signal System Error Detected", 931 "Address or Write Phase Parity Error Detected" 932 }; 933 934 void 935 ahd_pci_intr(struct ahd_softc *ahd) 936 { 937 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 938 const pcitag_t tag = ahd->dev_softc->pa_tag; 939 uint8_t pci_status[8]; 940 ahd_mode_state saved_modes; 941 pcireg_t pci_status1; 942 u_int intstat; 943 u_int i; 944 u_int reg; 945 946 intstat = ahd_inb(ahd, INTSTAT); 947 948 if ((intstat & SPLTINT) != 0) 949 ahd_pci_split_intr(ahd, intstat); 950 951 if ((intstat & PCIINT) == 0) 952 return; 953 954 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 955 saved_modes = ahd_save_modes(ahd); 956 ahd_dump_card_state(ahd); 957 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 958 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 959 960 if (i == 5) 961 continue; 962 pci_status[i] = ahd_inb(ahd, reg); 963 /* Clear latched errors. So our interrupt deasserts. */ 964 ahd_outb(ahd, reg, pci_status[i]); 965 } 966 967 for (i = 0; i < 8; i++) { 968 u_int bit; 969 970 if (i == 5) 971 continue; 972 973 for (bit = 0; bit < 8; bit++) { 974 975 if ((pci_status[i] & (0x1 << bit)) != 0) { 976 if (i == 7/*TARG*/ && bit == 3) 977 printf("%s: Signaled Target Abort\n", 978 ahd_name(ahd)); 979 else 980 printf("%s: %s in %s\n", ahd_name(ahd), 981 pci_status_strings[bit], 982 pci_status_source[i]); 983 } 984 } 985 } 986 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 987 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1); 988 989 ahd_restore_modes(ahd, saved_modes); 990 ahd_outb(ahd, CLRINT, CLRPCIINT); 991 ahd_unpause(ahd); 992 993 return; 994 } 995 996 void 997 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 998 { 999 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 1000 const pcitag_t tag = ahd->dev_softc->pa_tag; 1001 uint8_t split_status[4]; 1002 uint8_t split_status1[4]; 1003 uint8_t sg_split_status[2]; 1004 uint8_t sg_split_status1[2]; 1005 ahd_mode_state saved_modes; 1006 u_int i; 1007 pcireg_t pcix_status; 1008 1009 /* 1010 * Check for splits in all modes. Modes 0 and 1 1011 * additionally have SG engine splits to look at. 1012 */ 1013 pcix_status = pci_conf_read(pc, tag, ahd->pcix_off + 0x04); 1014 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1015 ahd_name(ahd), pcix_status); 1016 1017 saved_modes = ahd_save_modes(ahd); 1018 for (i = 0; i < 4; i++) { 1019 ahd_set_modes(ahd, i, i); 1020 1021 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1022 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1023 /* Clear latched errors. So our interrupt deasserts. */ 1024 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1025 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1026 if (i > 1) 1027 continue; 1028 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1029 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1030 /* Clear latched errors. So our interrupt deasserts. */ 1031 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1032 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1033 } 1034 1035 for (i = 0; i < 4; i++) { 1036 u_int bit; 1037 1038 for (bit = 0; bit < 8; bit++) { 1039 1040 if ((split_status[i] & (0x1 << bit)) != 0) { 1041 printf("%s: %s in %s\n", ahd_name(ahd), 1042 split_status_strings[bit], 1043 split_status_source[i]); 1044 } 1045 1046 if (i > 1) 1047 continue; 1048 1049 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1050 printf("%s: %s in %s\n", ahd_name(ahd), 1051 split_status_strings[bit], "SG"); 1052 } 1053 } 1054 } 1055 /* 1056 * Clear PCI-X status bits. 1057 */ 1058 pci_conf_write(pc, tag, ahd->pcix_off + 0x04, pcix_status); 1059 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1060 ahd_restore_modes(ahd, saved_modes); 1061 } 1062 1063 int 1064 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1065 { 1066 1067 ahd->chip = AHD_AIC7901; 1068 ahd->features = AHD_AIC7901_FE; 1069 return (ahd_aic790X_setup(ahd, pa)); 1070 } 1071 1072 int 1073 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1074 { 1075 1076 ahd->chip = AHD_AIC7901A; 1077 ahd->features = AHD_AIC7901A_FE; 1078 return (ahd_aic790X_setup(ahd, pa)); 1079 } 1080 1081 int 1082 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1083 { 1084 ahd->chip = AHD_AIC7902; 1085 ahd->features = AHD_AIC7902_FE; 1086 return (ahd_aic790X_setup(ahd, pa)); 1087 } 1088 1089 int 1090 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1091 { 1092 u_int rev; 1093 1094 rev = PCI_REVISION(pa->pa_class); 1095 #ifdef AHD_DEBUG 1096 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1097 #endif 1098 if (rev < ID_AIC7902_PCI_REV_A4) { 1099 printf("%s: Unable to attach to unsupported chip revision %d\n", 1100 ahd_name(ahd), rev); 1101 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1102 return (ENXIO); 1103 } 1104 1105 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1106 if (rev < ID_AIC7902_PCI_REV_B0) { 1107 /* 1108 * Enable A series workarounds. 1109 */ 1110 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1111 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1112 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1113 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1114 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1115 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1116 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1117 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1118 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1119 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1120 | AHD_FAINT_LED_BUG; 1121 1122 /* 1123 * IO Cell parameter setup. 1124 */ 1125 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1126 1127 if ((ahd->flags & AHD_HP_BOARD) == 0) 1128 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1129 } else { 1130 pcireg_t devconfig1; 1131 1132 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1133 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1134 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG 1135 | AHD_BUSFREEREV_BUG; 1136 1137 /* 1138 * Some issues have been resolved in the 7901B. 1139 */ 1140 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1141 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1142 1143 /* 1144 * IO Cell parameter setup. 1145 */ 1146 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1147 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1148 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1149 1150 /* 1151 * Set the PREQDIS bit for H2B which disables some workaround 1152 * that doesn't work on regular PCI busses. 1153 * XXX - Find out exactly what this does from the hardware 1154 * folks! 1155 */ 1156 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1157 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1158 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1159 } 1160 1161 return (0); 1162 } 1163