1 /* $OpenBSD: ahd_pci.c,v 1.20 2012/09/30 21:46:09 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Milos Urbanek, Kenneth R. Westerback & Marco Peereboom 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Product specific probe and attach routines for: 32 * aic7901 and aic7902 SCSI controllers 33 * 34 * Copyright (c) 1994-2001 Justin T. Gibbs. 35 * Copyright (c) 2000-2002 Adaptec Inc. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions, and the following disclaimer, 43 * without modification. 44 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 45 * substantially similar to the "NO WARRANTY" disclaimer below 46 * ("Disclaimer") and any redistribution must be conditioned upon 47 * including a substantially similar Disclaimer requirement for further 48 * binary redistribution. 49 * 3. Neither the names of the above-listed copyright holders nor the names 50 * of any contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * Alternatively, this software may be distributed under the terms of the 54 * GNU General Public License ("GPL") version 2 as published by the Free 55 * Software Foundation. 56 * 57 * NO WARRANTY 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 59 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 60 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 61 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 62 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 67 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGES. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 /* 74 __FBSDID("$FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.18 2004/02/04 16:38:38 gibbs Exp $"); 75 */ 76 77 #include <dev/ic/aic79xx_openbsd.h> 78 #include <dev/ic/aic79xx_inline.h> 79 #include <dev/ic/aic79xx.h> 80 81 #include <dev/pci/pcivar.h> 82 83 __inline uint64_t ahd_compose_id(u_int, u_int, u_int, u_int); 84 __inline uint64_t 85 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 86 { 87 uint64_t id; 88 89 id = subvendor 90 | (subdevice << 16) 91 | ((uint64_t)vendor << 32) 92 | ((uint64_t)device << 48); 93 94 return (id); 95 } 96 97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 98 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 99 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 100 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 101 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 102 103 #define ID_AIC7901 0x800F9005FFFF9005ull 104 #define ID_AHA_29320A 0x8000900500609005ull 105 #define ID_AHA_29320ALP 0x8017900500449005ull 106 #define ID_AHA_29320LPE 0x8017900500459005ull 107 108 #define ID_AIC7901A 0x801E9005FFFF9005ull 109 #define ID_AHA_29320LP 0x8014900500449005ull 110 111 #define ID_AIC7902 0x801F9005FFFF9005ull 112 #define ID_AIC7902_B 0x801D9005FFFF9005ull 113 #define ID_AHA_39320 0x8010900500409005ull 114 #define ID_AHA_29320 0x8012900500429005ull 115 #define ID_AHA_29320B 0x8013900500439005ull 116 #define ID_AHA_39320_B 0x8015900500409005ull 117 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 118 #define ID_AHA_39320A 0x8016900500409005ull 119 #define ID_AHA_39320D 0x8011900500419005ull 120 #define ID_AHA_39320D_B 0x801C900500419005ull 121 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 122 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 123 #define ID_AIC7902_PCI_REV_A4 0x3 124 #define ID_AIC7902_PCI_REV_B0 0x10 125 #define SUBID_HP 0x0E11 126 127 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 128 129 #define DEVID_9005_TYPE(id) ((id) & 0xF) 130 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 131 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 132 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 133 134 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 135 136 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 137 138 #define SUBID_9005_TYPE(id) ((id) & 0xF) 139 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 140 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 141 142 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 143 144 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 145 146 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 147 #define SUBID_9005_SEEPTYPE_NONE 0x0 148 #define SUBID_9005_SEEPTYPE_4K 0x1 149 150 ahd_device_setup_t ahd_aic7901_setup; 151 ahd_device_setup_t ahd_aic7901A_setup; 152 ahd_device_setup_t ahd_aic7902_setup; 153 ahd_device_setup_t ahd_aic790X_setup; 154 155 struct ahd_pci_identity ahd_pci_ident_table [] = 156 { 157 /* aic7901 based controllers */ 158 { 159 ID_AHA_29320A, 160 ID_ALL_MASK, 161 ahd_aic7901_setup 162 }, 163 { 164 ID_AHA_29320ALP, 165 ID_ALL_MASK, 166 ahd_aic7901_setup 167 }, 168 { 169 ID_AHA_29320LPE, 170 ID_ALL_MASK, 171 ahd_aic7901_setup 172 }, 173 /* aic7901A based controllers */ 174 { 175 ID_AHA_29320LP, 176 ID_ALL_MASK, 177 ahd_aic7901A_setup 178 }, 179 /* aic7902 based controllers */ 180 { 181 ID_AHA_29320, 182 ID_ALL_MASK, 183 ahd_aic7902_setup 184 }, 185 { 186 ID_AHA_29320B, 187 ID_ALL_MASK, 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320, 192 ID_ALL_MASK, 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320_B, 197 ID_ALL_MASK, 198 ahd_aic7902_setup 199 }, 200 { 201 ID_AHA_39320_B_DELL, 202 ID_ALL_MASK, 203 ahd_aic7902_setup 204 }, 205 { 206 ID_AHA_39320A, 207 ID_ALL_MASK, 208 ahd_aic7902_setup 209 }, 210 { 211 ID_AHA_39320D, 212 ID_ALL_MASK, 213 ahd_aic7902_setup 214 }, 215 { 216 ID_AHA_39320D_HP, 217 ID_ALL_MASK, 218 ahd_aic7902_setup 219 }, 220 { 221 ID_AHA_39320D_B, 222 ID_ALL_MASK, 223 ahd_aic7902_setup 224 }, 225 { 226 ID_AHA_39320D_B_HP, 227 ID_ALL_MASK, 228 ahd_aic7902_setup 229 }, 230 /* Generic chip probes for devices we don't know 'exactly' */ 231 { 232 ID_AIC7901 & ID_9005_GENERIC_MASK, 233 ID_9005_GENERIC_MASK, 234 ahd_aic7901_setup 235 }, 236 { 237 ID_AIC7901A & ID_DEV_VENDOR_MASK, 238 ID_DEV_VENDOR_MASK, 239 ahd_aic7901A_setup 240 }, 241 { 242 ID_AIC7902 & ID_9005_GENERIC_MASK, 243 ID_9005_GENERIC_MASK, 244 ahd_aic7902_setup 245 } 246 }; 247 248 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 249 250 #define DEVCONFIG 0x40 251 #define PCIXINITPAT 0x0000E000ul 252 #define PCIXINIT_PCI33_66 0x0000E000ul 253 #define PCIXINIT_PCIX50_66 0x0000C000ul 254 #define PCIXINIT_PCIX66_100 0x0000A000ul 255 #define PCIXINIT_PCIX100_133 0x00008000ul 256 #define PCI_BUS_MODES_INDEX(devconfig) \ 257 (((devconfig) & PCIXINITPAT) >> 13) 258 259 static const char *pci_bus_modes[] = 260 { 261 "PCI bus mode unknown", 262 "PCI bus mode unknown", 263 "PCI bus mode unknown", 264 "PCI bus mode unknown", 265 "PCI-X 101-133MHz", 266 "PCI-X 67-100MHz", 267 "PCI-X 50-66MHz", 268 "PCI 33 or 66MHz" 269 }; 270 271 #define TESTMODE 0x00000800ul 272 #define IRDY_RST 0x00000200ul 273 #define FRAME_RST 0x00000100ul 274 #define PCI64BIT 0x00000080ul 275 #define MRDCEN 0x00000040ul 276 #define ENDIANSEL 0x00000020ul 277 #define MIXQWENDIANEN 0x00000008ul 278 #define DACEN 0x00000004ul 279 #define STPWLEVEL 0x00000002ul 280 #define QWENDIANSEL 0x00000001ul 281 282 #define DEVCONFIG1 0x44 283 #define PREQDIS 0x01 284 285 #define CSIZE_LATTIME 0x0c 286 #define CACHESIZE 0x000000fful 287 #define LATTIME 0x0000ff00ul 288 289 int ahd_pci_probe(struct device *, void *, void *); 290 void ahd_pci_attach(struct device *, struct device *, void *); 291 292 struct cfattach ahd_pci_ca = { 293 sizeof(struct ahd_softc), ahd_pci_probe, ahd_pci_attach 294 }; 295 296 int ahd_check_extport(struct ahd_softc *ahd); 297 void ahd_configure_termination(struct ahd_softc *ahd, 298 u_int adapter_control); 299 void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 300 301 const struct ahd_pci_identity * 302 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 303 { 304 const struct ahd_pci_identity *entry; 305 u_int64_t full_id; 306 u_int i; 307 308 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 309 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 310 311 /* 312 * If we are configured to attach to HostRAID 313 * controllers, mask out the IROC/HostRAID bit 314 * in the 315 */ 316 if (ahd_attach_to_HostRAID_controllers) 317 full_id &= ID_ALL_IROC_MASK; 318 319 for (i = 0; i < ahd_num_pci_devs; i++) { 320 entry = &ahd_pci_ident_table[i]; 321 if (entry->full_id == (full_id & entry->id_mask)) { 322 return (entry); 323 } 324 } 325 return (NULL); 326 } 327 328 int 329 ahd_pci_probe(struct device *parent, void *match, void *aux) 330 { 331 const struct ahd_pci_identity *entry; 332 struct pci_attach_args *pa = aux; 333 pcireg_t subid; 334 335 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 336 entry = ahd_find_pci_device(pa->pa_id, subid); 337 return entry != NULL ? 1 : 0; 338 } 339 340 void 341 ahd_pci_attach(struct device *parent, struct device *self, void *aux) 342 { 343 const struct ahd_pci_identity *entry; 344 struct pci_attach_args *pa = aux; 345 struct ahd_softc *ahd = (void *)self; 346 pci_intr_handle_t ih; 347 const char *intrstr; 348 pcireg_t devconfig, memtype, subid; 349 uint16_t device, subvendor; 350 int error, ioh_valid, ioh2_valid, l, memh_valid; 351 352 ahd->dev_softc = pa; 353 ahd->parent_dmat = pa->pa_dmat; 354 355 if (ahd_alloc(ahd, ahd->sc_dev.dv_xname) == NULL) 356 return; 357 358 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 359 entry = ahd_find_pci_device(pa->pa_id, subid); 360 if (entry == NULL) 361 return; 362 363 /* 364 * Record if this is a HostRAID board. 365 */ 366 device = PCI_PRODUCT(pa->pa_id); 367 if (DEVID_9005_HOSTRAID(device)) 368 ahd->flags |= AHD_HOSTRAID_BOARD; 369 370 /* 371 * Record if this is an HP board. 372 */ 373 subvendor = PCI_VENDOR(subid); 374 if (subvendor == SUBID_HP) 375 ahd->flags |= AHD_HP_BOARD; 376 377 error = entry->setup(ahd, pa); 378 if (error != 0) 379 return; 380 381 /* XXX ahc on sparc64 needs this twice */ 382 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 383 384 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 385 ahd->chip |= AHD_PCI; 386 /* Disable PCIX workarounds when running in PCI mode. */ 387 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 388 } else { 389 ahd->chip |= AHD_PCIX; 390 } 391 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 392 393 memh_valid = ioh_valid = ioh2_valid = 0; 394 395 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 396 &ahd->pcix_off, NULL)) { 397 if (ahd->chip & AHD_PCIX) 398 printf("%s: warning: can't find PCI-X capability\n", 399 ahd_name(ahd)); 400 ahd->chip &= ~AHD_PCIX; 401 ahd->chip |= AHD_PCI; 402 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 403 } 404 405 /* 406 * Map PCI registers 407 */ 408 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 409 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 410 AHD_PCI_MEMADDR); 411 switch (memtype) { 412 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 413 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 414 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 415 memtype, 0, &ahd->tags[0], &ahd->bshs[0], NULL, 416 NULL, 0) == 0); 417 if (memh_valid) { 418 ahd->tags[1] = ahd->tags[0]; 419 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 420 /*offset*/0x100, /*size*/0x100, 421 &ahd->bshs[1]); 422 if (ahd_pci_test_register_access(ahd) != 0) 423 memh_valid = 0; 424 } 425 break; 426 default: 427 memh_valid = 0; 428 printf("%s: unknown memory type: 0x%x\n", 429 ahd_name(ahd), memtype); 430 break; 431 } 432 433 #ifdef AHD_DEBUG 434 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, shs0 " 435 "0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 436 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 437 #endif 438 } 439 440 if (!memh_valid) { 441 /* First BAR */ 442 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 443 PCI_MAPREG_TYPE_IO, 0, &ahd->tags[0], &ahd->bshs[0], NULL, 444 NULL, 0) == 0); 445 446 /* 2nd BAR */ 447 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 448 PCI_MAPREG_TYPE_IO, 0, &ahd->tags[1], &ahd->bshs[1], NULL, 449 NULL, 0) == 0); 450 451 #ifdef AHD_DEBUG 452 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, " 453 "shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], ahd->tags[1], 454 ahd->bshs[0], ahd->bshs[1]); 455 #endif 456 } 457 458 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 459 printf("%s: unable to map registers\n", ahd_name(ahd)); 460 return; 461 } 462 463 /* 464 * Set Power State D0. 465 */ 466 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 467 468 /* 469 * Should we bother disabling 39Bit addressing 470 * based on installed memory? 471 */ 472 if (sizeof(bus_addr_t) > 4) 473 ahd->flags |= AHD_39BIT_ADDRESSING; 474 475 /* 476 * If we need to support high memory, enable dual 477 * address cycles. This bit must be set to enable 478 * high address bit generation even if we are on a 479 * 64bit bus (PCI64BIT set in devconfig). 480 */ 481 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 482 if (bootverbose) 483 printf("%s: Enabling 39Bit Addressing\n", 484 ahd_name(ahd)); 485 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 486 devconfig |= DACEN; 487 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 488 } 489 490 ahd_softc_init(ahd); 491 492 /* 493 * Map the interrupts routines 494 */ 495 ahd->bus_intr = ahd_pci_intr; 496 497 error = ahd_reset(ahd, /*reinit*/FALSE); 498 if (error != 0) { 499 ahd_free(ahd); 500 return; 501 } 502 503 if (pci_intr_map(pa, &ih)) { 504 printf("%s: couldn't map interrupt\n", ahd_name(ahd)); 505 ahd_free(ahd); 506 return; 507 } 508 intrstr = pci_intr_string(pa->pa_pc, ih); 509 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 510 ahd_platform_intr, ahd, ahd->sc_dev.dv_xname); 511 if (ahd->ih == NULL) { 512 printf("%s: couldn't establish interrupt", ahd_name(ahd)); 513 if (intrstr != NULL) 514 printf(" at %s", intrstr); 515 printf("\n"); 516 ahd_free(ahd); 517 return; 518 } 519 if (intrstr != NULL) 520 printf(": %s\n", intrstr); 521 522 /* Get the size of the cache */ 523 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 524 ahd->pci_cachesize *= 4; 525 526 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 527 /* See if we have a SEEPROM and perform auto-term */ 528 error = ahd_check_extport(ahd); 529 if (error != 0) 530 return; 531 532 /* Core initialization */ 533 error = ahd_init(ahd); 534 if (error != 0) 535 return; 536 537 ahd_list_lock(&l); 538 /* 539 * Link this softc in with all other ahd instances. 540 */ 541 ahd_softc_insert(ahd); 542 ahd_list_unlock(&l); 543 544 /* complete the attach */ 545 ahd_attach(ahd); 546 } 547 548 /* 549 * Perform some simple tests that should catch situations where 550 * our registers are invalidly mapped. 551 */ 552 int 553 ahd_pci_test_register_access(struct ahd_softc *ahd) 554 { 555 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 556 const pcitag_t tag = ahd->dev_softc->pa_tag; 557 pcireg_t cmd; 558 u_int targpcistat; 559 pcireg_t pci_status1; 560 int error; 561 uint8_t hcntrl; 562 563 error = EIO; 564 565 /* 566 * Enable PCI error interrupt status, but suppress NMIs 567 * generated by SERR raised due to target aborts. 568 */ 569 cmd = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 570 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 571 cmd & ~PCI_COMMAND_SERR_ENABLE); 572 573 /* 574 * First a simple test to see if any 575 * registers can be read. Reading 576 * HCNTRL has no side effects and has 577 * at least one bit that is guaranteed to 578 * be zero so it is a good register to 579 * use for this test. 580 */ 581 hcntrl = ahd_inb(ahd, HCNTRL); 582 if (hcntrl == 0xFF) 583 goto fail; 584 585 /* 586 * Next create a situation where write combining 587 * or read prefetching could be initiated by the 588 * CPU or host bridge. Our device does not support 589 * either, so look for data corruption and/or flaged 590 * PCI errors. First pause without causing another 591 * chip reset. 592 */ 593 hcntrl &= ~CHIPRST; 594 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 595 while (ahd_is_paused(ahd) == 0) 596 ; 597 598 /* Clear any PCI errors that occurred before our driver attached. */ 599 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 600 targpcistat = ahd_inb(ahd, TARGPCISTAT); 601 ahd_outb(ahd, TARGPCISTAT, targpcistat); 602 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 603 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1); 604 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 605 ahd_outb(ahd, CLRINT, CLRPCIINT); 606 607 ahd_outb(ahd, SEQCTL0, PERRORDIS); 608 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 609 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 610 goto fail; 611 612 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 613 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 614 targpcistat = ahd_inb(ahd, TARGPCISTAT); 615 if ((targpcistat & STA) != 0) 616 goto fail; 617 } 618 619 error = 0; 620 621 fail: 622 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 623 624 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 625 targpcistat = ahd_inb(ahd, TARGPCISTAT); 626 627 /* Silently clear any latched errors. */ 628 ahd_outb(ahd, TARGPCISTAT, targpcistat); 629 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 630 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1); 631 ahd_outb(ahd, CLRINT, CLRPCIINT); 632 } 633 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 634 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, cmd); 635 return (error); 636 } 637 638 /* 639 * Check the external port logic for a serial eeprom 640 * and termination/cable detection contrls. 641 */ 642 int 643 ahd_check_extport(struct ahd_softc *ahd) 644 { 645 struct vpd_config vpd; 646 struct seeprom_config *sc; 647 u_int adapter_control; 648 int have_seeprom; 649 int error; 650 651 sc = ahd->seep_config; 652 have_seeprom = ahd_acquire_seeprom(ahd); 653 if (have_seeprom) { 654 u_int start_addr; 655 656 /* 657 * Fetch VPD for this function and parse it. 658 */ 659 if (bootverbose) 660 printf("%s: Reading VPD from SEEPROM...", 661 ahd_name(ahd)); 662 663 /* Address is always in units of 16bit words */ 664 start_addr = ((2 * sizeof(*sc)) 665 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 666 667 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 668 start_addr, sizeof(vpd)/2, 669 /*bytestream*/TRUE); 670 if (error == 0) 671 error = ahd_parse_vpddata(ahd, &vpd); 672 if (bootverbose) 673 printf("%s: VPD parsing %s\n", 674 ahd_name(ahd), 675 error == 0 ? "successful" : "failed"); 676 677 if (bootverbose) 678 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 679 680 /* Address is always in units of 16bit words */ 681 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 682 683 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 684 start_addr, sizeof(*sc)/2, 685 /*bytestream*/FALSE); 686 687 if (error != 0) { 688 printf("Unable to read SEEPROM\n"); 689 have_seeprom = 0; 690 } else { 691 have_seeprom = ahd_verify_cksum(sc); 692 693 if (bootverbose) { 694 if (have_seeprom == 0) 695 printf ("checksum error\n"); 696 else 697 printf ("done.\n"); 698 } 699 } 700 ahd_release_seeprom(ahd); 701 } 702 703 if (!have_seeprom) { 704 u_int nvram_scb; 705 706 /* 707 * Pull scratch ram settings and treat them as 708 * if they are the contents of an seeprom if 709 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 710 * in SCB 0xFF. We manually compose the data as 16bit 711 * values to avoid endian issues. 712 */ 713 ahd_set_scbptr(ahd, 0xFF); 714 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 715 if (nvram_scb != 0xFF 716 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 717 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 718 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 719 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 720 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 721 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 722 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 723 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 724 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 725 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 726 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 727 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 728 uint16_t *sc_data; 729 int i; 730 731 ahd_set_scbptr(ahd, nvram_scb); 732 sc_data = (uint16_t *)sc; 733 for (i = 0; i < 64; i += 2) 734 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 735 have_seeprom = ahd_verify_cksum(sc); 736 if (have_seeprom) 737 ahd->flags |= AHD_SCB_CONFIG_USED; 738 } 739 } 740 741 #ifdef AHD_DEBUG 742 if (have_seeprom != 0 743 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 744 uint16_t *sc_data; 745 int i; 746 747 printf("%s: Seeprom Contents:", ahd_name(ahd)); 748 sc_data = (uint16_t *)sc; 749 for (i = 0; i < (sizeof(*sc)); i += 2) 750 printf("\n\t0x%.4x", sc_data[i]); 751 printf("\n"); 752 } 753 #endif 754 755 if (!have_seeprom) { 756 if (bootverbose) 757 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 758 ahd->flags |= AHD_USEDEFAULTS; 759 error = ahd_default_config(ahd); 760 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 761 free(ahd->seep_config, M_DEVBUF); 762 ahd->seep_config = NULL; 763 } else { 764 error = ahd_parse_cfgdata(ahd, sc); 765 adapter_control = sc->adapter_control; 766 } 767 if (error != 0) 768 return (error); 769 770 ahd_configure_termination(ahd, adapter_control); 771 772 return (0); 773 } 774 775 void 776 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 777 { 778 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 779 const pcitag_t tag = ahd->dev_softc->pa_tag; 780 int error; 781 u_int sxfrctl1; 782 uint8_t termctl; 783 pcireg_t devconfig; 784 785 devconfig = pci_conf_read(pc, tag, DEVCONFIG); 786 devconfig &= ~STPWLEVEL; 787 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 788 devconfig |= STPWLEVEL; 789 if (bootverbose) 790 printf("%s: STPWLEVEL is %s\n", 791 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 792 pci_conf_write(pc, tag, DEVCONFIG, devconfig); 793 794 /* Make sure current sensing is off. */ 795 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 796 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 797 } 798 799 /* 800 * Read to sense. Write to set. 801 */ 802 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 803 if ((adapter_control & CFAUTOTERM) == 0) { 804 if (bootverbose) 805 printf("%s: Manual Primary Termination\n", 806 ahd_name(ahd)); 807 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 808 if ((adapter_control & CFSTERM) != 0) 809 termctl |= FLX_TERMCTL_ENPRILOW; 810 if ((adapter_control & CFWSTERM) != 0) 811 termctl |= FLX_TERMCTL_ENPRIHIGH; 812 } else if (error != 0) { 813 printf("%s: Primary Auto-Term Sensing failed! " 814 "Using Defaults.\n", ahd_name(ahd)); 815 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 816 } 817 818 if ((adapter_control & CFSEAUTOTERM) == 0) { 819 if (bootverbose) 820 printf("%s: Manual Secondary Termination\n", 821 ahd_name(ahd)); 822 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 823 if ((adapter_control & CFSELOWTERM) != 0) 824 termctl |= FLX_TERMCTL_ENSECLOW; 825 if ((adapter_control & CFSEHIGHTERM) != 0) 826 termctl |= FLX_TERMCTL_ENSECHIGH; 827 } else if (error != 0) { 828 printf("%s: Secondary Auto-Term Sensing failed! " 829 "Using Defaults.\n", ahd_name(ahd)); 830 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 831 } 832 833 /* 834 * Now set the termination based on what we found. 835 */ 836 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 837 ahd->flags &= ~AHD_TERM_ENB_A; 838 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 839 ahd->flags |= AHD_TERM_ENB_A; 840 sxfrctl1 |= STPWEN; 841 } 842 /* Must set the latch once in order to be effective. */ 843 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 844 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 845 846 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 847 if (error != 0) { 848 printf("%s: Unable to set termination settings!\n", 849 ahd_name(ahd)); 850 } else if (bootverbose) { 851 printf("%s: Primary High byte termination %sabled\n", 852 ahd_name(ahd), 853 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 854 855 printf("%s: Primary Low byte termination %sabled\n", 856 ahd_name(ahd), 857 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 858 859 printf("%s: Secondary High byte termination %sabled\n", 860 ahd_name(ahd), 861 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 862 863 printf("%s: Secondary Low byte termination %sabled\n", 864 ahd_name(ahd), 865 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 866 } 867 return; 868 } 869 870 #define DPE 0x80 871 #define SSE 0x40 872 #define RMA 0x20 873 #define RTA 0x10 874 #define STA 0x08 875 #define DPR 0x01 876 877 static const char *split_status_source[] = 878 { 879 "DFF0", 880 "DFF1", 881 "OVLY", 882 "CMC", 883 }; 884 885 static const char *pci_status_source[] = 886 { 887 "DFF0", 888 "DFF1", 889 "SG", 890 "CMC", 891 "OVLY", 892 "NONE", 893 "MSI", 894 "TARG" 895 }; 896 897 static const char *split_status_strings[] = 898 { 899 "%s: Received split response in %s.\n", 900 "%s: Received split completion error message in %s\n", 901 "%s: Receive overrun in %s\n", 902 "%s: Count not complete in %s\n", 903 "%s: Split completion data bucket in %s\n", 904 "%s: Split completion address error in %s\n", 905 "%s: Split completion byte count error in %s\n", 906 "%s: Signaled Target-abort to early terminate a split in %s\n" 907 }; 908 909 static const char *pci_status_strings[] = 910 { 911 "%s: Data Parity Error has been reported via PERR# in %s\n", 912 "%s: Target initial wait state error in %s\n", 913 "%s: Split completion read data parity error in %s\n", 914 "%s: Split completion address attribute parity error in %s\n", 915 "%s: Received a Target Abort in %s\n", 916 "%s: Received a Master Abort in %s\n", 917 "%s: Signal System Error Detected in %s\n", 918 "%s: Address or Write Phase Parity Error Detected in %s.\n" 919 }; 920 921 void 922 ahd_pci_intr(struct ahd_softc *ahd) 923 { 924 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 925 const pcitag_t tag = ahd->dev_softc->pa_tag; 926 uint8_t pci_status[8]; 927 ahd_mode_state saved_modes; 928 pcireg_t pci_status1; 929 u_int intstat; 930 u_int i; 931 u_int reg; 932 933 intstat = ahd_inb(ahd, INTSTAT); 934 935 if ((intstat & SPLTINT) != 0) 936 ahd_pci_split_intr(ahd, intstat); 937 938 if ((intstat & PCIINT) == 0) 939 return; 940 941 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 942 saved_modes = ahd_save_modes(ahd); 943 ahd_dump_card_state(ahd); 944 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 945 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 946 947 if (i == 5) 948 continue; 949 pci_status[i] = ahd_inb(ahd, reg); 950 /* Clear latched errors. So our interrupt deasserts. */ 951 ahd_outb(ahd, reg, pci_status[i]); 952 } 953 954 for (i = 0; i < 8; i++) { 955 u_int bit; 956 957 if (i == 5) 958 continue; 959 960 for (bit = 0; bit < 8; bit++) { 961 962 if ((pci_status[i] & (0x1 << bit)) != 0) { 963 static const char *s; 964 965 s = pci_status_strings[bit]; 966 if (i == 7/*TARG*/ && bit == 3) 967 s = "%s: Signaled Target Abort\n"; 968 printf(s, ahd_name(ahd), pci_status_source[i]); 969 } 970 } 971 } 972 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 973 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1); 974 975 ahd_restore_modes(ahd, saved_modes); 976 ahd_outb(ahd, CLRINT, CLRPCIINT); 977 ahd_unpause(ahd); 978 979 return; 980 } 981 982 void 983 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 984 { 985 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 986 const pcitag_t tag = ahd->dev_softc->pa_tag; 987 uint8_t split_status[4]; 988 uint8_t split_status1[4]; 989 uint8_t sg_split_status[2]; 990 uint8_t sg_split_status1[2]; 991 ahd_mode_state saved_modes; 992 u_int i; 993 pcireg_t pcix_status; 994 995 /* 996 * Check for splits in all modes. Modes 0 and 1 997 * additionally have SG engine splits to look at. 998 */ 999 pcix_status = pci_conf_read(pc, tag, ahd->pcix_off + 0x04); 1000 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1001 ahd_name(ahd), pcix_status); 1002 1003 saved_modes = ahd_save_modes(ahd); 1004 for (i = 0; i < 4; i++) { 1005 ahd_set_modes(ahd, i, i); 1006 1007 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1008 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1009 /* Clear latched errors. So our interrupt deasserts. */ 1010 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1011 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1012 if (i > 1) 1013 continue; 1014 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1015 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1016 /* Clear latched errors. So our interrupt deasserts. */ 1017 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1018 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1019 } 1020 1021 for (i = 0; i < 4; i++) { 1022 u_int bit; 1023 1024 for (bit = 0; bit < 8; bit++) { 1025 1026 if ((split_status[i] & (0x1 << bit)) != 0) { 1027 static const char *s; 1028 1029 s = split_status_strings[bit]; 1030 printf(s, ahd_name(ahd), 1031 split_status_source[i]); 1032 } 1033 1034 if (i > 1) 1035 continue; 1036 1037 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1038 static const char *s; 1039 1040 s = split_status_strings[bit]; 1041 printf(s, ahd_name(ahd), "SG"); 1042 } 1043 } 1044 } 1045 /* 1046 * Clear PCI-X status bits. 1047 */ 1048 pci_conf_write(pc, tag, ahd->pcix_off + 0x04, pcix_status); 1049 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1050 ahd_restore_modes(ahd, saved_modes); 1051 } 1052 1053 int 1054 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1055 { 1056 1057 ahd->chip = AHD_AIC7901; 1058 ahd->features = AHD_AIC7901_FE; 1059 return (ahd_aic790X_setup(ahd, pa)); 1060 } 1061 1062 int 1063 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1064 { 1065 1066 ahd->chip = AHD_AIC7901A; 1067 ahd->features = AHD_AIC7901A_FE; 1068 return (ahd_aic790X_setup(ahd, pa)); 1069 } 1070 1071 int 1072 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1073 { 1074 ahd->chip = AHD_AIC7902; 1075 ahd->features = AHD_AIC7902_FE; 1076 return (ahd_aic790X_setup(ahd, pa)); 1077 } 1078 1079 int 1080 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1081 { 1082 u_int rev; 1083 1084 rev = PCI_REVISION(pa->pa_class); 1085 #ifdef AHD_DEBUG 1086 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1087 #endif 1088 if (rev < ID_AIC7902_PCI_REV_A4) { 1089 printf("%s: Unable to attach to unsupported chip revision %d\n", 1090 ahd_name(ahd), rev); 1091 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1092 return (ENXIO); 1093 } 1094 1095 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1096 if (rev < ID_AIC7902_PCI_REV_B0) { 1097 /* 1098 * Enable A series workarounds. 1099 */ 1100 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1101 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1102 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1103 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1104 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1105 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1106 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1107 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1108 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1109 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1110 | AHD_FAINT_LED_BUG; 1111 1112 /* 1113 * IO Cell parameter setup. 1114 */ 1115 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1116 1117 if ((ahd->flags & AHD_HP_BOARD) == 0) 1118 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1119 } else { 1120 pcireg_t devconfig1; 1121 1122 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1123 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1124 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG 1125 | AHD_BUSFREEREV_BUG; 1126 1127 /* 1128 * Some issues have been resolved in the 7901B. 1129 */ 1130 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1131 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1132 1133 /* 1134 * IO Cell parameter setup. 1135 */ 1136 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1137 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1138 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1139 1140 /* 1141 * Set the PREQDIS bit for H2B which disables some workaround 1142 * that doesn't work on regular PCI busses. 1143 * XXX - Find out exactly what this does from the hardware 1144 * folks! 1145 */ 1146 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1147 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1148 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1149 } 1150 1151 return (0); 1152 } 1153