1 /* $OpenBSD: cs4280.c,v 1.45 2014/07/12 18:48:51 tedu Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 79 #include <sys/audioio.h> 80 #include <dev/audio_if.h> 81 #include <dev/midi_if.h> 82 #include <dev/mulaw.h> 83 #include <dev/auconv.h> 84 85 #include <dev/ic/ac97.h> 86 87 #include <machine/bus.h> 88 89 #define CSCC_PCI_BA0 0x10 90 #define CSCC_PCI_BA1 0x14 91 92 struct cs4280_dma { 93 bus_dmamap_t map; 94 caddr_t addr; /* real dma buffer */ 95 caddr_t dum; /* dummy buffer for audio driver */ 96 bus_dma_segment_t segs[1]; 97 int nsegs; 98 size_t size; 99 struct cs4280_dma *next; 100 }; 101 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 102 #define BUFADDR(p) ((void *)((p)->dum)) 103 #define KERNADDR(p) ((void *)((p)->addr)) 104 105 /* 106 * Software state 107 */ 108 struct cs4280_softc { 109 struct device sc_dev; 110 111 pci_intr_handle_t * sc_ih; 112 113 /* I/O (BA0) */ 114 bus_space_tag_t ba0t; 115 bus_space_handle_t ba0h; 116 117 /* BA1 */ 118 bus_space_tag_t ba1t; 119 bus_space_handle_t ba1h; 120 121 /* DMA */ 122 bus_dma_tag_t sc_dmatag; 123 struct cs4280_dma *sc_dmas; 124 125 void (*sc_pintr)(void *); /* dma completion intr handler */ 126 void *sc_parg; /* arg for sc_intr() */ 127 char *sc_ps, *sc_pe, *sc_pn; 128 int sc_pcount; 129 int sc_pi; 130 struct cs4280_dma *sc_pdma; 131 char *sc_pbuf; 132 #ifdef DIAGNOSTIC 133 char sc_prun; 134 #endif 135 136 void (*sc_rintr)(void *); /* dma completion intr handler */ 137 void *sc_rarg; /* arg for sc_intr() */ 138 char *sc_rs, *sc_re, *sc_rn; 139 int sc_rcount; 140 int sc_ri; 141 struct cs4280_dma *sc_rdma; 142 char *sc_rbuf; 143 int sc_rparam; /* record format */ 144 #ifdef DIAGNOSTIC 145 char sc_rrun; 146 #endif 147 148 #if NMIDI > 0 149 void (*sc_iintr)(void *, int); /* midi input ready handler */ 150 void (*sc_ointr)(void *); /* midi output ready handler */ 151 void *sc_arg; 152 #endif 153 154 u_int32_t pctl; 155 u_int32_t cctl; 156 157 struct ac97_codec_if *codec_if; 158 struct ac97_host_if host_if; 159 160 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 161 }; 162 163 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 164 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 165 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 166 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 167 168 int cs4280_match(struct device *, void *, void *); 169 void cs4280_attach(struct device *, struct device *, void *); 170 int cs4280_activate(struct device *, int); 171 void cs4280_attachhook(void *xsc); 172 int cs4280_intr(void *); 173 void cs4280_reset(void *); 174 int cs4280_download_image(struct cs4280_softc *); 175 176 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 177 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 178 struct cs4280_dma *); 179 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 180 181 #ifdef CS4280_DEBUG 182 int cs4280_check_images(struct cs4280_softc *); 183 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 184 u_int32_t); 185 #endif 186 187 struct cfdriver clcs_cd = { 188 NULL, "clcs", DV_DULL 189 }; 190 191 struct cfattach clcs_ca = { 192 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach, NULL, 193 cs4280_activate 194 }; 195 196 int cs4280_init(struct cs4280_softc *, int); 197 int cs4280_init2(struct cs4280_softc *, int); 198 int cs4280_open(void *, int); 199 void cs4280_close(void *); 200 201 int cs4280_query_encoding(void *, struct audio_encoding *); 202 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 203 int cs4280_round_blocksize(void *, int); 204 void cs4280_get_default_params(void *, int, struct audio_params *); 205 206 int cs4280_halt_output(void *); 207 int cs4280_halt_input(void *); 208 209 int cs4280_getdev(void *, struct audio_device *); 210 211 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 212 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 213 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 214 void *cs4280_malloc(void *, int, size_t, int, int); 215 void cs4280_free(void *, void *, int); 216 size_t cs4280_round_buffersize(void *, int, size_t); 217 paddr_t cs4280_mappage(void *, void *, off_t, int); 218 int cs4280_get_props(void *); 219 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 220 void *, struct audio_params *); 221 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *); 223 224 225 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 226 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 227 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 228 char *); 229 int cs4280_src_wait(struct cs4280_softc *); 230 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 231 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 232 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 233 void cs4280_reset_codec(void *sc); 234 235 void cs4280_clear_fifos(struct cs4280_softc *); 236 237 #if NMIDI > 0 238 void cs4280_midi_close(void *); 239 void cs4280_midi_getinfo(void *, struct midi_info *); 240 int cs4280_midi_open(void *, int, void (*)(void *, int), 241 void (*)(void *), void *); 242 int cs4280_midi_output(void *, int); 243 #endif 244 245 struct audio_hw_if cs4280_hw_if = { 246 cs4280_open, 247 cs4280_close, 248 NULL, 249 cs4280_query_encoding, 250 cs4280_set_params, 251 cs4280_round_blocksize, 252 NULL, 253 NULL, 254 NULL, 255 NULL, 256 NULL, 257 cs4280_halt_output, 258 cs4280_halt_input, 259 NULL, 260 cs4280_getdev, 261 NULL, 262 cs4280_mixer_set_port, 263 cs4280_mixer_get_port, 264 cs4280_query_devinfo, 265 cs4280_malloc, 266 cs4280_free, 267 cs4280_round_buffersize, 268 0, /* cs4280_mappage, */ 269 cs4280_get_props, 270 cs4280_trigger_output, 271 cs4280_trigger_input, 272 cs4280_get_default_params 273 }; 274 275 #if NMIDI > 0 276 struct midi_hw_if cs4280_midi_hw_if = { 277 cs4280_midi_open, 278 cs4280_midi_close, 279 cs4280_midi_output, 280 0, /* flush */ 281 cs4280_midi_getinfo, 282 0, /* ioctl */ 283 }; 284 #endif 285 286 287 288 struct audio_device cs4280_device = { 289 "CS4280", 290 "", 291 "cs4280" 292 }; 293 294 const struct pci_matchid cs4280_devices[] = { 295 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 296 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 297 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 298 }; 299 300 int 301 cs4280_match(struct device *parent, void *ma, void *aux) 302 { 303 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 304 nitems(cs4280_devices))); 305 } 306 307 int 308 cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) 309 { 310 struct cs4280_softc *sc = sc_; 311 int n; 312 313 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 314 /* 315 * Make sure that there is not data sitting around from a preivous 316 * uncompleted access. 317 */ 318 BA0READ4(sc, CS4280_ACSDA); 319 320 /* Set up AC97 control registers. */ 321 BA0WRITE4(sc, CS4280_ACCAD, add); 322 BA0WRITE4(sc, CS4280_ACCDA, 0); 323 BA0WRITE4(sc, CS4280_ACCTL, 324 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 325 326 if (cs4280_src_wait(sc) < 0) { 327 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 328 sc->sc_dev.dv_xname, add); 329 return (1); 330 } 331 332 /* wait for valid status bit is active */ 333 n = 0; 334 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 335 delay(1); 336 while (++n > 1000) { 337 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 338 sc->sc_dev.dv_xname, add); 339 return (1); 340 } 341 } 342 *data = BA0READ4(sc, CS4280_ACSDA); 343 DPRINTFN(5,("data=0x%04x\n", *data)); 344 return (0); 345 } 346 347 int 348 cs4280_write_codec(void *sc_, u_int8_t add, u_int16_t data) 349 { 350 struct cs4280_softc *sc = sc_; 351 352 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 353 BA0WRITE4(sc, CS4280_ACCAD, add); 354 BA0WRITE4(sc, CS4280_ACCDA, data); 355 BA0WRITE4(sc, CS4280_ACCTL, 356 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 357 358 if (cs4280_src_wait(sc) < 0) { 359 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 360 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 361 return (1); 362 } 363 return (0); 364 } 365 366 int 367 cs4280_src_wait(struct cs4280_softc *sc) 368 { 369 int n; 370 371 n = 0; 372 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 373 delay(1000); 374 if (++n > 1000) 375 return (-1); 376 } 377 return (0); 378 } 379 380 381 void 382 cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) 383 { 384 /* calculate capture rate: 385 * 386 * capture_coefficient_increment = -round(rate*128*65536/48000; 387 * capture_phase_increment = floor(48000*65536*1024/rate); 388 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 389 * cy = floor(cx/200); 390 * capture_sample_rate_correction = cx - 200*cy; 391 * capture_delay = ceil(24*48000/rate); 392 * capture_num_triplets = floor(65536*rate/24000); 393 * capture_group_length = 24000/GCD(rate, 24000); 394 * where GCD means "Greatest Common Divisor". 395 * 396 * capture_coefficient_increment, capture_phase_increment and 397 * capture_num_triplets are 32-bit signed quantities. 398 * capture_sample_rate_correction and capture_group_length are 399 * 16-bit signed quantities. 400 * capture_delay is a 14-bit unsigned quantity. 401 */ 402 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 403 u_int16_t csrc, cgl, cdlay; 404 405 /* XXX 406 * Even though, embedded_audio_spec says capture rate range 11025 to 407 * 48000, dhwiface.cpp says, 408 * 409 * "We can only decimate by up to a factor of 1/9th the hardware rate. 410 * Return an error if an attempt is made to stray outside that limit." 411 * 412 * so assume range as 48000/9 to 48000 413 */ 414 415 if (rate < 8000) 416 rate = 8000; 417 if (rate > 48000) 418 rate = 48000; 419 420 cx = rate << 16; 421 cci = cx / 48000; 422 cx -= cci * 48000; 423 cx <<= 7; 424 cci <<= 7; 425 cci += cx / 48000; 426 cci = - cci; 427 428 cx = 48000 << 16; 429 cpi = cx / rate; 430 cx -= cpi * rate; 431 cx <<= 10; 432 cpi <<= 10; 433 cy = cx / rate; 434 cpi += cy; 435 cx -= cy * rate; 436 437 cy = cx / 200; 438 csrc = cx - 200*cy; 439 440 cdlay = ((48000 * 24) + rate - 1) / rate; 441 #if 0 442 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 443 #endif 444 445 cnt = rate << 16; 446 cnt /= 24000; 447 448 cgl = 1; 449 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 450 if (((rate / tmp1) * tmp1) != rate) 451 cgl *= 2; 452 } 453 if (((rate / 3) * 3) != rate) 454 cgl *= 3; 455 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 456 if (((rate / tmp1) * tmp1) != rate) 457 cgl *= 5; 458 } 459 #if 0 460 /* XXX what manual says */ 461 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 462 tmp1 |= csrc<<16; 463 BA1WRITE4(sc, CS4280_CSRC, tmp1); 464 #else 465 /* suggested by cs461x.c (ALSA driver) */ 466 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 467 #endif 468 469 #if 0 470 /* I am confused. The sample rate calculation section says 471 * cci *is* 32-bit signed quantity but in the parameter description 472 * section, CCI only assigned 16bit. 473 * I believe size of the variable. 474 */ 475 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 476 tmp1 |= cci<<16; 477 BA1WRITE4(sc, CS4280_CCI, tmp1); 478 #else 479 BA1WRITE4(sc, CS4280_CCI, cci); 480 #endif 481 482 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 483 tmp1 |= cdlay <<18; 484 BA1WRITE4(sc, CS4280_CD, tmp1); 485 486 BA1WRITE4(sc, CS4280_CPI, cpi); 487 488 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 489 tmp1 |= cgl; 490 BA1WRITE4(sc, CS4280_CGL, tmp1); 491 492 BA1WRITE4(sc, CS4280_CNT, cnt); 493 494 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 495 tmp1 |= cgl; 496 BA1WRITE4(sc, CS4280_CGC, tmp1); 497 } 498 499 void 500 cs4280_set_dac_rate(struct cs4280_softc *sc, int rate) 501 { 502 /* 503 * playback rate may range from 8000Hz to 48000Hz 504 * 505 * play_phase_increment = floor(rate*65536*1024/48000) 506 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 507 * py=floor(px/200) 508 * play_sample_rate_correction = px - 200*py 509 * 510 * play_phase_increment is a 32bit signed quantity. 511 * play_sample_rate_correction is a 16bit signed quantity. 512 */ 513 int32_t ppi; 514 int16_t psrc; 515 u_int32_t px, py; 516 517 if (rate < 8000) 518 rate = 8000; 519 if (rate > 48000) 520 rate = 48000; 521 px = rate << 16; 522 ppi = px/48000; 523 px -= ppi*48000; 524 ppi <<= 10; 525 px <<= 10; 526 py = px / 48000; 527 ppi += py; 528 px -= py*48000; 529 py = px/200; 530 px -= py*200; 531 psrc = px; 532 #if 0 533 /* what manual says */ 534 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 535 BA1WRITE4(sc, CS4280_PSRC, 536 ( ((psrc<<16) & PSRC_MASK) | px )); 537 #else 538 /* suggested by cs461x.c (ALSA driver) */ 539 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 540 #endif 541 BA1WRITE4(sc, CS4280_PPI, ppi); 542 } 543 544 void 545 cs4280_attachhook(void *xsc) 546 { 547 struct cs4280_softc *sc = xsc; 548 mixer_ctrl_t ctl; 549 550 /* Initialization */ 551 if (cs4280_init2(sc, 1) != 0) 552 return; 553 554 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname); 555 556 /* Turn mute off of DAC, CD and master volumes by default */ 557 ctl.type = AUDIO_MIXER_ENUM; 558 ctl.un.ord = 0; /* off */ 559 560 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 561 AudioNmaster, AudioNmute); 562 cs4280_mixer_set_port(sc, &ctl); 563 564 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 565 AudioNdac, AudioNmute); 566 cs4280_mixer_set_port(sc, &ctl); 567 568 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 569 AudioNcd, AudioNmute); 570 cs4280_mixer_set_port(sc, &ctl); 571 572 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 573 574 #if NMIDI > 0 575 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 576 #endif 577 } 578 579 void 580 cs4280_attach(struct device *parent, struct device *self, void *aux) 581 { 582 struct cs4280_softc *sc = (struct cs4280_softc *) self; 583 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 584 pci_chipset_tag_t pc = pa->pa_pc; 585 char const *intrstr; 586 pci_intr_handle_t ih; 587 u_int32_t mem; 588 589 /* Map I/O register */ 590 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 591 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 592 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 593 printf(": can't map BA0 space\n"); 594 return; 595 } 596 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 597 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 598 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 599 printf(": can't map BA1 space\n"); 600 return; 601 } 602 603 sc->sc_dmatag = pa->pa_dmat; 604 605 /* Get out of power save mode if needed. */ 606 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 607 608 /* LATENCY_TIMER setting */ 609 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 610 if ( PCI_LATTIMER(mem) < 32 ) { 611 mem &= 0xffff00ff; 612 mem |= 0x00002000; 613 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 614 } 615 616 /* Map and establish the interrupt. */ 617 if (pci_intr_map(pa, &ih)) { 618 printf(": couldn't map interrupt\n"); 619 return; 620 } 621 intrstr = pci_intr_string(pc, ih); 622 623 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE, 624 cs4280_intr, sc, sc->sc_dev.dv_xname); 625 if (sc->sc_ih == NULL) { 626 printf(": couldn't establish interrupt"); 627 if (intrstr != NULL) 628 printf(" at %s", intrstr); 629 printf("\n"); 630 return; 631 } 632 printf(": %s\n", intrstr); 633 634 /* Initialization */ 635 if (cs4280_init(sc, 1) != 0) 636 return; 637 638 mountroothook_establish(cs4280_attachhook, sc); 639 640 /* AC 97 attachement */ 641 sc->host_if.arg = sc; 642 sc->host_if.attach = cs4280_attach_codec; 643 sc->host_if.read = cs4280_read_codec; 644 sc->host_if.write = cs4280_write_codec; 645 sc->host_if.reset = cs4280_reset_codec; 646 647 if (ac97_attach(&sc->host_if) != 0) { 648 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 } 652 653 int 654 cs4280_intr(void *p) 655 { 656 /* 657 * XXX 658 * 659 * Since CS4280 has only 4kB dma buffer and 660 * interrupt occurs every 2kB block, I create dummy buffer 661 * which returns to audio driver and actual dma buffer 662 * using in DMA transfer. 663 * 664 * 665 * ring buffer in audio.c is pointed by BUFADDR 666 * <------ ring buffer size == 64kB ------> 667 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 668 * |= = = =|= = = =|= = = =|= = = =|= = = =| 669 * | | | | | | <- call audio_intp every 670 * sc->sc_[pr]_count time. 671 * 672 * actual dma buffer is pointed by KERNADDR 673 * <-> dma buffer size = 4kB 674 * |= =| 675 * 676 * 677 */ 678 struct cs4280_softc *sc = p; 679 u_int32_t intr, mem; 680 char * empty_dma; 681 int handled = 0; 682 683 mtx_enter(&audio_lock); 684 /* grab interrupt register then clear it */ 685 intr = BA0READ4(sc, CS4280_HISR); 686 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 687 688 /* Playback Interrupt */ 689 if (intr & HISR_PINT) { 690 handled = 1; 691 mem = BA1READ4(sc, CS4280_PFIE); 692 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 693 if (sc->sc_pintr) { 694 if ((sc->sc_pi%sc->sc_pcount) == 0) 695 sc->sc_pintr(sc->sc_parg); 696 } else { 697 printf("unexpected play intr\n"); 698 } 699 /* copy buffer */ 700 ++sc->sc_pi; 701 empty_dma = sc->sc_pdma->addr; 702 if (sc->sc_pi&1) 703 empty_dma += CS4280_ICHUNK; 704 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 705 sc->sc_pn += CS4280_ICHUNK; 706 if (sc->sc_pn >= sc->sc_pe) 707 sc->sc_pn = sc->sc_ps; 708 BA1WRITE4(sc, CS4280_PFIE, mem); 709 } 710 /* Capture Interrupt */ 711 if (intr & HISR_CINT) { 712 int i; 713 int16_t rdata; 714 715 handled = 1; 716 mem = BA1READ4(sc, CS4280_CIE); 717 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 718 ++sc->sc_ri; 719 empty_dma = sc->sc_rdma->addr; 720 if ((sc->sc_ri&1) == 0) 721 empty_dma += CS4280_ICHUNK; 722 723 /* 724 * XXX 725 * I think this audio data conversion should be 726 * happend in upper layer, but I put this here 727 * since there is no conversion function available. 728 */ 729 switch(sc->sc_rparam) { 730 case CF_16BIT_STEREO: 731 /* just copy it */ 732 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 733 sc->sc_rn += CS4280_ICHUNK; 734 break; 735 case CF_16BIT_MONO: 736 for (i = 0; i < 512; i++) { 737 rdata = *((int16_t *)empty_dma)>>1; 738 empty_dma += 2; 739 rdata += *((int16_t *)empty_dma)>>1; 740 empty_dma += 2; 741 *((int16_t *)sc->sc_rn) = rdata; 742 sc->sc_rn += 2; 743 } 744 break; 745 case CF_8BIT_STEREO: 746 for (i = 0; i < 512; i++) { 747 rdata = *((int16_t*)empty_dma); 748 empty_dma += 2; 749 *sc->sc_rn++ = rdata >> 8; 750 rdata = *((int16_t*)empty_dma); 751 empty_dma += 2; 752 *sc->sc_rn++ = rdata >> 8; 753 } 754 break; 755 case CF_8BIT_MONO: 756 for (i = 0; i < 512; i++) { 757 rdata = *((int16_t*)empty_dma) >>1; 758 empty_dma += 2; 759 rdata += *((int16_t*)empty_dma) >>1; 760 empty_dma += 2; 761 *sc->sc_rn++ = rdata >>8; 762 } 763 break; 764 default: 765 /* Should not reach here */ 766 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 767 } 768 if (sc->sc_rn >= sc->sc_re) 769 sc->sc_rn = sc->sc_rs; 770 BA1WRITE4(sc, CS4280_CIE, mem); 771 if (sc->sc_rintr) { 772 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 773 sc->sc_rintr(sc->sc_rarg); 774 } else { 775 printf("unexpected record intr\n"); 776 } 777 } 778 779 #if NMIDI > 0 780 /* Midi port Interrupt */ 781 if (intr & HISR_MIDI) { 782 int data; 783 784 handled = 1; 785 DPRINTF(("i: %d: ", 786 BA0READ4(sc, CS4280_MIDSR))); 787 /* Read the received data */ 788 while ((sc->sc_iintr != NULL) && 789 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 790 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 791 DPRINTF(("r:%x\n",data)); 792 sc->sc_iintr(sc->sc_arg, data); 793 } 794 795 /* Write the data */ 796 #if 1 797 /* XXX: 798 * It seems "Transmit Buffer Full" never activate until EOI 799 * is delivered. Shall I throw EOI top of this routine ? 800 */ 801 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 802 DPRINTF(("w: ")); 803 if (sc->sc_ointr != NULL) 804 sc->sc_ointr(sc->sc_arg); 805 } 806 #else 807 while ((sc->sc_ointr != NULL) && 808 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 809 DPRINTF(("w: ")); 810 sc->sc_ointr(sc->sc_arg); 811 } 812 #endif 813 DPRINTF(("\n")); 814 } 815 #endif 816 mtx_leave(&audio_lock); 817 return handled; 818 } 819 820 821 /* Download Proceessor Code and Data image */ 822 823 int 824 cs4280_download(struct cs4280_softc *sc, const u_int32_t *src, u_int32_t offset, 825 u_int32_t len) 826 { 827 u_int32_t ctr; 828 829 #ifdef CS4280_DEBUG 830 u_int32_t con, data; 831 u_int8_t c0,c1,c2,c3; 832 #endif 833 if ((offset&3) || (len&3)) 834 return (-1); 835 836 len /= sizeof(u_int32_t); 837 for (ctr = 0; ctr < len; ctr++) { 838 /* XXX: 839 * I cannot confirm this is the right thing or not 840 * on BIG-ENDIAN machines. 841 */ 842 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 843 #ifdef CS4280_DEBUG 844 data = htole32(*(src+ctr)); 845 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 846 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 847 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 848 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 849 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 850 if (data != con ) { 851 printf("0x%06x: write=0x%08x read=0x%08x\n", 852 offset+ctr*4, data, con); 853 return (-1); 854 } 855 #endif 856 } 857 return (0); 858 } 859 860 struct BA1struct *BA1Struct; 861 862 int 863 cs4280_download_image(struct cs4280_softc *sc) 864 { 865 int idx, err = 0; 866 u_int32_t offset = 0; 867 static u_char *cs4280_firmware; 868 static size_t cs4280_firmwarelen; 869 870 if (cs4280_firmware == NULL) { 871 err = loadfirmware("cs4280", &cs4280_firmware, 872 &cs4280_firmwarelen); 873 if (err) 874 return (err); 875 } 876 877 BA1Struct = (struct BA1struct *)cs4280_firmware; 878 879 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 880 err = cs4280_download(sc, &BA1Struct->map[offset], 881 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size); 882 if (err != 0) { 883 printf("%s: load_image failed at %d\n", 884 sc->sc_dev.dv_xname, idx); 885 return (-1); 886 } 887 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 888 } 889 return (err); 890 } 891 892 #ifdef CS4280_DEBUG 893 int 894 cs4280_checkimage(struct cs4280_softc *sc, u_int32_t *src, u_int32_t offset, 895 u_int32_t len) 896 { 897 u_int32_t ctr, data; 898 int err = 0; 899 900 if ((offset&3) || (len&3)) 901 return -1; 902 903 len /= sizeof(u_int32_t); 904 for (ctr = 0; ctr < len; ctr++) { 905 /* I cannot confirm this is the right thing 906 * on BIG-ENDIAN machines 907 */ 908 data = BA1READ4(sc, offset+ctr*4); 909 if (data != htole32(*(src+ctr))) { 910 printf("0x%06x: 0x%08x(0x%08x)\n", 911 offset+ctr*4, data, *(src+ctr)); 912 *(src+ctr) = data; 913 ++err; 914 } 915 } 916 return (err); 917 } 918 919 int 920 cs4280_check_images(struct cs4280_softc *sc) 921 { 922 int idx, err; 923 u_int32_t offset = 0; 924 925 err = 0; 926 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 927 for (idx = 0; idx < 1; ++idx) { 928 err = cs4280_checkimage(sc, &BA1Struct->map[offset], 929 BA1Struct->memory[idx].offset, 930 BA1Struct->memory[idx].size); 931 if (err != 0) { 932 printf("%s: check_image failed at %d\n", 933 sc->sc_dev.dv_xname, idx); 934 } 935 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 936 } 937 return (err); 938 } 939 940 #endif 941 942 int 943 cs4280_attach_codec(void *sc_, struct ac97_codec_if *codec_if) 944 { 945 struct cs4280_softc *sc = sc_; 946 947 sc->codec_if = codec_if; 948 return (0); 949 } 950 951 void 952 cs4280_reset_codec(void *sc_) 953 { 954 struct cs4280_softc *sc = sc_; 955 int n; 956 957 /* Reset codec */ 958 BA0WRITE4(sc, CS4280_ACCTL, 0); 959 delay(100); /* delay 100us */ 960 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 961 962 /* 963 * It looks like we do the following procedure, too 964 */ 965 966 /* Enable AC-link sync generation */ 967 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 968 delay(50*1000); /* XXX delay 50ms */ 969 970 /* Assert valid frame signal */ 971 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 972 973 /* Wait for valid AC97 input slot */ 974 n = 0; 975 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 976 delay(1000); 977 if (++n > 1000) { 978 printf("reset_codec: AC97 inputs slot ready timeout\n"); 979 return; 980 } 981 } 982 } 983 984 985 /* Processor Soft Reset */ 986 void 987 cs4280_reset(void *sc_) 988 { 989 struct cs4280_softc *sc = sc_; 990 991 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 992 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 993 delay(100); 994 /* Clear RSTSP bit in SPCR */ 995 BA1WRITE4(sc, CS4280_SPCR, 0); 996 /* enable DMA reqest */ 997 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 998 } 999 1000 int 1001 cs4280_open(void *addr, int flags) 1002 { 1003 return (0); 1004 } 1005 1006 void 1007 cs4280_close(void *addr) 1008 { 1009 struct cs4280_softc *sc = addr; 1010 1011 /* XXX: already called in audio_close() */ 1012 cs4280_halt_output(sc); 1013 cs4280_halt_input(sc); 1014 1015 sc->sc_pintr = 0; 1016 sc->sc_rintr = 0; 1017 } 1018 1019 int 1020 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 1021 { 1022 switch (fp->index) { 1023 case 0: 1024 strlcpy(fp->name, AudioEulinear, sizeof fp->name); 1025 fp->encoding = AUDIO_ENCODING_ULINEAR; 1026 fp->precision = 8; 1027 fp->flags = 0; 1028 break; 1029 case 1: 1030 strlcpy(fp->name, AudioEmulaw, sizeof fp->name); 1031 fp->encoding = AUDIO_ENCODING_ULAW; 1032 fp->precision = 8; 1033 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1034 break; 1035 case 2: 1036 strlcpy(fp->name, AudioEalaw, sizeof fp->name); 1037 fp->encoding = AUDIO_ENCODING_ALAW; 1038 fp->precision = 8; 1039 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1040 break; 1041 case 3: 1042 strlcpy(fp->name, AudioEslinear, sizeof fp->name); 1043 fp->encoding = AUDIO_ENCODING_SLINEAR; 1044 fp->precision = 8; 1045 fp->flags = 0; 1046 break; 1047 case 4: 1048 strlcpy(fp->name, AudioEslinear_le, sizeof fp->name); 1049 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1050 fp->precision = 16; 1051 fp->flags = 0; 1052 break; 1053 case 5: 1054 strlcpy(fp->name, AudioEulinear_le, sizeof fp->name); 1055 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1056 fp->precision = 16; 1057 fp->flags = 0; 1058 break; 1059 case 6: 1060 strlcpy(fp->name, AudioEslinear_be, sizeof fp->name); 1061 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1062 fp->precision = 16; 1063 fp->flags = 0; 1064 break; 1065 case 7: 1066 strlcpy(fp->name, AudioEulinear_be, sizeof fp->name); 1067 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1068 fp->precision = 16; 1069 fp->flags = 0; 1070 break; 1071 default: 1072 return (EINVAL); 1073 } 1074 fp->bps = AUDIO_BPS(fp->precision); 1075 fp->msb = 1; 1076 1077 return (0); 1078 } 1079 1080 int 1081 cs4280_set_params(void *addr, int setmode, int usemode, 1082 struct audio_params *play, struct audio_params *rec) 1083 { 1084 struct cs4280_softc *sc = addr; 1085 struct audio_params *p; 1086 int mode; 1087 1088 for (mode = AUMODE_RECORD; mode != -1; 1089 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1090 if ((setmode & mode) == 0) 1091 continue; 1092 1093 p = mode == AUMODE_PLAY ? play : rec; 1094 if (p == play) { 1095 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1096 p->sample_rate, p->precision, p->channels)); 1097 } else { 1098 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1099 p->sample_rate, p->precision, p->channels)); 1100 } 1101 /* play back data format may be 8- or 16-bit and 1102 * either stereo or mono. 1103 * playback rate may range from 8000Hz to 48000Hz 1104 * 1105 * capture data format must be 16bit stereo 1106 * and sample rate range from 11025Hz to 48000Hz. 1107 * 1108 * XXX: it looks like to work with 8000Hz, 1109 * although data sheets say lower limit is 1110 * 11025 Hz. 1111 */ 1112 if (p->sample_rate < 8000) 1113 p->sample_rate = 8000; 1114 if (p->sample_rate > 48000) 1115 p->sample_rate = 48000; 1116 if (p->precision > 16) 1117 p->precision = 16; 1118 if (p->channels > 2) 1119 p->channels = 2; 1120 p->factor = 1; 1121 p->sw_code = 0; 1122 1123 /* capturing data is slinear */ 1124 switch (p->encoding) { 1125 case AUDIO_ENCODING_SLINEAR_BE: 1126 if (mode == AUMODE_RECORD) { 1127 if (p->precision == 16) 1128 p->sw_code = swap_bytes; 1129 } 1130 break; 1131 case AUDIO_ENCODING_SLINEAR_LE: 1132 break; 1133 case AUDIO_ENCODING_ULINEAR_BE: 1134 if (mode == AUMODE_RECORD) { 1135 if (p->precision == 16) 1136 p->sw_code = change_sign16_swap_bytes_le; 1137 else 1138 p->sw_code = change_sign8; 1139 } 1140 break; 1141 case AUDIO_ENCODING_ULINEAR_LE: 1142 if (mode == AUMODE_RECORD) { 1143 if (p->precision == 16) 1144 p->sw_code = change_sign16_le; 1145 else 1146 p->sw_code = change_sign8; 1147 } 1148 break; 1149 case AUDIO_ENCODING_ULAW: 1150 if (mode == AUMODE_PLAY) { 1151 p->factor = 2; 1152 p->sw_code = mulaw_to_slinear16_le; 1153 } else { 1154 p->sw_code = slinear8_to_mulaw; 1155 } 1156 break; 1157 case AUDIO_ENCODING_ALAW: 1158 if (mode == AUMODE_PLAY) { 1159 p->factor = 2; 1160 p->sw_code = alaw_to_slinear16_le; 1161 } else { 1162 p->sw_code = slinear8_to_alaw; 1163 } 1164 break; 1165 default: 1166 return (EINVAL); 1167 } 1168 p->bps = AUDIO_BPS(p->precision); 1169 p->msb = 1; 1170 } 1171 1172 /* set sample rate */ 1173 cs4280_set_dac_rate(sc, play->sample_rate); 1174 cs4280_set_adc_rate(sc, rec->sample_rate); 1175 return (0); 1176 } 1177 1178 int 1179 cs4280_round_blocksize(void *hdl, int blk) 1180 { 1181 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1182 } 1183 1184 size_t 1185 cs4280_round_buffersize(void *addr, int direction, size_t size) 1186 { 1187 /* although real dma buffer size is 4KB, 1188 * let the audio.c driver use a larger buffer. 1189 * ( suggested by Lennart Augustsson. ) 1190 */ 1191 return (size); 1192 } 1193 1194 void 1195 cs4280_get_default_params(void *addr, int mode, struct audio_params *params) 1196 { 1197 ac97_get_default_params(params); 1198 } 1199 1200 int 1201 cs4280_get_props(void *hdl) 1202 { 1203 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1204 #ifdef notyet 1205 /* XXX 1206 * How can I mmap ? 1207 */ 1208 AUDIO_PROP_MMAP 1209 #endif 1210 1211 } 1212 1213 int 1214 cs4280_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1215 { 1216 struct cs4280_softc *sc = addr; 1217 1218 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1219 } 1220 1221 paddr_t 1222 cs4280_mappage(void *addr, void *mem, off_t off, int prot) 1223 { 1224 struct cs4280_softc *sc = addr; 1225 struct cs4280_dma *p; 1226 1227 if (off < 0) 1228 return (-1); 1229 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1230 ; 1231 if (!p) { 1232 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1233 return (-1); 1234 } 1235 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1236 off, prot, BUS_DMA_WAITOK)); 1237 } 1238 1239 1240 int 1241 cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip) 1242 { 1243 struct cs4280_softc *sc = addr; 1244 1245 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1246 } 1247 1248 int 1249 cs4280_get_portnum_by_name(struct cs4280_softc *sc, char *class, char *device, 1250 char *qualifier) 1251 { 1252 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1253 device, qualifier)); 1254 } 1255 1256 int 1257 cs4280_halt_output(void *addr) 1258 { 1259 struct cs4280_softc *sc = addr; 1260 u_int32_t mem; 1261 1262 mtx_enter(&audio_lock); 1263 mem = BA1READ4(sc, CS4280_PCTL); 1264 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1265 #ifdef DIAGNOSTIC 1266 sc->sc_prun = 0; 1267 #endif 1268 mtx_leave(&audio_lock); 1269 return (0); 1270 } 1271 1272 int 1273 cs4280_halt_input(void *addr) 1274 { 1275 struct cs4280_softc *sc = addr; 1276 u_int32_t mem; 1277 1278 mtx_enter(&audio_lock); 1279 mem = BA1READ4(sc, CS4280_CCTL); 1280 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1281 #ifdef DIAGNOSTIC 1282 sc->sc_rrun = 0; 1283 #endif 1284 mtx_leave(&audio_lock); 1285 return (0); 1286 } 1287 1288 int 1289 cs4280_getdev(void *addr, struct audio_device *retp) 1290 { 1291 *retp = cs4280_device; 1292 return (0); 1293 } 1294 1295 int 1296 cs4280_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1297 { 1298 struct cs4280_softc *sc = addr; 1299 int val; 1300 1301 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1302 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1303 return (val); 1304 } 1305 1306 1307 int 1308 cs4280_freemem(struct cs4280_softc *sc, struct cs4280_dma *p) 1309 { 1310 bus_dmamap_unload(sc->sc_dmatag, p->map); 1311 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1312 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1313 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1314 return (0); 1315 } 1316 1317 int 1318 cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align, 1319 struct cs4280_dma *p) 1320 { 1321 int error; 1322 1323 /* XXX */ 1324 p->size = size; 1325 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1326 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1327 &p->nsegs, BUS_DMA_NOWAIT); 1328 if (error) { 1329 printf("%s: unable to allocate dma, error=%d\n", 1330 sc->sc_dev.dv_xname, error); 1331 return (error); 1332 } 1333 1334 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1335 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1336 if (error) { 1337 printf("%s: unable to map dma, error=%d\n", 1338 sc->sc_dev.dv_xname, error); 1339 goto free; 1340 } 1341 1342 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1343 0, BUS_DMA_NOWAIT, &p->map); 1344 if (error) { 1345 printf("%s: unable to create dma map, error=%d\n", 1346 sc->sc_dev.dv_xname, error); 1347 goto unmap; 1348 } 1349 1350 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1351 BUS_DMA_NOWAIT); 1352 if (error) { 1353 printf("%s: unable to load dma map, error=%d\n", 1354 sc->sc_dev.dv_xname, error); 1355 goto destroy; 1356 } 1357 return (0); 1358 1359 destroy: 1360 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1361 unmap: 1362 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1363 free: 1364 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1365 return (error); 1366 } 1367 1368 1369 void * 1370 cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags) 1371 { 1372 struct cs4280_softc *sc = addr; 1373 struct cs4280_dma *p; 1374 caddr_t q; 1375 int error; 1376 1377 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1378 q = malloc(size, pool, flags); 1379 if (!q) 1380 return (0); 1381 p = malloc(sizeof(*p), pool, flags); 1382 if (!p) { 1383 free(q,pool, 0); 1384 return (0); 1385 } 1386 /* 1387 * cs4280 has fixed 4kB buffer 1388 */ 1389 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1390 1391 if (error) { 1392 free(q, pool, 0); 1393 free(p, pool, 0); 1394 return (0); 1395 } 1396 1397 p->next = sc->sc_dmas; 1398 sc->sc_dmas = p; 1399 p->dum = q; /* return to audio driver */ 1400 1401 return (p->dum); 1402 } 1403 1404 void 1405 cs4280_free(void *addr, void *ptr, int pool) 1406 { 1407 struct cs4280_softc *sc = addr; 1408 struct cs4280_dma **pp, *p; 1409 1410 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1411 if (BUFADDR(p) == ptr) { 1412 cs4280_freemem(sc, p); 1413 *pp = p->next; 1414 free(p->dum, pool, 0); 1415 free(p, pool, 0); 1416 return; 1417 } 1418 } 1419 } 1420 1421 int 1422 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 1423 void (*intr)(void *), void *arg, struct audio_params *param) 1424 { 1425 struct cs4280_softc *sc = addr; 1426 u_int32_t pfie, pctl, mem, pdtc; 1427 struct cs4280_dma *p; 1428 1429 #ifdef DIAGNOSTIC 1430 if (sc->sc_prun) 1431 printf("cs4280_trigger_output: already running\n"); 1432 sc->sc_prun = 1; 1433 #endif 1434 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1435 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1436 sc->sc_pintr = intr; 1437 sc->sc_parg = arg; 1438 1439 /* stop playback DMA */ 1440 mem = BA1READ4(sc, CS4280_PCTL); 1441 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1442 1443 /* setup PDTC */ 1444 pdtc = BA1READ4(sc, CS4280_PDTC); 1445 pdtc &= ~PDTC_MASK; 1446 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1447 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1448 1449 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1450 param->precision, param->factor, param->channels, 1451 param->encoding)); 1452 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1453 ; 1454 if (p == NULL) { 1455 printf("cs4280_trigger_output: bad addr %p\n", start); 1456 return (EINVAL); 1457 } 1458 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1459 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1460 "4kB align\n", DMAADDR(p)); 1461 return (EINVAL); 1462 } 1463 1464 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1465 sc->sc_ps = (char *)start; 1466 sc->sc_pe = (char *)end; 1467 sc->sc_pdma = p; 1468 sc->sc_pbuf = KERNADDR(p); 1469 sc->sc_pi = 0; 1470 sc->sc_pn = sc->sc_ps; 1471 if (blksize >= CS4280_DCHUNK) { 1472 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1473 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1474 ++sc->sc_pi; 1475 } else { 1476 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1477 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1478 } 1479 1480 /* initiate playback dma */ 1481 mtx_enter(&audio_lock); 1482 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1483 1484 /* set PFIE */ 1485 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1486 1487 if (param->precision * param->factor == 8) 1488 pfie |= PFIE_8BIT; 1489 if (param->channels == 1) 1490 pfie |= PFIE_MONO; 1491 1492 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1493 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1494 pfie |= PFIE_SWAPPED; 1495 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1496 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1497 pfie |= PFIE_UNSIGNED; 1498 1499 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1500 1501 cs4280_set_dac_rate(sc, param->sample_rate); 1502 1503 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1504 pctl |= sc->pctl; 1505 BA1WRITE4(sc, CS4280_PCTL, pctl); 1506 mtx_leave(&audio_lock); 1507 return (0); 1508 } 1509 1510 int 1511 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 1512 void (*intr)(void *), void *arg, struct audio_params *param) 1513 { 1514 struct cs4280_softc *sc = addr; 1515 u_int32_t cctl, cie; 1516 struct cs4280_dma *p; 1517 1518 #ifdef DIAGNOSTIC 1519 if (sc->sc_rrun) 1520 printf("cs4280_trigger_input: already running\n"); 1521 sc->sc_rrun = 1; 1522 #endif 1523 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1524 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1525 sc->sc_rintr = intr; 1526 sc->sc_rarg = arg; 1527 1528 sc->sc_ri = 0; 1529 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1530 sc->sc_rs = (char *)start; 1531 sc->sc_re = (char *)end; 1532 sc->sc_rn = sc->sc_rs; 1533 1534 /* setup format information for internal converter */ 1535 sc->sc_rparam = 0; 1536 if (param->precision == 8) { 1537 sc->sc_rparam += CF_8BIT; 1538 sc->sc_rcount <<= 1; 1539 } 1540 if (param->channels == 1) { 1541 sc->sc_rparam += CF_MONO; 1542 sc->sc_rcount <<= 1; 1543 } 1544 1545 /* stop capture DMA */ 1546 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1547 BA1WRITE4(sc, CS4280_CCTL, cctl); 1548 1549 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1550 ; 1551 if (!p) { 1552 printf("cs4280_trigger_input: bad addr %p\n", start); 1553 return (EINVAL); 1554 } 1555 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1556 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1557 "4kB align\n", DMAADDR(p)); 1558 return (EINVAL); 1559 } 1560 sc->sc_rdma = p; 1561 sc->sc_rbuf = KERNADDR(p); 1562 1563 /* initiate capture dma */ 1564 mtx_enter(&audio_lock); 1565 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1566 1567 /* set CIE */ 1568 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1569 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1570 1571 cs4280_set_adc_rate(sc, param->sample_rate); 1572 1573 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1574 cctl |= sc->cctl; 1575 BA1WRITE4(sc, CS4280_CCTL, cctl); 1576 mtx_leave(&audio_lock); 1577 return (0); 1578 } 1579 1580 1581 int 1582 cs4280_init(struct cs4280_softc *sc, int init) 1583 { 1584 int n; 1585 u_int32_t mem; 1586 1587 /* Start PLL out in known state */ 1588 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1589 /* Start serial ports out in known state */ 1590 BA0WRITE4(sc, CS4280_SERMC1, 0); 1591 1592 /* Specify type of CODEC */ 1593 /* XXX should no be here */ 1594 #define SERACC_CODEC_TYPE_1_03 1595 #ifdef SERACC_CODEC_TYPE_1_03 1596 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1597 #else 1598 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1599 #endif 1600 1601 /* Reset codec */ 1602 BA0WRITE4(sc, CS4280_ACCTL, 0); 1603 delay(100); /* delay 100us */ 1604 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1605 1606 /* Enable AC-link sync generation */ 1607 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1608 delay(50*1000); /* delay 50ms */ 1609 1610 /* Set the serial port timing configuration */ 1611 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1612 1613 /* Setup clock control */ 1614 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1615 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1616 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1617 1618 /* Power up the PLL */ 1619 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1620 delay(50*1000); /* delay 50ms */ 1621 1622 /* Turn on clock */ 1623 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1624 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1625 1626 /* Set the serial port FIFO pointer to the 1627 * first sample in FIFO. (not documented) */ 1628 cs4280_clear_fifos(sc); 1629 1630 #if 0 1631 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1632 BA0WRITE4(sc, CS4280_SERBSP, 0); 1633 #endif 1634 1635 /* Configure the serial port */ 1636 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1637 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1638 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1639 1640 /* Wait for CODEC ready */ 1641 n = 0; 1642 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1643 delay(125); 1644 if (++n > 1000) { 1645 printf("%s: codec ready timeout\n", 1646 sc->sc_dev.dv_xname); 1647 return(1); 1648 } 1649 } 1650 1651 /* Assert valid frame signal */ 1652 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1653 1654 /* Wait for valid AC97 input slot */ 1655 n = 0; 1656 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1657 (ACISV_ISV3 | ACISV_ISV4)) { 1658 delay(1000); 1659 if (++n > 1000) { 1660 printf("AC97 inputs slot ready timeout\n"); 1661 return(1); 1662 } 1663 } 1664 1665 /* Set AC97 output slot valid signals */ 1666 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1667 1668 /* reset the processor */ 1669 cs4280_reset(sc); 1670 return (0); 1671 } 1672 1673 int 1674 cs4280_init2(struct cs4280_softc *sc, int init) 1675 { 1676 int n; 1677 u_int32_t mem; 1678 1679 /* Download the image to the processor */ 1680 if (cs4280_download_image(sc) != 0) { 1681 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1682 return(1); 1683 } 1684 1685 /* Save playback parameter and then write zero. 1686 * this ensures that DMA doesn't immediately occur upon 1687 * starting the processor core 1688 */ 1689 mem = BA1READ4(sc, CS4280_PCTL); 1690 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1691 cs4280_halt_output(sc); 1692 1693 /* Save capture parameter and then write zero. 1694 * this ensures that DMA doesn't immediately occur upon 1695 * starting the processor core 1696 */ 1697 mem = BA1READ4(sc, CS4280_CCTL); 1698 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1699 cs4280_halt_input(sc); 1700 1701 /* MSH: need to power up ADC and DAC? */ 1702 1703 /* Processor Startup Procedure */ 1704 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1705 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1706 1707 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1708 n = 0; 1709 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1710 delay(10); 1711 if (++n > 1000) { 1712 printf("SPCR 1->0 transition timeout\n"); 1713 return(1); 1714 } 1715 } 1716 1717 n = 0; 1718 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1719 delay(10); 1720 if (++n > 1000) { 1721 printf("SPCS 0->1 transition timeout\n"); 1722 return(1); 1723 } 1724 } 1725 /* Processor is now running !!! */ 1726 1727 /* Setup volume */ 1728 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1729 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1730 1731 /* Interrupt enable */ 1732 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1733 1734 /* playback interrupt enable */ 1735 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1736 mem |= PFIE_PI_ENABLE; 1737 BA1WRITE4(sc, CS4280_PFIE, mem); 1738 /* capture interrupt enable */ 1739 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1740 mem |= CIE_CI_ENABLE; 1741 BA1WRITE4(sc, CS4280_CIE, mem); 1742 1743 #if NMIDI > 0 1744 /* Reset midi port */ 1745 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1746 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1747 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1748 /* midi interrupt enable */ 1749 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1750 BA0WRITE4(sc, CS4280_MIDCR, mem); 1751 #endif 1752 return(0); 1753 } 1754 1755 int 1756 cs4280_activate(struct device *self, int act) 1757 { 1758 struct cs4280_softc *sc = (struct cs4280_softc *)self; 1759 int rv = 0; 1760 1761 switch (act) { 1762 case DVACT_SUSPEND: 1763 /* should I powerdown here ? */ 1764 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1765 break; 1766 case DVACT_RESUME: 1767 cs4280_close(sc); 1768 cs4280_init(sc, 0); 1769 cs4280_init2(sc, 0); 1770 ac97_resume(&sc->host_if, sc->codec_if); 1771 rv = config_activate_children(self, act); 1772 break; 1773 default: 1774 rv = config_activate_children(self, act); 1775 break; 1776 } 1777 return (rv); 1778 } 1779 1780 void 1781 cs4280_clear_fifos(struct cs4280_softc *sc) 1782 { 1783 int pd = 0, cnt, n; 1784 u_int32_t mem; 1785 1786 /* 1787 * If device power down, power up the device and keep power down 1788 * state. 1789 */ 1790 mem = BA0READ4(sc, CS4280_CLKCR1); 1791 if (!(mem & CLKCR1_SWCE)) { 1792 printf("cs4280_clear_fifo: power down found.\n"); 1793 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1794 pd = 1; 1795 } 1796 BA0WRITE4(sc, CS4280_SERBWP, 0); 1797 for (cnt = 0; cnt < 256; cnt++) { 1798 n = 0; 1799 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1800 delay(1000); 1801 if (++n > 1000) { 1802 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1803 break; 1804 } 1805 } 1806 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1807 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1808 } 1809 if (pd) 1810 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1811 } 1812 1813 #if NMIDI > 0 1814 int 1815 cs4280_midi_open(void *addr, int flags, void (*iintr)(void, int), 1816 void (*ointr)(void *), void *arg) 1817 { 1818 struct cs4280_softc *sc = addr; 1819 u_int32_t mem; 1820 1821 DPRINTF(("midi_open\n")); 1822 sc->sc_iintr = iintr; 1823 sc->sc_ointr = ointr; 1824 sc->sc_arg = arg; 1825 1826 /* midi interrupt enable */ 1827 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1828 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1829 BA0WRITE4(sc, CS4280_MIDCR, mem); 1830 #ifdef CS4280_DEBUG 1831 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1832 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1833 return(EINVAL); 1834 } 1835 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1836 #endif 1837 return (0); 1838 } 1839 1840 void 1841 cs4280_midi_close(void *addr) 1842 { 1843 struct cs4280_softc *sc = addr; 1844 u_int32_t mem; 1845 1846 DPRINTF(("midi_close\n")); 1847 mem = BA0READ4(sc, CS4280_MIDCR); 1848 mem &= ~MIDCR_MASK; 1849 BA0WRITE4(sc, CS4280_MIDCR, mem); 1850 1851 sc->sc_iintr = 0; 1852 sc->sc_ointr = 0; 1853 } 1854 1855 int 1856 cs4280_midi_output(void *addr, int d) 1857 { 1858 struct cs4280_softc *sc = addr; 1859 u_int32_t mem; 1860 int x; 1861 1862 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1863 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1864 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1865 mem |= d & MIDWP_MASK; 1866 DPRINTFN(5,("midi_output d=0x%08x",d)); 1867 BA0WRITE4(sc, CS4280_MIDWP, mem); 1868 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1869 DPRINTF(("Bad write data: %d %d", 1870 mem, BA0READ4(sc, CS4280_MIDWP))); 1871 return(EIO); 1872 } 1873 return (0); 1874 } 1875 delay(MIDI_BUSY_DELAY); 1876 } 1877 return (EIO); 1878 } 1879 1880 void 1881 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1882 { 1883 mi->name = "CS4280 MIDI UART"; 1884 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1885 } 1886 1887 #endif 1888