1 /* $OpenBSD: cz.c,v 1.25 2021/01/01 10:21:26 jan Exp $ */ 2 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Zembu Labs, Inc. 6 * All rights reserved. 7 * 8 * Authors: Jason R. Thorpe <thorpej@zembu.com> 9 * Bill Studenmund <wrstuden@zembu.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Zembu Labs, Inc. 22 * 4. Neither the name of Zembu Labs nor the names of its employees may 23 * be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 28 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 29 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 40 * 41 * Some notes: 42 * 43 * - The Cyclades-Z has fully automatic hardware (and software!) 44 * flow control. We only utilize RTS/CTS flow control here, 45 * and it is implemented in a very simplistic manner. This 46 * may be an area of future work. 47 * 48 * - The PLX can map the either the board's RAM or host RAM 49 * into the MIPS's memory window. This would enable us to 50 * use less expensive (for us) memory reads/writes to host 51 * RAM, rather than time-consuming reads/writes to PCI 52 * memory space. However, the PLX can only map a 0-128M 53 * window, so we would have to ensure that the DMA address 54 * of the host RAM fits there. This is kind of a pain, 55 * so we just don't bother right now. 56 * 57 * - In a perfect world, we would use the autoconfiguration 58 * mechanism to attach the TTYs that we find. However, 59 * that leads to somewhat icky looking autoconfiguration 60 * messages (one for every TTY, up to 64 per board!). So 61 * we don't do it that way, but assign minors as if there 62 * were the max of 64 ports per board. 63 * 64 * - We don't bother with PPS support here. There are so many 65 * ports, each with a large amount of buffer space, that the 66 * normal mode of operation is to poll the boards regularly 67 * (generally, every 20ms or so). This makes this driver 68 * unsuitable for PPS, as the latency will be generally too 69 * high. 70 */ 71 /* 72 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 73 * for FreeBSD 3.2. 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/proc.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/tty.h> 82 #include <sys/conf.h> 83 #include <sys/time.h> 84 #include <sys/kernel.h> 85 #include <sys/fcntl.h> 86 #include <sys/syslog.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/pci/czreg.h> 92 93 #include <dev/pci/plx9060reg.h> 94 #include <dev/pci/plx9060var.h> 95 96 #include <dev/microcode/cyclades/cyzfirm.h> 97 98 #define CZ_DRIVER_VERSION 0x20000411 99 100 #define CZ_POLL_MS 20 101 102 /* These are the interrupts we always use. */ 103 #define CZ_INTERRUPTS \ 104 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 105 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 106 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 107 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 108 109 /* 110 * cztty_softc: 111 * 112 * Per-channel (TTY) state. 113 */ 114 struct cztty_softc { 115 struct cz_softc *sc_parent; 116 struct tty *sc_tty; 117 118 struct timeout sc_diag_to; 119 120 int sc_channel; /* Also used to flag unattached chan */ 121 #define CZTTY_CHANNEL_DEAD -1 122 123 bus_space_tag_t sc_chan_st; /* channel space tag */ 124 bus_space_handle_t sc_chan_sh; /* channel space handle */ 125 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 126 127 u_int sc_overflows, 128 sc_parity_errors, 129 sc_framing_errors, 130 sc_errors; 131 132 int sc_swflags; 133 134 u_int32_t sc_rs_control_dtr, 135 sc_chanctl_hw_flow, 136 sc_chanctl_comm_baud, 137 sc_chanctl_rs_control, 138 sc_chanctl_comm_data_l, 139 sc_chanctl_comm_parity; 140 }; 141 142 /* 143 * cz_softc: 144 * 145 * Per-board state. 146 */ 147 struct cz_softc { 148 struct device cz_dev; /* generic device info */ 149 struct plx9060_config cz_plx; /* PLX 9060 config info */ 150 bus_space_tag_t cz_win_st; /* window space tag */ 151 bus_space_handle_t cz_win_sh; /* window space handle */ 152 struct timeout cz_timeout; /* timeout for polling-mode */ 153 154 void *cz_ih; /* interrupt handle */ 155 156 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 157 int cz_nchannels; /* number of channels */ 158 int cz_nopenchan; /* number of open channels */ 159 struct cztty_softc *cz_ports; /* our array of ports */ 160 161 bus_addr_t cz_fwctl; /* offset of firmware control */ 162 }; 163 164 int cz_match(struct device *, void *, void *); 165 void cz_attach(struct device *, struct device *, void *); 166 int cz_wait_pci_doorbell(struct cz_softc *, char *); 167 168 struct cfattach cz_ca = { 169 sizeof(struct cz_softc), cz_match, cz_attach 170 }; 171 172 void cz_reset_board(struct cz_softc *); 173 int cz_load_firmware(struct cz_softc *); 174 175 int cz_intr(void *); 176 void cz_poll(void *); 177 int cztty_transmit(struct cztty_softc *, struct tty *); 178 int cztty_receive(struct cztty_softc *, struct tty *); 179 180 struct cztty_softc * cztty_getttysoftc(dev_t dev); 181 int cztty_findmajor(void); 182 int cztty_major; 183 int cztty_attached_ttys; 184 185 cdev_decl(cztty); 186 187 void czttystart(struct tty *tp); 188 int czttyparam(struct tty *tp, struct termios *t); 189 void cztty_shutdown(struct cztty_softc *sc); 190 void cztty_modem(struct cztty_softc *sc, int onoff); 191 void cztty_break(struct cztty_softc *sc, int onoff); 192 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 193 int cztty_to_tiocm(struct cztty_softc *sc); 194 void cztty_diag(void *arg); 195 196 struct cfdriver cz_cd = { 197 0, "cz", DV_TTY 198 }; 199 200 /* 201 * Macros to read and write the PLX. 202 */ 203 #define CZ_PLX_READ(cz, reg) \ 204 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 205 #define CZ_PLX_WRITE(cz, reg, val) \ 206 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 207 (reg), (val)) 208 209 /* 210 * Macros to read and write the FPGA. We must already be in the FPGA 211 * window for this. 212 */ 213 #define CZ_FPGA_READ(cz, reg) \ 214 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 215 #define CZ_FPGA_WRITE(cz, reg, val) \ 216 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 217 218 /* 219 * Macros to read and write the firmware control structures in board RAM. 220 */ 221 #define CZ_FWCTL_READ(cz, off) \ 222 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 223 (cz)->cz_fwctl + (off)) 224 225 #define CZ_FWCTL_WRITE(cz, off, val) \ 226 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 227 (cz)->cz_fwctl + (off), (val)) 228 229 /* 230 * Convenience macros for cztty routines. PLX window MUST be to RAM. 231 */ 232 #define CZTTY_CHAN_READ(sc, off) \ 233 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 234 235 #define CZTTY_CHAN_WRITE(sc, off, val) \ 236 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 237 (off), (val)) 238 239 #define CZTTY_BUF_READ(sc, off) \ 240 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 241 242 #define CZTTY_BUF_WRITE(sc, off, val) \ 243 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 244 (off), (val)) 245 246 /* 247 * Convenience macros. 248 */ 249 #define CZ_WIN_RAM(cz) \ 250 do { \ 251 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 252 delay(100); \ 253 } while (0) 254 255 #define CZ_WIN_FPGA(cz) \ 256 do { \ 257 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 258 delay(100); \ 259 } while (0) 260 261 /***************************************************************************** 262 * Cyclades-Z controller code starts here... 263 *****************************************************************************/ 264 265 /* 266 * cz_match: 267 * 268 * Determine if the given PCI device is a Cyclades-Z board. 269 */ 270 int 271 cz_match(parent, match, aux) 272 struct device *parent; 273 void *match, *aux; 274 { 275 struct pci_attach_args *pa = aux; 276 277 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES && 278 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CYCLADES_CYCLOMZ_2) 279 return (1); 280 return (0); 281 } 282 283 /* 284 * cz_attach: 285 * 286 * A Cyclades-Z board was found; attach it. 287 */ 288 void 289 cz_attach(parent, self, aux) 290 struct device *parent, *self; 291 void *aux; 292 { 293 struct cz_softc *cz = (void *) self; 294 struct pci_attach_args *pa = aux; 295 pci_chipset_tag_t pc = pa->pa_pc; 296 pci_intr_handle_t ih; 297 const char *intrstr = NULL; 298 struct cztty_softc *sc; 299 struct tty *tp; 300 int i; 301 302 cz->cz_plx.plx_pc = pa->pa_pc; 303 cz->cz_plx.plx_tag = pa->pa_tag; 304 305 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 306 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 307 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) { 308 printf(": unable to map PLX registers\n"); 309 return; 310 } 311 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 312 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 313 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) { 314 printf(": unable to map device window\n"); 315 return; 316 } 317 318 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 319 cz->cz_nopenchan = 0; 320 321 /* 322 * Make sure that the board is completely stopped. 323 */ 324 CZ_WIN_FPGA(cz); 325 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 326 327 /* 328 * Load the board's firmware. 329 */ 330 if (cz_load_firmware(cz) != 0) 331 return; 332 333 /* 334 * Now that we're ready to roll, map and establish the interrupt 335 * handler. 336 */ 337 if (pci_intr_map(pa, &ih) != 0) { 338 /* 339 * The common case is for Cyclades-Z boards to run 340 * in polling mode, and thus not have an interrupt 341 * mapped for them. Don't bother reporting that 342 * the interrupt is not mappable, since this isn't 343 * really an error. 344 */ 345 cz->cz_ih = NULL; 346 goto polling_mode; 347 } else { 348 intrstr = pci_intr_string(pa->pa_pc, ih); 349 cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY, 350 cz_intr, cz, cz->cz_dev.dv_xname); 351 } 352 if (cz->cz_ih == NULL) { 353 printf(": unable to establish interrupt"); 354 if (intrstr != NULL) 355 printf(" at %s", intrstr); 356 printf("\n"); 357 /* We will fall-back on polling mode. */ 358 } else 359 printf(": %s\n", intrstr); 360 361 polling_mode: 362 if (cz->cz_ih == NULL) { 363 timeout_set(&cz->cz_timeout, cz_poll, cz); 364 printf("%s: polling mode, %d ms interval\n", 365 cz->cz_dev.dv_xname, CZ_POLL_MS); 366 } 367 368 if (cztty_major == 0) 369 cztty_major = cztty_findmajor(); 370 /* 371 * Allocate sufficient pointers for the children and 372 * attach them. Set all ports to a reasonable initial 373 * configuration while we're at it: 374 * 375 * disabled 376 * 8N1 377 * default baud rate 378 * hardware flow control. 379 */ 380 CZ_WIN_RAM(cz); 381 382 if (cz->cz_nchannels == 0) { 383 /* No channels? No more work to do! */ 384 return; 385 } 386 387 cz->cz_ports = mallocarray(cz->cz_nchannels, 388 sizeof(struct cztty_softc), M_DEVBUF, M_WAITOK | M_ZERO); 389 cztty_attached_ttys += cz->cz_nchannels; 390 391 for (i = 0; i < cz->cz_nchannels; i++) { 392 sc = &cz->cz_ports[i]; 393 394 sc->sc_channel = i; 395 sc->sc_chan_st = cz->cz_win_st; 396 sc->sc_parent = cz; 397 398 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 399 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 400 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 401 printf("%s: unable to subregion channel %d control\n", 402 cz->cz_dev.dv_xname, i); 403 sc->sc_channel = CZTTY_CHANNEL_DEAD; 404 continue; 405 } 406 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 407 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 408 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 409 printf("%s: unable to subregion channel %d buffer\n", 410 cz->cz_dev.dv_xname, i); 411 sc->sc_channel = CZTTY_CHANNEL_DEAD; 412 continue; 413 } 414 415 timeout_set(&sc->sc_diag_to, cztty_diag, sc); 416 417 tp = ttymalloc(0); 418 tp->t_dev = makedev(cztty_major, 419 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 420 tp->t_oproc = czttystart; 421 tp->t_param = czttyparam; 422 423 sc->sc_tty = tp; 424 425 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 426 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 427 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 428 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 429 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 430 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 431 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 432 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 433 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 434 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 435 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 436 } 437 } 438 439 /* 440 * cz_reset_board: 441 * 442 * Reset the board via the PLX. 443 */ 444 void 445 cz_reset_board(struct cz_softc *cz) 446 { 447 u_int32_t reg; 448 449 reg = CZ_PLX_READ(cz, PLX_CONTROL); 450 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 451 delay(1000); 452 453 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 454 delay(1000); 455 456 /* Now reload the PLX from its EEPROM. */ 457 reg = CZ_PLX_READ(cz, PLX_CONTROL); 458 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 459 delay(1000); 460 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 461 } 462 463 /* 464 * cz_load_firmware: 465 * 466 * Load the ZFIRM firmware into the board's RAM and start it 467 * running. 468 */ 469 int 470 cz_load_firmware(struct cz_softc *cz) 471 { 472 struct zfirm_header *zfh; 473 struct zfirm_config *zfc; 474 struct zfirm_block *zfb, *zblocks; 475 const u_int8_t *cp; 476 const char *board; 477 u_int32_t fid; 478 int i, j, nconfigs, nblocks, nbytes; 479 480 zfh = (struct zfirm_header *) cycladesz_firmware; 481 482 /* Find the config header. */ 483 if (letoh32(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 484 printf("%s: bad ZFIRM config offset: 0x%x\n", 485 cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff)); 486 return (EIO); 487 } 488 zfc = (struct zfirm_config *)(cycladesz_firmware + 489 letoh32(zfh->zfh_configoff)); 490 nconfigs = letoh32(zfh->zfh_nconfig); 491 492 /* Locate the correct configuration for our board. */ 493 for (i = 0; i < nconfigs; i++, zfc++) { 494 if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 && 495 letoh32(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 496 break; 497 } 498 if (i == nconfigs) { 499 printf("%s: unable to locate config header\n", 500 cz->cz_dev.dv_xname); 501 return (EIO); 502 } 503 504 nblocks = letoh32(zfc->zfc_nblocks); 505 zblocks = (struct zfirm_block *)(cycladesz_firmware + 506 letoh32(zfh->zfh_blockoff)); 507 508 /* 509 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 510 * necessary. 511 */ 512 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 513 #if 0 514 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 515 #endif 516 ) { 517 #ifdef CZ_DEBUG 518 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 519 #endif 520 CZ_WIN_FPGA(cz); 521 for (i = 0; i < nblocks; i++) { 522 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 523 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 524 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FPGA) { 525 nbytes = letoh32(zfb->zfb_size); 526 cp = &cycladesz_firmware[ 527 letoh32(zfb->zfb_fileoff)]; 528 for (j = 0; j < nbytes; j++, cp++) { 529 bus_space_write_1(cz->cz_win_st, 530 cz->cz_win_sh, 0, *cp); 531 /* FPGA needs 30-100us to settle. */ 532 delay(10); 533 } 534 } 535 } 536 #ifdef CZ_DEBUG 537 printf("done\n"); 538 #endif 539 } 540 541 /* Now load the firmware. */ 542 CZ_WIN_RAM(cz); 543 544 for (i = 0; i < nblocks; i++) { 545 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 546 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 547 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 548 const u_int32_t *lp; 549 u_int32_t ro = letoh32(zfb->zfb_ramoff); 550 nbytes = letoh32(zfb->zfb_size); 551 lp = (const u_int32_t *) 552 &cycladesz_firmware[letoh32(zfb->zfb_fileoff)]; 553 for (j = 0; j < nbytes; j += 4, lp++) { 554 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 555 ro + j, letoh32(*lp)); 556 delay(10); 557 } 558 } 559 } 560 561 /* Now restart the MIPS. */ 562 CZ_WIN_FPGA(cz); 563 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 564 565 /* Wait for the MIPS to start, then report the results. */ 566 CZ_WIN_RAM(cz); 567 568 #ifdef CZ_DEBUG 569 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 570 #endif 571 for (i = 0; i < 100; i++) { 572 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 573 ZFIRM_SIG_OFF); 574 if (fid == ZFIRM_SIG) { 575 /* MIPS has booted. */ 576 break; 577 } else if (fid == ZFIRM_HLT) { 578 /* 579 * The MIPS has halted, usually due to a power 580 * shortage on the expansion module. 581 */ 582 printf("%s: MIPS halted; possible power supply " 583 "problem\n", cz->cz_dev.dv_xname); 584 return (EIO); 585 } else { 586 #ifdef CZ_DEBUG 587 if ((i % 8) == 0) 588 printf("."); 589 #endif 590 delay(250000); 591 } 592 } 593 #ifdef CZ_DEBUG 594 printf("\n"); 595 #endif 596 if (i == 100) { 597 CZ_WIN_FPGA(cz); 598 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 599 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 600 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 601 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 602 CZ_FPGA_READ(cz, FPGA_VERSION)); 603 return (EIO); 604 } 605 606 /* 607 * Locate the firmware control structures. 608 */ 609 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 610 ZFIRM_CTRLADDR_OFF); 611 #ifdef CZ_DEBUG 612 printf("%s: FWCTL structure at offset 0x%08lx\n", 613 cz->cz_dev.dv_xname, cz->cz_fwctl); 614 #endif 615 616 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 617 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 618 619 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 620 621 switch (cz->cz_mailbox0) { 622 case MAILBOX0_8Zo_V1: 623 board = "Cyclades-8Zo ver. 1"; 624 break; 625 626 case MAILBOX0_8Zo_V2: 627 board = "Cyclades-8Zo ver. 2"; 628 break; 629 630 case MAILBOX0_Ze_V1: 631 board = "Cyclades-Ze"; 632 break; 633 634 default: 635 board = "unknown Cyclades Z-series"; 636 break; 637 } 638 639 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 640 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 641 if (cz->cz_nchannels == 0) 642 printf("no channels attached, "); 643 else 644 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 645 cz->cz_nchannels, cztty_attached_ttys, 646 cztty_attached_ttys + (cz->cz_nchannels - 1)); 647 printf("firmware %x.%x.%x\n", 648 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 649 650 return (0); 651 } 652 653 /* 654 * cz_poll: 655 * 656 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 657 * ms. 658 */ 659 void 660 cz_poll(void *arg) 661 { 662 int s = spltty(); 663 struct cz_softc *cz = arg; 664 665 cz_intr(cz); 666 timeout_add_msec(&cz->cz_timeout, CZ_POLL_MS); 667 668 splx(s); 669 } 670 671 /* 672 * cz_intr: 673 * 674 * Interrupt service routine. 675 * 676 * We either are receiving an interrupt directly from the board, or we are 677 * in polling mode and it's time to poll. 678 */ 679 int 680 cz_intr(void *arg) 681 { 682 int rval = 0; 683 u_int command, channel, param; 684 struct cz_softc *cz = arg; 685 struct cztty_softc *sc; 686 struct tty *tp; 687 688 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 689 rval = 1; 690 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 691 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 692 693 /* now clear this interrupt, posslibly enabling another */ 694 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 695 696 if (cz->cz_ports == NULL) { 697 #ifdef CZ_DEBUG 698 printf("%s: interrupt on channel %d, but no channels\n", 699 cz->cz_dev.dv_xname, channel); 700 #endif 701 continue; 702 } 703 704 sc = &cz->cz_ports[channel]; 705 706 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 707 break; 708 709 tp = sc->sc_tty; 710 711 switch (command) { 712 case C_CM_TXFEMPTY: /* transmit cases */ 713 case C_CM_TXBEMPTY: 714 case C_CM_TXLOWWM: 715 case C_CM_INTBACK: 716 if (!ISSET(tp->t_state, TS_ISOPEN)) { 717 #ifdef CZ_DEBUG 718 printf("%s: tx intr on closed channel %d\n", 719 cz->cz_dev.dv_xname, channel); 720 #endif 721 break; 722 } 723 724 if (cztty_transmit(sc, tp)) { 725 /* 726 * Do wakeup stuff here. 727 */ 728 ttwakeup(tp); 729 wakeup(tp); 730 } 731 break; 732 733 case C_CM_RXNNDT: /* receive cases */ 734 case C_CM_RXHIWM: 735 case C_CM_INTBACK2: /* from restart ?? */ 736 #if 0 737 case C_CM_ICHAR: 738 #endif 739 if (!ISSET(tp->t_state, TS_ISOPEN)) { 740 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 741 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 742 break; 743 } 744 745 if (cztty_receive(sc, tp)) { 746 /* 747 * Do wakeup stuff here. 748 */ 749 ttwakeup(tp); 750 wakeup(tp); 751 } 752 break; 753 754 case C_CM_MDCD: 755 if (!ISSET(tp->t_state, TS_ISOPEN)) 756 break; 757 758 (void) (*linesw[tp->t_line].l_modem)(tp, 759 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 760 CHNCTL_RS_STATUS))); 761 break; 762 763 case C_CM_MDSR: 764 case C_CM_MRI: 765 case C_CM_MCTS: 766 case C_CM_MRTS: 767 break; 768 769 case C_CM_IOCTLW: 770 break; 771 772 case C_CM_PR_ERROR: 773 sc->sc_parity_errors++; 774 goto error_common; 775 776 case C_CM_FR_ERROR: 777 sc->sc_framing_errors++; 778 goto error_common; 779 780 case C_CM_OVR_ERROR: 781 sc->sc_overflows++; 782 error_common: 783 if (sc->sc_errors++ == 0) 784 timeout_add_sec(&sc->sc_diag_to, 60); 785 break; 786 787 case C_CM_RXBRK: 788 if (!ISSET(tp->t_state, TS_ISOPEN)) 789 break; 790 791 /* 792 * A break is a \000 character with TTY_FE error 793 * flags set. So TTY_FE by itself works. 794 */ 795 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 796 ttwakeup(tp); 797 wakeup(tp); 798 break; 799 800 default: 801 #ifdef CZ_DEBUG 802 printf("%s: channel %d: Unknown interrupt 0x%x\n", 803 cz->cz_dev.dv_xname, sc->sc_channel, command); 804 #endif 805 break; 806 } 807 } 808 809 return (rval); 810 } 811 812 /* 813 * cz_wait_pci_doorbell: 814 * 815 * Wait for the pci doorbell to be clear - wait for pending 816 * activity to drain. 817 */ 818 int 819 cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring) 820 { 821 int error; 822 823 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 824 error = tsleep_nsec(cz, TTIPRI | PCATCH, wstring, 825 MSEC_TO_NSEC(10)); 826 if ((error != 0) && (error != EWOULDBLOCK)) 827 return (error); 828 } 829 return (0); 830 } 831 832 /***************************************************************************** 833 * Cyclades-Z TTY code starts here... 834 *****************************************************************************/ 835 836 #define CZTTYDIALOUT_MASK 0x80 837 838 #define CZTTY_CZ(sc) ((sc)->sc_parent) 839 840 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 841 842 struct cztty_softc * 843 cztty_getttysoftc(dev_t dev) 844 { 845 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 846 struct cz_softc *cz; 847 848 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 849 k = j; 850 cz = (struct cz_softc *)device_lookup(&cz_cd, i); 851 if (cz == NULL) 852 continue; 853 if (cz->cz_ports == NULL) 854 continue; 855 j += cz->cz_nchannels; 856 if (j > u) 857 break; 858 } 859 860 if (i >= cz_cd.cd_ndevs) 861 return (NULL); 862 else 863 return (&cz->cz_ports[u - k]); 864 } 865 866 int 867 cztty_findmajor(void) 868 { 869 int maj; 870 871 for (maj = 0; maj < nchrdev; maj++) { 872 if (cdevsw[maj].d_open == czttyopen) 873 break; 874 } 875 876 return (maj == nchrdev) ? 0 : maj; 877 } 878 879 /* 880 * czttytty: 881 * 882 * Return a pointer to our tty. 883 */ 884 struct tty * 885 czttytty(dev_t dev) 886 { 887 struct cztty_softc *sc = CZTTY_SOFTC(dev); 888 889 #ifdef DIAGNOSTIC 890 if (sc == NULL) 891 panic("czttytty"); 892 #endif 893 894 return (sc->sc_tty); 895 } 896 897 /* 898 * cztty_shutdown: 899 * 900 * Shut down a port. 901 */ 902 void 903 cztty_shutdown(struct cztty_softc *sc) 904 { 905 struct cz_softc *cz = CZTTY_CZ(sc); 906 struct tty *tp = sc->sc_tty; 907 int s; 908 909 s = spltty(); 910 911 /* Clear any break condition set with TIOCSBRK. */ 912 cztty_break(sc, 0); 913 914 /* 915 * Hang up if necessary. Wait a bit, so the other side has time to 916 * notice even if we immediately open the port again. 917 */ 918 if (ISSET(tp->t_cflag, HUPCL)) { 919 cztty_modem(sc, 0); 920 tsleep_nsec(tp, TTIPRI, ttclos, SEC_TO_NSEC(1)); 921 } 922 923 /* Disable the channel. */ 924 cz_wait_pci_doorbell(cz, "czdis"); 925 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 926 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 927 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 928 929 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 930 #ifdef CZ_DEBUG 931 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 932 #endif 933 timeout_del(&cz->cz_timeout); 934 } 935 936 splx(s); 937 } 938 939 /* 940 * czttyopen: 941 * 942 * Open a Cyclades-Z serial port. 943 */ 944 int 945 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 946 { 947 struct cztty_softc *sc = CZTTY_SOFTC(dev); 948 struct cz_softc *cz; 949 struct tty *tp; 950 int s, error; 951 952 if (sc == NULL) 953 return (ENXIO); 954 955 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 956 return (ENXIO); 957 958 cz = CZTTY_CZ(sc); 959 tp = sc->sc_tty; 960 961 if (ISSET(tp->t_state, TS_ISOPEN) && 962 ISSET(tp->t_state, TS_XCLUDE) && 963 suser(p) != 0) 964 return (EBUSY); 965 966 s = spltty(); 967 968 /* 969 * Do the following iff this is a first open. 970 */ 971 if (!ISSET(tp->t_state, TS_ISOPEN)) { 972 struct termios t; 973 974 tp->t_dev = dev; 975 976 /* If we're turning things on, enable interrupts */ 977 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 978 #ifdef CZ_DEBUG 979 printf("%s: Enabling polling.\n", 980 cz->cz_dev.dv_xname); 981 #endif 982 timeout_add_msec(&cz->cz_timeout, CZ_POLL_MS); 983 } 984 985 /* 986 * Enable the channel. Don't actually ring the 987 * doorbell here; czttyparam() will do it for us. 988 */ 989 cz_wait_pci_doorbell(cz, "czopen"); 990 991 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 992 993 /* 994 * Initialize the termios status to the defaults. Add in the 995 * sticky bits from TIOCSFLAGS. 996 */ 997 t.c_ispeed = 0; 998 t.c_ospeed = TTYDEF_SPEED; 999 t.c_cflag = TTYDEF_CFLAG; 1000 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1001 SET(t.c_cflag, CLOCAL); 1002 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1003 SET(t.c_cflag, CRTSCTS); 1004 1005 /* 1006 * Reset the input and output rings. Do this before 1007 * we call czttyparam(), as that function enables 1008 * the channel. 1009 */ 1010 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1011 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1012 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1013 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1014 1015 /* Make sure czttyparam() will see changes. */ 1016 tp->t_ospeed = 0; 1017 (void) czttyparam(tp, &t); 1018 tp->t_iflag = TTYDEF_IFLAG; 1019 tp->t_oflag = TTYDEF_OFLAG; 1020 tp->t_lflag = TTYDEF_LFLAG; 1021 ttychars(tp); 1022 ttsetwater(tp); 1023 1024 /* 1025 * Turn on DTR. We must always do this, even if carrier is not 1026 * present, because otherwise we'd have to use TIOCSDTR 1027 * immediately after setting CLOCAL, which applications do not 1028 * expect. We always assert DTR while the device is open 1029 * unless explicitly requested to deassert it. 1030 */ 1031 cztty_modem(sc, 1); 1032 } 1033 1034 splx(s); 1035 1036 error = (*linesw[tp->t_line].l_open)(dev, tp, p); 1037 if (error) 1038 goto bad; 1039 1040 return (0); 1041 1042 bad: 1043 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1044 /* 1045 * We failed to open the device, and nobody else had it opened. 1046 * Clean up the state as appropriate. 1047 */ 1048 cztty_shutdown(sc); 1049 } 1050 1051 return (error); 1052 } 1053 1054 /* 1055 * czttyclose: 1056 * 1057 * Close a Cyclades-Z serial port. 1058 */ 1059 int 1060 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1061 { 1062 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1063 struct tty *tp = sc->sc_tty; 1064 1065 /* XXX This is for cons.c. */ 1066 if (!ISSET(tp->t_state, TS_ISOPEN)) 1067 return (0); 1068 1069 (*linesw[tp->t_line].l_close)(tp, flags, p); 1070 ttyclose(tp); 1071 1072 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1073 /* 1074 * Although we got a last close, the device may still be in 1075 * use; e.g. if this was the dialout node, and there are still 1076 * processes waiting for carrier on the non-dialout node. 1077 */ 1078 cztty_shutdown(sc); 1079 } 1080 1081 return (0); 1082 } 1083 1084 /* 1085 * czttyread: 1086 * 1087 * Read from a Cyclades-Z serial port. 1088 */ 1089 int 1090 czttyread(dev_t dev, struct uio *uio, int flags) 1091 { 1092 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1093 struct tty *tp = sc->sc_tty; 1094 1095 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1096 } 1097 1098 /* 1099 * czttywrite: 1100 * 1101 * Write to a Cyclades-Z serial port. 1102 */ 1103 int 1104 czttywrite(dev_t dev, struct uio *uio, int flags) 1105 { 1106 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1107 struct tty *tp = sc->sc_tty; 1108 1109 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1110 } 1111 1112 /* 1113 * czttyioctl: 1114 * 1115 * Perform a control operation on a Cyclades-Z serial port. 1116 */ 1117 int 1118 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1119 { 1120 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1121 struct tty *tp = sc->sc_tty; 1122 int s, error; 1123 1124 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1125 if (error >= 0) 1126 return (error); 1127 1128 error = ttioctl(tp, cmd, data, flag, p); 1129 if (error >= 0) 1130 return (error); 1131 1132 error = 0; 1133 1134 s = spltty(); 1135 1136 switch (cmd) { 1137 case TIOCSBRK: 1138 cztty_break(sc, 1); 1139 break; 1140 1141 case TIOCCBRK: 1142 cztty_break(sc, 0); 1143 break; 1144 1145 case TIOCGFLAGS: 1146 *(int *)data = sc->sc_swflags; 1147 break; 1148 1149 case TIOCSFLAGS: 1150 error = suser(p); 1151 if (error) 1152 break; 1153 sc->sc_swflags = *(int *)data; 1154 break; 1155 1156 case TIOCSDTR: 1157 cztty_modem(sc, 1); 1158 break; 1159 1160 case TIOCCDTR: 1161 cztty_modem(sc, 0); 1162 break; 1163 1164 case TIOCMSET: 1165 case TIOCMBIS: 1166 case TIOCMBIC: 1167 tiocm_to_cztty(sc, cmd, *(int *)data); 1168 break; 1169 1170 case TIOCMGET: 1171 *(int *)data = cztty_to_tiocm(sc); 1172 break; 1173 1174 default: 1175 error = ENOTTY; 1176 break; 1177 } 1178 1179 splx(s); 1180 1181 return (error); 1182 } 1183 1184 /* 1185 * cztty_break: 1186 * 1187 * Set or clear BREAK on a port. 1188 */ 1189 void 1190 cztty_break(struct cztty_softc *sc, int onoff) 1191 { 1192 struct cz_softc *cz = CZTTY_CZ(sc); 1193 1194 cz_wait_pci_doorbell(cz, "czbreak"); 1195 1196 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1197 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1198 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1199 } 1200 1201 /* 1202 * cztty_modem: 1203 * 1204 * Set or clear DTR on a port. 1205 */ 1206 void 1207 cztty_modem(struct cztty_softc *sc, int onoff) 1208 { 1209 struct cz_softc *cz = CZTTY_CZ(sc); 1210 1211 if (sc->sc_rs_control_dtr == 0) 1212 return; 1213 1214 cz_wait_pci_doorbell(cz, "czmod"); 1215 1216 if (onoff) 1217 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1218 else 1219 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1220 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1221 1222 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1223 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1224 } 1225 1226 /* 1227 * tiocm_to_cztty: 1228 * 1229 * Process TIOCM* ioctls. 1230 */ 1231 void 1232 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1233 { 1234 struct cz_softc *cz = CZTTY_CZ(sc); 1235 u_int32_t czttybits; 1236 1237 czttybits = 0; 1238 if (ISSET(ttybits, TIOCM_DTR)) 1239 SET(czttybits, C_RS_DTR); 1240 if (ISSET(ttybits, TIOCM_RTS)) 1241 SET(czttybits, C_RS_RTS); 1242 1243 cz_wait_pci_doorbell(cz, "cztiocm"); 1244 1245 switch (how) { 1246 case TIOCMBIC: 1247 CLR(sc->sc_chanctl_rs_control, czttybits); 1248 break; 1249 1250 case TIOCMBIS: 1251 SET(sc->sc_chanctl_rs_control, czttybits); 1252 break; 1253 1254 case TIOCMSET: 1255 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1256 SET(sc->sc_chanctl_rs_control, czttybits); 1257 break; 1258 } 1259 1260 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1261 1262 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1263 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1264 } 1265 1266 /* 1267 * cztty_to_tiocm: 1268 * 1269 * Process the TIOCMGET ioctl. 1270 */ 1271 int 1272 cztty_to_tiocm(struct cztty_softc *sc) 1273 { 1274 struct cz_softc *cz = CZTTY_CZ(sc); 1275 u_int32_t rs_status, op_mode; 1276 int ttybits = 0; 1277 1278 cz_wait_pci_doorbell(cz, "cztty"); 1279 1280 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1281 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1282 1283 if (ISSET(rs_status, C_RS_RTS)) 1284 SET(ttybits, TIOCM_RTS); 1285 if (ISSET(rs_status, C_RS_CTS)) 1286 SET(ttybits, TIOCM_CTS); 1287 if (ISSET(rs_status, C_RS_DCD)) 1288 SET(ttybits, TIOCM_CAR); 1289 if (ISSET(rs_status, C_RS_DTR)) 1290 SET(ttybits, TIOCM_DTR); 1291 if (ISSET(rs_status, C_RS_RI)) 1292 SET(ttybits, TIOCM_RNG); 1293 if (ISSET(rs_status, C_RS_DSR)) 1294 SET(ttybits, TIOCM_DSR); 1295 1296 if (ISSET(op_mode, C_CH_ENABLE)) 1297 SET(ttybits, TIOCM_LE); 1298 1299 return (ttybits); 1300 } 1301 1302 /* 1303 * czttyparam: 1304 * 1305 * Set Cyclades-Z serial port parameters from termios. 1306 * 1307 * XXX Should just copy the whole termios after making 1308 * XXX sure all the changes could be done. 1309 */ 1310 int 1311 czttyparam(struct tty *tp, struct termios *t) 1312 { 1313 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1314 struct cz_softc *cz = CZTTY_CZ(sc); 1315 u_int32_t rs_status; 1316 int ospeed, cflag; 1317 1318 ospeed = t->c_ospeed; 1319 cflag = t->c_cflag; 1320 1321 /* Check requested parameters. */ 1322 if (ospeed < 0) 1323 return (EINVAL); 1324 if (t->c_ispeed && t->c_ispeed != ospeed) 1325 return (EINVAL); 1326 1327 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1328 SET(cflag, CLOCAL); 1329 CLR(cflag, HUPCL); 1330 } 1331 1332 /* 1333 * If there were no changes, don't do anything. This avoids dropping 1334 * input and improves performance when all we did was frob things like 1335 * VMIN and VTIME. 1336 */ 1337 if (tp->t_ospeed == ospeed && 1338 tp->t_cflag == cflag) 1339 return (0); 1340 1341 /* Data bits. */ 1342 sc->sc_chanctl_comm_data_l = 0; 1343 switch (t->c_cflag & CSIZE) { 1344 case CS5: 1345 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1346 break; 1347 1348 case CS6: 1349 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1350 break; 1351 1352 case CS7: 1353 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1354 break; 1355 1356 case CS8: 1357 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1358 break; 1359 } 1360 1361 /* Stop bits. */ 1362 if (t->c_cflag & CSTOPB) { 1363 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1364 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1365 else 1366 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1367 } else 1368 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1369 1370 /* Parity. */ 1371 if (t->c_cflag & PARENB) { 1372 if (t->c_cflag & PARODD) 1373 sc->sc_chanctl_comm_parity = C_PR_ODD; 1374 else 1375 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1376 } else 1377 sc->sc_chanctl_comm_parity = C_PR_NONE; 1378 1379 /* 1380 * Initialize flow control pins depending on the current flow control 1381 * mode. 1382 */ 1383 if (ISSET(t->c_cflag, CRTSCTS)) { 1384 sc->sc_rs_control_dtr = C_RS_DTR; 1385 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1386 } else if (ISSET(t->c_cflag, MDMBUF)) { 1387 sc->sc_rs_control_dtr = 0; 1388 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1389 } else { 1390 /* 1391 * If no flow control, then always set RTS. This will make 1392 * the other side happy if it mistakenly thinks we're doing 1393 * RTS/CTS flow control. 1394 */ 1395 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1396 sc->sc_chanctl_hw_flow = 0; 1397 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1398 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1399 else 1400 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1401 } 1402 1403 /* Baud rate. */ 1404 sc->sc_chanctl_comm_baud = ospeed; 1405 1406 /* Copy to tty. */ 1407 tp->t_ispeed = 0; 1408 tp->t_ospeed = t->c_ospeed; 1409 tp->t_cflag = t->c_cflag; 1410 1411 /* 1412 * Now load the channel control structure. 1413 */ 1414 1415 cz_wait_pci_doorbell(cz, "czparam"); 1416 1417 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1418 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1419 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1420 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1421 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1422 1423 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1424 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1425 1426 cz_wait_pci_doorbell(cz, "czparam"); 1427 1428 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1429 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1430 1431 cz_wait_pci_doorbell(cz, "czparam"); 1432 1433 /* 1434 * Update the tty layer's idea of the carrier bit, in case we changed 1435 * CLOCAL. We don't hang up here; we only do that by explicit 1436 * request. 1437 */ 1438 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1439 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1440 1441 return (0); 1442 } 1443 1444 /* 1445 * czttystart: 1446 * 1447 * Start or restart transmission. 1448 */ 1449 void 1450 czttystart(struct tty *tp) 1451 { 1452 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1453 int s; 1454 1455 s = spltty(); 1456 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1457 goto out; 1458 1459 ttwakeupwr(tp); 1460 if (tp->t_outq.c_cc == 0) 1461 goto out; 1462 1463 cztty_transmit(sc, tp); 1464 out: 1465 splx(s); 1466 } 1467 1468 /* 1469 * czttystop: 1470 * 1471 * Stop output, e.g., for ^S or output flush. 1472 */ 1473 int 1474 czttystop(struct tty *tp, int flag) 1475 { 1476 1477 /* 1478 * XXX We don't do anything here, yet. Mostly, I don't know 1479 * XXX exactly how this should be implemented on this device. 1480 * XXX We've given a big chunk of data to the MIPS already, 1481 * XXX and I don't know how we request the MIPS to stop sending 1482 * XXX the data. So, punt for now. --thorpej 1483 */ 1484 return (0); 1485 } 1486 1487 /* 1488 * cztty_diag: 1489 * 1490 * Issue a scheduled diagnostic message. 1491 */ 1492 void 1493 cztty_diag(void *arg) 1494 { 1495 struct cztty_softc *sc = arg; 1496 struct cz_softc *cz = CZTTY_CZ(sc); 1497 u_int overflows, parity_errors, framing_errors; 1498 int s; 1499 1500 s = spltty(); 1501 1502 overflows = sc->sc_overflows; 1503 sc->sc_overflows = 0; 1504 1505 parity_errors = sc->sc_parity_errors; 1506 sc->sc_parity_errors = 0; 1507 1508 framing_errors = sc->sc_framing_errors; 1509 sc->sc_framing_errors = 0; 1510 1511 sc->sc_errors = 0; 1512 1513 splx(s); 1514 1515 log(LOG_WARNING, 1516 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1517 cz->cz_dev.dv_xname, sc->sc_channel, 1518 overflows, overflows == 1 ? "" : "s", 1519 parity_errors, 1520 framing_errors, framing_errors == 1 ? "" : "s"); 1521 } 1522 1523 /* 1524 * tx and rx ring buffer size macros: 1525 * 1526 * The transmitter and receiver both use ring buffers. For each one, there 1527 * is a get (consumer) and a put (producer) offset. The get value is the 1528 * next byte to be read from the ring, and the put is the next one to be 1529 * put into the ring. get == put means the ring is empty. 1530 * 1531 * For each ring, the firmware controls one of (get, put) and this driver 1532 * controls the other. For transmission, this driver updates put to point 1533 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1534 * for receive, the driver controls put, and this driver controls get. 1535 */ 1536 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1537 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1538 1539 /* 1540 * cztty_transmit() 1541 * 1542 * Look at the tty for this port and start sending. 1543 */ 1544 int 1545 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1546 { 1547 struct cz_softc *cz = CZTTY_CZ(sc); 1548 u_int move, get, put, size, address; 1549 #ifdef HOSTRAMCODE 1550 int error, done = 0; 1551 #else 1552 int done = 0; 1553 #endif 1554 1555 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1556 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1557 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1558 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1559 1560 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1561 #ifdef HOSTRAMCODE 1562 if (0) { 1563 move = min(tp->t_outq.c_cc, move); 1564 error = q_to_b(&tp->t_outq, 0, move); 1565 if (error != move) { 1566 printf("%s: channel %d: error moving to " 1567 "transmit buf\n", cz->cz_dev.dv_xname, 1568 sc->sc_channel); 1569 move = error; 1570 } 1571 } else { 1572 #endif 1573 move = min(ndqb(&tp->t_outq, 0), move); 1574 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1575 address + put, tp->t_outq.c_cf, move); 1576 ndflush(&tp->t_outq, move); 1577 #ifdef HOSTRAMCODE 1578 } 1579 #endif 1580 1581 put = ((put + move) % size); 1582 done = 1; 1583 } 1584 if (done) { 1585 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1586 } 1587 return (done); 1588 } 1589 1590 int 1591 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1592 { 1593 struct cz_softc *cz = CZTTY_CZ(sc); 1594 u_int get, put, size, address; 1595 int done = 0, ch; 1596 1597 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1598 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1599 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1600 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1601 1602 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1603 #ifdef HOSTRAMCODE 1604 if (hostram) 1605 ch = ((char *)fifoaddr)[get]; 1606 } else { 1607 #endif 1608 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1609 address + get); 1610 #ifdef HOSTRAMCODE 1611 } 1612 #endif 1613 (*linesw[tp->t_line].l_rint)(ch, tp); 1614 get = (get + 1) % size; 1615 done = 1; 1616 } 1617 if (done) { 1618 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1619 } 1620 return (done); 1621 } 1622