1 /* $OpenBSD: cz.c,v 1.20 2014/07/13 23:10:23 deraadt Exp $ */ 2 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Zembu Labs, Inc. 6 * All rights reserved. 7 * 8 * Authors: Jason R. Thorpe <thorpej@zembu.com> 9 * Bill Studenmund <wrstuden@zembu.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Zembu Labs, Inc. 22 * 4. Neither the name of Zembu Labs nor the names of its employees may 23 * be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 28 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 29 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 40 * 41 * Some notes: 42 * 43 * - The Cyclades-Z has fully automatic hardware (and software!) 44 * flow control. We only utilize RTS/CTS flow control here, 45 * and it is implemented in a very simplistic manner. This 46 * may be an area of future work. 47 * 48 * - The PLX can map the either the board's RAM or host RAM 49 * into the MIPS's memory window. This would enable us to 50 * use less expensive (for us) memory reads/writes to host 51 * RAM, rather than time-consuming reads/writes to PCI 52 * memory space. However, the PLX can only map a 0-128M 53 * window, so we would have to ensure that the DMA address 54 * of the host RAM fits there. This is kind of a pain, 55 * so we just don't bother right now. 56 * 57 * - In a perfect world, we would use the autoconfiguration 58 * mechanism to attach the TTYs that we find. However, 59 * that leads to somewhat icky looking autoconfiguration 60 * messages (one for every TTY, up to 64 per board!). So 61 * we don't do it that way, but assign minors as if there 62 * were the max of 64 ports per board. 63 * 64 * - We don't bother with PPS support here. There are so many 65 * ports, each with a large amount of buffer space, that the 66 * normal mode of operation is to poll the boards regularly 67 * (generally, every 20ms or so). This makes this driver 68 * unsuitable for PPS, as the latency will be generally too 69 * high. 70 */ 71 /* 72 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 73 * for FreeBSD 3.2. 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/proc.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/tty.h> 82 #include <sys/conf.h> 83 #include <sys/time.h> 84 #include <sys/kernel.h> 85 #include <sys/fcntl.h> 86 #include <sys/syslog.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/pci/czreg.h> 92 93 #include <dev/pci/plx9060reg.h> 94 #include <dev/pci/plx9060var.h> 95 96 #include <dev/microcode/cyclades/cyzfirm.h> 97 98 #define CZ_DRIVER_VERSION 0x20000411 99 100 #define CZ_POLL_MS 20 101 102 /* These are the interrupts we always use. */ 103 #define CZ_INTERRUPTS \ 104 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 105 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 106 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 107 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 108 109 /* 110 * cztty_softc: 111 * 112 * Per-channel (TTY) state. 113 */ 114 struct cztty_softc { 115 struct cz_softc *sc_parent; 116 struct tty *sc_tty; 117 118 struct timeout sc_diag_to; 119 120 int sc_channel; /* Also used to flag unattached chan */ 121 #define CZTTY_CHANNEL_DEAD -1 122 123 bus_space_tag_t sc_chan_st; /* channel space tag */ 124 bus_space_handle_t sc_chan_sh; /* channel space handle */ 125 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 126 127 u_int sc_overflows, 128 sc_parity_errors, 129 sc_framing_errors, 130 sc_errors; 131 132 int sc_swflags; 133 134 u_int32_t sc_rs_control_dtr, 135 sc_chanctl_hw_flow, 136 sc_chanctl_comm_baud, 137 sc_chanctl_rs_control, 138 sc_chanctl_comm_data_l, 139 sc_chanctl_comm_parity; 140 }; 141 142 /* 143 * cz_softc: 144 * 145 * Per-board state. 146 */ 147 struct cz_softc { 148 struct device cz_dev; /* generic device info */ 149 struct plx9060_config cz_plx; /* PLX 9060 config info */ 150 bus_space_tag_t cz_win_st; /* window space tag */ 151 bus_space_handle_t cz_win_sh; /* window space handle */ 152 struct timeout cz_timeout; /* timeout for polling-mode */ 153 154 void *cz_ih; /* interrupt handle */ 155 156 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 157 int cz_nchannels; /* number of channels */ 158 int cz_nopenchan; /* number of open channels */ 159 struct cztty_softc *cz_ports; /* our array of ports */ 160 161 bus_addr_t cz_fwctl; /* offset of firmware control */ 162 }; 163 164 int cz_match(struct device *, void *, void *); 165 void cz_attach(struct device *, struct device *, void *); 166 int cz_wait_pci_doorbell(struct cz_softc *, char *); 167 168 struct cfattach cz_ca = { 169 sizeof(struct cz_softc), cz_match, cz_attach 170 }; 171 172 void cz_reset_board(struct cz_softc *); 173 int cz_load_firmware(struct cz_softc *); 174 175 int cz_intr(void *); 176 void cz_poll(void *); 177 int cztty_transmit(struct cztty_softc *, struct tty *); 178 int cztty_receive(struct cztty_softc *, struct tty *); 179 180 struct cztty_softc * cztty_getttysoftc(dev_t dev); 181 int cztty_findmajor(void); 182 int cztty_major; 183 int cztty_attached_ttys; 184 int cz_timeout_ticks; 185 186 cdev_decl(cztty); 187 188 void czttystart(struct tty *tp); 189 int czttyparam(struct tty *tp, struct termios *t); 190 void cztty_shutdown(struct cztty_softc *sc); 191 void cztty_modem(struct cztty_softc *sc, int onoff); 192 void cztty_break(struct cztty_softc *sc, int onoff); 193 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 194 int cztty_to_tiocm(struct cztty_softc *sc); 195 void cztty_diag(void *arg); 196 197 struct cfdriver cz_cd = { 198 0, "cz", DV_TTY 199 }; 200 201 /* 202 * Macros to read and write the PLX. 203 */ 204 #define CZ_PLX_READ(cz, reg) \ 205 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 206 #define CZ_PLX_WRITE(cz, reg, val) \ 207 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 208 (reg), (val)) 209 210 /* 211 * Macros to read and write the FPGA. We must already be in the FPGA 212 * window for this. 213 */ 214 #define CZ_FPGA_READ(cz, reg) \ 215 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 216 #define CZ_FPGA_WRITE(cz, reg, val) \ 217 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 218 219 /* 220 * Macros to read and write the firmware control structures in board RAM. 221 */ 222 #define CZ_FWCTL_READ(cz, off) \ 223 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 224 (cz)->cz_fwctl + (off)) 225 226 #define CZ_FWCTL_WRITE(cz, off, val) \ 227 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 228 (cz)->cz_fwctl + (off), (val)) 229 230 /* 231 * Convenience macros for cztty routines. PLX window MUST be to RAM. 232 */ 233 #define CZTTY_CHAN_READ(sc, off) \ 234 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 235 236 #define CZTTY_CHAN_WRITE(sc, off, val) \ 237 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 238 (off), (val)) 239 240 #define CZTTY_BUF_READ(sc, off) \ 241 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 242 243 #define CZTTY_BUF_WRITE(sc, off, val) \ 244 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 245 (off), (val)) 246 247 /* 248 * Convenience macros. 249 */ 250 #define CZ_WIN_RAM(cz) \ 251 do { \ 252 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 253 delay(100); \ 254 } while (0) 255 256 #define CZ_WIN_FPGA(cz) \ 257 do { \ 258 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 259 delay(100); \ 260 } while (0) 261 262 /***************************************************************************** 263 * Cyclades-Z controller code starts here... 264 *****************************************************************************/ 265 266 /* 267 * cz_match: 268 * 269 * Determine if the given PCI device is a Cyclades-Z board. 270 */ 271 int 272 cz_match(parent, match, aux) 273 struct device *parent; 274 void *match, *aux; 275 { 276 struct pci_attach_args *pa = aux; 277 278 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES && 279 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CYCLADES_CYCLOMZ_2) 280 return (1); 281 return (0); 282 } 283 284 /* 285 * cz_attach: 286 * 287 * A Cyclades-Z board was found; attach it. 288 */ 289 void 290 cz_attach(parent, self, aux) 291 struct device *parent, *self; 292 void *aux; 293 { 294 struct cz_softc *cz = (void *) self; 295 struct pci_attach_args *pa = aux; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const char *intrstr = NULL; 299 struct cztty_softc *sc; 300 struct tty *tp; 301 int i; 302 303 cz->cz_plx.plx_pc = pa->pa_pc; 304 cz->cz_plx.plx_tag = pa->pa_tag; 305 306 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 307 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 308 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) { 309 printf(": unable to map PLX registers\n"); 310 return; 311 } 312 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 313 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 314 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) { 315 printf(": unable to map device window\n"); 316 return; 317 } 318 319 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 320 cz->cz_nopenchan = 0; 321 322 /* 323 * Make sure that the board is completely stopped. 324 */ 325 CZ_WIN_FPGA(cz); 326 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 327 328 /* 329 * Load the board's firmware. 330 */ 331 if (cz_load_firmware(cz) != 0) 332 return; 333 334 /* 335 * Now that we're ready to roll, map and establish the interrupt 336 * handler. 337 */ 338 if (pci_intr_map(pa, &ih) != 0) { 339 /* 340 * The common case is for Cyclades-Z boards to run 341 * in polling mode, and thus not have an interrupt 342 * mapped for them. Don't bother reporting that 343 * the interrupt is not mappable, since this isn't 344 * really an error. 345 */ 346 cz->cz_ih = NULL; 347 goto polling_mode; 348 } else { 349 intrstr = pci_intr_string(pa->pa_pc, ih); 350 cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY, 351 cz_intr, cz, cz->cz_dev.dv_xname); 352 } 353 if (cz->cz_ih == NULL) { 354 printf(": unable to establish interrupt"); 355 if (intrstr != NULL) 356 printf(" at %s", intrstr); 357 printf("\n"); 358 /* We will fall-back on polling mode. */ 359 } else 360 printf(": %s\n", intrstr); 361 362 polling_mode: 363 if (cz->cz_ih == NULL) { 364 timeout_set(&cz->cz_timeout, cz_poll, cz); 365 if (cz_timeout_ticks == 0) 366 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 367 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 368 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 369 cz_timeout_ticks == 1 ? "" : "s"); 370 } 371 372 if (cztty_major == 0) 373 cztty_major = cztty_findmajor(); 374 /* 375 * Allocate sufficient pointers for the children and 376 * attach them. Set all ports to a reasonable initial 377 * configuration while we're at it: 378 * 379 * disabled 380 * 8N1 381 * default baud rate 382 * hardware flow control. 383 */ 384 CZ_WIN_RAM(cz); 385 386 if (cz->cz_nchannels == 0) { 387 /* No channels? No more work to do! */ 388 return; 389 } 390 391 cz->cz_ports = mallocarray(cz->cz_nchannels, 392 sizeof(struct cztty_softc), M_DEVBUF, M_WAITOK | M_ZERO); 393 cztty_attached_ttys += cz->cz_nchannels; 394 395 for (i = 0; i < cz->cz_nchannels; i++) { 396 sc = &cz->cz_ports[i]; 397 398 sc->sc_channel = i; 399 sc->sc_chan_st = cz->cz_win_st; 400 sc->sc_parent = cz; 401 402 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 403 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 404 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 405 printf("%s: unable to subregion channel %d control\n", 406 cz->cz_dev.dv_xname, i); 407 sc->sc_channel = CZTTY_CHANNEL_DEAD; 408 continue; 409 } 410 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 411 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 412 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 413 printf("%s: unable to subregion channel %d buffer\n", 414 cz->cz_dev.dv_xname, i); 415 sc->sc_channel = CZTTY_CHANNEL_DEAD; 416 continue; 417 } 418 419 timeout_set(&sc->sc_diag_to, cztty_diag, sc); 420 421 tp = ttymalloc(0); 422 tp->t_dev = makedev(cztty_major, 423 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 424 tp->t_oproc = czttystart; 425 tp->t_param = czttyparam; 426 427 sc->sc_tty = tp; 428 429 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 430 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 431 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 432 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 433 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 434 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 435 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 436 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 437 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 438 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 439 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 440 } 441 } 442 443 /* 444 * cz_reset_board: 445 * 446 * Reset the board via the PLX. 447 */ 448 void 449 cz_reset_board(struct cz_softc *cz) 450 { 451 u_int32_t reg; 452 453 reg = CZ_PLX_READ(cz, PLX_CONTROL); 454 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 455 delay(1000); 456 457 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 458 delay(1000); 459 460 /* Now reload the PLX from its EEPROM. */ 461 reg = CZ_PLX_READ(cz, PLX_CONTROL); 462 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 463 delay(1000); 464 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 465 } 466 467 /* 468 * cz_load_firmware: 469 * 470 * Load the ZFIRM firmware into the board's RAM and start it 471 * running. 472 */ 473 int 474 cz_load_firmware(struct cz_softc *cz) 475 { 476 struct zfirm_header *zfh; 477 struct zfirm_config *zfc; 478 struct zfirm_block *zfb, *zblocks; 479 const u_int8_t *cp; 480 const char *board; 481 u_int32_t fid; 482 int i, j, nconfigs, nblocks, nbytes; 483 484 zfh = (struct zfirm_header *) cycladesz_firmware; 485 486 /* Find the config header. */ 487 if (letoh32(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 488 printf("%s: bad ZFIRM config offset: 0x%x\n", 489 cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff)); 490 return (EIO); 491 } 492 zfc = (struct zfirm_config *)(cycladesz_firmware + 493 letoh32(zfh->zfh_configoff)); 494 nconfigs = letoh32(zfh->zfh_nconfig); 495 496 /* Locate the correct configuration for our board. */ 497 for (i = 0; i < nconfigs; i++, zfc++) { 498 if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 && 499 letoh32(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 500 break; 501 } 502 if (i == nconfigs) { 503 printf("%s: unable to locate config header\n", 504 cz->cz_dev.dv_xname); 505 return (EIO); 506 } 507 508 nblocks = letoh32(zfc->zfc_nblocks); 509 zblocks = (struct zfirm_block *)(cycladesz_firmware + 510 letoh32(zfh->zfh_blockoff)); 511 512 /* 513 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 514 * necessary. 515 */ 516 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 517 #if 0 518 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 519 #endif 520 ) { 521 #ifdef CZ_DEBUG 522 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 523 #endif 524 CZ_WIN_FPGA(cz); 525 for (i = 0; i < nblocks; i++) { 526 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 527 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 528 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FPGA) { 529 nbytes = letoh32(zfb->zfb_size); 530 cp = &cycladesz_firmware[ 531 letoh32(zfb->zfb_fileoff)]; 532 for (j = 0; j < nbytes; j++, cp++) { 533 bus_space_write_1(cz->cz_win_st, 534 cz->cz_win_sh, 0, *cp); 535 /* FPGA needs 30-100us to settle. */ 536 delay(10); 537 } 538 } 539 } 540 #ifdef CZ_DEBUG 541 printf("done\n"); 542 #endif 543 } 544 545 /* Now load the firmware. */ 546 CZ_WIN_RAM(cz); 547 548 for (i = 0; i < nblocks; i++) { 549 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 550 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 551 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 552 const u_int32_t *lp; 553 u_int32_t ro = letoh32(zfb->zfb_ramoff); 554 nbytes = letoh32(zfb->zfb_size); 555 lp = (const u_int32_t *) 556 &cycladesz_firmware[letoh32(zfb->zfb_fileoff)]; 557 for (j = 0; j < nbytes; j += 4, lp++) { 558 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 559 ro + j, letoh32(*lp)); 560 delay(10); 561 } 562 } 563 } 564 565 /* Now restart the MIPS. */ 566 CZ_WIN_FPGA(cz); 567 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 568 569 /* Wait for the MIPS to start, then report the results. */ 570 CZ_WIN_RAM(cz); 571 572 #ifdef CZ_DEBUG 573 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 574 #endif 575 for (i = 0; i < 100; i++) { 576 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 577 ZFIRM_SIG_OFF); 578 if (fid == ZFIRM_SIG) { 579 /* MIPS has booted. */ 580 break; 581 } else if (fid == ZFIRM_HLT) { 582 /* 583 * The MIPS has halted, usually due to a power 584 * shortage on the expansion module. 585 */ 586 printf("%s: MIPS halted; possible power supply " 587 "problem\n", cz->cz_dev.dv_xname); 588 return (EIO); 589 } else { 590 #ifdef CZ_DEBUG 591 if ((i % 8) == 0) 592 printf("."); 593 #endif 594 delay(250000); 595 } 596 } 597 #ifdef CZ_DEBUG 598 printf("\n"); 599 #endif 600 if (i == 100) { 601 CZ_WIN_FPGA(cz); 602 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 603 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 604 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 605 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 606 CZ_FPGA_READ(cz, FPGA_VERSION)); 607 return (EIO); 608 } 609 610 /* 611 * Locate the firmware control structures. 612 */ 613 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 614 ZFIRM_CTRLADDR_OFF); 615 #ifdef CZ_DEBUG 616 printf("%s: FWCTL structure at offset 0x%08lx\n", 617 cz->cz_dev.dv_xname, cz->cz_fwctl); 618 #endif 619 620 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 621 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 622 623 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 624 625 switch (cz->cz_mailbox0) { 626 case MAILBOX0_8Zo_V1: 627 board = "Cyclades-8Zo ver. 1"; 628 break; 629 630 case MAILBOX0_8Zo_V2: 631 board = "Cyclades-8Zo ver. 2"; 632 break; 633 634 case MAILBOX0_Ze_V1: 635 board = "Cyclades-Ze"; 636 break; 637 638 default: 639 board = "unknown Cyclades Z-series"; 640 break; 641 } 642 643 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 644 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 645 if (cz->cz_nchannels == 0) 646 printf("no channels attached, "); 647 else 648 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 649 cz->cz_nchannels, cztty_attached_ttys, 650 cztty_attached_ttys + (cz->cz_nchannels - 1)); 651 printf("firmware %x.%x.%x\n", 652 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 653 654 return (0); 655 } 656 657 /* 658 * cz_poll: 659 * 660 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 661 * ms. 662 */ 663 void 664 cz_poll(void *arg) 665 { 666 int s = spltty(); 667 struct cz_softc *cz = arg; 668 669 cz_intr(cz); 670 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 671 672 splx(s); 673 } 674 675 /* 676 * cz_intr: 677 * 678 * Interrupt service routine. 679 * 680 * We either are receiving an interrupt directly from the board, or we are 681 * in polling mode and it's time to poll. 682 */ 683 int 684 cz_intr(void *arg) 685 { 686 int rval = 0; 687 u_int command, channel, param; 688 struct cz_softc *cz = arg; 689 struct cztty_softc *sc; 690 struct tty *tp; 691 692 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 693 rval = 1; 694 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 695 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 696 697 /* now clear this interrupt, posslibly enabling another */ 698 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 699 700 if (cz->cz_ports == NULL) { 701 #ifdef CZ_DEBUG 702 printf("%s: interrupt on channel %d, but no channels\n", 703 cz->cz_dev.dv_xname, channel); 704 #endif 705 continue; 706 } 707 708 sc = &cz->cz_ports[channel]; 709 710 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 711 break; 712 713 tp = sc->sc_tty; 714 715 switch (command) { 716 case C_CM_TXFEMPTY: /* transmit cases */ 717 case C_CM_TXBEMPTY: 718 case C_CM_TXLOWWM: 719 case C_CM_INTBACK: 720 if (!ISSET(tp->t_state, TS_ISOPEN)) { 721 #ifdef CZ_DEBUG 722 printf("%s: tx intr on closed channel %d\n", 723 cz->cz_dev.dv_xname, channel); 724 #endif 725 break; 726 } 727 728 if (cztty_transmit(sc, tp)) { 729 /* 730 * Do wakeup stuff here. 731 */ 732 ttwakeup(tp); 733 wakeup(tp); 734 } 735 break; 736 737 case C_CM_RXNNDT: /* receive cases */ 738 case C_CM_RXHIWM: 739 case C_CM_INTBACK2: /* from restart ?? */ 740 #if 0 741 case C_CM_ICHAR: 742 #endif 743 if (!ISSET(tp->t_state, TS_ISOPEN)) { 744 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 745 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 746 break; 747 } 748 749 if (cztty_receive(sc, tp)) { 750 /* 751 * Do wakeup stuff here. 752 */ 753 ttwakeup(tp); 754 wakeup(tp); 755 } 756 break; 757 758 case C_CM_MDCD: 759 if (!ISSET(tp->t_state, TS_ISOPEN)) 760 break; 761 762 (void) (*linesw[tp->t_line].l_modem)(tp, 763 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 764 CHNCTL_RS_STATUS))); 765 break; 766 767 case C_CM_MDSR: 768 case C_CM_MRI: 769 case C_CM_MCTS: 770 case C_CM_MRTS: 771 break; 772 773 case C_CM_IOCTLW: 774 break; 775 776 case C_CM_PR_ERROR: 777 sc->sc_parity_errors++; 778 goto error_common; 779 780 case C_CM_FR_ERROR: 781 sc->sc_framing_errors++; 782 goto error_common; 783 784 case C_CM_OVR_ERROR: 785 sc->sc_overflows++; 786 error_common: 787 if (sc->sc_errors++ == 0) 788 timeout_add_sec(&sc->sc_diag_to, 60); 789 break; 790 791 case C_CM_RXBRK: 792 if (!ISSET(tp->t_state, TS_ISOPEN)) 793 break; 794 795 /* 796 * A break is a \000 character with TTY_FE error 797 * flags set. So TTY_FE by itself works. 798 */ 799 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 800 ttwakeup(tp); 801 wakeup(tp); 802 break; 803 804 default: 805 #ifdef CZ_DEBUG 806 printf("%s: channel %d: Unknown interrupt 0x%x\n", 807 cz->cz_dev.dv_xname, sc->sc_channel, command); 808 #endif 809 break; 810 } 811 } 812 813 return (rval); 814 } 815 816 /* 817 * cz_wait_pci_doorbell: 818 * 819 * Wait for the pci doorbell to be clear - wait for pending 820 * activity to drain. 821 */ 822 int 823 cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring) 824 { 825 int error; 826 827 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 828 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 829 if ((error != 0) && (error != EWOULDBLOCK)) 830 return (error); 831 } 832 return (0); 833 } 834 835 /***************************************************************************** 836 * Cyclades-Z TTY code starts here... 837 *****************************************************************************/ 838 839 #define CZTTYDIALOUT_MASK 0x80 840 841 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 842 #define CZTTY_CZ(sc) ((sc)->sc_parent) 843 844 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 845 846 struct cztty_softc * 847 cztty_getttysoftc(dev_t dev) 848 { 849 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 850 struct cz_softc *cz; 851 852 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 853 k = j; 854 cz = (struct cz_softc *)device_lookup(&cz_cd, i); 855 if (cz == NULL) 856 continue; 857 if (cz->cz_ports == NULL) 858 continue; 859 j += cz->cz_nchannels; 860 if (j > u) 861 break; 862 } 863 864 if (i >= cz_cd.cd_ndevs) 865 return (NULL); 866 else 867 return (&cz->cz_ports[u - k]); 868 } 869 870 int 871 cztty_findmajor(void) 872 { 873 int maj; 874 875 for (maj = 0; maj < nchrdev; maj++) { 876 if (cdevsw[maj].d_open == czttyopen) 877 break; 878 } 879 880 return (maj == nchrdev) ? 0 : maj; 881 } 882 883 /* 884 * czttytty: 885 * 886 * Return a pointer to our tty. 887 */ 888 struct tty * 889 czttytty(dev_t dev) 890 { 891 struct cztty_softc *sc = CZTTY_SOFTC(dev); 892 893 #ifdef DIAGNOSTIC 894 if (sc == NULL) 895 panic("czttytty"); 896 #endif 897 898 return (sc->sc_tty); 899 } 900 901 /* 902 * cztty_shutdown: 903 * 904 * Shut down a port. 905 */ 906 void 907 cztty_shutdown(struct cztty_softc *sc) 908 { 909 struct cz_softc *cz = CZTTY_CZ(sc); 910 struct tty *tp = sc->sc_tty; 911 int s; 912 913 s = spltty(); 914 915 /* Clear any break condition set with TIOCSBRK. */ 916 cztty_break(sc, 0); 917 918 /* 919 * Hang up if necessary. Wait a bit, so the other side has time to 920 * notice even if we immediately open the port again. 921 */ 922 if (ISSET(tp->t_cflag, HUPCL)) { 923 cztty_modem(sc, 0); 924 (void) tsleep(tp, TTIPRI, ttclos, hz); 925 } 926 927 /* Disable the channel. */ 928 cz_wait_pci_doorbell(cz, "czdis"); 929 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 930 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 931 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 932 933 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 934 #ifdef CZ_DEBUG 935 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 936 #endif 937 timeout_del(&cz->cz_timeout); 938 } 939 940 splx(s); 941 } 942 943 /* 944 * czttyopen: 945 * 946 * Open a Cyclades-Z serial port. 947 */ 948 int 949 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 950 { 951 struct cztty_softc *sc = CZTTY_SOFTC(dev); 952 struct cz_softc *cz; 953 struct tty *tp; 954 int s, error; 955 956 if (sc == NULL) 957 return (ENXIO); 958 959 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 960 return (ENXIO); 961 962 cz = CZTTY_CZ(sc); 963 tp = sc->sc_tty; 964 965 if (ISSET(tp->t_state, TS_ISOPEN) && 966 ISSET(tp->t_state, TS_XCLUDE) && 967 suser(p, 0) != 0) 968 return (EBUSY); 969 970 s = spltty(); 971 972 /* 973 * Do the following iff this is a first open. 974 */ 975 if (!ISSET(tp->t_state, TS_ISOPEN)) { 976 struct termios t; 977 978 tp->t_dev = dev; 979 980 /* If we're turning things on, enable interrupts */ 981 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 982 #ifdef CZ_DEBUG 983 printf("%s: Enabling polling.\n", 984 cz->cz_dev.dv_xname); 985 #endif 986 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 987 } 988 989 /* 990 * Enable the channel. Don't actually ring the 991 * doorbell here; czttyparam() will do it for us. 992 */ 993 cz_wait_pci_doorbell(cz, "czopen"); 994 995 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 996 997 /* 998 * Initialize the termios status to the defaults. Add in the 999 * sticky bits from TIOCSFLAGS. 1000 */ 1001 t.c_ispeed = 0; 1002 t.c_ospeed = TTYDEF_SPEED; 1003 t.c_cflag = TTYDEF_CFLAG; 1004 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1005 SET(t.c_cflag, CLOCAL); 1006 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1007 SET(t.c_cflag, CRTSCTS); 1008 1009 /* 1010 * Reset the input and output rings. Do this before 1011 * we call czttyparam(), as that function enables 1012 * the channel. 1013 */ 1014 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1015 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1016 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1017 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1018 1019 /* Make sure czttyparam() will see changes. */ 1020 tp->t_ospeed = 0; 1021 (void) czttyparam(tp, &t); 1022 tp->t_iflag = TTYDEF_IFLAG; 1023 tp->t_oflag = TTYDEF_OFLAG; 1024 tp->t_lflag = TTYDEF_LFLAG; 1025 ttychars(tp); 1026 ttsetwater(tp); 1027 1028 /* 1029 * Turn on DTR. We must always do this, even if carrier is not 1030 * present, because otherwise we'd have to use TIOCSDTR 1031 * immediately after setting CLOCAL, which applications do not 1032 * expect. We always assert DTR while the device is open 1033 * unless explicitly requested to deassert it. 1034 */ 1035 cztty_modem(sc, 1); 1036 } 1037 1038 splx(s); 1039 1040 error = ttyopen(CZTTY_DIALOUT(dev), tp, p); 1041 if (error) 1042 goto bad; 1043 1044 error = (*linesw[tp->t_line].l_open)(dev, tp, p); 1045 if (error) 1046 goto bad; 1047 1048 return (0); 1049 1050 bad: 1051 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1052 /* 1053 * We failed to open the device, and nobody else had it opened. 1054 * Clean up the state as appropriate. 1055 */ 1056 cztty_shutdown(sc); 1057 } 1058 1059 return (error); 1060 } 1061 1062 /* 1063 * czttyclose: 1064 * 1065 * Close a Cyclades-Z serial port. 1066 */ 1067 int 1068 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1069 { 1070 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1071 struct tty *tp = sc->sc_tty; 1072 1073 /* XXX This is for cons.c. */ 1074 if (!ISSET(tp->t_state, TS_ISOPEN)) 1075 return (0); 1076 1077 (*linesw[tp->t_line].l_close)(tp, flags, p); 1078 ttyclose(tp); 1079 1080 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1081 /* 1082 * Although we got a last close, the device may still be in 1083 * use; e.g. if this was the dialout node, and there are still 1084 * processes waiting for carrier on the non-dialout node. 1085 */ 1086 cztty_shutdown(sc); 1087 } 1088 1089 return (0); 1090 } 1091 1092 /* 1093 * czttyread: 1094 * 1095 * Read from a Cyclades-Z serial port. 1096 */ 1097 int 1098 czttyread(dev_t dev, struct uio *uio, int flags) 1099 { 1100 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1101 struct tty *tp = sc->sc_tty; 1102 1103 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1104 } 1105 1106 /* 1107 * czttywrite: 1108 * 1109 * Write to a Cyclades-Z serial port. 1110 */ 1111 int 1112 czttywrite(dev_t dev, struct uio *uio, int flags) 1113 { 1114 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1115 struct tty *tp = sc->sc_tty; 1116 1117 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1118 } 1119 1120 #if 0 1121 /* 1122 * czttypoll: 1123 * 1124 * Poll a Cyclades-Z serial port. 1125 */ 1126 int 1127 czttypoll(dev_t dev, int events, struct proc *p) 1128 { 1129 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1130 struct tty *tp = sc->sc_tty; 1131 1132 return ((*linesw[tp->t_line].l_poll)(tp, events, p)); 1133 } 1134 #endif 1135 1136 /* 1137 * czttyioctl: 1138 * 1139 * Perform a control operation on a Cyclades-Z serial port. 1140 */ 1141 int 1142 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1143 { 1144 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1145 struct tty *tp = sc->sc_tty; 1146 int s, error; 1147 1148 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1149 if (error >= 0) 1150 return (error); 1151 1152 error = ttioctl(tp, cmd, data, flag, p); 1153 if (error >= 0) 1154 return (error); 1155 1156 error = 0; 1157 1158 s = spltty(); 1159 1160 switch (cmd) { 1161 case TIOCSBRK: 1162 cztty_break(sc, 1); 1163 break; 1164 1165 case TIOCCBRK: 1166 cztty_break(sc, 0); 1167 break; 1168 1169 case TIOCGFLAGS: 1170 *(int *)data = sc->sc_swflags; 1171 break; 1172 1173 case TIOCSFLAGS: 1174 error = suser(p, 0); 1175 if (error) 1176 break; 1177 sc->sc_swflags = *(int *)data; 1178 break; 1179 1180 case TIOCSDTR: 1181 cztty_modem(sc, 1); 1182 break; 1183 1184 case TIOCCDTR: 1185 cztty_modem(sc, 0); 1186 break; 1187 1188 case TIOCMSET: 1189 case TIOCMBIS: 1190 case TIOCMBIC: 1191 tiocm_to_cztty(sc, cmd, *(int *)data); 1192 break; 1193 1194 case TIOCMGET: 1195 *(int *)data = cztty_to_tiocm(sc); 1196 break; 1197 1198 default: 1199 error = ENOTTY; 1200 break; 1201 } 1202 1203 splx(s); 1204 1205 return (error); 1206 } 1207 1208 /* 1209 * cztty_break: 1210 * 1211 * Set or clear BREAK on a port. 1212 */ 1213 void 1214 cztty_break(struct cztty_softc *sc, int onoff) 1215 { 1216 struct cz_softc *cz = CZTTY_CZ(sc); 1217 1218 cz_wait_pci_doorbell(cz, "czbreak"); 1219 1220 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1221 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1222 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1223 } 1224 1225 /* 1226 * cztty_modem: 1227 * 1228 * Set or clear DTR on a port. 1229 */ 1230 void 1231 cztty_modem(struct cztty_softc *sc, int onoff) 1232 { 1233 struct cz_softc *cz = CZTTY_CZ(sc); 1234 1235 if (sc->sc_rs_control_dtr == 0) 1236 return; 1237 1238 cz_wait_pci_doorbell(cz, "czmod"); 1239 1240 if (onoff) 1241 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1242 else 1243 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1244 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1245 1246 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1247 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1248 } 1249 1250 /* 1251 * tiocm_to_cztty: 1252 * 1253 * Process TIOCM* ioctls. 1254 */ 1255 void 1256 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1257 { 1258 struct cz_softc *cz = CZTTY_CZ(sc); 1259 u_int32_t czttybits; 1260 1261 czttybits = 0; 1262 if (ISSET(ttybits, TIOCM_DTR)) 1263 SET(czttybits, C_RS_DTR); 1264 if (ISSET(ttybits, TIOCM_RTS)) 1265 SET(czttybits, C_RS_RTS); 1266 1267 cz_wait_pci_doorbell(cz, "cztiocm"); 1268 1269 switch (how) { 1270 case TIOCMBIC: 1271 CLR(sc->sc_chanctl_rs_control, czttybits); 1272 break; 1273 1274 case TIOCMBIS: 1275 SET(sc->sc_chanctl_rs_control, czttybits); 1276 break; 1277 1278 case TIOCMSET: 1279 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1280 SET(sc->sc_chanctl_rs_control, czttybits); 1281 break; 1282 } 1283 1284 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1285 1286 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1287 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1288 } 1289 1290 /* 1291 * cztty_to_tiocm: 1292 * 1293 * Process the TIOCMGET ioctl. 1294 */ 1295 int 1296 cztty_to_tiocm(struct cztty_softc *sc) 1297 { 1298 struct cz_softc *cz = CZTTY_CZ(sc); 1299 u_int32_t rs_status, op_mode; 1300 int ttybits = 0; 1301 1302 cz_wait_pci_doorbell(cz, "cztty"); 1303 1304 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1305 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1306 1307 if (ISSET(rs_status, C_RS_RTS)) 1308 SET(ttybits, TIOCM_RTS); 1309 if (ISSET(rs_status, C_RS_CTS)) 1310 SET(ttybits, TIOCM_CTS); 1311 if (ISSET(rs_status, C_RS_DCD)) 1312 SET(ttybits, TIOCM_CAR); 1313 if (ISSET(rs_status, C_RS_DTR)) 1314 SET(ttybits, TIOCM_DTR); 1315 if (ISSET(rs_status, C_RS_RI)) 1316 SET(ttybits, TIOCM_RNG); 1317 if (ISSET(rs_status, C_RS_DSR)) 1318 SET(ttybits, TIOCM_DSR); 1319 1320 if (ISSET(op_mode, C_CH_ENABLE)) 1321 SET(ttybits, TIOCM_LE); 1322 1323 return (ttybits); 1324 } 1325 1326 /* 1327 * czttyparam: 1328 * 1329 * Set Cyclades-Z serial port parameters from termios. 1330 * 1331 * XXX Should just copy the whole termios after making 1332 * XXX sure all the changes could be done. 1333 */ 1334 int 1335 czttyparam(struct tty *tp, struct termios *t) 1336 { 1337 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1338 struct cz_softc *cz = CZTTY_CZ(sc); 1339 u_int32_t rs_status; 1340 int ospeed, cflag; 1341 1342 ospeed = t->c_ospeed; 1343 cflag = t->c_cflag; 1344 1345 /* Check requested parameters. */ 1346 if (ospeed < 0) 1347 return (EINVAL); 1348 if (t->c_ispeed && t->c_ispeed != ospeed) 1349 return (EINVAL); 1350 1351 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1352 SET(cflag, CLOCAL); 1353 CLR(cflag, HUPCL); 1354 } 1355 1356 /* 1357 * If there were no changes, don't do anything. This avoids dropping 1358 * input and improves performance when all we did was frob things like 1359 * VMIN and VTIME. 1360 */ 1361 if (tp->t_ospeed == ospeed && 1362 tp->t_cflag == cflag) 1363 return (0); 1364 1365 /* Data bits. */ 1366 sc->sc_chanctl_comm_data_l = 0; 1367 switch (t->c_cflag & CSIZE) { 1368 case CS5: 1369 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1370 break; 1371 1372 case CS6: 1373 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1374 break; 1375 1376 case CS7: 1377 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1378 break; 1379 1380 case CS8: 1381 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1382 break; 1383 } 1384 1385 /* Stop bits. */ 1386 if (t->c_cflag & CSTOPB) { 1387 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1388 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1389 else 1390 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1391 } else 1392 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1393 1394 /* Parity. */ 1395 if (t->c_cflag & PARENB) { 1396 if (t->c_cflag & PARODD) 1397 sc->sc_chanctl_comm_parity = C_PR_ODD; 1398 else 1399 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1400 } else 1401 sc->sc_chanctl_comm_parity = C_PR_NONE; 1402 1403 /* 1404 * Initialize flow control pins depending on the current flow control 1405 * mode. 1406 */ 1407 if (ISSET(t->c_cflag, CRTSCTS)) { 1408 sc->sc_rs_control_dtr = C_RS_DTR; 1409 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1410 } else if (ISSET(t->c_cflag, MDMBUF)) { 1411 sc->sc_rs_control_dtr = 0; 1412 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1413 } else { 1414 /* 1415 * If no flow control, then always set RTS. This will make 1416 * the other side happy if it mistakenly thinks we're doing 1417 * RTS/CTS flow control. 1418 */ 1419 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1420 sc->sc_chanctl_hw_flow = 0; 1421 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1422 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1423 else 1424 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1425 } 1426 1427 /* Baud rate. */ 1428 sc->sc_chanctl_comm_baud = ospeed; 1429 1430 /* Copy to tty. */ 1431 tp->t_ispeed = 0; 1432 tp->t_ospeed = t->c_ospeed; 1433 tp->t_cflag = t->c_cflag; 1434 1435 /* 1436 * Now load the channel control structure. 1437 */ 1438 1439 cz_wait_pci_doorbell(cz, "czparam"); 1440 1441 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1442 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1443 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1444 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1445 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1446 1447 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1448 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1449 1450 cz_wait_pci_doorbell(cz, "czparam"); 1451 1452 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1453 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1454 1455 cz_wait_pci_doorbell(cz, "czparam"); 1456 1457 /* 1458 * Update the tty layer's idea of the carrier bit, in case we changed 1459 * CLOCAL. We don't hang up here; we only do that by explicit 1460 * request. 1461 */ 1462 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1463 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1464 1465 return (0); 1466 } 1467 1468 /* 1469 * czttystart: 1470 * 1471 * Start or restart transmission. 1472 */ 1473 void 1474 czttystart(struct tty *tp) 1475 { 1476 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1477 int s; 1478 1479 s = spltty(); 1480 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1481 goto out; 1482 1483 ttwakeupwr(tp); 1484 if (tp->t_outq.c_cc == 0) 1485 goto out; 1486 1487 cztty_transmit(sc, tp); 1488 out: 1489 splx(s); 1490 } 1491 1492 /* 1493 * czttystop: 1494 * 1495 * Stop output, e.g., for ^S or output flush. 1496 */ 1497 int 1498 czttystop(struct tty *tp, int flag) 1499 { 1500 1501 /* 1502 * XXX We don't do anything here, yet. Mostly, I don't know 1503 * XXX exactly how this should be implemented on this device. 1504 * XXX We've given a big chunk of data to the MIPS already, 1505 * XXX and I don't know how we request the MIPS to stop sending 1506 * XXX the data. So, punt for now. --thorpej 1507 */ 1508 return (0); 1509 } 1510 1511 /* 1512 * cztty_diag: 1513 * 1514 * Issue a scheduled diagnostic message. 1515 */ 1516 void 1517 cztty_diag(void *arg) 1518 { 1519 struct cztty_softc *sc = arg; 1520 struct cz_softc *cz = CZTTY_CZ(sc); 1521 u_int overflows, parity_errors, framing_errors; 1522 int s; 1523 1524 s = spltty(); 1525 1526 overflows = sc->sc_overflows; 1527 sc->sc_overflows = 0; 1528 1529 parity_errors = sc->sc_parity_errors; 1530 sc->sc_parity_errors = 0; 1531 1532 framing_errors = sc->sc_framing_errors; 1533 sc->sc_framing_errors = 0; 1534 1535 sc->sc_errors = 0; 1536 1537 splx(s); 1538 1539 log(LOG_WARNING, 1540 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1541 cz->cz_dev.dv_xname, sc->sc_channel, 1542 overflows, overflows == 1 ? "" : "s", 1543 parity_errors, 1544 framing_errors, framing_errors == 1 ? "" : "s"); 1545 } 1546 1547 /* 1548 * tx and rx ring buffer size macros: 1549 * 1550 * The transmitter and receiver both use ring buffers. For each one, there 1551 * is a get (consumer) and a put (producer) offset. The get value is the 1552 * next byte to be read from the ring, and the put is the next one to be 1553 * put into the ring. get == put means the ring is empty. 1554 * 1555 * For each ring, the firmware controls one of (get, put) and this driver 1556 * controls the other. For transmission, this driver updates put to point 1557 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1558 * for receive, the driver controls put, and this driver controls get. 1559 */ 1560 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1561 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1562 1563 /* 1564 * cztty_transmit() 1565 * 1566 * Look at the tty for this port and start sending. 1567 */ 1568 int 1569 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1570 { 1571 struct cz_softc *cz = CZTTY_CZ(sc); 1572 u_int move, get, put, size, address; 1573 #ifdef HOSTRAMCODE 1574 int error, done = 0; 1575 #else 1576 int done = 0; 1577 #endif 1578 1579 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1580 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1581 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1582 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1583 1584 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1585 #ifdef HOSTRAMCODE 1586 if (0) { 1587 move = min(tp->t_outq.c_cc, move); 1588 error = q_to_b(&tp->t_outq, 0, move); 1589 if (error != move) { 1590 printf("%s: channel %d: error moving to " 1591 "transmit buf\n", cz->cz_dev.dv_xname, 1592 sc->sc_channel); 1593 move = error; 1594 } 1595 } else { 1596 #endif 1597 move = min(ndqb(&tp->t_outq, 0), move); 1598 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1599 address + put, tp->t_outq.c_cf, move); 1600 ndflush(&tp->t_outq, move); 1601 #ifdef HOSTRAMCODE 1602 } 1603 #endif 1604 1605 put = ((put + move) % size); 1606 done = 1; 1607 } 1608 if (done) { 1609 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1610 } 1611 return (done); 1612 } 1613 1614 int 1615 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1616 { 1617 struct cz_softc *cz = CZTTY_CZ(sc); 1618 u_int get, put, size, address; 1619 int done = 0, ch; 1620 1621 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1622 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1623 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1624 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1625 1626 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1627 #ifdef HOSTRAMCODE 1628 if (hostram) 1629 ch = ((char *)fifoaddr)[get]; 1630 } else { 1631 #endif 1632 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1633 address + get); 1634 #ifdef HOSTRAMCODE 1635 } 1636 #endif 1637 (*linesw[tp->t_line].l_rint)(ch, tp); 1638 get = (get + 1) % size; 1639 done = 1; 1640 } 1641 if (done) { 1642 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1643 } 1644 return (done); 1645 } 1646