1 /* 2 * Copyright 2017 Valve Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Andres Rodriguez <andresx7@gmail.com> 23 */ 24 25 #include <linux/fdtable.h> 26 #include <linux/file.h> 27 #include <linux/pid.h> 28 29 #include <drm/amdgpu_drm.h> 30 31 #include "amdgpu.h" 32 33 #include "amdgpu_vm.h" 34 35 enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority) 36 { 37 switch (amdgpu_priority) { 38 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 39 return DRM_SCHED_PRIORITY_HIGH_HW; 40 case AMDGPU_CTX_PRIORITY_HIGH: 41 return DRM_SCHED_PRIORITY_HIGH_SW; 42 case AMDGPU_CTX_PRIORITY_NORMAL: 43 return DRM_SCHED_PRIORITY_NORMAL; 44 case AMDGPU_CTX_PRIORITY_LOW: 45 case AMDGPU_CTX_PRIORITY_VERY_LOW: 46 return DRM_SCHED_PRIORITY_LOW; 47 case AMDGPU_CTX_PRIORITY_UNSET: 48 return DRM_SCHED_PRIORITY_UNSET; 49 default: 50 WARN(1, "Invalid context priority %d\n", amdgpu_priority); 51 return DRM_SCHED_PRIORITY_INVALID; 52 } 53 } 54 55 static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, 56 int fd, 57 enum drm_sched_priority priority) 58 { 59 STUB(); 60 return -ENOSYS; 61 #ifdef notyet 62 struct fd f = fdget(fd); 63 struct amdgpu_fpriv *fpriv; 64 struct amdgpu_ctx *ctx; 65 uint32_t id; 66 int r; 67 68 if (!f.file) 69 return -EINVAL; 70 71 r = amdgpu_file_to_fpriv(f.file, &fpriv); 72 if (r) { 73 fdput(f); 74 return r; 75 } 76 77 idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) 78 amdgpu_ctx_priority_override(ctx, priority); 79 80 fdput(f); 81 return 0; 82 #endif 83 } 84 85 static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev, 86 int fd, 87 unsigned ctx_id, 88 enum drm_sched_priority priority) 89 { 90 STUB(); 91 return -ENOSYS; 92 #ifdef notyet 93 struct fd f = fdget(fd); 94 struct amdgpu_fpriv *fpriv; 95 struct amdgpu_ctx *ctx; 96 int r; 97 98 if (!f.file) 99 return -EINVAL; 100 101 r = amdgpu_file_to_fpriv(f.file, &fpriv); 102 if (r) { 103 fdput(f); 104 return r; 105 } 106 107 ctx = amdgpu_ctx_get(fpriv, ctx_id); 108 109 if (!ctx) { 110 fdput(f); 111 return -EINVAL; 112 } 113 114 amdgpu_ctx_priority_override(ctx, priority); 115 amdgpu_ctx_put(ctx); 116 fdput(f); 117 118 return 0; 119 #endif 120 } 121 122 int amdgpu_sched_ioctl(struct drm_device *dev, void *data, 123 struct drm_file *filp) 124 { 125 union drm_amdgpu_sched *args = data; 126 struct amdgpu_device *adev = dev->dev_private; 127 enum drm_sched_priority priority; 128 int r; 129 130 priority = amdgpu_to_sched_priority(args->in.priority); 131 if (priority == DRM_SCHED_PRIORITY_INVALID) 132 return -EINVAL; 133 134 switch (args->in.op) { 135 case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: 136 r = amdgpu_sched_process_priority_override(adev, 137 args->in.fd, 138 priority); 139 break; 140 case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE: 141 r = amdgpu_sched_context_priority_override(adev, 142 args->in.fd, 143 args->in.ctx_id, 144 priority); 145 break; 146 default: 147 DRM_ERROR("Invalid sched op specified: %d\n", args->in.op); 148 r = -EINVAL; 149 break; 150 } 151 152 return r; 153 } 154